LED driving circuit and driving method thereof

Abstract

An LED driving circuit and a driving method thereof are disclosed. A driving method of an LED driving circuit comprising a data transmission device, a bridge integrated circuit, and a plurality of data driving devices may comprise the steps in which: first to N-th (N is a natural number of 3 or greater) data driving devices sequentially register IDs; the first to N-th data driving devices sequentially generate instructions; the first to N-th data driving devices sequentially generate registers; and the first to N-th driving devices sequentially read the registers, wherein the first data driving device among the plurality of data driving devices receives an identification number from the data transmission device, stores the identification number as its own identification number, modulates the identification number, and transmits the modulated identification number to a neighboring data driving device, thereby reducing the number of required lanes compared to a conventional control method of directly controlling each driver integrated circuit in a microcontroller unit.

Description

LED driving circuit and driving method thereof

[0001] This embodiment relates to an LED driving circuit and a driving method thereof.

[0002] As informatization advances, various display devices capable of visualizing information are being developed. Liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, and plasma display panels (PDPs) are representative examples of displays that have been developed or are currently under development. These displays are evolving to enable the appropriate display of high-resolution images.

[0003] In LED display technology, modularized LED pixels can be arranged in the required number to form a single large panel, or unit panels composed of multiple LED pixels can be arranged in the required number to form a single large panel structure. Thus, LED display technology facilitates the implementation of large-scale displays by expanding and arranging LED pixels as needed.

[0004] LED displays have the advantage of not only being able to be enlarged but also being able to diversify panel sizes. In LED display technology, the horizontal and vertical sizes can be adjusted in various ways depending on the appropriate arrangement of LED pixels.

[0005] The purpose of this embodiment is to provide an LED driving circuit and a driving method thereof that can reduce the number of required lanes compared to a conventional control method in which each driver integrated circuit is directly controlled by a microcontroller unit.

[0006] The purpose of this embodiment is to provide an LED driving circuit and a driving method thereof, in which a plurality of driver integrated circuits can synchronize the start time of FPWM (Frequency Pulse Width Modulation) by resetting a vertical synchronization signal.

[0007] The purpose of this embodiment is to provide an LED driving circuit and a driving method thereof, in which a plurality of driver integrated circuits can synchronize the dimming start time by an input synchronization signal generated by an FPWM.

[0008] An LED driving circuit according to the present embodiment comprises: a data transmission device that transmits a clock signal, a data signal, and an identification number for controlling an LED driving current; a bridge integrated circuit that includes a plurality of lanes (LANE) and receives the clock signal and the data signal; and a plurality of data driving devices that receive the clock signal and the data signal from the lanes and sequentially transmit them, wherein a first data driving device among the plurality of data driving devices receives the identification number, stores it as its own identification number, modulates the identification number, and transmits it to a neighboring data driving device.

[0009] When the plurality of data driving devices register an ID, the data transmission device loads a number that is 1 less than the number of integrated circuits connected to the LANE provided in the bridge integrated circuit into the ID, and transmits a preamble signal, the ID, and an ID allocation command to the first data driving device, and when the preamble signal and the ID allocation command are input, the first data driving device registers the ID received from the data transmission device as its ID, loads a number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal, the ID, and the ID allocation command to the second data driving device, and when the second data driving device inputs the preamble signal and the ID allocation command, the ID received from the first data driving device as its ID, loads a number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal, the ID, and the ID allocation command to the third data driving device, and the Nth (N is a natural number equal to or greater than 3) data When the above preamble signal and ID assignment command are input, the driving device can register the ID received from the (N-1) data driving device as its own ID.

[0010] The above Nth data driving device may further include a step of transmitting an ID allocation completion signal to the data transmission device if the registered ID is 0.

[0011] The first data driving device may further include a step of transmitting a standby command to the second data driving device when the preamble signal and the ID assignment command are input.

[0012] The second data driving device may further include a step of transmitting a standby command to the third data driving device when the preamble signal and the ID assignment command are input.

[0013] When the first to Nth data driving devices write a command, the data transmission device may transmit the preamble signal, the command writing command, and the address to the first data driving device, and the first data driving device may decode the address when the command writing command is input and latch the command, decrement its ID by 1 for each clock, and write the latched command when the ID becomes 0, and the second data driving device may decode the address when the command writing command is input and latch the command, decrement its ID by 1 for each clock, and write the latched command when the ID becomes 0, and the Nth data driving device may decode the address when the command writing command is input and latch the command, decrement its ID by 1 for each clock, and write the latched command when the ID becomes 0.

[0014] The first to Nth data driving devices can be synchronized with the start point of FPWM (Frequency Pulse Width Modulation) by resetting the vertical synchronization signal.

[0015] The first to n data driving devices can have their dimming start time synchronized by an input synchronization signal generated by FPWM (Frequency Pulse Width Modulation).

[0016] When the first to Nth data driving devices write a register, the data transmission device transmits the preamble signal, the register writing command, the address, and N data to the first data driving device, and when the register writing command of the data transmission device is input, the first data driving device receives the address, multiplies its own ID by the number of bits among the N pieces of input data, recognizes that the input data is its own data, and updates it; when the register writing command of the first data driving device is input, the second data driving device receives the address, multiplies its own ID by the number of bits among the N pieces of input data, recognizes that the input data is its own data, and updates it; when the register writing command of the (N-1)th data driving device is input, the Nth data driving device receives the address, multiplies its own ID by the number of bits among the N pieces of input data, recognizes that the input data is its own data, and updates it.

[0017] The method may include a step in which, when the first to Nth data driving devices read a register, the data transmission device transmits the preamble signal, the register read command, and the address to the first data driving device, the first data driving device receives the address when the register read command of the data transmission device is input, prepares data of the corresponding address, decrements its ID by 1 for each clock, and outputs the prepared data when the ID becomes 0, the second data driving device receives the address when the register read command of the data driving device is input, prepares data of the corresponding address, decrements its ID by 1 for each clock, and outputs the prepared data when the ID becomes 0, and the Nth data driving device prepares data of the corresponding address when the register read command of the (N-1)th data driving device is input, decrements its ID by 1 for each clock, and outputs the prepared data when the ID becomes 0.

[0018] According to one embodiment of the present invention, a driving method of an LED driving circuit is provided, wherein the LED driving circuit comprises a data transmission device, a bridge integrated circuit, and a plurality of data driving devices, the driving method comprising: a step in which first to Nth (N is a natural number equal to or greater than 3) data driving devices sequentially register IDs; a step in which the first to Nth data driving devices sequentially write commands; a step in which the first to Nth data driving devices sequentially write registers; and a step in which the first to Nth data driving devices sequentially read registers, wherein a first data driving device among the plurality of data driving devices receives an identification number from the data transmission device, stores it as its own identification number, modulates the identification number, and transmits the modified identification number to a neighboring data driving device.

[0019] The step of registering the ID by the first to Nth data driving devices comprises: a step in which the data transmission device loads a number that is 1 less than the number of integrated circuits connected to the LANEs provided in the bridge integrated circuit into the ID, and transmits a preamble signal, the ID, and an ID allocation command to the first data driving device; a step in which the first data driving device, when the preamble signal and the ID allocation command are input, registers the ID received from the data transmission device as its own ID; a step in which the first data driving device loads a number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal, the ID, and the ID allocation command to the second data driving device; a step in which the second data driving device, when the preamble signal and the ID allocation command are input, registers the ID received from the first data driving device as its own ID; The second data driving device may include a step of loading a number obtained by subtracting 1 from the registered ID into the ID and transmitting the preamble signal, the ID, and the ID allocation command to the third data driving device; and a step of the Nth data driving device registering the ID received from the (N-1)th data driving device as its own ID when the preamble signal and the ID allocation command are input.

[0020] According to this embodiment, the number of required lanes can be reduced compared to the conventional control method in which each driver integrated circuit is directly controlled by a microcontroller unit.

[0021] According to this embodiment, a plurality of driver integrated circuits can be synchronized at the start point of Frequency Pulse Width Modulation (FPWM) by resetting the vertical synchronization signal.

[0022] According to this embodiment, the dimming start time of multiple driver integrated circuits can be synchronized by an input synchronization signal generated by the FPWM.

[0023] Figure 1 is a block diagram of an LED driving circuit according to one embodiment of the present invention.

[0024] FIG. 2 is a schematic diagram showing a state in which an ID is assigned when registering an ID in the first to third driver integrated circuits according to one embodiment of the present invention.

[0025] FIG. 3 is a timing diagram for explaining a process in which the first to third driver integrated circuits register an ID according to one embodiment of the present invention.

[0026] FIG. 4 is a schematic diagram showing a state in which an ID is assigned when writing a command in the first and second driver integrated circuits according to one embodiment of the present invention.

[0027] FIG. 5 is a timing diagram for explaining a process in which the first and second driver integrated circuits according to one embodiment of the present invention write a command.

[0028] FIG. 6 is a timing diagram for explaining a process in which the first to Nth driver integrated circuits according to one embodiment of the present invention write a register.

[0029] FIG. 7 is a timing diagram for explaining a process in which the first to Nth driver integrated circuits read a register according to one embodiment of the present invention.

[0030] Figure 8 is a block diagram showing the logic of a driver integrated circuit according to one embodiment of the present invention.

[0031] FIG. 9 is a timing diagram for explaining synchronization of a driver integrated circuit according to one embodiment of the present invention.

[0032] FIG. 10 is a timing diagram for explaining a vertical synchronization signal command according to one embodiment of the present invention.

[0033] Fig. 11 is a timing diagram for explaining the generation of an input synchronization signal by FPWM and SCK division according to one embodiment of the present invention.

[0034] FIG. 12 is a timing diagram for explaining LED dimming with FPWM synchronization between driver integrated circuits according to one embodiment of the present invention.

[0035] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0036] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative and are not limited to the matters illustrated in the drawings. Like reference numerals refer to like components throughout the specification. In addition, in describing the present invention, if a detailed description of a related known technology is judged to unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When the terms “includes,” “has,” and “consists of” are used in this specification, other parts may be added unless “only” is used. When a component is expressed in the singular, it includes a case where the plural is included unless there is a specifically explicit description.

[0037] When interpreting a component, it is interpreted as including the error range even if there is no separate explicit description.

[0038] When describing a positional relationship, for example, when the positional relationship between two parts is described as 'on top of', 'upper part of', 'lower part of', 'next to', etc., one or more other parts may be located between the two parts, unless 'right away' or 'directly' is used.

[0039] When describing a temporal relationship, for example, when the temporal continuity is described as 'after', 'following', 'next to', 'before', etc., it can also include cases where it is not continuous, as long as 'right away' or 'directly' is not used.

[0040] The term "~unit" used herein refers to a unit that processes at least one function or operation, and may refer to, for example, a software or hardware component. The function provided by the "~unit" may be performed separately by multiple components or may be integrated with other additional components. The "~unit" of this specification may be implemented through a single circuit or multiple circuits, or through a single device or multiple devices.

[0041] The individual features of the various embodiments of this specification may be partially or wholly combined or combined with each other, and may be technically capable of various interconnections and operations, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0042] In this specification, the data transmission device and the data driving device are each implemented as a microcontroller unit. The data driving device is implemented as a driver integrated circuit.

[0043] In this embodiment, the LED driving circuit includes: a data transmission device that transmits a clock signal, a data signal, and an identification number for controlling an LED driving current; a bridge integrated circuit that includes a plurality of lanes (LANE) and receives the clock signal and the data signal; and a plurality of data driving devices that receive the clock signal and the data signal from the lanes and sequentially transmit them, wherein a first data driving device among the plurality of data driving devices receives the identification number, stores it as its own identification number, modulates the identification number, and transmits it to a neighboring data driving device.

[0044] In the present embodiment, a driving method of an LED driving circuit comprises a data transmission device, a bridge integrated circuit, and a plurality of data driving devices, the driving method comprising: a step in which first to Nth data driving devices sequentially register IDs; a step in which the first to Nth data driving devices sequentially write commands; a step in which the first to Nth data driving devices sequentially write registers; and a step in which the first to Nth data driving devices sequentially read registers, wherein a first data driving device among the plurality of data driving devices receives an identification number from the data transmission device, stores it as its own identification number, modulates the identification number, and transmits it to a neighboring data driving device.

[0045] Hereinafter, an LED driving circuit and its driving method according to the present embodiment will be described with reference to the attached drawings.

[0046] Figure 1 is a block diagram of an LED driving circuit according to one embodiment of the present invention.

[0047] Referring to FIG. 1, the LED driving circuit may include a micro controller unit (MCU) 100, a bridge integrated circuit (bridge integrated circuit) 200, and first to Nth (N is a natural number greater than or equal to 3) driver integrated circuits (311, 312, ..., 369).

[0048] The microcontroller unit (100) is equipped with a standard SPI (Serial Peripheral Interface) 1 and a standard SPI 2 internally. The standard SPI 1 is equipped with terminals of CSB (Chip Select Bar), 1, SCLK (Serial Clock) 1, SDI (Serial Data Input) 1, and SDO (Serial Data Output) 1, and the standard SPI 2 is equipped with terminals of CSB 2, SCLK 2, SDI 2, and SDO 2.

[0049] The microcontroller unit (100) generates a serial clock signal for controlling the LED driving current through SCLK 1 and SCLK 2, and generates a serial data input signal through SDI 1 and SDI 2. In addition, the microcontroller unit (100) receives a serial data output signal from the SPI control unit (210).

[0050] The bridge integrated circuit (200) includes a Serial Peripheral Interface (SPI) control unit (210) and a plurality of lanes (LANEs, 221, 222, 223, 224, 225, 226). The plurality of lanes include a first lane (221), a second lane (222), a third lane (223), a fourth lane (224), a fifth lane (225), and a sixth lane (226). The first lane (221) is connected to CSB 1, SCLK 1, SDI 1, and SDO 1 of the SPI control unit (210), and the second lane (222) is connected to CSB 2, SCLK 2, SDI 2, and SDO 2 of the SPI control unit (210). The third lane (223) is connected to CSB 3, SCLK 3, SDI 3, and SDO 3 of the SPI control unit (210), the fourth lane (224) is connected to CSB 4, SCLK 4, SDI 4, and SDO 4 of the SPI control unit (210), the fifth lane (225) is connected to CSB 5, SCLK 5, SDI 5, and SDO 5 of the SPI control unit (210), and the sixth lane (226) is connected to CSB 6, SCLK 6, SDI 6, and SDO 6 of the SPI control unit (210). The SPI control unit (210) transmits a CSB signal, a serial clock signal, and a serial data input signal to the first to sixth lanes (221, 222, 223, 224, 225, 226), respectively, and receives a serial data output signal from the first to sixth lanes (221, 222, 223, 224, 225, 226).

[0051] The bridge integrated circuit (200) receives a serial clock signal (SCLK 1, SCLK 2) and a serial data input signal (SDI 1, SDI 2) from the microcontroller unit (100).

[0052] The first to Nth driver integrated circuits (311, 312, ..., 369) sequentially receive the serial clock signal and the serial data input signal from the lanes (221, 222, 223, 224, 225, 226). That is, the serial clock signal and the serial data input signal are sequentially transmitted to the first driver integrated circuit (311, 321, 331, 341, 351, 361), the second driver integrated circuit (312, 322, 332, 342, 352, 362), ..., the Nth driver integrated circuit (319, 329, 339, 349, 359, 369). And, when the Nth driver integrated circuit (319, 329, ..., 369) receives a serial clock signal and a serial data input signal, it transmits a serial clock signal output and a serial data output signal to the first to sixth lanes (221, 222, 223, 224, 225, 226).

[0053] The first to Nth driver integrated circuits (311, 312, ..., 369) sequentially perform operations of registering an ID, writing a command, writing a register, and reading a register. That is, the operations of registering an ID, writing a command, and writing a register, and reading a register are transmitted in the following order: the first driver integrated circuit (311, 321, 331, 341, 351, 361), the second driver integrated circuit (312, 322, 332, 342, 352, 362), ..., the Nth driver integrated circuit (319, 329, 339, 349, 359, 369).

[0054] FIG. 2 is a schematic diagram showing a state in which an ID is assigned when registering an ID in the first to third driver integrated circuits according to one embodiment of the present invention, and FIG. 3 is a timing diagram for explaining a process in which the first to third driver integrated circuits according to one embodiment of the present invention register an ID.

[0055] Referring to FIG. 2, when there are three driver integrated circuits (D-IC #2, DC #1, D-IC #0), the ID of the first driver integrated circuit to which the serial clock signal (SCK) and the serial data input signal (SDI) are input is 2, the ID of the second driver integrated circuit is 1, and the ID of the third driver integrated circuit is 0.

[0056] Referring to FIG. 3, the process of registering an ID by the first to Nth driver integrated circuits is described. In this embodiment, for convenience, only the first to third driver integrated circuits (D-IC #2, DC #1, D-IC #0) are illustrated.

[0057] The microcontroller unit loads a number that is 1 less than the number of integrated circuits connected to the LANE of the bridge integrated circuit into the ID, and transmits a preamble signal (SIF_START=8'hFA), ID, and ID assignment command (CMD=000) to the first driver integrated circuit (D-IC #2). The reason for loading a number that is 1 less than the number of integrated circuits into the ID and transmitting it to the first driver integrated circuit (D-IC #2) is that the IDs sequentially decrease by 1 from the first driver integrated circuit (D-IC #2) to the Nth driver integrated circuit, so that the ID of the Nth driver integrated circuit must become 0. When the ID becomes 0, the Nth driver integrated circuit transmits an ID assignment completion signal to the microcontroller unit through the bridge integrated circuit.

[0058] When a preamble signal (SIF_START=8'hFA) and an ID assignment command (CMD=000) are input, the first driver integrated circuit (D-IC #2) registers the ID[4:0](=2) received from the microcontroller unit as its own ID, loads the number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal (SIF_START=8'hFA), ID, and ID assignment command (CMD=000) to the second driver integrated circuit (DC #1). However, when the preamble signal (SIF_START=8'hFA) and the ID assignment command (CMD=000) are input, the first driver integrated circuit (D-IC #2) first transmits a standby command (CMD=001) to the second driver integrated circuit (DC #1). By transmitting a wait command (CMD=001), the second driver integrated circuit (DC #1) waits until it receives an ID assignment command (CMD=000) from the first driver integrated circuit (D-IC #2).

[0059] When a preamble signal (SIF_START=8'hFA) and an ID assignment command (CMD=000) are input, the second driver integrated circuit (DC #1) registers the ID[4:0](=2) received from the first driver integrated circuit (D-IC #2) as its own ID, loads the number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal (SIF_START=8'hFA), ID, and ID assignment command to the third driver integrated circuit (D-IC #0). However, when the preamble signal (SIF_START=8'hFA) and the ID assignment command are input, the second driver integrated circuit (DC #1) first transmits a standby command (CMD=001) to the third driver integrated circuit (D-IC #0). By transmitting a wait command (CMD=001), the third driver integrated circuit (D-IC #0) waits until it receives an ID assignment command (CMD=000) from the second driver integrated circuit (DC #1).

[0060] The third driver integrated circuit (D-IC #0) can register the ID[4:0](=2) received from the second driver integrated circuit (DC #1) as its own ID when a preamble signal (SIF_START=8'hFA) and an ID assignment command (CMD=000) are input. If the registered ID[4:0](=2) of the third driver integrated circuit (D-IC #0) is 0, the third driver integrated circuit (D-IC #0) transmits an ID assignment completion signal (ID[4:0]="11111") to the microcontroller unit through the bridge integrated circuit.

[0061] In this way, when a preamble signal and an ID assignment command (CMD=000) are input, the Nth driver integrated circuit can register the ID received from the (N-1)th driver integrated circuit (not shown) as its own ID. If the registered ID of the Nth driver integrated circuit is 0, the Nth driver integrated circuit transmits an ID assignment completion signal (ID[4:0]="11111") to the microcontroller unit via the bridge integrated circuit.

[0062] FIG. 4 is a schematic diagram showing a state in which an ID is assigned when writing a command in the first and second driver integrated circuits according to one embodiment of the present invention, and FIG. 5 is a timing diagram for explaining a process in which the first and second driver integrated circuits according to one embodiment of the present invention write a command.

[0063] Referring to FIG. 4, when there are two driver integrated circuits (D-IC #1, D-IC #0), the ID of the first driver integrated circuit (D-IC #1) to which the serial clock signal (SCK) and the serial data input signal (SDI) are input is 1, and the ID of the second driver integrated circuit (D-IC #0) is 0.

[0064] Referring to FIG. 5, the process of the first to Nth driver integrated circuits writing commands is described. In this embodiment, for convenience, only the first to second driver integrated circuits (D-IC #1, D-IC #0) are illustrated.

[0065] The microcontroller unit sends a preamble signal (SIF_START=8'hF5), a command writing command (CMD=010) and an address (ADDR[4:0]) to the first driver integrated circuit (D-IC #1).

[0066] The first driver integrated circuit (D-IC #1) decodes the address (ADDR[4:0]) when a command writing command (CMD=010) is input, latches the command, and decrements its ID by 1 for each clock, and writes the latched command when the ID becomes 0.

[0067] The second driver integrated circuit (D-IC #0) decodes the address (ADDR[4:0]) when a command writing command (CMD=010) is input, latches the command, and decrements its ID by 1 for each clock, and writes the latched command when the ID becomes 0.

[0068] In this way, when a command writing command (CMD=010) is input, the Nth driver integrated circuit (not shown) decodes the address (ADDR[4:0]) to latch the command, and decrements its ID by 1 for each clock, and writes the latched command when the ID becomes 0.

[0069] The first to Nth driver integrated circuits can synchronize the start time of FPWM (Frequency Pulse Width Modulation) by resetting the vertical synchronization signal, or the start time of dimming can be synchronized by an input synchronization signal generated by FPWM (Frequency Pulse Width Modulation).

[0070] FIG. 6 is a timing diagram for explaining a process in which the first to Nth driver integrated circuits according to one embodiment of the present invention write a register.

[0071] Referring to FIG. 4, when there are two driver integrated circuits (D-IC #1, D-IC #0), the ID of the first driver integrated circuit (D-IC #1) to which the serial clock signal (SCK) and the serial data input signal (SDI) are input is 1, and the ID of the second driver integrated circuit (D-IC #0) is 0.

[0072] Referring to FIG. 6, the process of writing registers by the first to Nth driver integrated circuits is described. In this embodiment, for convenience, only the first to second drivers (DC #1, D-IC #0) are illustrated.

[0073] The microcontroller unit transmits a preamble signal (SIF_START=8'hF5), a register write command (CMD=011), an address (ADDR[4:0]) and N (the number of driver ICs) data [23:0] to the first driver IC (DC #1).

[0074] When the first driver integrated circuit (DC #1) receives the register write command (CMD=011) of the microcontroller unit, it receives the address (ADDR[4:0]), multiplies its own ID by the number of bits among the N pieces of input data, and then recognizes that the input data is its own data and updates it.

[0075] When the register writing command (CMD=011) of the first driver integrated circuit (DC #1) is input, the second driver integrated circuit (DC #0) receives the address (ADDR[4"0]), multiplies the number of bits by the number of bits obtained by subtracting 1 from its own ID among the input N pieces of data, and then recognizes that the input data is its own data and updates it.

[0076] In this way, when the register write command (CMD=011) of the (N-1) driver integrated circuit is input, the Nth driver integrated circuit (not shown) receives the address (ADDR[4"0]), multiplies the number of bits by the number of bits obtained by subtracting 1 from its own ID among the input N pieces of data, and then recognizes that the input data is its own data and updates it.

[0077] FIG. 7 is a timing diagram for explaining a process in which the first to Nth driver integrated circuits read a register according to one embodiment of the present invention.

[0078] Referring to FIG. 4, when there are two driver integrated circuits (D-IC #1, D-IC #0), the ID of the first driver integrated circuit (D-IC #1) to which the serial clock signal (SCK) and the serial data input signal (SDI) are input is 1, and the ID of the second driver integrated circuit (D-IC #0) is 0.

[0079] Referring to Fig. 7, the process of the first to Nth driver integrated circuits reading the register is described. In this embodiment, for convenience, only the first and second drivers (D-IC #2, DC #1) are illustrated.

[0080] The microcontroller unit sends a preamble signal (SIF_START=8'hF5), a register read command (CMD=111) and an address (ADDR[4:0]) to the first driver integrated circuit (D-IC #1).

[0081] When the first driver integrated circuit (D-IC #1) receives a register read command (CMD=111) of the microcontroller unit, it receives an address (ADDR[4:0]) and prepares data of the corresponding address (ADDR[4:0]), and decrements its own ID by 1 for each clock, and outputs the prepared data when the ID becomes 0.

[0082] When a register read command (CMD=111) of the first driver integrated circuit (D-IC #1) is input, the second driver integrated circuit (D-IC #0) receives an address (ADDR[4:0]) and prepares data of the corresponding address (ADDR[4:0]), and decrements its own ID by 1 for each clock, and outputs the prepared data when the ID becomes 0.

[0083] In this way, when the register read command (CMD=111) of the (N-1) driver IC is input, the Nth driver IC prepares the data of the corresponding address (ADDR[4:0]), decreases its ID by 1 for each clock, and outputs the prepared data when the ID becomes 0. Since the last driver IC has an ID of 0, it prepares the data of the address (ADDR[4:0]), and then outputs the prepared data immediately.

[0084] Figure 8 is a block diagram showing the logic of a driver integrated circuit according to one embodiment of the present invention.

[0085] Referring to FIG. 8, the SPI (Serial Peripheral Interface, 10) receives SCK (serial clock signal) and SDI (serial data input) and transmits them to the command register (20). The command register (20) transmits PWM_Div[7.0] to the clock divider (Clock Divider, 30), and the clock divider (30) divides the clock to adjust the FPWM frequency divided into SCK according to the value of PWM_DIV[7.0]. By adjusting the FPWM frequency divided into SCK, the number of required lanes (LAME) can be reduced compared to the conventional control method in which each driver integrated circuit is directly controlled in the microcontroller unit.

[0086] SPI (10) transmits a vertical synchronization signal command (VSYNC Command) to the input synchronization signal generator (I_VSYNC Generator, 40), and at this time, FPWM is input to the input synchronization signal generator (40). By SPI (10) transmitting a vertical synchronization signal command (VSYNC Command) to the input synchronization signal generator (I_VSYNC Generator, 40), the number of required lanes can be reduced compared to the conventional control method in which each driver integrated circuit is directly controlled in a microcontroller unit.

[0087] The input synchronization signal generator (40) transmits an input synchronization signal to the dimming data control unit (50), and FPWM is input to the dimming data control unit (500). Dimming data is transmitted and received between the SPI (10) and the dimming data control unit (50).

[0088] The dimming data control unit (50) transmits dimming data to the PWM (Pulse Width Modulation) timing control unit (60), and the PWM timing control unit (60) controls the PWM timing of connected channels 1 to N.

[0089] FIG. 9 is a timing diagram for explaining synchronization of a driver integrated circuit according to one embodiment of the present invention.

[0090] Referring to Figure 9, while the clock signal of SCK is generated, the vertical synchronization signal command is turned on (ON) for one cycle, and FPWM is turned off (OFF). At this time, the vertical synchronization signal is reset.

[0091] After the vertical synchronization signal is reset, the input synchronization signal (I_VSYNC) is turned on for one cycle of FPWM, and dimming begins from this time.

[0092] Through this process, the first to nth driver integrated circuits can synchronize the start points of Frequency Pulse Width Modulation (FPWM) by resetting the vertical synchronization signal. In addition, the first to nth driver integrated circuits can synchronize the start points of dimming by the input synchronization signal generated by the FPWM.

[0093] FIG. 10 is a timing diagram for explaining a vertical synchronization signal command according to one embodiment of the present invention.

[0094] Referring to Figure 10, N SCKs (serial clock signals) and N SDIs (serial data input signals) are arranged in a timing diagram.

[0095] D-IC #1 generates SCK #N and SDI #N, D-IC #2 generates SCK #N-1 and SDI #N-1, and in the same way, D-IC #N generates SCK #1 and SDI #1. SCK #1 to SCK #N form a clock at a regular cycle, and the vertical sync signal latch is performed when the vertical sync signal command is turned on.

[0096] The input stage of the vertical synchronization signal command protocol is as follows.

[0097] 1) D-IC (Driver Integrated Circuit) #1 START[7:0], CMD[2:0], ADDR[4:0] transmission

[0098] 2) SCK / SDI transmits signals simultaneously to D-IC #N while bypassing D-IC.

[0099] 3) Decoding CMD[2:0] and ADDR[4:0]

[0100] 4) For command protocol, the command latch is placed in the mode D-IC after clocking as many times as its ID #.

[0101] 5) Simultaneous generation of FPWM synchronization and I_VSYNC (input synchronization signal) between D-ICs by generating vertical synchronization signal commands

[0102] Fig. 11 is a timing diagram for explaining the generation of an input synchronization signal by FPWM and SCK division according to one embodiment of the present invention.

[0103] Referring to Figure 11, SCK (serial clock signal) #1 has a constant period, and FPWM_DIV 1, FPWM_DIV 2, and FPWM_DIV 3 have constant periods but different pulse widths.

[0104] When the vertical synchronization signal (VSYNC) command is on, the vertical synchronization signal (VSYNC) is latched. When the vertical synchronization signal is reset along with the latch, FPWM_DIV 1, FPWM_DIV 2, and FPWM_DIV 3 are turned off. When the vertical synchronization signal is released from reset, SCK, FPWM_DIV 1, FPWM_DIV 2, and FPWM_DIV 3 are all turned on.

[0105] After the vertical synchronization signal is reset, the input synchronization signal (i_VSYNC) is turned on with the pulse width size of FPWM_DIV 3 while FPWM_DIV 3 with the largest pulse width is turned off.

[0106] The steps for generating the FPWM clock and input synchronization signal (i_VSYNC) are as follows.

[0107] 1) Write PWM_DIV[7:0] register to all Daisy Chained D-ICs

[0108] 2) FPWM clock is generated after dividing SCK according to PWM_DIV[7:0]

[0109] 3) Write dimming data and send VSYNC command

[0110] 4) Synchronize FPWM start between D-ICs using VSYNC command

[0111] 5) Create i_VSYNC and start LED dimming

[0112] FIG. 12 is a timing diagram for explaining LED dimming with FPWM synchronization between driver integrated circuits according to one embodiment of the present invention.

[0113] Referring to FIG. 12, the vertical synchronization signal (VSYNC) command has pulses, and the interval between pulses has a frame rate of 60 Hz, 120 Hz, 144 Hz, ...

[0114] After each pulse generated by the vertical synchronization signal command, an input synchronization signal (i_VSYNC) is generated.

[0115] Driver integrated circuits (D-ICs) #1, #2, #3, #4, ..., #N enable dimming of the LED during the dimming time by FPWM_DIV(n).

[0116] In this way, smooth dimming control is possible by resolving synchronization issues between driver integrated circuits in a 2-wire interface.

[0117] While the embodiments of the present invention described above have been described with reference to the drawings to aid understanding, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true scope of technical protection of the present invention should be defined by the appended claims.

Claims

1. A data transmission device that transmits a clock signal, data signal, and identification number for controlling the LED driving current; A bridge integrated circuit including a plurality of lanes (LANE) and receiving the clock signal and the data signal; and An LED driving circuit comprising a plurality of data driving devices that receive the clock signal and the data signal from the above lane and sequentially transmit them, wherein a first data driving device among the plurality of data driving devices receives the identification number and stores it as its own identification number, modulates the identification number, and transmits it to a neighboring data driving device.

2. In paragraph 1, When the above multiple data drive devices register an ID, The above data transmission device loads a number that is 1 less than the number of integrated circuits connected to the LANE provided in the bridge integrated circuit into the ID, and transmits a preamble signal, the ID, and an ID assignment command to the first data driving device. When the preamble signal and the ID allocation command are input, the first data driving device registers the ID received from the data transmission device as its own ID, loads a number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal, the ID, and the ID allocation command to the second data driving device. When the preamble signal and the ID allocation command are input, the second data driving device registers the ID received from the first data driving device as its own ID, loads a number obtained by subtracting 1 from the registered ID into the ID, and transmits the preamble signal, the ID, and the ID allocation command to the third data driving device. The above Nth (N is a natural number greater than or equal to 3) data driving device is an LED driving circuit that registers the ID received from the (N-1)th data driving device as its own ID when the above preamble signal and ID allocation command are input.

3. In paragraph 2, An LED driving circuit further comprising a step of transmitting an ID allocation completion signal to the data transmission device if the registered ID of the Nth data driving device is 0.

4. In paragraph 2, An LED driving circuit, wherein the first data driving device further includes a step of transmitting a standby command to the second data driving device when the preamble signal and the ID assignment command are input.

5. In paragraph 2, An LED driving circuit further comprising a step of transmitting a standby command to the third data driving device when the second data driving device inputs the preamble signal and the ID assignment command.

6. In paragraph 2, When the first to Nth data driving devices write a command, The above data transmission device transmits the preamble signal, the command writing command and the address to the first data driving device, The above first data driving device decodes the address when the command writing command is input, latches the command, decreases its ID by 1 for each clock, and writes the latched command when the ID becomes 0. The second data driving device decodes the address when the command writing command is input, latches the command, decreases its ID by 1 for each clock, and writes the latched command when the ID becomes 0. An LED driving circuit, comprising a step of the Nth data driving device decoding the address when the command writing command is input, latching the command, and decreasing its own ID by 1 for each clock and writing the latched command when the ID becomes 0.

7. In paragraph 6, The above first to Nth data driving devices are LED driving circuits in which the vertical synchronization signal is reset to synchronize the start point of FPWM (Frequency Pulse Width Modulation).

8. In paragraph 2, The above first to nth data driving devices are LED driving circuits in which the dimming start point is synchronized by an input synchronization signal generated by FPWM (Frequency Pulse Width Modulation).

9. In paragraph 2, When the first to Nth data driving devices write a register, The above data transmission device transmits the preamble signal, the register write command, the address and N data to the first data driving device, When the register writing command of the data transmission device is input, the first data driving device receives the address, multiplies its own ID by the number of bits among the input N pieces of data, and then recognizes that the input data is its own data and updates it. When the register writing command of the first data driving device is input, the second data driving device receives the address, multiplies the number of bits by the number of N pieces of input data obtained by subtracting 1 from its own ID, and then recognizes that the input data is its own data and updates it. An LED driving circuit in which, when a register writing command of the (N-1)th data driving device is input, the Nth data driving device receives the address, multiplies the number of bits by the number of N pieces of input data obtained by subtracting 1 from its own ID, and then recognizes that the input data is its own data and updates it.

10. In paragraph 2, When the first to Nth data driving devices read the register, The above data transmission device transmits the preamble signal, register read command and address to the first data driving device, When the above first data driving device receives a register read command from the above data transmission device, it receives the address and prepares data of the corresponding address, and decrements its ID by 1 for each clock and outputs the prepared data when the ID becomes 0. The second data driving device receives the address when a register read command of the data driving device is input, prepares data of the corresponding address, decreases its ID by 1 for each clock, and outputs the prepared data when the ID becomes 0. An LED driving circuit, comprising a step of preparing data of a corresponding address when a register read command of an (N-1)th data driving device is input, and decrementing its own ID by 1 for each clock and outputting the prepared data when the ID becomes 0.

11. A method for driving an LED driving circuit having a data transmission device, a bridge integrated circuit, and a plurality of data driving devices, A step in which the first to Nth (N is a natural number greater than or equal to 3) data driving devices sequentially register their IDs; A step in which the first to Nth data driving devices sequentially write commands; The step of sequentially writing registers by the first to Nth data driving devices; and A method for driving an LED driving circuit, comprising a step in which the first to Nth data driving devices sequentially read registers, wherein the first data driving device among the plurality of data driving devices receives an identification number from the data transmission device, stores it as its own identification number, modulates the identification number, and transmits it to a neighboring data driving device.

12. In paragraph 11, The step of registering the ID of the first to Nth data driving devices is as follows: A step of the data transmission device loading a number that is 1 less than the number of integrated circuits connected to the LANE provided in the bridge integrated circuit into the ID, and transmitting a preamble signal, the ID, and an ID allocation command to the first data driving device; A step for the first data driving device to register an ID received from the data transmission device as its own ID when the preamble signal and the ID allocation command are input; A step of loading a number obtained by subtracting 1 from the registered ID into the ID, and transmitting the preamble signal, the ID, and the ID allocation command to the second data driving device; A step for the second data driving device to register the ID received from the first data driving device as its own ID when the preamble signal and ID allocation command are input; The step of the second data driving device loading a number obtained by subtracting 1 from the registered ID into the ID and transmitting the preamble signal, the ID, and the ID allocation command to the third data driving device; and A step in which the above Nth data driving device registers the ID received from the (N-1)th data driving device as its own ID when the above preamble signal and ID allocation command are input. A method for driving an LED driving circuit, comprising:

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