Gold-silver alloy bump, and preparation method therefor and application thereof

Abstract

The present invention relates to the technical field of semiconductor flip chip packaging. Disclosed are a gold-silver alloy bump, and a preparation method therefor and an application thereof. The gold-silver alloy bump consists of two gold-silver alloy layers, which are respectively a connecting layer and a protective layer; the content of gold in the connecting layer is 20-50 wt%; the thickness of the protective layer is much smaller than that of the connecting layer, and the content of gold in the protective layer is 60 wt% or above. The gold-silver alloy bump provided by the present invention has hardness, roughness and sulfurization resistance comparable to those of a pure gold bump, can meet technical requirements of flip chip packaging, and can greatly reduce cost. According to the preparation method for the gold-silver alloy bump provided by the present invention, the gold-silver alloy bump having a double-layer structure in the present application can be obtained by using the same equipment and plating solution and only changing the current density; the preparation process is simplified, the production efficiency is improved, and the production cost is reduced.

Description

A gold-silver alloy bump and its preparation method and application Technical Field

[0001] The invention belongs to the technical field of semiconductor flip chip packaging and relates to a gold-silver alloy bump and a preparation method and application thereof. Background Art

[0002] Flip-chip packaging technology uses bumps on the chip to directly interconnect components face-down to a substrate, carrier, or circuit board. Flip-chip eliminates redundant packaging steps while offering advantages such as reduced size, high-frequency operation, low parasitics, and high I / O density. Flip-chip packaging is suitable for a variety of chips, including LCDs, image sensors, memory, microprocessors, and microwave radio frequency (RF) chips. Specific applications include mobile phones, televisions, computers, tablets, and cameras.

[0003] To ensure chip performance, the bumps used in flip-chips are usually made of pure gold due to its excellent properties. Silver, another precious metal, also has good electrical and thermal conductivity and is much cheaper than gold. However, using pure silver to make bumps can lead to problems such as silver needles, silver migration, and easy oxidation and sulfidation, which cannot meet chip performance requirements. If silver can partially replace gold, the cost of gold bumps can be greatly reduced. In addition, gold-silver alloy bumps have lower resistance and higher thermal conductivity than pure gold bumps, which helps improve the chip's heat dissipation performance and increase electrical interconnection density. However, using electroplating to make gold-silver alloy bumps to replace gold bumps presents the following technical problems that need to be solved.

[0004] First, the hardness of gold-silver alloy bumps after annealing must match that of pure gold bumps. In chip-on-film (COF) packaging, because the bumps are directly pressed together with the copper traces on the polyimide film through the solder layer, the bump hardness cannot be too high, generally requiring 45-75HV after annealing, otherwise the bumps may cause the conductive traces to crack. In chip-on-glass (COG) packaging, the bumps connect to the copper traces on the glass substrate through an anisotropic conductive film. The bump hardness must be sufficient to facilitate the pressing of the anisotropic conductive film, generally requiring a bump hardness between 75-105HV. Second, compared to gold, the surface of silver easily sulfides in air. Once sulfides form, connectivity with tin solder or anisotropic conductive film is poor, potentially affecting the electrical connection between the silver and copper traces. Therefore, the anti-sulfurization performance of gold-silver alloy bumps needs to be addressed. Finally, the surface roughness of the bump after electroplating cannot be too high. Generally, the roughness Ra is required to be less than 100nm. If it is too high, it may affect the electrical interconnection with the copper circuit.

[0005] Patent publication number CN104099653B discloses a semiconductor structure and its manufacturing method, specifically a silver alloy electroplating solution for preparing silver alloy bumps. The solution contains potassium silver cyanide and / or potassium gold cyanide and potassium palladium cyanide. The pH of the solution is controlled within the range of 6 to 8, and the solution also contains a small amount of oxalate. As is well known, silver ions are photosensitive. Without a silver ion stabilizer, the plating solution will quickly precipitate silver metal, making the solution unstable.

[0006] This invention patent also discloses three structures that use silver alloy bumps to replace pure gold bumps. The first is to directly use the silver alloy bump body to replace the gold bump. Since the silver alloy or part of the surface has no anti-oxidation or anti-sulfurization protection, reliability problems may arise due to the oxidation or sulfidation of silver in the future. In particular, the patent emphasizes that the silver alloy bump is mainly silver and the gold atomic ratio should be controlled below 25%. The second is a laminated structure. First, the silver alloy bump body is prepared, and then a gold bump structure of a certain thickness is prepared on the top surface of the silver alloy bump. To prepare the metal on the top surface, such as pure gold, a second electroplating solution and its device are required, which increases the process complexity and equipment cost. The third is an enclosing structure. First, the silver alloy bump is prepared, and then the metal enclosing layer is formed on the top and side of the silver alloy bump by electroplating or chemical plating. Compared with pure gold, silver alloy is easily oxidized or sulfided, so the first or second structure is used. Although the third structure solves the problem of silver alloy oxidation or sulfidation due to the gold surrounding structure, this process requires two photoresist exposure and development, and two different electroplating solutions, which increases the complexity and cost of the process.

[0007] Patent publication number CN101225536B discloses a gold-silver alloy electroplating solution composed of potassium gold cyanide with a gold content of 1-30 g / L, potassium silver cyanide with a silver content of 1-200 ppm, 30-100 g / L of potassium pyrophosphate, 20-50 g / L of boric acid, and 0.05-150 g / L of ethylenediamine, ethylenediaminetetraacetic acid, diethylenetriamine, triethylenetetramine, tetraethylenepentamine, or pentaethylenehexamine. The electroplated gold-silver alloy contains 0.3-2.0 wt% silver, and the hardness of the gold-silver alloy is 150-200 HV. This patent is primarily targeted at connector applications and is not suitable for flip-chip bump production.

[0008] The invention patent with announcement number CH412508 discloses an electroplating solution for preparing gold-silver alloy. In addition to potassium gold cyanide and potassium silver cyanide, the plating solution contains 60g / L of potassium cyanide. A large amount of free cyanide may cause the photoresist to penetrate or swell, destroying the structure of the bump. At the same time, the presence of a large amount of free cyanide is not conducive to environmental protection. Technical issues

[0009] The primary objective of this invention is to provide a gold-silver alloy bump. Through meticulous research, the inventors have devised a gold-silver alloy bump structure, optimized the gold-silver ratio, and controlled the grain size of the gold-silver alloy. The resulting gold-silver alloy bump retains the excellent electrical and thermal conductivity of the gold-silver alloy while meeting the technical requirements for flip-chip packaging, including hardness, sulfurization resistance, and surface roughness. This allows it to replace pure gold bumps and significantly reduce bump costs. This objective is achieved through the following specific technical solutions. Technical Solutions

[0010] A gold-silver alloy bump characterized by comprising two gold-silver alloy layers: a connection layer and a protective layer. The connection layer has a gold content of 20-50% by weight, while the protective layer has a gold content of at least 60% by weight. The overall shape and size of the gold-silver alloy bump are consistent with existing pure gold bumps used in flip-chip packaging.

[0011] Furthermore, the average grain size of the gold-silver alloy layer is 0.10-0.30 μm. The grain size of the gold-silver alloy layer can be measured using an EBSD (Electron Back Scattered Diffraction) method or other feasible methods.

[0012] Through extensive research, the inventors discovered that the annealed hardness and roughness of gold-silver alloy bumps are closely related to the gold content and grain size of the gold-silver alloy. When the gold content is 20-50wt% and the average grain size is 0.10-0.30μm, the annealed hardness of the gold-silver alloy bumps is between 45-105HV, and the coating roughness Ra is less than 100nm, which can meet the bump hardness and roughness requirements of flip-chip packaging. However, the anti-sulfurization performance of the gold-silver alloy bumps requires a gold content of at least 60wt% in the gold-silver alloy to meet the requirements of flip-chip packaging. To this end, the inventors have developed the above-mentioned gold-silver alloy bumps composed of two layers of gold-silver alloy. The connecting layer is connected to the substrate, carrier, or circuit board, and its specific gold content and grain size ensure that the bump hardness and roughness meet the requirements. The protective layer increases the gold content to at least 60wt%, ensuring that the overall anti-sulfurization performance of the bump meets the requirements. At the same time, the thickness of the protective layer is much smaller than the connecting layer, which has little effect on the overall hardness and roughness.

[0013] Furthermore, the gold content in the gold-silver alloy of the connection layer is 20-40 wt %, so that its hardness is 45-75 HV, meeting the COF packaging requirements.

[0014] Furthermore, the gold content in the gold-silver alloy of the connection layer is 30-50 wt %, so that its hardness is 75-105 HV, meeting the COG packaging requirements.

[0015] Furthermore, the thickness of the connecting layer is 7-20 μm, and the thickness of the protective layer is 10-500 nm.

[0016] Another object of the present invention is to provide a method for preparing a gold-silver alloy bump. By optimizing the composition of the electroplating solution, different gold contents can be obtained using the same electroplating solution by simply varying the current density. Thus, the double-layer gold-silver alloy bump of the present invention can be produced using the same equipment without changing the plating solution, simplifying the preparation process, improving production efficiency, and reducing production costs. This object is achieved through the following specific technical solutions.

[0017] A method for preparing a gold-silver alloy bump, characterized by comprising the following steps:

[0018] S1. Pre-treating the chip to be packaged by preparing an electroplating solution, wherein the electroplating solution comprises the following components: potassium aurous cyanide (molecular formula KAu(CN)2), potassium silver cyanide (molecular formula KAg(CN)2), potassium pyrophosphate and hydantoin, with a pH value of 8-10;

[0019] S2: placing the chip to be packaged in the electroplating solution of step S1, and using low current density electroplating to prepare a connection layer of gold-silver alloy bumps;

[0020] S3 uses the same electroplating solution and equipment, adopting high current density electroplating to prepare the protective layer of gold-silver alloy bumps;

[0021] S4 removes auxiliary materials of the chip to be packaged;

[0022] S5 is to perform annealing treatment on the gold-silver alloy bumps.

[0023] Furthermore, the low current density in step S2 is 0.3-0.6A / dm 2 (ASD), the plating time is 30-60min.

[0024] Furthermore, the high current density in step S3 is 1.1-1.3 ASD, and the electroplating time is 20-40 s.

[0025] Furthermore, in step S4, removing the auxiliary materials from the chip to be packaged includes using a degumming solution to remove the photoresist from the chip to be packaged, using an etching solution to remove the gold seed layer on the silicon substrate of the chip to be packaged, and removing the titanium tungsten (TiW) layer on the silicon substrate of the chip to be packaged. The degumming solution is N-methylpyrrolidone, the etching solution is a thiourea solution, and the substance used to remove the titanium tungsten layer is an H2O2 solution. Compared to the commonly used iodine / potassium iodide etching solution, the thiourea solution removes the gold seed layer without etching the gold-silver alloy bumps.

[0026] Furthermore, the annealing temperature in step S5 is 270-300° C., and the annealing time is 5-60 min.

[0027] Another object of the present invention is to provide an application of the gold-silver alloy bump, wherein the gold-silver alloy bump is used for flip-chip packaging.

[0028] Furthermore, the flip chip includes a liquid crystal display, an image sensor, a memory, a microprocessor or a microwave radio frequency chip.

[0029] Another object of the present invention is to provide a gold-silver alloy bump obtained by the preparation method provided by the present invention, and an application of the gold-silver alloy bump, wherein the gold-silver alloy bump is used for flip-chip packaging.

[0030] Furthermore, the flip chip includes a liquid crystal display, an image sensor, a memory, a microprocessor or a microwave radio frequency chip. Beneficial effects

[0031] The present invention has the following beneficial technical effects: The gold-silver alloy bumps provided by the present invention have hardness, roughness, and sulfurization resistance comparable to pure gold bumps, meeting the technical requirements of flip-chip packaging while significantly reducing costs. The gold-silver alloy bump preparation method provided by the present invention can produce the double-layer gold-silver alloy bumps of the present invention using the same equipment and plating solution, simply by changing the circuit density. This simplifies the preparation process, improves production efficiency, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a graph showing the relationship between the gold content and annealing hardness in a gold-silver alloy.

[0033] FIG2 is a graph showing the relationship between the gold content in the gold-silver alloy and the roughness of the coating.

[0034] Figures 3 and 4 are photographs showing the compatibility of plating solution and photoresist.

[0035] FIG5 and FIG6 are scanning electron microscope photos of the gold-silver alloy bump after removing the photoresist.

[0036] FIG. 7 is a diagram showing the crystal structure analysis results of EDSB in Example 1 and Example 2.

[0037] FIG8 is a graph showing the anti-sulfurization performance of gold-silver alloys with different gold contents.

[0038] FIG9 is a schematic flow chart of a method for preparing a gold-silver alloy bump according to the present invention. Modes for Carrying Out the Invention

[0039] The following is a clear and complete description of the technical solution of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0040] In the description of the present invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, quantity, or position.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] The inventors systematically studied the relationship between the gold content and annealing hardness in the gold-silver alloy. As shown in Figure 1, it can be seen that when the gold content in the gold-silver alloy is 20-50wt%, the annealing hardness is in the range of 45-105HV, which meets the requirements of flip-chip packaging for bump hardness.

[0043] The inventors systematically studied the relationship between the gold content and roughness in the gold-silver alloy. As shown in Figure 2, it can be seen that when the gold content in the gold-silver alloy is 20-50wt%, the roughness is below 100nm, which meets the roughness requirements of flip-chip packaging.

[0044] As shown in Figures 1 and 2, not all gold-silver alloy ratios meet the hardness and roughness requirements for flip-chip packaging. With a gold content above 50% by weight, the hardness of the annealed gold-silver alloy may exceed 105 HV. At the same time, when the gold content is less than 20% or greater than 50% by weight, the roughness Ra of the coating exceeds 100 nm. Therefore, the gold content in the gold-silver alloy bumps that meet the requirements should be between 20% and 50% by weight. Figure 1 further divides the operating ranges for gold-silver alloys into low hardness (45-75 HV) and high hardness (75-105 HV), used for COF and COG packaging, respectively. It can be seen that the gold content for low-hardness gold-silver alloy electroplating should be between 20% and 40% by weight, while the gold content for high-hardness gold-silver alloy electroplating should be between 30% and 50% by weight. Because the annealing hardness is affected by the annealing temperature and annealing time, for gold-silver alloy bumps with a gold content between 30% and 40%, the annealing hardness can be adjusted through the annealing conditions to meet the COF or COG packaging requirements.

[0045] The process for preparing a gold-silver alloy bump according to the present invention is shown in Figure 9. The structure of the chip to be packaged includes a silicon substrate transistor layer 101, an aluminum electrode 102, a passivation layer 103, a TiW adhesion layer 104, a gold seed layer 105, and a photoresist 106. The chip to be packaged is placed in an electroplating solution and subjected to a first low-current-density, long-term electroplating process to form a connecting layer, a gold-silver alloy layer 107. A second high-current-density, short-term electroplating process then occurs to form a protective layer, a gold-silver alloy layer 108. The electroplating solution contains the following components and concentrations: 6-10 g / L potassium auronitrile cyanide, 4-7 g / L potassium silver cyanide, 50-70 g / L potassium pyrophosphate, 20-40 g / L hydantoin, and a pH of 8-10. The connecting layer, gold-silver alloy layer 107, has a thickness of 7-20 μm and a gold content of 20-50 wt%. The protective layer, gold-silver alloy layer 108, has a thickness of 10-500 nm and a gold content of at least 60 wt%. EBSD analysis revealed an average equivalent circular diameter of 0.10-0.30 μm for the grains. After electroplating, the photoresist 106 of the chip to be packaged is removed using an NMP stripper. The gold seed layer 105 on the silicon substrate of the chip to be packaged is removed using an etchant. Finally, an H₂O₂ solution is used to remove the TiW layer 104 on the silicon substrate of the chip to be packaged. Finally, the gold-silver alloy bumps are annealed at a temperature of 270-300°C for 5-60 minutes. Example 1

[0046] The method for preparing a gold-silver alloy bump with low hardness includes the following steps.

[0047] S1 is to pre-treat the chip to be packaged, and prepare the electroplating solution, including the following components: potassium gold cyanide 6g / L, potassium silver cyanide 7g / L, potassium pyrophosphate 60g / L, hydantoin 30g / L, pH value 9, temperature 30℃.

[0048] In step S2, the chip to be packaged is placed in the electroplating solution from step S1 and electroplated using a low current density to form a gold-silver alloy connection layer for the gold-silver alloy bumps. The current density is 0.4 ASD, the electroplating time is 45 minutes, the plating height is 10 μm, the gold content is 30 wt%, and the roughness Ra is 65 nm.

[0049] S3 used the same electroplating solution and equipment, employing high current density electroplating to create the protective layer of gold-silver alloy for the gold-silver alloy bumps. The current density was 1.2 ASD, and the plating time was 30 seconds. This layer of gold and silver was approximately 200nm thick, with a gold content of 67wt%, and an overall roughness of 74nm for the gold-silver alloy bumps.

[0050] S4 uses a degumming solution to remove the photoresist of the chip to be packaged;

[0051] S5 uses an etching solution to remove the gold seed layer on the silicon substrate of the chip to be packaged;

[0052] S6 removes the TiW layer on the silicon substrate of the chip to be packaged;

[0053] In S7, the gold-silver alloy bump is annealed at a temperature of 290° C. for 30 min. After annealing, the hardness of the gold-silver alloy bump is 65 HV.

[0054] The pH of the gold bump plating solution used for pure gold is generally maintained between 5 and 7, while the gold-silver alloy plating solution used in the present invention is maintained between 8 and 10. A high pH in the photoresist can cause photoresist swelling or reduce the bonding strength between the photoresist and the substrate, resulting in seepage plating, which can affect circuit manufacturing accuracy. As shown in Figures 3 (magnification 200) and 4 (magnification 500), the width of the gold-silver alloy bump is 20μm, the width of the photoresist (JSRTHB-126N) between the bumps is 8μm, and the plating height is 10μm. No seepage plating or photoresist swelling was observed using the gold-silver alloy plating solution of the present invention. Figures 5 and 6 show gold-silver alloy bumps prepared using the present invention, after the photoresist was removed using NMP. The surface of the gold-silver alloy bump is smooth and uniformly crystallized, with no coarse crystals that would cause excessive local roughness. Example 2

[0055] The method for preparing a gold-silver alloy bump with high hardness includes the following steps.

[0056] S1 is to pre-treat the chip to be packaged, and prepare the electroplating solution, including the following components: 10g / L potassium cyanide gold, 4g / L potassium silver cyanide, 60g / L potassium pyrophosphate, 30g / L hydantoin, pH 9, temperature 30℃.

[0057] In step S2, the chip to be packaged is placed in the electroplating solution from step S1 and electroplated using a low current density to form a connection layer for the gold-silver alloy bumps. The current density is 0.5 ASD, the plating time is 36 minutes, the plating height is 10 μm, the gold content is 42 wt%, and the roughness Ra is 71 nm.

[0058] S3 used the same electroplating solution and equipment, employing high current density electroplating to create a protective layer for the gold-silver alloy bumps. The current density was 1.2 ASD, and the plating time was 20 seconds. The thickness of this layer of gold and silver was approximately 150nm, with a gold content of 72wt%. The overall roughness of the gold-silver alloy bumps was 82nm.

[0059] S4 uses a degumming solution to remove the photoresist of the chip to be packaged;

[0060] S5 uses an etching solution to remove the gold seed layer on the silicon substrate of the chip to be packaged;

[0061] S6 removes the TiW layer on the silicon substrate of the chip to be packaged;

[0062] In S7, the gold-silver alloy bump is annealed at a temperature of 290° C. for 30 min. After annealing, the hardness of the gold-silver alloy bump is 95 HV. Example 3

[0063] The grain sizes of the gold-silver alloy bumps obtained in Example 1 and Example 2 were detected.

[0064] EBSD was used to analyze the microstructure of the gold-silver alloy coatings on the gold-silver alloy bumps obtained in Examples 1 and 2. Figure 7 shows the EDSB crystal structure analysis: a1 and a2 are the IPF maps and grain distribution maps of Example 1 before annealing, b1 and b2 are the IPF maps and grain distribution maps after annealing. c1 and c2 are the IPF maps and grain distribution maps of Example 2 before annealing, and d1 and d2 are the IPF maps and grain distribution maps after annealing.

[0065] The gold-silver alloy of Example 1, before annealing, had a median equivalent circular diameter of 0.23 μm, corresponding to an equivalent circular diameter of 0.14-0.69 μm for ±2 standard deviations (2.5%-97.5% of the data range). After annealing, the median equivalent circular diameter of the grains was 0.28 μm, corresponding to an equivalent circular diameter of 0.14-0.89 μm for ±2 standard deviations. The gold-silver alloy of Example 2, before annealing, had a median equivalent circular diameter of 0.18 μm, corresponding to an equivalent circular diameter of 0.14-0.34 μm for ±2 standard deviations. After annealing, the median equivalent circular diameter of the grains was 0.27 μm, corresponding to an equivalent circular diameter of 0.14-1.75 μm for ±2 standard deviations. From the above data, it can be seen that increasing the gold content in the coating reduces the overall size of the grains, which is consistent with the conclusion that increasing the gold content in the coating increases the hardness of the coating. Comparing the grain sizes before and after annealing, the larger grains account for a larger proportion in the coating after annealing. Compared with patent CN104099653B, the average diameter of the grains is 0.7-0.8μm, and the standard deviation is 0.2-0.4μm. It can be seen that the method of the present invention can produce gold-silver alloys with smaller grains and more uniform distribution. In addition, from the grain distribution described in CN104099653B (Figure 2), it can be seen that larger grains account for a larger proportion, while in the present invention, smaller grains account for a larger proportion, which is a significant difference between the two. Example 4

[0066] The anti-sulfurization and anti-oxidation properties of gold-silver alloy bumps with different gold contents were tested.

[0067] Compared to pure gold, silver coatings lack the ability to resist sulfidation or oxidation. Therefore, the sulfidation and oxidation resistance of gold-silver alloys with varying gold contents was evaluated. The electroplated gold-silver alloys were placed in a 1% sodium sulfide solution for 30 minutes, then rinsed and air-dried. The color of the samples before and after immersion was compared to assess the coating's sulfidation resistance. In the same 1% sodium sulfide solution, the electroplated gold-silver alloys were placed for 1 minute, then exposed to air for 10 minutes without rinsing. The samples were then rinsed and air-dried. The oxidation resistance of the coatings was assessed by comparing the colors before and after immersion. As shown in Figure 8, pure silver coatings exhibit poor resistance to both oxidation and sulfidation, with a significant color change after immersion in the NaS solution. Gold-silver coatings with gold contents above 30wt% exhibit significantly improved sulfidation resistance, with little color change after immersion in the NaS solution for 30 minutes. However, when it comes to the plating solution's antioxidant capacity, after soaking in NaS solution for one minute and then oxidizing in air for 10 minutes, the coating still shows some discoloration for coatings with a gold content below 60%, indicating that the antioxidant capacity is still insufficient. For coatings with a gold content above 60%, the color is very close to that of pure gold, and the coating's antioxidant and sulfidation resistance have been significantly improved.

[0068] Although the embodiments of the present invention have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from the principles and intent of the present invention. The scope of protection of the present invention is defined by the claims and their equivalents.

Claims

1. A gold-silver alloy bump, characterized in that, The gold-silver alloy bump is composed of two gold-silver alloy layers, namely a connection layer and a protection layer; the gold content in the connection layer is 20-50 wt%; the gold content in the protection layer is more than 60 wt%.

2. The gold-silver alloy bump according to claim 1, characterized in that, The average grain size of the grains in the gold-silver alloy layer is 0.10-0.30 μm.

3. The gold-silver alloy bump according to claim 1 or 2, characterized in that, The gold content in the connection layer is 20-40 wt%.

4. The gold-silver alloy bump according to claim 1 or 2, characterized in that The gold content in the connection layer is 30-50 wt%.

5. The gold-silver alloy bump according to claim 1 or 2, characterized in that, The thickness of the connection layer is 7-20 μm, and the thickness of the protection layer is 10-500 nm.

6. A method for preparing a gold-silver alloy bump, characterized in that, It includes the following steps: S1 Pretreat the chip to be encapsulated and prepare the electroplating solution. The electroplating solution includes the following components: potassium gold cyanide, potassium silver cyanide, potassium pyrophosphate, and hydantoin, with a pH value of 8-10; S2 Place the chip to be encapsulated in the electroplating solution of step S1 and perform electroplating with a low current density to prepare the connection layer of the gold-silver alloy bump; S3 Use the same electroplating solution and equipment and perform electroplating with a high current density to prepare the protection layer of the gold-silver alloy bump; S4 Remove the auxiliary materials of the chip to be encapsulated; S5 Anneal the gold-silver alloy bump.

7. The preparation method according to claim 6, characterized in that, The low current density described in step S2 is 0.3 - 0.6 A / dm 2 , and the electroplating time is 30 - 60 min.

8. The preparation method according to claim 6, characterized in that, The high current density described in step S3 is 1.1 - 1.3 A / dm 2 , and the electroplating time is 20 - 40 s.

9. The preparation method according to claim 6, characterized in that, In step S4, removing the auxiliary materials of the chip to be encapsulated includes using a de-bonding solution to remove the photoresist of the chip to be encapsulated, using an etching solution to remove the gold seed layer on the silicon substrate of the chip to be encapsulated, and removing the titanium-tungsten layer on the silicon substrate of the chip to be encapsulated; the de-bonding solution is N-methylpyrrolidone, the etching solution is a thiourea solution, and the substance for removing the titanium-tungsten layer is an H2O2 solution.

10. The preparation method according to claim 6, characterized in that, The annealing temperature in step S5 is 270-300 °C, and the annealing time is 5-60 min.

11. The application of the gold-silver alloy bump according to any one of claims 1-5, wherein the gold-silver alloy bump is used for flip-chip packaging.

12. The application according to claim 11, wherein The flip-chip includes a liquid crystal display, an image sensor, a memory, a microprocessor, or a microwave radio frequency chip.

13. The gold-silver alloy bump prepared by the preparation method according to any one of claims 6-10.

14. The application of the gold-silver alloy bump according to claim 13, characterized in that, The gold-silver alloy bump is used for flip-chip packaging.

15. The application according to claim 14, wherein The flip-chip includes a liquid crystal display, an image sensor, a memory, a microprocessor, or a microwave radio frequency chip.

Images