Low-noise amplifier and radio frequency power amplifier module

Abstract

The present invention provides a low-noise amplifier and a radio frequency power amplifier module. The low-noise amplifier comprises a signal input end, an input matching circuit, a first resistor, a frequency offset compensation circuit, a first field-effect transistor, a second field-effect transistor, an input attenuation circuit, a third field-effect transistor, a source attenuation circuit, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, an attenuation branch, a seventh field-effect transistor, a second resistor, a first capacitor, an output matching circuit, an output attenuation circuit, and a signal output end. According to the low-noise amplifier of the present invention, the gain, the noise coefficient, the IIP3 index and the current of the low-noise amplifier can be kept in balance, thereby improving the overall performance of the low-noise amplifier.

Description

Low noise amplifier and RF power amplifier module Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a low noise amplifier and a radio frequency power amplifier module. Background Art

[0002] With the rapid development of wireless communication technology, electronic devices with wireless communication functions such as mobile phones and tablets have become necessities in people's lives. The low-noise amplifier in the receiver is a key link in electronic devices, and its performance directly affects the user experience of the electronic devices.

[0003] The performance of a low-noise amplifier mainly includes gain, noise figure, and IIP3. In the application of electronic devices, as the strength of the input signal changes, the gain, noise figure, and IIP3 indicators required by the low-noise amplifier are also different. Generally speaking, as the input signal increases, the required gain is lower, the IIP3 indicator requirement is higher, and the noise figure needs to be appropriately deteriorated. In addition, in order to meet the increasing needs, power consumption has also become a performance indicator of the low-noise amplifier. At low gain, the noise figure, IIP3 indicator, and current need to maintain a balance, that is, each indicator is kept within its corresponding amount to improve the overall performance of the low-noise amplifier. However, the low-noise amplifier structure in the related art cannot maintain a balance between its gain, noise figure, IIP3 indicator, and current, thereby greatly reducing its overall performance.

[0004] Therefore, a new low noise amplifier is urgently needed to solve the above problems. Summary of the Invention

[0005] In response to the above shortcomings of the existing technology, the present invention proposes a low-noise amplifier and a radio frequency power amplifier module to solve the problem that the low-noise amplifier structure in the related art cannot maintain a balance between its gain, noise figure, IIP3 index and current, thereby reducing its overall performance.

[0006] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a low-noise amplifier, comprising a signal input terminal, an input matching circuit, a first resistor, a frequency offset compensation circuit, a first field-effect transistor, a second field-effect transistor, an input attenuation circuit, a third field-effect transistor, a source attenuation circuit, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, an attenuation branch, a seventh field-effect transistor, a second resistor, a first capacitor, an output matching circuit, an output attenuation circuit, and a signal output terminal;

[0008] The input end of the input matching circuit is connected to the signal input end;

[0009] A first end of the first resistor is connected to the output end of the input matching circuit, and a second end of the first resistor is used to connect to a first bias voltage;

[0010] The input end of the frequency offset compensation circuit, the gate of the first field effect transistor, the gate of the second field effect transistor, and the input end of the input attenuation circuit are respectively connected to the output end of the input matching circuit; the frequency offset compensation circuit is used to process the received signal to compensate for the frequency offset, so that the signal can be correctly demodulated and processed;

[0011] The gate of the third field effect transistor is connected to the first output terminal of the input attenuation circuit; the source of the third field effect transistor is connected to the second output terminal of the input attenuation circuit; the input attenuation circuit is used to attenuate the received signal;

[0012] The input end of the source attenuation circuit is respectively connected to the output end of the frequency offset compensation circuit, the source of the first field effect transistor, the source of the second field effect transistor, the second output end of the input attenuation circuit, and the source of the third field effect transistor, and the output end of the source attenuation circuit is grounded; the source attenuation circuit is used to divide the overdrive voltage and weaken the nonlinearity between the leakage current and the overdrive voltage;

[0013] The source of the fourth field effect transistor is connected to the drain of the first field effect transistor;

[0014] The source of the fifth field effect transistor is connected to the drain of the second field effect transistor;

[0015] The source of the sixth field effect transistor is connected to the drain of the third field effect transistor; the gates of the fourth field effect transistor, the fifth field effect transistor, and the sixth field effect transistor are respectively connected to an external control circuit; the drain of the fifth field effect transistor and the drain of the sixth field effect transistor are respectively connected to the drain of the fourth field effect transistor;

[0016] The input end of the attenuation branch is connected to the drain of the fourth field effect transistor, and the output end of the attenuation branch is grounded; the attenuation branch is used to control the attenuation amount by the resistance value;

[0017] The source of the seventh field effect transistor is connected to the drain of the fourth field effect transistor;

[0018] A first end of the second resistor is connected to the gate of the seventh field effect transistor, and a second end of the second resistor is used to connect to a second bias voltage;

[0019] A first end of the first capacitor is connected to the gate of the seventh field effect transistor, and a second end of the first capacitor is grounded;

[0020] The first input terminal of the output matching circuit is connected to a power supply, and the second input terminal of the output matching circuit is connected to the drain of the seventh field effect transistor;

[0021] The input end of the output attenuation circuit is respectively connected to the drain of the seventh field effect transistor and the output end of the output matching circuit; the output end of the output attenuation circuit is connected to the signal output end; the output attenuation circuit is used to attenuate the output signal.

[0022] Preferably, the input attenuation circuit includes an eighth field effect transistor, a second capacitor, a third resistor, a fourth resistor, a ninth field effect transistor, and a tenth field effect transistor;

[0023] The source of the eighth field effect transistor serves as the input terminal of the input attenuation circuit, and the drain of the eighth field effect transistor serves as the first output terminal and the second output terminal of the input attenuation circuit respectively;

[0024] The first end of the second capacitor is connected to the drain of the eighth field effect transistor;

[0025] The first end of the third resistor and the first end of the fourth resistor are respectively connected to the second end of the second capacitor;

[0026] The drain of the ninth field effect transistor is connected to the second end of the third resistor;

[0027] The drain of the tenth field effect transistor is connected to the second end of the fourth resistor; the gate of the eighth field effect transistor, the gate of the ninth field effect transistor and the gate of the tenth field effect transistor are respectively connected to an external control circuit; the source of the tenth field effect transistor is connected to the source of the ninth field effect transistor.

[0028] Preferably, the source attenuation circuit includes a first inductor, a second inductor, an eleventh field-effect transistor, a twelfth field-effect transistor, a fifth resistor, a sixth resistor, a thirteenth field-effect transistor, and a fourteenth field-effect transistor;

[0029] The first end of the first inductor serves as the input end of the source attenuation circuit;

[0030] The first end of the second inductor is connected to the second end of the first inductor;

[0031] The drain of the eleventh field effect transistor is connected to the second end of the first inductor;

[0032] The drain of the twelfth field effect transistor is connected to the second end of the second inductor;

[0033] The first end of the fifth resistor and the first end of the sixth resistor are respectively connected to the second end of the second inductor;

[0034] The drain of the thirteenth field effect transistor is connected to the second end of the fifth resistor;

[0035] The drain of the fourteenth field-effect transistor is connected to the second end of the sixth resistor; the gate of the eleventh field-effect transistor, the gate of the twelfth field-effect transistor, the gate of the thirteenth field-effect transistor, and the gate of the fourteenth field-effect transistor are respectively connected to an external control circuit; the source of the eleventh field-effect transistor, the source of the twelfth field-effect transistor, the source of the thirteenth field-effect transistor, and the source of the fourteenth field-effect transistor collectively serve as the output end of the source attenuation circuit.

[0036] Preferably, the attenuation branch includes a third capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a fifteenth field effect transistor, a sixteenth field effect transistor, and a seventeenth field effect transistor;

[0037] The first end of the third capacitor serves as the input end of the attenuation branch;

[0038] The first end of the seventh resistor, the first end of the eighth resistor, and the first end of the ninth resistor are respectively connected to the second end of the third capacitor;

[0039] The drain of the fifteenth field effect transistor is connected to the second end of the seventh resistor;

[0040] The drain of the sixteenth field effect transistor is connected to the second end of the eighth resistor;

[0041] The drain of the seventeenth field-effect transistor is connected to the second end of the ninth resistor; the gate of the fifteenth field-effect transistor, the gate of the sixteenth field-effect transistor and the gate of the seventeenth field-effect transistor are respectively connected to an external control circuit; the source of the fifteenth field-effect transistor, the source of the sixteenth field-effect transistor and the source of the seventeenth field-effect transistor jointly serve as the output end of the attenuation branch.

[0042] Preferably, the frequency deviation compensation circuit includes a fourth capacitor, a fifth capacitor, a sixth capacitor, an eighteenth field effect transistor, and a nineteenth field effect transistor;

[0043] The first end of the fourth capacitor, the first end of the fifth capacitor, and the first end of the sixth capacitor collectively serve as an input end of the frequency offset compensation circuit;

[0044] The gate of the eighteenth field effect transistor and the gate of the nineteenth field effect transistor are respectively connected to an external control circuit; the drain of the eighteenth field effect transistor is connected to the second end of the fifth capacitor, and the drain of the nineteenth field effect transistor is connected to the second end of the sixth capacitor;

[0045] The second end of the fourth capacitor, the source of the eighteenth field effect transistor, and the source of the nineteenth field effect transistor collectively serve as the output end of the frequency deviation compensation circuit.

[0046] In a second aspect, the present invention provides a radio frequency power amplifier module, which includes the low noise amplifier as described above.

[0047] Compared with the related art, the low-noise amplifier in the present invention controls the gain, noise figure, IIP3 index and current change of the low-noise amplifier by designing a signal input end, an input matching circuit, a first resistor, a frequency deviation compensation circuit, a first field-effect transistor, a second field-effect transistor, an input attenuation circuit, a third field-effect transistor, a source attenuation circuit, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, an attenuation branch, a seventh field-effect transistor, a second resistor, a first capacitor, an output matching circuit, an output attenuation circuit and a signal output end, and limits the connection method of each component, so that the gain, noise figure, IIP3 index and current change of the low-noise amplifier can be controlled, so that the gain, noise figure, IIP3 index and current of the low-noise amplifier can maintain a balance, thereby improving its overall performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0049] FIG1 is a diagram showing the overall circuit structure of a low noise amplifier provided by an embodiment of the present invention;

[0050] FIG2 is a circuit structure diagram of an input attenuation circuit in a low noise amplifier provided by an embodiment of the present invention;

[0051] FIG3 is a circuit structure diagram of a source attenuation circuit in a low noise amplifier provided by an embodiment of the present invention;

[0052] FIG4 is a circuit structure diagram of an attenuation branch in a low noise amplifier provided by an embodiment of the present invention;

[0053] FIG5 is a circuit structure diagram of an intermediate frequency offset compensation circuit for a low noise amplifier provided by an embodiment of the present invention.

[0054] Among them, 100, low noise amplifier; 1, input matching circuit; 2, frequency offset compensation circuit; 3, input attenuation circuit; 4, source attenuation circuit; 5, attenuation branch; 6, output matching circuit; 7, output attenuation circuit. DETAILED DESCRIPTION

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are for the purpose of describing specific embodiments only and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0056] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0058] Example 1

[0059] An embodiment of the present invention provides a low-noise amplifier 100, as shown in Figures 1 to 5, which includes a signal input terminal RFIN, an input matching circuit 1, a first resistor R1, a frequency offset compensation circuit 2, a first field-effect transistor M1, a second field-effect transistor M2, an input attenuation circuit 3, a third field-effect transistor M3, a source attenuation circuit 4, a fourth field-effect transistor S4, a fifth field-effect transistor S5, a sixth field-effect transistor S6, an attenuation branch 5, a seventh field-effect transistor M7, a second resistor R2, a first capacitor C1, an output matching circuit 6, an output attenuation circuit 7, and a signal output terminal RFOUT.

[0060] The input end of the input matching circuit 1 is connected to the signal input end RFIN.

[0061] A first end of the first resistor R1 is connected to the output end of the input matching circuit 1 , and a second end of the first resistor R1 is connected to an external first bias voltage VCS.

[0062] The input end of the frequency offset compensation circuit 2, the gate of the first field effect transistor M1, the gate of the second field effect transistor M2, and the input end of the input attenuation circuit 3 are respectively connected to the output end of the input matching circuit 1; the frequency offset compensation circuit 2 is used to process the received signal to compensate for the frequency offset so that the signal can be correctly demodulated and processed.

[0063] The gate of the third field effect transistor M3 is connected to the first output terminal of the input attenuation circuit 3; the source of the third field effect transistor M3 is connected to the second output terminal of the input attenuation circuit 3; the input attenuation circuit 3 is used to attenuate the received signal.

[0064] The input end of the source attenuation circuit 4 is respectively connected to the output end of the frequency deviation compensation circuit 2, the source of the first field effect transistor M1, the source of the second field effect transistor M2, the second output end of the input attenuation circuit 3 and the source of the third field effect transistor M3, and the output end of the source attenuation circuit 4 is grounded (GND); the source attenuation circuit 4 is used to divide the over-drive voltage and weaken the nonlinearity between the leakage current and the over-drive voltage.

[0065] The source of the fourth field effect transistor S4 is connected to the drain of the first field effect transistor M1 .

[0066] The source of the fifth field effect transistor S5 is connected to the drain of the second field effect transistor M2 .

[0067] The source of the sixth field effect transistor S6 is connected to the drain of the third field effect transistor M3; the gate of the fourth field effect transistor S4, the gate of the fifth field effect transistor S5 and the gate of the sixth field effect transistor S6 are respectively connected to the external control circuit; the drain of the fifth field effect transistor S5 and the drain of the sixth field effect transistor S6 are respectively connected to the drain of the fourth field effect transistor S4.

[0068] The input end of the attenuation branch 5 is connected to the drain of the fourth field effect transistor S4, and the output end of the attenuation branch 5 is grounded; the attenuation branch 5 is used to control the attenuation amount by the resistance value.

[0069] The source of the seventh field effect transistor M7 is connected to the drain of the fourth field effect transistor S4 .

[0070] A first end of the second resistor R2 is connected to the gate of the seventh field effect transistor M7, and a second end of the second resistor R2 is connected to an external second bias voltage VCG. The second bias voltage VCG and the first bias voltage VCS are two different bias voltages.

[0071] A first end of the first capacitor C1 is connected to the gate of the seventh field effect transistor M7 , and a second end of the first capacitor C1 is grounded.

[0072] A first input terminal of the output matching circuit 6 is connected to a power supply, and a second input terminal of the output matching circuit 6 is connected to a drain of the seventh field effect transistor M7 .

[0073] The input end of the output attenuation circuit 7 is respectively connected to the drain of the seventh field effect transistor M7 and the output end of the output matching circuit 6; the output end of the output attenuation circuit 7 is connected to the signal output end RFOUT; the output attenuation circuit 7 is used to attenuate the output signal.

[0074] Specifically, the input attenuation circuit 3 includes an eighth field effect transistor S8 , a second capacitor C2 , a third resistor R3 , a fourth resistor R4 , a ninth field effect transistor S9 , and a tenth field effect transistor S10 .

[0075] The source of the eighth field effect transistor S8 serves as the input end of the input attenuation circuit 3 , and the drain of the eighth field effect transistor S8 serves as the first output end and the second output end of the input attenuation circuit 3 .

[0076] A first terminal of the second capacitor C2 is connected to the drain of the eighth field effect transistor S8 .

[0077] A first end of the third resistor R3 and a first end of the fourth resistor R4 are respectively connected to the second end of the second capacitor C2 .

[0078] The drain of the ninth field effect transistor S9 is connected to the second end of the third resistor R3 .

[0079] The drain of the tenth field-effect transistor S10 is connected to the second end of the fourth resistor R4; the gate of the eighth field-effect transistor S8, the gate of the ninth field-effect transistor S9 and the gate of the tenth field-effect transistor S10 are respectively connected to the external control circuit; the source of the tenth field-effect transistor S10 is connected to the source of the ninth field-effect transistor S9.

[0080] Specifically, the source attenuation circuit 4 includes a first inductor L1 , a second inductor L2 , an eleventh field effect transistor S11 , a twelfth field effect transistor S12 , a fifth resistor R5 , a sixth resistor R6 , a thirteenth field effect transistor S13 , and a fourteenth field effect transistor S14 .

[0081] The first end of the first inductor L1 serves as the input end of the source attenuation circuit 4 .

[0082] A first end of the second inductor L2 is connected to the second end of the first inductor L1 .

[0083] The drain of the eleventh field effect transistor S11 is connected to the second end of the first inductor L1 .

[0084] The drain of the twelfth field effect transistor S12 is connected to the second end of the second inductor L2 .

[0085] A first end of the fifth resistor R5 and a first end of the sixth resistor R6 are respectively connected to the second end of the second inductor L2 .

[0086] The drain of the thirteenth field effect transistor S13 is connected to the second end of the fifth resistor R5.

[0087] The drain of the fourteenth field-effect transistor S14 is connected to the second end of the sixth resistor R6; the gate of the eleventh field-effect transistor S11, the gate of the twelfth field-effect transistor S12, the gate of the thirteenth field-effect transistor S13, and the gate of the fourteenth field-effect transistor S14 are respectively connected to an external control circuit; the source of the eleventh field-effect transistor S11, the source of the twelfth field-effect transistor S12, the source of the thirteenth field-effect transistor S13, and the source of the fourteenth field-effect transistor S14 collectively serve as the output end of the source attenuation circuit 4.

[0088] Specifically, the attenuation branch 5 includes a third capacitor C3, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a fifteenth field effect transistor S15, a sixteenth field effect transistor S16, and a seventeenth field effect transistor S17.

[0089] The first end of the third capacitor C3 serves as the input end of the attenuation branch 5 .

[0090] A first end of the seventh resistor R7 , a first end of the eighth resistor R8 , and a first end of the ninth resistor R9 are respectively connected to the second end of the third capacitor C3 .

[0091] The drain of the fifteenth field effect transistor S15 is connected to the second end of the seventh resistor R7.

[0092] The drain of the sixteenth field effect transistor S16 is connected to the second end of the eighth resistor R8.

[0093] The drain of the seventeenth field-effect transistor S17 is connected to the second end of the ninth resistor R9; the gate of the fifteenth field-effect transistor S15, the gate of the sixteenth field-effect transistor S16, and the gate of the seventeenth field-effect transistor S17 are respectively connected to the external control circuit; the source of the fifteenth field-effect transistor S15, the source of the sixteenth field-effect transistor S16, and the source of the seventeenth field-effect transistor S17 collectively serve as the output end of the attenuation branch 5.

[0094] Specifically, the frequency offset compensation circuit 2 includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, an eighteenth field effect transistor S18, and a nineteenth field effect transistor S19.

[0095] The first end of the fourth capacitor C4 , the first end of the fifth capacitor C5 , and the first end of the sixth capacitor C6 serve together as an input end of the frequency offset compensation circuit 2 .

[0096] The gate of the eighteenth field effect transistor S18 and the gate of the nineteenth field effect transistor S19 are respectively connected to the external control circuit; the drain of the eighteenth field effect transistor S18 is connected to the second end of the fifth capacitor C5, and the drain of the nineteenth field effect transistor S19 is connected to the second end of the sixth capacitor C6.

[0097] The second end of the fourth capacitor C4 , the source of the eighteenth field effect transistor S18 , and the source of the nineteenth field effect transistor S19 collectively serve as the output end of the frequency offset compensation circuit 2 .

[0098] In this embodiment, the above-mentioned field effect tube can also be called a transistor.

[0099] The low-noise amplifier 100 in this embodiment mainly controls the various indicators (gain, noise figure, IIP3 indicator and current) of each gain level through adjustment in the following six ways to make it adaptable to various application scenarios. Specifically, the attenuation amount is reasonably set, and one or more methods are used in combination.

[0100] The first method: By designing the connection method of the first field-effect transistor M1 to the seventh field-effect transistor M7, the area of ​​the common source tube can be reduced, thereby directly changing the size of gm (transconductance) to achieve the effect of reducing current and reducing the introduction of nonlinear capacitance. It can also significantly improve the IIP3 index, but the degree of noise deterioration is relatively large.

[0101] The second method: Input attenuation circuit 3 can improve the IIP3 index, but the deterioration of the noise figure is also obvious.

[0102] The third approach: The first and second inductors L1 and L2 of the source attenuation circuit 4 inherently have a certain Q value, which acts as a voltage divider for the drive voltage, weakening the nonlinear relationship between leakage current and drive voltage. This can improve IIP3 and reduce current, but this depends on the size of gm. The fifth and sixth resistors R5 and R6 in the source attenuation circuit 4 are equivalent to their input terminals, equivalent to dividing the gain by a common-source stage. Therefore, the degradation of the noise figure is less than that of the input attenuation. However, the addition of the fifth and sixth resistors R5 and R6 will shift the fifth field-effect transistor S5 toward higher frequencies, necessitating the addition of some gate-source capacitance to compensate for this.

[0103] The fourth method: the attenuation branch 5 is loaded at the output of the common-source amplifier and the input of the common-gate amplifier, thereby improving the IIP3 index, but it also has a deteriorating effect on the noise figure, but the degree is not as obvious as directly adding attenuation at the input of the common-source amplifier.

[0104] The fifth method: The attenuation circuit directly adds an attenuation network at the signal output end RFOUT. This will not deteriorate the noise figure, and will not improve the IIP3 index and power consumption, and the attenuation amount is stable.

[0105] The sixth method is to connect an external first bias voltage VCS and an external second bias voltage VCG to essentially change the overdrive voltage to make some fine adjustments to achieve a precise gain level.

[0106] In the low-noise amplifier 100 of this embodiment, the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, and the seventh field-effect transistor M7 form a cascode amplifier. The area connected to the cascode amplifier is selected by the fourth field-effect transistor S4, the fifth field-effect transistor S5, and the sixth field-effect transistor S6. An attenuation branch 5 is connected between the fourth field-effect transistor S4, the fifth field-effect transistor S5, and the sixth field-effect transistor S6 and the cascode amplifier. This allows the variation of various indicators to be controlled by the value of the added resistance. The source attenuation circuit 4 loaded at the source controls the variation of various indicators by selecting the values ​​of the connected inductors (first inductor L1 and second inductor L2) and resistors (fifth resistor R5 and sixth resistor R6). The input attenuation circuit 3 is connected to the gate of the cascode amplifier. When in use, the eighth field-effect transistor S8 provides a series on-resistance, and the variation of various indicators is also controlled by the value of the connected parallel resistor. The output attenuation circuit 7 is connected after the output matching circuit 6 and is typically a π-type attenuation circuit or an L-type attenuation circuit.

[0107] The low-noise amplifier 100 in this embodiment is designed to include a signal input terminal RFIN, an input matching circuit 1, a first resistor R1, a frequency offset compensation circuit 2, a first field-effect transistor M1, a second field-effect transistor M2, an input attenuation circuit 3, a third field-effect transistor M3, a source attenuation circuit 4, a fourth field-effect transistor S4, a fifth field-effect transistor S5, a sixth field-effect transistor S6, an attenuation branch 5, a seventh field-effect transistor M7, a second resistor R2, a first capacitor C1, an output matching circuit 6, an output attenuation circuit 7, and a signal output terminal RFOUT, and defines the connection method of each component. This allows the gain, noise figure, IIP3 indicator, and current variation of the low-noise amplifier 100 to be controlled, thereby maintaining a balance among the gain, noise figure, IIP3 indicator, and current of the low-noise amplifier 100, thereby improving its overall performance.

[0108] Example 2

[0109] An embodiment of the present invention provides a radio frequency power amplifier module, which includes the low-noise amplifier 100 of the first embodiment. Since the radio frequency power amplifier module in this embodiment includes the low-noise amplifier 100 of the first embodiment, the technical effects achieved are the same as those achieved by the low-noise amplifier 100 of the first embodiment, and are not further described here.

[0110] It should be noted that the various embodiments described above with reference to the accompanying drawings are intended only to illustrate the present invention and are not intended to limit the scope of the present invention. Those skilled in the art should understand that any modifications or equivalent substitutions to the present invention that do not depart from the spirit and scope of the present invention are intended to be encompassed within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include the plural form, and vice versa. Furthermore, unless otherwise specified, all or part of any embodiment may be used in combination with all or part of any other embodiment.

Claims

1. A low-noise amplifier, characterized in that, The low-noise amplifier includes a signal input terminal, an input matching circuit, a first resistor, a frequency offset compensation circuit, a first field-effect transistor, a second field-effect transistor, an input attenuation circuit, a third field-effect transistor, a source attenuation circuit, a fourth field-effect transistor, a fifth field-effect transistor, a sixth field-effect transistor, an attenuation branch, a seventh field-effect transistor, a second resistor, a first capacitor, an output matching circuit, an output attenuation circuit, and a signal output terminal; The input terminal of the input matching circuit is connected to the signal input terminal; The first end of the first resistor is connected to the output terminal of the input matching circuit, and the second end of the first resistor is used to connect to a first bias voltage; The input terminal of the frequency offset compensation circuit, the gate of the first field-effect transistor, the gate of the second field-effect transistor, and the input terminal of the input attenuation circuit are respectively connected to the output terminal of the input matching circuit; the frequency offset compensation circuit is used to process the received signal to compensate for the frequency offset so that the signal can be correctly demodulated and processed; The gate of the third field-effect transistor is connected to the first output terminal of the input attenuation circuit; The source of the third field-effect transistor is connected to the second output terminal of the input attenuation circuit; the input attenuation circuit is used to attenuate the received signal; The input terminal of the source attenuation circuit is respectively connected to the output terminal of the frequency offset compensation circuit, the source of the first field-effect transistor, the source of the second field-effect transistor, the second output terminal of the input attenuation circuit, and the source of the third field-effect transistor, and the output terminal of the source attenuation circuit is grounded; the source attenuation circuit is used to divide the overdrive voltage and weaken the non-linearity between the leakage current and the overdrive voltage; The source of the fourth field-effect transistor is connected to the drain of the first field-effect transistor; The source of the fifth field-effect transistor is connected to the drain of the second field-effect transistor; The source of the sixth field-effect transistor is connected to the drain of the third field-effect transistor; The gates of the fourth field-effect transistor, the fifth field-effect transistor, and the sixth field-effect transistor are respectively connected to an external control circuit; the drains of the fifth field-effect transistor and the sixth field-effect transistor are respectively connected to the drain of the fourth field-effect transistor; The input terminal of the attenuation branch is connected to the drain of the fourth field-effect transistor, and the output terminal of the attenuation branch is grounded; the attenuation branch is used to control the amount of attenuation by the resistance value; The source of the seventh field-effect transistor is connected to the drain of the fourth field-effect transistor; The first end of the second resistor is connected to the gate of the seventh field-effect transistor, and the second end of the second resistor is used to connect to a second bias voltage; The first end of the first capacitor is connected to the gate of the seventh field-effect transistor, and the second end of the first capacitor is grounded; The first input terminal of the output matching circuit is connected to the power supply, and the second input terminal of the output matching circuit is connected to the drain of the seventh field-effect transistor; The input end of the output attenuation circuit is respectively connected to the drain of the seventh field effect transistor and the output end of the output matching circuit; the output end of the output attenuation circuit is connected to the signal output end; the output attenuation circuit is used for attenuating the output signal.

2. The low-noise amplifier according to claim 1, characterized in that, The input attenuation circuit includes an eighth field effect transistor, a second capacitor, a third resistor, a fourth resistor, a ninth field effect transistor, and a tenth field effect transistor; The source of the eighth field effect transistor serves as the input end of the input attenuation circuit, and the drain of the eighth field effect transistor serves as the first output end and the second output end of the input attenuation circuit respectively; The first end of the second capacitor is connected to the drain of the eighth field effect transistor; The first ends of the third resistor and the fourth resistor are respectively connected to the second end of the second capacitor; The drain of the ninth field effect transistor is connected to the second end of the third resistor; The drain of the tenth field effect transistor is connected to the second end of the fourth resistor; The gates of the eighth field effect transistor, the ninth field effect transistor, and the tenth field effect transistor are respectively connected to an external control circuit; the source of the tenth field effect transistor and the source of the ninth field effect transistor are connected.

3. The low-noise amplifier according to claim 1, wherein The source attenuation circuit includes a first inductor, a second inductor, an eleventh field effect transistor, a twelfth field effect transistor, a fifth resistor, a sixth resistor, a thirteenth field effect transistor, and a fourteenth field effect transistor; The first end of the first inductor serves as the input end of the source attenuation circuit; The first end of the second inductor is connected to the second end of the first inductor; The drain of the eleventh field effect transistor is connected to the second end of the first inductor; The drain of the twelfth field effect transistor is connected to the second end of the second inductor; The first ends of the fifth resistor and the sixth resistor are respectively connected to the second end of the second inductor; The drain of the thirteenth field effect transistor is connected to the second end of the fifth resistor; The drain of the fourteenth field effect transistor is connected to the second end of the sixth resistor; the gates of the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor, and the fourteenth field effect transistor are respectively connected to an external control circuit; the sources of the eleventh field effect transistor, the twelfth field effect transistor, the thirteenth field effect transistor, and the fourteenth field effect transistor jointly serve as the output end of the source attenuation circuit.

4. The low-noise amplifier according to claim 1, wherein The attenuation branch includes a third capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a fifteenth field effect transistor, a sixteenth field effect transistor, and a seventeenth field effect transistor; The first end of the third capacitor serves as the input end of the attenuation branch; The first ends of the seventh resistor, the eighth resistor, and the ninth resistor are respectively connected to the second end of the third capacitor; The drain of the fifteenth field effect transistor is connected to the second end of the seventh resistor; The drain of the sixteenth field effect transistor is connected to the second end of the eighth resistor; The drain of the seventeenth field effect transistor is connected to the second end of the ninth resistor; the gates of the fifteenth field effect transistor, the sixteenth field effect transistor, and the seventeenth field effect transistor are respectively connected to an external control circuit; the sources of the fifteenth field effect transistor, the sixteenth field effect transistor, and the seventeenth field effect transistor together serve as the output end of the attenuation branch.

5. The low-noise amplifier according to claim 1, wherein The frequency offset compensation circuit includes a fourth capacitor, a fifth capacitor, a sixth capacitor, an eighteenth field effect transistor, and a nineteenth field effect transistor; The first ends of the fourth capacitor, the fifth capacitor, and the sixth capacitor together serve as the input end of the frequency offset compensation circuit; The gates of the eighteenth field effect transistor and the nineteenth field effect transistor are respectively connected to an external control circuit; the drain of the eighteenth field effect transistor is connected to the second end of the fifth capacitor, and the drain of the nineteenth field effect transistor is connected to the second end of the sixth capacitor; The second end of the fourth capacitor, the source of the eighteenth field effect transistor, and the source of the nineteenth field effect transistor together serve as the output end of the frequency offset compensation circuit.

6. A radio frequency power amplifier module, characterized in that, The RF power amplifier module includes the low-noise amplifier according to any one of claims 1 to 5.

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