Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units, each of which comprises a pixel driving circuit, wherein the pixel driving circuit at least comprises a driving transistor, a first reset transistor, a data writing transistor, a light emission control transistor, a first capacitor, and a second capacitor, a first electrode of the first reset transistor being connected to a reference signal line, a second electrode of the first reset transistor being connected to a gate electrode of the driving transistor, a first electrode of the light emission control transistor being connected to a first power line, a second electrode of the light emission control transistor being connected to a first electrode of the driving transistor, a second electrode of the driving transistor being connected to a second electrode plate of the first capacitor, a first electrode of the data writing transistor being connected to a data signal line, and a second electrode of the data writing transistor being connected to a fourth electrode plate of the second capacitor; and the driving transistor being an oxide transistor, and the width-to-length ratio of the driving transistor being 1.25 to 2.67.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 8, 2024, with application number 202410028796.5 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along a second direction, wherein one end of at least one first data connection line is connected to the data signal line and the other end is connected to the second data connection line, and the first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, wherein the pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor and a second capacitor, wherein the first capacitor includes a first plate and a second plate, and the second capacitor includes a third plate and a fourth plate ; The first electrode of the first reset transistor is connected to the reference signal line, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, the first electrode of the light-emitting control transistor is connected to the first power line, the second electrode of the light-emitting control transistor is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the second plate of the first capacitor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is connected to the fourth plate of the second capacitor, and the first plate of the first capacitor is connected to the third plate of the second capacitor; the driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is 1.25 to 2.67.

[0006] In an exemplary embodiment, an orthographic projection of the data signal line on the substrate does not overlap with orthographic projections of channel regions of the driving transistor, the first reset transistor, the data writing transistor, and the light emission control transistor on the substrate.

[0007] In an exemplary embodiment, in at least one circuit unit, the data signal line includes at least one straight segment and at least one bent segment, and the bent segment is configured to increase an extension length of the data signal line.

[0008] In an exemplary embodiment, at least one second data link line is disposed between two adjacent first power lines in the first direction, or at least one second data link line is disposed between two adjacent data signal lines in the first direction.

[0009] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to the first direction, the first power lines of the two circuit units are connected to each other in an integrated structure.

[0010] In an exemplary embodiment, at least one circuit unit further includes a first power connection line extending along the first direction, the first power line is in the shape of a straight line or a broken line extending along the second direction, and the first power line is connected to the first power connection line to form a mesh structure for transmitting the first power signal.

[0011] In an exemplary embodiment, at least one circuit unit further includes a second power line having a width greater than a width of the first power line, the width being a dimension in the first direction.

[0012] In an exemplary embodiment, the display substrate further includes a plurality of auxiliary cathodes, the auxiliary cathodes being arranged on a side of the second power line away from the substrate, the orthographic projection of at least one auxiliary cathode on the substrate at least partially overlapping with the orthographic projection of the second power line on the substrate, the auxiliary cathodes being connected to the second power line through auxiliary vias, and the auxiliary cathodes being configured to be connected to the cathodes of the light-emitting devices.

[0013] In an exemplary embodiment, an orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the first reset transistor and the data write transistor on the substrate, and an orthographic projection of the second power line on the substrate at least partially overlaps with an orthographic projection of the drive transistor and the light emission control transistor on the substrate.

[0014] In an exemplary embodiment, at least one circuit unit further includes a data connection electrode, the data connection electrode being connected to the first data connection line, and the second data connection line being connected to the data connection electrode through a via; at least one circuit unit further includes a dummy electrode, the second data connection line being connected to the dummy electrode through a via, and the position and shape of the dummy electrode in one circuit unit being the same as the position and shape of the data connection electrode in another circuit unit.

[0015] In an exemplary embodiment, in a direction perpendicular to the substrate, the display substrate includes at least a first source-drain metal layer and a second source-drain metal layer arranged in sequence along a direction away from the substrate, and the first data connection line is arranged in the first source-drain metal layer; at least one first data connection line is provided with a first break, the first break cuts off the first data connection line, and the orthographic projection of the first break on the substrate at least partially overlaps with the orthographic projection of the second source-drain metal layer on the substrate.

[0016] In an exemplary embodiment, in a direction perpendicular to the substrate, the display substrate includes at least a first source-drain metal layer and a second source-drain metal layer arranged in sequence along a direction away from the substrate, and the second data connection line is arranged in the second source-drain metal layer; at least one second data connection line is provided with a second break, the second break cuts off the second data connection line, and the orthographic projection of the second break on the substrate at least partially overlaps with the orthographic projection of the first source-drain metal layer on the substrate.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a second reset transistor, a third reset transistor and a data control transistor; the first electrode of the second reset transistor is connected to the reference signal line, and the second electrode of the second reset transistor is connected to the first plate of the first capacitor and the third plate of the second capacitor; the first electrode of the third reset transistor is connected to the initial signal line, and the second electrode of the third reset transistor is connected to the second electrode of the driving transistor; the first electrode of the data control transistor is connected to the gate electrode of the driving transistor, and the second electrode of the data control transistor is connected to the second electrode of the data writing transistor; the first reset transistor, the second reset transistor, the third reset transistor, the data writing transistor, the light emitting control transistor and the data control transistor are oxide transistors.

[0018] In an exemplary embodiment, the first reset transistor includes at least a first bottom gate electrode and a first top gate electrode, and in at least one circuit unit and a circuit unit adjacent to the first direction, the first bottom gate electrodes in the two circuit units are an integrated structure connected to each other, and the first top gate electrodes in the two circuit units are an integrated structure connected to each other; and / or, the data write transistor includes at least a fourth bottom gate electrode and a fourth top gate electrode, and in at least one circuit unit and a circuit unit adjacent to the first direction, the fourth bottom gate electrodes in the two circuit units are an integrated structure connected to each other, and the fourth top gate electrodes in the two circuit units are an integrated structure connected to each other; and / or, the data control transistor includes at least a sixth bottom gate electrode and a sixth top gate electrode, and in at least one circuit unit and a circuit unit adjacent to the first direction, the sixth bottom gate electrodes in the two circuit units are an integrated structure connected to each other, and the sixth top gate electrodes in the two circuit units are an integrated structure connected to each other.

[0019] In an exemplary embodiment, a first bottom gate connection block is provided on the first bottom gate electrode, a first top gate connection block is provided on the first top gate electrode, the first bottom gate connection block is configured to be connected to the first scan signal line through a first bottom gate connection via, the first top gate connection block is configured to be connected to the first scan signal line through a first top gate connection via, and in at least one circuit unit and a circuit unit adjacent in the first direction, two circuit units share the first bottom gate connection via, and two circuit units share the first top gate connection via; and / or a fourth bottom gate connection block is provided on the fourth bottom gate electrode, a fourth top gate connection block is provided on the fourth top gate electrode, the fourth bottom gate connection block is configured to be connected to the third scan signal line through a fourth bottom gate connection via, and the fourth top gate The connection block is configured to be connected to the third scan signal line through a fourth top gate connection via, and in at least one circuit unit and a circuit unit adjacent to the first direction, two circuit units share the fourth bottom gate connection via, and two circuit units share the fourth top gate connection via; and / or, a sixth bottom gate connection block is provided on the sixth bottom gate electrode, and a sixth top gate connection block is provided on the sixth top gate electrode, the sixth bottom gate connection block is configured to be connected to the fourth scan signal line through the sixth bottom gate connection via, and the sixth top gate connection block is configured to be connected to the fourth scan signal line through the sixth top gate connection via, and in at least one circuit unit and a circuit unit adjacent to the first direction, two circuit units share the sixth bottom gate connection via, and two circuit units share the sixth top gate connection via.

[0020] In an exemplary embodiment, the second reset transistor includes at least a second bottom gate electrode and a second top gate electrode, and in at least one circuit unit, the first bottom gate electrode and the second bottom gate electrode are an integrated structure connected to each other, and the first top gate electrode and the second top gate electrode are an integrated structure connected to each other.

[0021] In an exemplary embodiment, the first reset transistor includes at least a first active layer, and in at least one circuit unit and a circuit unit adjacent to the first direction, the first active layers in two circuit units are connected to each other in an integrated structure.

[0022] In an exemplary embodiment, the reference signal line is connected to the first region of the first active layer through a first active via, and two circuit units of at least one circuit unit and adjacent circuit units in the first direction share the first active via.

[0023] In an exemplary embodiment, the third reset transistor includes at least a seventh active layer, and in at least one circuit unit and a circuit unit adjacent to the first direction, the seventh active layers in two circuit units are connected to each other in an integrated structure.

[0024] In an exemplary embodiment, the initial signal line is connected to the first region of the seventh active layer through a seventh active via, and two circuit units of at least one circuit unit and adjacent circuit units in the first direction share the seventh active via.

[0025] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0026] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along a second direction, wherein one end of at least one first data connection line is connected to the data signal line and the other end is connected to the second data connection line, and the first direction and the second direction intersect; the manufacturing method comprising:

[0027] A pixel driving circuit is formed in at least one circuit unit, and the pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light-emitting control transistor, a first capacitor and a second capacitor, the first capacitor including a first plate and a second plate, and the second capacitor including a third plate and a fourth plate; the first electrode of the first reset transistor is connected to the reference signal line, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, the first electrode of the light-emitting control transistor is connected to the first power line, the second electrode of the light-emitting control transistor is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the second plate of the first capacitor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is connected to the fourth plate of the second capacitor, and the first plate of the first capacitor is connected to the third plate of the second capacitor; the driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is 1.25 to 2.67.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic structural diagram of a display substrate;

[0032] FIG3A is a schematic diagram of a planar structure of a display area in a display substrate;

[0033] FIG3B is a schematic diagram of a planar structure of a display area in another display substrate;

[0034] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0035] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0036] FIG6 is a driving timing diagram of the pixel driving circuit shown in FIG5 ;

[0037] FIG7A is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0038] FIG7B is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure;

[0039] FIG8 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] FIG9 is a schematic diagram of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0041] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0042] 11A and 11B are schematic diagrams of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0043] 12A and 12B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0044] FIG12C is an enlarged view of the third transistor in FIG12A ;

[0045] FIG13 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern;

[0046] 14A and 14B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0047] FIG15 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern;

[0048] 16A and 16B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0049] FIG17 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0050] FIG18 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0051] FIG19 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0052] 20A and 20B are schematic diagrams of the embodiment shown in FIG19 after forming a fourth conductive layer pattern;

[0053] 21A and 21B are schematic diagrams of the embodiment shown in FIG19 after forming a fifth conductive layer pattern;

[0054] FIG22 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0055] FIG23 is a schematic diagram of the embodiment shown in FIG22 after forming a first conductive layer pattern;

[0056] FIG24 is a schematic diagram of the embodiment shown in FIG22 after forming a second conductive layer pattern;

[0057] FIG25 is a schematic diagram of the embodiment shown in FIG22 after forming a semiconductor layer pattern;

[0058] FIG26 is a schematic diagram of the embodiment shown in FIG22 after forming a third conductive layer pattern;

[0059] FIG27 is a schematic diagram of the embodiment shown in FIG22 after forming a fourth insulating layer pattern;

[0060] FIG28 is a schematic diagram of the embodiment shown in FIG22 after forming a fourth conductive layer pattern;

[0061] FIG29 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure;

[0062] FIG30 is a schematic diagram of the embodiment shown in FIG29 after forming a first conductive layer pattern;

[0063] FIG31 is a schematic diagram of the embodiment shown in FIG29 after forming a second conductive layer pattern;

[0064] FIG32 is a schematic diagram of the embodiment shown in FIG29 after forming a semiconductor layer pattern;

[0065] FIG33 is a schematic diagram of the embodiment shown in FIG29 after forming a third conductive layer pattern;

[0066] FIG34 is a schematic diagram of the embodiment shown in FIG29 after forming a fourth conductive layer pattern.

[0067] Explanation of Reference Numerals: 11—first electrode plate; 12—second electrode plate; 13—third electrode plate; 14—fourth electrode plate; 15—electrode plate connecting block; 21—first bottom gate electrode; 22—second bottom gate electrode; 24—fourth bottom gate electrode; 26—sixth bottom gate electrode; 27—first shielding line; 28—second shielding line; 31—first active layer; 32—second active layer; 33—third active layer; 34—fourth active layer; 35—fifth active layer; 36—sixth active layer; 37—seventh active layer; 41—first top gate electrode; 42—second top gate electrode; 43—third top gate electrode; 44—fourth top gate electrode; 46—sixth top gate electrode; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 61—first scanning signal line; 62—second scanning signal line; 63—third scanning signal line; 64—fourth scanning signal line; 65—light-emitting signal line; 66—reference signal line; 67—initial signal line; 68—first power connection line; 71—first power line; 72—second power line; 73—data signal line; 74—anode connecting electrode; 81—first data connection line; 82—second data connection line; 83—data connection block; 84—data connection electrode; 85—dummy electrode; 90—auxiliary cathode; 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0069] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0070] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0071] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0072] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0073] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0074] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0075] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0076] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0077] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0078] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0079] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0080] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic images or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0081] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bending area 202, a driver chip area and a binding pin area arranged in sequence along a direction away from the display area, and the lead area 201 is connected to the display area 100 and includes at least a data lead. The bending area 202 is connected to the lead area 201 and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (Bonding Pad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0082] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0083] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 can be provided with an isolation dam, and the isolation dam can extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of one side of the display area binding area or the border area.

[0084] FIG3A is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG3A , the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0085] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged in an RGBG pattern.

[0086] Figure 3B is a schematic diagram of the planar structure of the display area in another display substrate. As shown in Figure 3B , the pixel unit P may include three sub-pixels: the first sub-pixel P1 may be a red sub-pixel emitting red light, the second sub-pixel P2 may be a blue sub-pixel emitting blue light, and the third sub-pixel P3 may be a green sub-pixel emitting green light. The three sub-pixels may be arranged in a Real RGB manner.

[0087] In other exemplary embodiments, three sub-pixels or four sub-pixels may be arranged in parallel horizontally or vertically, and the present disclosure does not limit this.

[0088] Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of four sub-pixels within the display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the display region may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display region may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0089] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0090] With the development of OLED display technology, consumers have increasingly higher requirements for the display effects of display products, and extremely narrow bezels have become a new trend in the development of display products. Therefore, narrow bezels or even bezel-free designs are gaining increasing attention in the design of OLED display products. In a display substrate, because the signal lines of the integrated circuits and bonding pads in the binding area need to be introduced to the wider display area through data lead-out lines in a fan-out manner, the lead-out area occupies a large space, resulting in a larger width of the lower bezel. In addition, as the size of the display substrate increases, the yield of display substrates using low-temperature polysilicon (LTPS) thin-film transistors decreases, resulting in higher costs.

[0091] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, the display substrate may include a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along a second direction, one end of at least one first data connection line is connected to the data signal line and the other end is connected to the second data connection line, and the first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor and a second capacitor, the first capacitor includes a first plate and a second plate, and the second capacitor includes a third plate and a fourth plate ; The first electrode of the first reset transistor is connected to the reference signal line, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, the first electrode of the light-emitting control transistor is connected to the first power line, the second electrode of the light-emitting control transistor is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the second plate of the first capacitor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is connected to the fourth plate of the second capacitor, and the first plate of the first capacitor is connected to the third plate of the second capacitor; the driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is 1.25 to 2.67.

[0092] In an exemplary embodiment, an orthographic projection of the data signal line on the substrate does not overlap with orthographic projections of channel regions of the driving transistor, the first reset transistor, the data writing transistor, and the light emission control transistor on the substrate.

[0093] In an exemplary embodiment, in at least one circuit unit, the data signal line includes at least one straight segment and at least one bent segment, and the bent segment is configured to increase an extension length of the data signal line.

[0094] In an exemplary embodiment, at least one second data link line is disposed between two adjacent first power lines in the first direction, or at least one second data link line is disposed between two adjacent data signal lines in the first direction.

[0095] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to the first direction, the first power lines of the two circuit units are connected to each other in an integrated structure.

[0096] In an exemplary embodiment, at least one circuit unit further includes a first power connection line extending along the first direction, the first power line is in the shape of a straight line or a broken line extending along the second direction, and the first power line is connected to the first power connection line to form a mesh structure for transmitting the first power signal.

[0097] In an exemplary embodiment, at least one circuit unit further includes a second power line having a width greater than a width of the first power line, the width being a dimension in the first direction.

[0098] In an exemplary embodiment, the display substrate further includes a plurality of auxiliary cathodes, the auxiliary cathodes being arranged on a side of the second power line away from the substrate, the orthographic projection of at least one auxiliary cathode on the substrate at least partially overlapping with the orthographic projection of the second power line on the substrate, the auxiliary cathodes being connected to the second power line through auxiliary vias, and the auxiliary cathodes being configured to be connected to the cathodes of the light-emitting devices.

[0099] In an exemplary embodiment, an orthographic projection of the first power line on the substrate at least partially overlaps with an orthographic projection of the first reset transistor and the data write transistor on the substrate, and an orthographic projection of the second power line on the substrate at least partially overlaps with an orthographic projection of the drive transistor and the light emission control transistor on the substrate.

[0100] The display substrate of this embodiment is described below with reference to some examples.

[0101] Figure 5 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 5, in an exemplary embodiment, the pixel driving circuit according to the exemplary embodiment of the present disclosure adopts a 7T2C structure. The pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and two capacitors C. The pixel driving circuit is respectively connected to nine signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, an emission signal line EM, a reference signal line REF, an initial signal line INIT, a data signal line DATA, and a first power line VDD).

[0102] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the first electrode of the sixth transistor T6, and the gate electrode of the third transistor T3, respectively; the second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the sixth transistor T6, and the second end of the second capacitor C2, respectively; the third node N3 is connected to the second electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the second end of the first capacitor C1, respectively; and the fourth node N4 is connected to the second electrode of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2, respectively.

[0103] In an exemplary embodiment, the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the reference signal line REF, and a second electrode of the first transistor T1 is connected to the first node N1.

[0104] In an exemplary embodiment, the second transistor T2 may be referred to as a second reset transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the reference signal line REF, and a second electrode of the second transistor T2 is connected to the fourth node N4.

[0105] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and a second electrode of the third transistor T3 is connected to the third node N3.

[0106] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0107] In an exemplary embodiment, the fifth transistor T5 can be referred to as a light emitting control transistor, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3.

[0108] In an exemplary embodiment, the sixth transistor T6 may be referred to as a data control transistor, a gate electrode of the sixth transistor T6 is connected to the fourth scan signal line S4 , a first electrode of the sixth transistor T6 is connected to the first node N1 , and a second electrode of the sixth transistor T6 is connected to the second node N2 .

[0109] In an exemplary embodiment, the seventh transistor T7 may be referred to as a third reset transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and a second electrode of the seventh transistor T7 is connected to the third node N3 .

[0110] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the third node N3, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0111] In an exemplary embodiment, the seven transistors of the pixel driving circuit may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the yield of the product.

[0112] In an exemplary embodiment, all seven transistors of the pixel driving circuit may be oxide transistors. The active layers of the oxide transistors may be made of oxide semiconductors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage. Using a display substrate equipped with oxide transistors can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0113] In an exemplary embodiment, the first power line VDD may be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS may be configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The reference signal line REF and the initial voltage signal may be constant voltage signals, which are not limited in this disclosure.

[0114] FIG6 is a driving timing diagram of the pixel driving circuit shown in FIG5. As shown in FIG6, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0115] The first phase A1 is called the initialization phase. The signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals, while the signals on the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line EM are low-level signals. This turns on the first transistor T1, the second transistor T2, and the seventh transistor T7, while turning off the other switching transistors.

[0116] The first transistor T1 is turned on, causing the reference signal provided by the reference signal line REF to be supplied to the first node N1, initializing the first node N1 (resetting the gate electrode of the third transistor T3), and the potential of the first node N1 is Vref. The second transistor T2 is turned on, causing the reference signal provided by the reference signal line REF to be supplied to the fourth node N4, initializing the fourth node N4 (resetting the first end of the first capacitor C1 and the first end of the second capacitor C2), and the potential of the fourth node N4 is Vref. The seventh transistor T7 is turned on, causing the initial signal provided by the initial signal line INIT to be supplied to the third node N3, initializing the third node N3 (resetting the second electrode of the third transistor T3 and the second end of the second capacitor C2), and the potential of the third node N3 is Vinit. At the same time, the voltage difference between Vinit and Vref turns on the third transistor T3.

[0117] In an exemplary embodiment, Vref is the voltage of the reference signal, which may be approximately 2.5V, and Vinit is the voltage of the initial signal, which may be approximately 1.5V.

[0118] In an exemplary embodiment, the resetting of the first node N1 , the third node N3 , and the fourth node N4 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0119] The second phase A2 is called the compensation phase. The signals on the first scanning signal line S1 and the light-emitting signal line EM are high-level signals, while the signals on the second scanning signal line S2, the third scanning signal line S3, and the fourth scanning signal line S4 are low-level signals. This turns on the first transistor T1, the second transistor T2, and the fifth transistor T5, while turning off the other switching transistors.

[0120] The first transistor T1 and the second transistor T2 are turned on so that the potentials of the first node N1 and the fourth node N4 remain at Vref. Since the third transistor T3 is turned on, the fifth transistor T5 is turned on so that the first power signal output by the first power line VDD is written into the third node N3 through the turned-on third transistor T3, so that the potential of the third node N3 gradually increases.

[0121] In an exemplary embodiment, the voltage of the first power signal outputted by the first power line VDD may be approximately 11.5V.

[0122] The third phase A3 is called the data writing phase. The signal on the luminous signal line EM is a continuously high-level signal, the signals on the second scanning signal line S2 and the fourth scanning signal line S4 are continuously low-level signals, and the signals on the first scanning signal line S1 and the third scanning signal line S3 are high-level signals for a period of time and then change to low-level signals, causing the fifth transistor T5 to be continuously turned on. The first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on for a period of time and then turned off.

[0123] The fourth transistor T4 is turned on, causing the data signal output from the data signal line DATA to be written to the second node N2 and stored in the second capacitor C2. The fifth transistor T5 is continuously turned on, causing the potential of the third node N3 to gradually increase until the potential reaches Vref-Vth. This causes the gate-source voltage difference Vgs of the third transistor T3 to equal Vth, turning off the third transistor T3. This causes the threshold voltage Vth of the third transistor T3 to be written to the third node N3 and stored in the first capacitor C1. Thus, the threshold voltage Vth begins to be written in the second phase (compensation phase) A2, and the threshold voltage writing is completed in the third phase (data writing phase) A3. The threshold voltage writing continues from the second phase A2 to the third phase A3. After the threshold voltage Vth is written to the third node N3, the first transistor T1 and the second transistor T2 are turned off.

[0124] In the fourth phase A4, called the light-emitting phase, the signals on the fourth scanning signal line S4 and the light-emitting signal line EM are high-level signals, and the signals on the first scanning signal line S1, the second scanning signal line S2, and the third scanning signal line S3 are low-level signals, turning on the fifth transistor T5 and the sixth transistor T6.

[0125] The sixth transistor T6 is turned on, connecting the first node N1 and the second node N2. The data voltage stored in the second node N2 is written to the first node N1. The potential of the first node N1 (the potential of the gate electrode of the third transistor T3) is Vg = Vd + Vld + VSS - (Vref - Vth); the potential of the third node N3 (the potential of the second electrode of the third transistor T3) is Vs = Vld + VSS. Therefore, the gate-source voltage difference of the third transistor T3 is Vgs = Vdata - Vref + Vth. Vld is the voltage of the light-emitting device EL, VSS is the voltage of the second power signal, and Vd is the voltage of the data signal. The fifth transistor T5 is turned on, so that the first power signal output from the first power line VDD provides a driving voltage to the first electrode of the light-emitting element EL by turning on the third transistor T3, driving the light-emitting element EL to emit light.

[0126] The output current I of the third transistor T3 satisfies the following formula: I=(μWCox / 2L)(Vgs-Vth) 2 =(μWCox / 2L)(Vdata-Vref) 2 .

[0127] Wherein, μ is the carrier mobility; Cox is the gate electrode capacitance per unit area; W is the channel width of the third transistor T3; and L is the channel length of the third transistor T3.

[0128] According to the above formula for the output current of the third transistor T3, it can be seen that the output current of the pixel driving circuit is independent of the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the output current. The output current can be controlled by controlling the data voltage Vd to control the brightness of the light-emitting device EL.

[0129] The pixel driving circuit and driving method provided in the exemplary embodiments of the present disclosure store the data signal in the second capacitor during the write phase, rather than directly writing it to the gate electrode of the third transistor T3. During the compensation phase, the threshold voltage of the third transistor T3 is stored in the first capacitor. This allows the data signal and the threshold voltage of the third transistor T3 to be stored independently, preventing the stored data signal and the stored threshold voltage from interfering with each other. Using the second capacitor to write the data signal to the gate electrode of the third transistor T3 during the light-emitting phase not only ensures a stable voltage difference between the data signal and the second electrode of the driving transistor T3, but also prevents differences between the actual brightness of the light-emitting device and the designed brightness due to varying degrees of interference between different data signals, thereby improving image quality.

[0130] Figure 7A is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Within a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. As shown in Figure 7A, within a plane parallel to the display substrate, the display substrate may include at least a display area 100, a binding area 200 located on one side of the display area 100 in the second direction Y, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 73, a plurality of first data connection lines 81, and a plurality of second data connection lines 82. At least one circuit unit may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, at least one of which may include a light-emitting device connected to a pixel driving circuit of a corresponding circuit unit. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0131] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0132] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0133] In an exemplary embodiment, the first data connection line 81 can be in the shape of a straight line or a zigzag line extending along the first direction X, and the data signal line 73 and the second data connection line 82 can be in the shape of a straight line or a zigzag line extending along the second direction Y. At least one data signal line 73 is connected to multiple pixel driving circuits in a cell column, and the data signal line 73 is configured to provide data signals to the connected pixel driving circuit. One end of at least one first data connection line 81 is connected to a data signal line 73, and the other end is connected to one end of a second data connection line 82. The other end of the second data connection line 82 extends to the binding area and is connected to a data lead-out line 80. This connects the data signal line 73 in the display area to the data lead-out line 80 in the binding area 200 via the first data connection line 81 and the second data connection line 82, forming a data connection line fanout in the display area (FIAA) structure. In an exemplary embodiment, the data connection lines include the first data connection line 81 and the second data connection line 82.

[0134] In an exemplary embodiment, the binding area 200 may include a lead line area 201, a bend area 202, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area. The lead line area 201 is connected to the display area 100, and the bend area 202 is connected to the lead line area 201. The lead line area 201 may be provided with a plurality of data lead lines 80, which extend in a direction away from the display area. The first ends of some of the data lead lines 80 are correspondingly connected to the second data connection lines 82 in the display area 100, and the first ends of another portion of the data lead lines 80 are correspondingly connected to the data signal lines 73 in the display area 100. The second ends of all the data lead lines 80 extend along the second direction Y, cross the bend area, and are connected to the integrated circuit in the driver chip area, so that the integrated circuit applies data signals to the data signal lines via the data lead lines and the data connection lines. Since the first data connection line 81 and the second data connection line 82 are arranged in the display area, the length of the lead line area in the second direction Y can be effectively reduced, the width of the lower frame can be greatly reduced, the screen-to-body ratio is increased, and it is conducive to achieving full-screen display.

[0135] FIG7B is a schematic diagram of the structure of a data connection line according to an exemplary embodiment of the present disclosure. As shown in FIG7B , since the first data connection line 81 and the second data connection line 82 are provided in a portion of the display area, the display area can be divided into a first area 110, a second area 120, and a third area 130 based on the presence or absence of the data connection line and the direction in which the data connection line extends. The first area 110 can be the area where the first data connection line 81 is provided (which can be referred to as the area where the connection line is horizontally routed), the second area 120 can be the area where the second data connection line 82 is provided (which can be referred to as the area where the connection line is vertically routed), and the third area 130 can be the area where the first data connection line 81 and the second data connection line 82 are not provided (which can be referred to as the normal area). The first area 110, the second area 120, and the third area 130 are all provided with data signal lines 73.

[0136] In the exemplary embodiment, the division of the various regions shown in FIG8 is merely an example. Since the first region 110, the second region 120, and the third region 130 are divided based on the presence or absence of data connection lines and the direction in which the data connection lines extend, the shapes of the three regions can be regular polygons or irregular polygons. The display area can be divided into one or more first regions 110, one or more second regions 120, and one or more third regions 130, but this disclosure does not limit this.

[0137] FIG8 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, which is an enlarged view of the area A in FIG7B , illustrating the structure of a circuit unit having one circuit row and four circuit columns. As shown in FIG8 , in a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of which may include a pixel driving circuit, which may be connected to a first scanning signal line 61, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a light-emitting signal line 65, a reference signal line 66, an initial signal line 67, a first power supply line 71, and a data signal line 73, respectively. The first scanning signal line 61 to the fourth scanning signal line 64 are configured to provide the first scanning signal to the fourth scanning signal, respectively, to the pixel driving circuit, the light-emitting signal line 63 is configured to provide the light-emitting control signal to the pixel driving circuit, and the reference signal line 66, the initial signal line 67, the first power supply line 71, and the data signal line 73 are configured to provide the reference signal, the initial signal, the first power supply signal, and the data signal, respectively, to the pixel driving circuit. The plurality of signal lines connected to the pixel driving circuit may be located within the circuit unit.

[0138] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the light-emitting signal line 65, the reference signal line 66 and the initial signal line 67 can be straight lines or zigzag lines extending along the first direction X, the shape of the first power line 71 can be a zigzag line extending along the second direction Y, and the shape of the data signal line 73 can be a straight line extending along the second direction Y.

[0139] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the first direction X may be the direction of unit rows, and the second direction Y may be the direction of unit columns.

[0140] In an exemplary embodiment, multiple circuit units on a display substrate can be compressed horizontally and vertically to create routing spaces, with the routing spaces configured to accommodate first and second data connection lines 81 and 82. Specifically, two unit columns can be grouped together, and a vertical routing space can be compressed horizontally to create one vertical routing space. That is, a vertical routing space for arranging the second data connection line 82 is compressed every two unit columns. Four unit rows can be grouped together, and a horizontal routing space can be compressed vertically to create one horizontal routing space. That is, a horizontal routing space for arranging the first data connection line 81 is compressed every four unit rows.

[0141] In an exemplary embodiment, the pixel driving circuit may include at least a first capacitor, a second capacitor, and a plurality of oxide transistors. The plurality of oxide transistors may include a first transistor T1 serving as a first reset transistor, a second transistor T2 serving as a second reset transistor, a third transistor T3 serving as a drive transistor, a fourth transistor T4 serving as a data write transistor, a fifth transistor T5 serving as a light emission control transistor, a sixth transistor T6 serving as a data control transistor, and a seventh transistor T7 serving as a third reset transistor. The first capacitor may include a stacked first plate and a second plate, and the second capacitor may include a stacked third plate and a fourth plate.

[0142] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first electrode of the first transistor T1 is connected to the reference signal line 66, and the second electrode of the first transistor T1 is connected to the gate electrode of the third transistor T3. The gate electrode of the second transistor T2 is connected to the first scan signal line 61, the first electrode of the second transistor T2 is connected to the reference signal line 66, and the second electrode of the second transistor T2 is connected to the first plate of the first capacitor and the third plate of the second capacitor, respectively. The first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5, and the second electrode of the third transistor T3 is connected to the second plate of the first capacitor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first electrode of the fourth transistor T4 is connected to the data signal line 73, and the second electrode of the fourth transistor T4 is connected to the fourth plate of the second capacitor. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 65, and the first electrode of the fifth transistor T5 is connected to the first power line 71. The gate electrode of the sixth transistor T6 is connected to the fourth scanning signal line 64, the first electrode of the sixth transistor T6 is connected to the gate electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the fourth plate of the second capacitor. The gate electrode of the seventh transistor T7 is connected to the second scanning signal line 62, the first electrode of the seventh transistor T7 is connected to the initial signal line 67, and the second electrode of the seventh transistor T7 is connected to the second plate of the first capacitor.

[0143] In an exemplary embodiment, the width-to-length ratio of the third transistor T3 may be 1.25 to 2.67.

[0144] In an exemplary embodiment, in at least one circuit unit, an orthographic projection of the data signal line 73 on the substrate does not overlap with an orthographic projection of the channel regions of the first to seventh transistors T1 to T7 on the substrate.

[0145] In an exemplary embodiment, at least one circuit unit may further include at least one first power connection line 68 extending along the first direction X, and the first power line 71 and the first power connection line 68 are interconnected to form a mesh structure for transmitting the first power signal.

[0146] In an exemplary embodiment, an orthographic projection of the first power line 71 on the substrate at least partially overlaps with orthographic projections of the first transistor T1 , the fourth transistor T4 , and the sixth transistor T6 on the substrate.

[0147] In an exemplary embodiment, at least one circuit unit may further include a second power line 72 , and the shape of the second power line 72 may be a zigzag line extending along the second direction Y or a zigzag line.

[0148] In an exemplary embodiment, the width of the second power line 72 may be greater than the width of the first power line 71 , and the width may be a dimension in the first direction X.

[0149] In an exemplary embodiment, an orthographic projection of the second power line 72 on the substrate at least partially overlaps with orthographic projections of the third transistor T3 , the fifth transistor T5 , and the seventh transistor T7 on the substrate.

[0150] In an exemplary embodiment, the drive structure layer may further include at least one first data connection line 81 and at least one second data connection line 82. The first data connection line 81 may be in the shape of a straight line or a zigzag line extending along a first direction X and may be arranged in the horizontal routing space between cell rows. The second data connection line 82 may be in the shape of a straight line or a zigzag line extending along a second direction Y and may be arranged in the vertical routing space between cell columns. One end of the at least one first data connection line 81 is connected to the data signal line 73, and the other end is connected to the second data connection line 82, forming a structure in which the data connection lines are located in the display area.

[0151] In an exemplary embodiment, at least one second data link line 82 may be disposed between adjacent first power lines 71 in the first direction X. For example, the second data link line 82 may be disposed between the first power line 71 in the Nth unit column and the first power line 71 in the N+1th unit column. For another example, the second data link line 82 may be disposed between the first power line 71 in the N+2th unit column and the first power line 71 in the N+3th unit column.

[0152] In an exemplary embodiment, at least one circuit unit may further include a data connection block 83 and a data connection electrode 84, the data connection electrode 84 being connected to the first data connection line 81 through the data connection block 83, and the second data connection line 82 being connected to the data connection electrode 84 through a via, thereby realizing the connection between the first data connection line 81 and the second data connection line 82.

[0153] In an exemplary embodiment, the first data connection line 81 , the data connection block 83 , and the data connection electrode 84 may be an integral structure connected to each other.

[0154] In an exemplary embodiment, at least one circuit unit may further include a dummy electrode 85, and the second data connection line 82 may be connected to the dummy electrode 85 through a via. The position and shape of the dummy electrode 85 in one circuit unit may be substantially the same as the position and shape of the data connection electrode 84 in another circuit unit, so that the data connection electrode 84 and the dummy electrode 85 have the same morphology and via connection structure.

[0155] In an exemplary embodiment, at least one first data connection line 81 may be provided with a first break K1, which cuts off the first data connection line 81. The orthographic projection of the first break K1 on the substrate at least partially overlaps with the orthographic projection of the first power line 71 or the second power line 72 on the substrate.

[0156] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate may be located within the range of the orthographic projection of the first power line 71 or the second power line 72 on the substrate.

[0157] In an exemplary embodiment, at least one second data connection line 82 may be provided with a second break K2 that cuts off the second data connection line 82. The orthographic projection of the second break K2 on the substrate at least partially overlaps with the orthographic projection of the reference signal line 66 or the initial signal line 67 on the substrate.

[0158] In an exemplary embodiment, the orthographic projection of the second break K2 on the substrate may be located within the range of the orthographic projection of the reference signal line 66 or the initial signal line 67 on the substrate.

[0159] In an exemplary embodiment, within a unit row, the pixel driving circuits in two adjacent circuit units may be symmetrically arranged relative to a column centerline, where the column centerline may be a straight line located between two adjacent circuit units in the first direction X and extending along the second direction Y. For example, the pixel driving circuits in the Nth unit column and the N+1th unit column may be symmetrically arranged relative to the column centerline. For another example, the pixel driving circuits in the N+1th unit column and the N+2th unit column may be symmetrically arranged relative to the column centerline.

[0160] In an exemplary embodiment, pixel driving circuits in adjacent unit rows may be substantially the same.

[0161] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving circuit layer may include at least a first conductive layer (first gate metal layer), a second conductive layer (second gate metal layer), a semiconductor layer, a third conductive layer (third gate metal layer), a fourth conductive layer (first source-drain metal layer), and a fifth conductive layer (second source-drain metal layer), which are sequentially arranged in a direction away from the substrate. The first plate of the first capacitor and the third plate of the second capacitor may be arranged in the first conductive layer, the second plate of the first capacitor and the fourth plate of the second capacitor may be arranged in the second conductive layer, the second scan signal line 62 and the light emitting signal line 65 may be arranged in the third conductive layer, the first scan signal line 61, the third scan signal line 63, the fourth scan signal line 64, the reference signal line 66, the initial signal line 67, and the first data connection line 81 may be arranged in the fourth conductive layer, and the first power line 71, the second power line 72, the data signal line 73, and the second data connection line 82 may be arranged in the fifth conductive layer.

[0162] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating, and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching, and this disclosure does not limit this. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are provided in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0163] In an exemplary embodiment, taking four circuit units of one unit row (Mth unit row) and four unit columns (Nth unit column, N+1th unit column, N+2th unit column, N+3th unit column) as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0164] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG9 . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0165] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least a first plate 11 of a first capacitor, a third plate 13 of a second capacitor, and a plate connection block 15 .

[0166] In an exemplary embodiment, the first electrode plate 11 of the first capacitor may be shaped like a wine glass, and the corners of the wine glass may be chamfered or grooved. The first electrode plate 11 may serve as the lower electrode plate of the first capacitor.

[0167] In an exemplary embodiment, the third plate 13 of the second capacitor can be arranged on the side of the first plate 11 in the opposite direction of the second direction Y. The shape of the third plate 13 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The third plate 13 can serve as the lower plate of the second capacitor.

[0168] In an exemplary embodiment, the first electrode plate 11 and the third electrode plate 13 may be an integrated structure connected to each other, that is, the lower electrode plate of the first capacitor and the lower electrode plate of the second capacitor are an integrated structure.

[0169] In an exemplary embodiment, the plate connection block 15 may be in the shape of a block (e.g., a rectangle), and may be disposed on one side of the first electrode 11 in the first direction X or on the side opposite to the first direction X, and connected to the first electrode 11. The plate connection block 15 is configured to be connected to a fourth connection electrode formed subsequently.

[0170] In an exemplary embodiment, the first electrode plate 11 , the third electrode plate 13 , and the electrode plate connecting block 15 may be an integral structure connected to each other.

[0171] In an exemplary embodiment, the spacing between the first conductive layers of two adjacent circuit cells in a cell row may be different. For example, the spacing between the first conductive layer in the Nth cell column and the first conductive layer in the N+1th cell column may be greater than the spacing between the first conductive layer in the N+1th cell column and the first conductive layer in the N+2th cell column.

[0172] In an exemplary embodiment, in a cell row, the first conductive layers of two adjacent circuit cells may be symmetrically arranged relative to a column centerline, where the column centerline may be a straight line located between two adjacent circuit cells in the first direction X and extending along the second direction Y. For example, the first conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the first conductive layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0173] In example embodiments, the first conductive layers in adjacent cell rows may be substantially the same.

[0174] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on the substrate having the aforementioned pattern, patterning the second conductive film through a patterning process to form a first insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0175] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second plate 12 of the first capacitor, a fourth plate 14 of the second capacitor, a first bottom gate electrode 21, a second bottom gate electrode 22, a fourth bottom gate electrode 24, a sixth bottom gate electrode 26, a first shielding line 27 and a second shielding line 28.

[0176] In an exemplary embodiment, the second plate 12 of the first capacitor may be shaped like a wine glass, and the orthographic projection of the second plate 12 on the substrate at least partially overlaps the orthographic projection of the first plate 11 on the substrate. In an exemplary embodiment, the second plate 12 may serve as the upper plate of the first capacitor, and the first plate 11 and the second plate 12 constitute the first capacitor.

[0177] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 on the substrate is located within the range of the orthographic projection of the first electrode plate 11 on the substrate.

[0178] In an exemplary embodiment, the fourth electrode plate 14 of the second capacitor can be disposed on a side of the second electrode plate 12 opposite to the second direction Y. The fourth electrode plate 14 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps the orthographic projection of the third electrode plate 13 on the substrate. In an exemplary embodiment, the third electrode plate 13 and the fourth electrode plate 14 constitute the second capacitor.

[0179] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 14 on the substrate is located within the range of the orthographic projection of the third electrode plate 13 on the substrate.

[0180] In an exemplary embodiment, the shape of the first bottom gate electrode 21 can be block-shaped (such as a rectangle) and can be arranged on one side of the second electrode plate 12 in the first direction X or on the side opposite to the first direction X. The first bottom gate electrode 21 can serve as the bottom gate electrode of the first transistor T1 and can also serve as a shielding layer of the first transistor T1 to shield the channel region of the first transistor T1 and ensure the electrical performance of the oxide first transistor T1.

[0181] In an exemplary embodiment, the second bottom gate electrode 22 may be in a block shape (such as a rectangle) and may be disposed between the second electrode plate 12 and the first bottom gate electrode 21. The second bottom gate electrode 22 may serve as the bottom gate electrode of the second transistor T2 and may also serve as a shielding layer of the second transistor T2 to shield the channel region of the second transistor T2 and ensure the electrical performance of the oxide second transistor T2.

[0182] In an exemplary embodiment, in at least one circuit unit, the first bottom-gate electrode 21 and the second bottom-gate electrode 22 are an integral structure connected to each other.

[0183] In an exemplary embodiment, the first bottom gate electrodes 21 of two adjacent circuit cells in the first direction X may be interconnected as an integral structure. For example, the first bottom gate electrode 21 of the Nth cell column and the first bottom gate electrode 21 of the N+1th cell column may be interconnected as an integral structure. For another example, the first bottom gate electrode 21 of the N+2th cell column and the first bottom gate electrode 21 of the N+3th cell column may be interconnected as an integral structure.

[0184] In this exemplary embodiment, since the first bottom gate electrode 21 and the second bottom gate electrode 22 in a circuit unit are interconnected as an integral structure, the first bottom gate electrodes 21 and the second bottom gate electrodes 22 of two adjacent circuit units in the first direction X are also interconnected as an integral structure. For example, the first bottom gate electrodes 21 and the second bottom gate electrodes 22 in the Nth and N+1th cell columns in a cell row can be interconnected as an integral structure. For another example, the first bottom gate electrodes 21 and the second bottom gate electrodes 22 in the N+2th and N+3th cell columns in a cell row can be interconnected as an integral structure.

[0185] In an exemplary embodiment, a first bottom gate connection block 21-1 may be provided on the first bottom gate electrode 21. The first bottom gate connection block 21-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the first bottom gate electrode 21 away from the sixth bottom gate electrode 26 and connected to the first bottom gate electrode 21. The first bottom gate connection block 21-1 is configured to be connected to a first scan signal line formed subsequently.

[0186] In an exemplary embodiment, the first bottom gate connection block 21-1 can be arranged in the middle position of the first bottom gate electrode 21 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the first bottom gate electrodes 21 of the two circuit units share the same first bottom gate connection block 21-1.

[0187] The present disclosure provides an integrated structure in which the first bottom gate electrodes of adjacent circuit units are interconnected, so that the first transistors T1 of two adjacent pixel driving circuits share the same bottom gate electrode and bottom gate connection block. This can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units while ensuring the display resolution (PPI).

[0188] In an exemplary embodiment, the shape of the fourth bottom gate electrode 24 can be block-shaped (such as a rectangle) and can be arranged on one side of the fourth electrode plate 14 in the first direction X or on the side opposite to the first direction X. The fourth bottom gate electrode 24 can serve as the bottom gate electrode of the fourth transistor T4 and can also serve as a shielding layer of the fourth transistor T4 to shield the channel region of the fourth transistor T4 and ensure the electrical performance of the oxide fourth transistor T4.

[0189] In an exemplary embodiment, the fourth bottom gate electrodes 24 of two adjacent circuit cells in the first direction X may be interconnected as an integral structure. For example, the fourth bottom gate electrode 24 of the Nth cell column and the fourth bottom gate electrode 24 of the N+1th cell column may be interconnected as an integral structure. For another example, the fourth bottom gate electrode 24 of the N+2th cell column and the fourth bottom gate electrode 24 of the N+3th cell column may be interconnected as an integral structure.

[0190] In an exemplary embodiment, a fourth bottom gate connection block 24-1 may be provided on the fourth bottom gate electrode 24. The fourth bottom gate connection block 24-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the fourth bottom gate electrode 24 away from the sixth bottom gate electrode 26 and connected to the fourth bottom gate electrode 24. The fourth bottom gate connection block 24-1 is configured to be connected to a third scan signal line formed subsequently.

[0191] In an exemplary embodiment, the fourth bottom gate connection block 24-1 can be arranged in the middle position of the fourth bottom gate electrode 24 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the fourth bottom gate electrodes 24 of the two circuit units share the same fourth bottom gate connection block 24-1.

[0192] The present disclosure provides an integrated structure in which the fourth bottom gate electrodes of adjacent circuit units are interconnected, so that the fourth transistors T4 of two adjacent pixel driving circuits share the same bottom gate electrode and bottom gate connection block. This can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units while ensuring the display resolution (PPI).

[0193] In an exemplary embodiment, the shape of the sixth bottom gate electrode 26 can be block-shaped (such as a rectangle), and can be arranged on one side of the fourth electrode plate 14 in the first direction X or on the side opposite to the first direction X, and is located on one side of the fourth bottom gate electrode 24 in the second direction Y. The sixth bottom gate electrode 26 can serve as the bottom gate electrode of the sixth transistor T6, and can also serve as a shielding layer of the sixth transistor T6 to shield the channel region of the sixth transistor T6 and ensure the electrical performance of the oxide sixth transistor T6.

[0194] In an exemplary embodiment, the sixth bottom gate electrodes 26 of two adjacent circuit cells in some first directions X may be interconnected as a single unit. For example, the sixth bottom gate electrode 26 of the Nth unit column and the sixth bottom gate electrode 26 of the N+1th unit column may be interconnected as a single unit. For another example, the sixth bottom gate electrode 26 of the N+2th unit column and the sixth bottom gate electrode 26 of the N+3th unit column may be interconnected as a single unit.

[0195] In an exemplary embodiment, a sixth bottom gate connection block 26-1 may be provided on the sixth bottom gate electrode 26. The sixth bottom gate connection block 26-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the sixth bottom gate electrode 26 close to the first bottom gate electrode 21 and connected to the sixth bottom gate electrode 26. The sixth bottom gate connection block 26-1 is configured to be connected to a fourth scan signal line formed subsequently.

[0196] In an exemplary embodiment, the sixth bottom gate connection block 26-1 can be arranged in the middle position of the sixth bottom gate electrode 26 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the sixth bottom gate electrodes 26 of the two circuit units share the same sixth bottom gate connection block 26-1.

[0197] The present disclosure provides an integrated structure in which the sixth bottom gate electrodes of adjacent circuit units are interconnected, so that the sixth transistors T6 of two adjacent pixel driving circuits share the same bottom gate electrode and bottom gate connection block. This can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units while ensuring the display resolution (PPI).

[0198] In an exemplary embodiment, the first shielding line 27 may be in the shape of a straight line or a broken line extending along the first direction X and may be disposed on the side of the second electrode plate 12 away from the fourth electrode plate 14. In an exemplary embodiment, the first shielding line 27 may be a straight line of varying width. The width of the first shielding line 27 at the location where it overlaps with the subsequently formed seventh active layer may be greater than the width at other locations. The first shielding line 27 at the wider location may serve as a shielding layer for the seventh transistor T7, thereby shielding the channel region of the seventh transistor T7 and ensuring the electrical performance of the oxide seventh transistor T7. In an exemplary embodiment, the first shielding line 27 may also serve as the bottom gate electrode of the seventh transistor T7.

[0199] In an exemplary embodiment, the second shielding line 28 may be in the shape of a straight line or a broken line extending along the first direction X and may be disposed on the side of the fourth electrode plate 14 away from the second electrode plate 12. In an exemplary embodiment, the second shielding line 28 may be a straight line of varying width. The width of the second shielding line 28 at the location where it overlaps with the subsequently formed fifth active layer may be greater than the width at other locations. The second shielding line 28 at the wider location may serve as a shielding layer for the fifth transistor T5, thereby shielding the channel region of the fifth transistor T5 and ensuring the electrical performance of the oxide-based fifth transistor T5. In an exemplary embodiment, the second shielding line 28 may also serve as the bottom gate electrode of the fifth transistor T5.

[0200] In an exemplary embodiment, the second conductive layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the second conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the second conductive layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0201] In example embodiments, the second conductive layers in adjacent cell rows may be substantially the same.

[0202] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a second insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the semiconductor layer in FIG11A .

[0203] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include a first active layer 31 of the first transistor T1 to a seventh active layer 37 of the seventh transistor T7, and the first active layer 31, the second active layer 32, the fourth active layer 34 and the sixth active layer 36 may be an integrated structure connected to each other, and the third active layer 33, the fifth active layer 35 and the seventh active layer 37 may be an integrated structure connected to each other.

[0204] In an exemplary embodiment, in the first direction X, the first active layer 31, the second active layer 32, the fourth active layer 34, and the sixth active layer 36 may be located on the same side of the third active layer 33 in the first direction X. In the second direction Y, the fourth active layer 34 and the fifth active layer 35 may be located on a side of the third active layer 33 in the opposite direction of the second direction Y, and the first active layer 31, the second active layer 32, and the seventh active layer 37 may be located on one side of the third active layer 33 in the second direction Y.

[0205] In an exemplary embodiment, the third active layer 33 may have a hexagonal shape, the first active layer 31, the second active layer 32, the fourth active layer 34, the fifth active layer 35, and the sixth active layer 36 may have a strip shape extending along the second direction Y, and the seventh active layer 37 may have an "L" shape.

[0206] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The orthographic projection of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the first bottom-gate electrode 21 on the substrate, and the overlapping region may serve as the channel region of the first transistor T1. The orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the second bottom-gate electrode 22 on the substrate, and the overlapping region may serve as the channel region of the second transistor T2. The orthographic projection of the third active layer 33 on the substrate at least partially overlaps with the orthographic projection of the second electrode 12 (the bottom-gate electrode of the third transistor T3) on the substrate, and the overlapping region may serve as the channel region of the third transistor T3. The orthographic projection of the fourth active layer 34 on the substrate at least partially overlaps with the orthographic projection of the fourth bottom-gate electrode 24 on the substrate, and the overlapping region serves as the channel region of the fourth transistor T4. The orthographic projection of the fifth active layer 35 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 28 on the substrate, and the overlapping area serves as the channel region of the fifth transistor T5. The orthographic projection of the sixth active layer 36 on the substrate at least partially overlaps with the orthographic projection of the sixth bottom-gate electrode 26 on the substrate, and the overlapping area serves as the channel region of the sixth transistor T6. The orthographic projection of the seventh active layer 37 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 27 on the substrate, and the overlapping area serves as the channel region of the seventh transistor T7.

[0207] In an exemplary embodiment, the first region 31-1 of the first active layer and the first region 32-1 of the second active layer may be connected to each other, and the first region 31-1 of the first active layer may serve as the first region 32-1 of the second active layer. The second region 31-2 of the first active layer and the first region 36-1 of the sixth active layer may be connected to each other, and the second region 31-2 of the first active layer may serve as the first region 36-1 of the sixth active layer. The first region 33-1 of the third active layer and the second region 35-2 of the fifth active layer may be connected to each other, and the first region 33-1 of the third active layer may serve as the second region 35-2 of the fifth active layer. The second region 33-2 of the third active layer and the second region 37-2 of the seventh active layer may be connected to each other, and the second region 33-2 of the third active layer may serve as the second region 37-2 of the seventh active layer. The second region 34-2 of the fourth active layer and the second region 36-2 of the sixth active layer may be connected to each other, and the second region 34-2 of the fourth active layer may serve as the second region 36-2 of the sixth active layer. The second region 32 - 2 of the second active layer, the first region 34 - 1 of the fourth active layer 34 , the first region 35 of the fifth active layer 35 , and the first region 37 - 1 of the seventh active layer may be separately provided.

[0208] In an exemplary embodiment, within a cell row, the semiconductor layers of two adjacent circuit cells may be symmetrically arranged relative to the column centerline. For example, the semiconductor layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the semiconductor layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0209] In example embodiments, semiconductor layers in adjacent cell rows may be substantially the same.

[0210] In an exemplary embodiment, the semiconductor layer may be made of an oxide, meaning that the first to seventh transistors T1 to T7 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc oxynitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.

[0211] (14) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process to form a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0212] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate includes at least: a first top gate electrode 41, a second top gate electrode 42, a third top gate electrode 43, a fourth top gate electrode 44, a sixth top gate electrode 46, a second scan signal line 62 and a light emitting signal line 65.

[0213] In an exemplary embodiment, the first top-gate electrode 41 may be block-shaped (e.g., rectangular), and the orthographic projection of the first top-gate electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first top-gate electrode 41 may serve as the top-gate electrode of the first transistor T1. In an exemplary embodiment, the orthographic projection of the first top-gate electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first bottom-gate electrode 21 on the substrate. The first top-gate electrode 41 and the first bottom-gate electrode 21 form the first transistor T1 with a top-gate and bottom-gate structure.

[0214] In an exemplary embodiment, the second top-gate electrode 42 may be block-shaped (e.g., rectangular), and the orthographic projection of the second top-gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second top-gate electrode 42 may serve as the top-gate electrode of the second transistor T2. In an exemplary embodiment, the orthographic projection of the second top-gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second bottom-gate electrode 22 on the substrate. The second top-gate electrode 42 and the second bottom-gate electrode 22 form the second transistor T2 with a top-gate and bottom-gate structure.

[0215] In an exemplary embodiment, in at least one circuit unit, the first top gate electrode 41 and the second top gate electrode 42 are an integral structure connected to each other.

[0216] In an exemplary embodiment, the first top gate electrodes 41 of two adjacent circuit cells in the first direction X may be interconnected as an integral structure. For example, the first top gate electrode 41 of the Nth cell column and the first top gate electrode 41 of the N+1th cell column may be interconnected as an integral structure. For another example, the first top gate electrode 41 of the N+2th cell column and the first top gate electrode 41 of the N+3th cell column may be interconnected as an integral structure.

[0217] In this exemplary embodiment, since the first top gate electrode 41 and the second top gate electrode 42 in a circuit unit are interconnected as an integral structure, the first top gate electrodes 41 and the second top gate electrodes 42 of two adjacent circuit units in the first direction X are also interconnected as an integral structure. For example, the first top gate electrode 41 and the second top gate electrode 42 in the Nth cell column and the N+1th cell column in a cell row can be interconnected as an integral structure. For another example, the first top gate electrode 41 and the second top gate electrode 42 in the N+2th cell column and the N+3th cell column in a cell row can be interconnected as an integral structure.

[0218] In an exemplary embodiment, a first top gate connection block 41-1 may be provided on the first top gate electrode 41. The first top gate connection block 41-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the first top gate electrode 41 close to the sixth top gate electrode 46 and connected to the first top gate electrode 41. The first top gate connection block 41-1 is configured to be connected to a first scan signal line formed subsequently.

[0219] In an exemplary embodiment, the first top gate connection block 41-1 can be set in the middle position of the first top gate electrode 41 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the first top gate electrodes 41 of the two circuit units share the same first top gate connection block 41-1.

[0220] The present disclosure provides an integrated structure in which the first top gate electrodes of adjacent circuit units are interconnected, so that the first transistors T1 of two adjacent pixel driving circuits share the same top gate electrode and top gate connection block. This can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units while ensuring the display resolution (PPI).

[0221] In an exemplary embodiment, the shape of the third top gate electrode 43 can be a strip shape extending along the first direction X, the orthographic projection of the third top gate electrode 43 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate, and the third top gate electrode 43 can serve as the gate electrode of the third transistor T3, which is a transistor with a top gate structure.

[0222] In an exemplary embodiment, the fourth top-gate electrode 44 may be block-shaped (e.g., rectangular), and the orthographic projection of the fourth top-gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth top-gate electrode 44 may serve as the top-gate electrode of the fourth transistor T4. In an exemplary embodiment, the orthographic projection of the fourth top-gate electrode 44 on the substrate at least partially overlaps with the orthographic projection of the fourth bottom-gate electrode 24 on the substrate. The fourth top-gate electrode 44 and the fourth bottom-gate electrode 24 form the fourth transistor T4 with a top-gate and bottom-gate structure.

[0223] In an exemplary embodiment, the fourth top gate electrodes 44 of two adjacent circuit cells in some first directions X may be interconnected as an integral structure. For example, the fourth top gate electrode 44 of the Nth cell column and the fourth top gate electrode 44 of the N+1th cell column may be interconnected as an integral structure. For another example, the fourth top gate electrode 44 of the N+2th cell column and the fourth top gate electrode 44 of the N+3th cell column may be interconnected as an integral structure.

[0224] In an exemplary embodiment, a fourth top gate connection block 44-1 may be provided on the fourth top gate electrode 44. The fourth top gate connection block 44-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the fourth top gate electrode 44 close to the sixth top gate electrode 46 and connected to the fourth top gate electrode 44. The fourth top gate connection block 44-1 is configured to be connected to a third scan signal line formed subsequently.

[0225] In an exemplary embodiment, the fourth top gate connection block 44-1 can be set in the middle position of the fourth top gate electrode 44 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the fourth top gate electrodes 44 of the two circuit units share the same fourth top gate connection block 44-1.

[0226] The present disclosure provides an integrated structure in which the fourth top gate electrodes of adjacent circuit units are interconnected, so that the fourth transistors T4 of two adjacent pixel driving circuits share the same top gate electrode and top gate connection block. This can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units while ensuring the display resolution (PPI).

[0227] In an exemplary embodiment, the sixth top-gate electrode 46 may be block-shaped (e.g., rectangular), and the orthographic projection of the sixth top-gate electrode 46 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate. The sixth top-gate electrode 46 may serve as the top-gate electrode of the sixth transistor T6. In an exemplary embodiment, the orthographic projection of the sixth top-gate electrode 46 on the substrate at least partially overlaps with the orthographic projection of the sixth bottom-gate electrode 26 on the substrate. The sixth top-gate electrode 46 and the sixth bottom-gate electrode 26 form a sixth transistor T6 with a top-gate and bottom-gate structure.

[0228] In an exemplary embodiment, the sixth top gate electrodes 46 of two adjacent circuit cells in some first directions X may be interconnected as a single unit. For example, the sixth top gate electrode 46 of the Nth unit column and the sixth top gate electrode 46 of the N+1th unit column may be interconnected as a single unit. For another example, the sixth top gate electrode 46 of the N+2th unit column and the sixth top gate electrode 46 of the N+3th unit column may be interconnected as a single unit.

[0229] In an exemplary embodiment, a sixth top gate connection block 46-1 may be provided on the sixth top gate electrode 46. The sixth top gate connection block 46-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the sixth top gate electrode 46 away from the first top gate electrode 41 and connected to the sixth top gate electrode 46. The sixth top gate connection block 46-1 is configured to be connected to a fourth scan signal line formed subsequently.

[0230] In an exemplary embodiment, the sixth top gate connection block 46-1 can be set in the middle position of the sixth top gate electrode 46 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the sixth top gate electrodes 46 of the two circuit units share the same sixth top gate connection block 46-1.

[0231] The present disclosure provides an integrated structure in which the sixth top gate electrodes of adjacent circuit units are interconnected, so that the sixth transistors T6 of two adjacent pixel driving circuits share the same top gate electrode and top gate connection block. This can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units while ensuring the display resolution (PPI).

[0232] In an exemplary embodiment, the shape of the second scan signal line 62 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side of the second electrode plate 12 away from the fourth electrode plate 14. The area where the second scan signal line 62 overlaps with the seventh active layer serves as the top gate electrode of the seventh transistor T7.

[0233] In an exemplary embodiment, the second scan signal line 62 may be a straight line of unequal width. The width of the second scan signal line 62 at the location where it overlaps with the seventh active layer may be greater than the width at other locations. The orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 27 on the substrate. The second scan signal line 62 and the first shielding line 27 may be connected to the same signal source, so that the first shielding line 27 can serve as the bottom gate electrode of the seventh transistor T7, and the second scan signal line 62 can serve as the top gate electrode of the seventh transistor T7, forming the seventh transistor T7 with a top-gate and bottom-gate structure.

[0234] In an exemplary embodiment, the shape of the light-emitting signal line 65 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side of the fourth electrode 14 away from the second electrode 12. The area where the light-emitting signal line 65 overlaps with the fifth active layer serves as the top gate electrode of the fifth transistor T5.

[0235] In an exemplary embodiment, the light-emitting signal line 65 may be a straight line of unequal width. The width of the light-emitting signal line 65 at the location where it overlaps with the fifth active layer may be greater than the width at other locations. The orthographic projection of the light-emitting signal line 65 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 28 on the substrate. The light-emitting signal line 65 and the second shielding line 28 may be connected to the same signal source, so that the second shielding line 28 can serve as the bottom gate electrode of the fifth transistor T5, and the light-emitting signal line 65 can serve as the top gate electrode of the fifth transistor T5, forming a top-gate and bottom-gate structure of the fifth transistor T5.

[0236] In an exemplary embodiment, the third conductive layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the third conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. For another example, the third conductive layers of the N+1th cell column and the N+2th cell column may be symmetrically arranged relative to the column centerline.

[0237] In example embodiments, the third conductive layers in adjacent cell rows may be substantially the same.

[0238] In an exemplary embodiment, after forming the third conductive layer pattern, the third conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the second conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the third conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer to the seventh active layer are both conductorized.

[0239] FIG12C is an enlarged view of the third transistor in FIG12A . As shown in FIG12A , FIG12B , and FIG12C , the overlapping area between the orthographic projection of the third top gate electrode 43 on the substrate and the orthographic projection of the third active layer on the substrate constitutes the channel region of the third transistor T3. The channel region has a channel length L and a channel width W. The channel length L is the dimension in the second direction Y, and the channel width W is the dimension in the first direction X.

[0240] In an exemplary embodiment, the aspect ratio of the third transistor T3 serving as the driving transistor is a ratio of a channel width W to a channel length L, ie, W / L.

[0241] In an exemplary embodiment, the width-to-length ratio W / L of the third transistor T3 may be less than 1. The width-to-length ratio W / L of the third transistor T3 may be approximately 0.27 to 0.8. For example, the width-to-length ratio W / L may be approximately 6 / 10, or approximately 6 / 14, or approximately 6 / 18, or approximately 6 / 22. For another example, the width-to-length ratio W / L may be approximately 8 / 10, or approximately 8 / 14, or approximately 8 / 18, or approximately 8 / 22.

[0242] In a preferred embodiment, the width-to-length ratio W / L of the third transistor T3 may be approximately 0.44 to 0.8. For example, the width-to-length ratio W / L may be approximately 8 / 10. For another example, the width-to-length ratio W / L may be approximately 8 / 14. For another example, the width-to-length ratio W / L may be approximately 8 / 18.

[0243] In another exemplary embodiment, the width-to-length ratio W / L of the third transistor T3 may be greater than 1. The width-to-length ratio W / L of the third transistor T3 may be approximately 1.25 to 2.67. For example, the width-to-length ratio W / L may be approximately 10 / 6, or approximately 12 / 6, or approximately 14 / 6, or approximately 16 / 6. For another example, the width-to-length ratio W / L may be approximately 10 / 8, or approximately 12 / 8, or approximately 14 / 8, or approximately 16 / 8.

[0244] In a preferred embodiment, the width-to-length ratio W / L of the third transistor T3 may be approximately 1.67 to 2.67. For example, the width-to-length ratio W / L may be approximately 10 / 6. For another example, the width-to-length ratio W / L may be approximately 12 / 6. For another example, the width-to-length ratio W / L may be approximately 14 / 6 or 16 / 6.

[0245] The present disclosure can effectively improve the driving performance of the pixel driving circuit and enhance the display quality by setting the width-to-length ratio of the third transistor T3.

[0246] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein the fourth insulating layer is provided with a plurality of vias, as shown in FIG. 13 .

[0247] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17 and an eighteenth via V18.

[0248] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the first region of the first active layer (also the first region of the second active layer) on the substrate. The third and fourth insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer (also the first region of the second active layer). The first via V1 is configured to connect a subsequently formed reference signal line to the first region of the first active layer (also the first region of the second active layer) through the via. In an exemplary embodiment, the first via V1 can be referred to as a first active via.

[0249] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the sixth active layer) on the substrate, the third insulating layer and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer (also the first region of the sixth active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the sixth active layer) through the via hole.

[0250] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the third insulating layer and the fourth insulating layer within the third via hole V3 are etched away to expose the surface of the second region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed fourth connecting electrode to the second region of the second active layer through the via hole.

[0251] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the third insulating layer and the fourth insulating layer in the fourth via hole V4 are etched away to expose the surface of the first region of the fourth active layer, and the fourth via hole V4 is configured to connect a subsequently formed fifth connecting electrode to the first region of the fourth active layer through the via hole.

[0252] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the third insulating layer and the fourth insulating layer within the fifth via V5 are etched away to expose the surface of the first region of the fifth active layer, and the fifth via V5 is configured to connect a subsequently formed first power connection line to the first region of the fifth active layer through the via.

[0253] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the second area of ​​the seventh active layer) on the substrate, the third insulating layer and the fourth insulating layer within the sixth via hole V6 are etched away to expose the surface of the second area of ​​the third active layer (also the second area of ​​the seventh active layer), and the sixth via hole V6 is configured to connect the subsequently formed third connecting electrode to the first area of ​​the second area of ​​the third active layer (also the second area of ​​the seventh active layer) through the via hole.

[0254] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate. The third insulating layer and the fourth insulating layer within the seventh via V7 are etched away, exposing the surface of the first region of the seventh active layer. The seventh via V7 is configured to connect a subsequently formed initial signal line to the first region of the seventh active layer through the via. In an exemplary embodiment, the seventh via V7 can be referred to as a seventh active via.

[0255] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first bottom gate connection block 21-1 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the first bottom gate connection block 21-1, and the eighth via hole V8 is configured to connect the subsequently formed first scan signal line to the first bottom gate connection block 21-1 through the via hole.

[0256] In an exemplary embodiment, because the first bottom-gate electrodes 21 of the two circuit units share the same first bottom-gate connection block 21-1, the two circuit units can share the same eighth via V8, effectively reducing the occupied space of the pixel driving circuit and facilitating the compactness of the circuit units. In an exemplary embodiment, the eighth via V8 can be referred to as a first bottom-gate connection via.

[0257] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first top gate connection block 41-1 on the substrate, the fourth insulating layer in the ninth via hole V9 is etched away to expose the surface of the first top gate connection block 41-1, and the ninth via hole V9 is configured to connect the subsequently formed first scan signal line to the first top gate connection block 41-1 through the via hole.

[0258] In an exemplary embodiment, because the first top gate electrodes 41 of the two circuit units share the same first top gate connection block 41-1, the two circuit units can share the same ninth via hole V9, which can effectively reduce the occupied space of the pixel driving circuit and facilitate the compression of the circuit units. In an exemplary embodiment, the ninth via hole V9 can be referred to as a first top gate connection via hole.

[0259] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the fourth bottom gate connection block 24-1 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the fourth bottom gate connection block 24-1, and the tenth via hole V10 is configured to connect a subsequently formed third scan signal line to the fourth bottom gate connection block 24-1 through the via hole.

[0260] In an exemplary embodiment, since the fourth bottom-gate electrodes 24 of the two circuit units share the same fourth bottom-gate connection block 24-1, the two circuit units can share the same tenth via hole V10, which can effectively reduce the occupied space of the pixel driving circuit and facilitate the compression of the circuit units. In an exemplary embodiment, the tenth via hole V10 can be referred to as a fourth bottom-gate connection via hole.

[0261] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the fourth top gate connection block 44-1 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the fourth top gate connection block 44-1, and the eleventh via hole V11 is configured to connect a subsequently formed third scan signal line to the fourth top gate connection block 44-1 through the via hole.

[0262] In an exemplary embodiment, since the fourth top gate electrodes 44 of the two circuit units share the same fourth top gate connection block 44-1, the two circuit units can share the same eleventh via hole V11, which can effectively reduce the occupied space of the pixel driving circuit and facilitate the compression of the circuit units. In an exemplary embodiment, the eleventh via hole V11 can be referred to as a fourth top gate connection via hole.

[0263] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the sixth bottom gate connection block 26-1 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the sixth bottom gate connection block 26-1, and the twelfth via hole V12 is configured to connect the subsequently formed fourth scan signal line to the sixth bottom gate connection block 26-1 through the via hole.

[0264] In the exemplary embodiment, since the sixth bottom gate electrodes 26 of the two circuit units share the same sixth bottom gate connection block 26-1, the two circuit units can share the same twelfth via hole V12, which can effectively reduce the occupied space of the pixel driving circuit and facilitate the compression of the circuit units. In the exemplary embodiment, the twelfth via hole V12 can be referred to as the sixth bottom gate connection via hole.

[0265] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the sixth top gate connection block 46-1 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away, exposing the surface of the sixth top gate connection block 46-1, and the thirteenth via hole V13 is configured to connect the subsequently formed fourth scan signal line to the sixth top gate connection block 46-1 through the via hole.

[0266] In an exemplary embodiment, since the sixth top gate electrodes 46 of the two circuit units share the same sixth top gate connection block 46-1, the two circuit units can share the same thirteenth via hole V13, which can effectively reduce the occupied space of the pixel driving circuit and facilitate the compression of the circuit units. In an exemplary embodiment, the thirteenth via hole V13 can be referred to as the sixth top gate connection via hole.

[0267] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the third top gate electrode 43 on the substrate, the fourth insulating layer in the fourteenth via V14 is etched away to expose the surface of the third top gate electrode 43, and the fourteenth via V14 is configured to connect the subsequently formed first connecting electrode 51 to the third top gate electrode 43 through the via.

[0268] In an exemplary embodiment, the orthographic projection of the fifteenth via hole V15 on the substrate is located within the range of the orthographic projection of the fourth electrode plate 14 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifteenth via hole V15 are etched away to expose the surface of the fourth electrode plate 14, and the fifteenth via hole V15 is configured to connect the subsequently formed second connecting electrode to the fourth electrode plate 14 through the via hole.

[0269] In an exemplary embodiment, the orthographic projection of the sixteenth via hole V16 on the substrate is located within the range of the orthographic projection of the electrode plate connecting block 15 on the substrate, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the sixteenth via hole V16 are etched away to expose the surface of the electrode plate connecting block 15, and the sixteenth via hole V16 is configured to connect the subsequently formed fourth connecting electrode to the electrode plate connecting block 15 through the via hole.

[0270] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer (also the second region of the sixth active layer) on the substrate, the third insulating layer and the fourth insulating layer in the seventeenth via hole V17 are etched away to expose the surface of the second region of the fourth active layer (also the second region of the sixth active layer), and the seventeenth via hole V17 is configured to connect a subsequently formed second connecting electrode to the second region of the fourth active layer (also the second region of the sixth active layer) through the via hole.

[0271] In an exemplary embodiment, the orthographic projection of the eighteenth via hole V18 on the substrate is located within the range of the orthographic projection of the second electrode plate 12 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighteenth via hole V18 are etched away to expose the surface of the second electrode plate 12, and the eighteenth via hole V18 is configured to connect the subsequently formed third connecting electrode to the second electrode plate 12 through the via hole.

[0272] (16) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIG14A and FIG14B , where FIG14B is a plan view schematic diagram of the fourth conductive layer in FIG14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0273] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a first scanning signal line 61, a third scanning signal line 63, a fourth scanning signal line 64, a reference signal line 66, an initial signal line 67 and a first power connection line 68.

[0274] In an exemplary embodiment, the first scan signal line 61, the third scan signal line 63, the fourth scan signal line 64, the reference signal line 66, the initial signal line 67, and the first power connection line 68 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be continuously arranged in a unit row. The third scan signal line 63, the fourth scan signal line 64, and the first power connection line 68 may be located on a side of the third top gate electrode 43 opposite to the second direction Y, and the first scan signal line 61, the reference signal line 66, and the initial signal line 67 may be located on a side of the third top gate electrode 43 in the second direction Y.

[0275] In an exemplary embodiment, the fourth scan signal line 64 can be located on the side of the third top gate electrode 43 in the opposite direction of the second direction Y, the third scan signal line 63 can be located on the side of the fourth scan signal line 64 away from the third top gate electrode 43, and the first power connection line 68 can be located on the side of the third scan signal line 63 away from the third top gate electrode 43.

[0276] In an exemplary embodiment, the first scan signal line 61 can be located on the side of the third top gate electrode 43 in the second direction Y, the reference signal line 66 can be located on the side of the first scan signal line 61 away from the third top gate electrode 43, and the initial signal line 67 can be located on the side of the reference signal line 66 away from the third top gate electrode 43.

[0277] In the exemplary embodiment, the orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps with the orthographic projections of the first bottom gate electrode 21, the second bottom gate electrode 22, the first top gate electrode 41, and the second top gate electrode 42 on the substrate. The first scan signal line 61 is connected to the first bottom gate connection block 21-1 via the eighth via V8 and to the first top gate connection block 41-1 via the ninth via V9. Since the first bottom gate connection block 21-1 is connected to the first bottom gate electrode 21 and the second bottom gate electrode 22, respectively, and the first top gate connection block 41-1 is connected to the first top gate electrode 41 and the second top gate electrode 42, respectively, the first scan signal line 61 is simultaneously connected to the bottom gate electrode of the first transistor T1, the top gate electrode of the first transistor T1, the bottom gate electrode of the second transistor T2, and the top gate electrode of the second transistor T2. The first scan signal line 61 can simultaneously control the conduction or disconnection of the first transistor T1 and the second transistor T2.

[0278] In the exemplary embodiment, the orthographic projection of the third scan signal line 63 on the substrate at least partially overlaps with the orthographic projections of the fourth bottom gate electrode 24 and the fourth top gate electrode 44 on the substrate. The third scan signal line 63 is connected to the fourth bottom gate connection block 24-1 via the tenth via hole V10, and is connected to the fourth top gate connection block 44-1 via the eleventh via hole V11. Since the fourth bottom gate connection block 24-1 is connected to the fourth bottom gate electrode 24, and the fourth top gate connection block 44-1 is connected to the fourth top gate electrode 44, the third scan signal line 63 is simultaneously connected to the bottom gate electrode and the top gate electrode of the fourth transistor T4. The third scan signal line 63 can control the conduction or disconnection of the fourth transistor T4.

[0279] In the exemplary embodiment, the orthographic projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the orthographic projections of the sixth bottom gate electrode 26 and the sixth top gate electrode 46 on the substrate. The fourth scan signal line 64 is connected to the sixth bottom gate connection block 26-1 via the twelfth via V12, and is connected to the sixth top gate connection block 46-1 via the thirteenth via V13. Since the sixth bottom gate connection block 26-1 is connected to the sixth bottom gate electrode 26, and the sixth top gate connection block 46-1 is connected to the sixth top gate electrode 46, the fourth scan signal line 64 is simultaneously connected to the bottom gate electrode and the top gate electrode of the sixth transistor T6. The fourth scan signal line 64 can control the conduction or disconnection of the sixth transistor T6.

[0280] In an exemplary embodiment, the present disclosure effectively reduces the resistance of the scan signal lines and the voltage drop of the scan signals by setting the first scan signal line 61, the third scan signal line 63 and the fourth scan signal line 64 in the first source-drain metal (SD1) layer, thereby increasing the compensation speed and improving the display quality.

[0281] In an exemplary embodiment, the reference signal line 66 is connected to the first region of the first active layer (also the first region of the second active layer) in each circuit unit through the first via V1, thereby enabling the reference signal line 66 to simultaneously write the reference signal into the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0282] In an exemplary embodiment, the orthographic projection of the reference signal line 66 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 62 on the substrate. The reference signal line 66 having a constant voltage signal can effectively shield the interference of other signals in the pixel driving circuit on the second scanning signal line 62, thereby improving the transmission quality of the second scanning signal.

[0283] In an exemplary embodiment, the initial signal line 67 is connected to the first region of the seventh active layer in each circuit unit through the seventh via hole V7 , thereby enabling the initial signal line 67 to write the initial signal into the first electrode of the seventh transistor T7 .

[0284] In an exemplary embodiment, the first power connection line 68 is connected to the first region of the fifth active layer through the fifth via V5. Since the first power connection line 68 is connected to the first power line formed subsequently, the first power line can write the first power signal into the first electrode of the fifth transistor T5.

[0285] In an exemplary embodiment, a first power connection block 68-1 may be connected to the first power connection line 68. The first power connection block 68-1 is configured to be connected to a first power line formed later. In an exemplary embodiment, the first power connection line 68 may be provided in each circuit unit.

[0286] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the sixth active layer) via a second via hole V2, and a second end of the first connection electrode 51 is connected to the third top gate electrode 43 via a fourteenth via hole V14. In an exemplary embodiment, the first connection electrode 51 interconnects the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first electrode of the sixth transistor T6, forming a first node N1 of the pixel driving circuit.

[0287] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip extending along the first direction X. A first end of the second connection electrode 52 is connected to the second region of the fourth active layer (also the second region of the sixth active layer) via a seventeenth via hole V17, and a second end of the second connection electrode 52 is connected to the fourth electrode plate 14 via a fifteenth via hole V15. In an exemplary embodiment, the second connection electrode 52 interconnects the second electrode of the fourth transistor T4, the second electrode of the sixth transistor T6, and the fourth electrode plate 14 of the second capacitor, forming a second node N2 of the pixel driving circuit.

[0288] In an exemplary embodiment, the third connection electrode 53 may be L-shaped. A first end of the third connection electrode 53 is connected to the second region of the third active layer (also the second region of the seventh active layer) via a sixth via hole V6, and a second end of the third connection electrode 53 is connected to the second electrode plate 12 via an eighteenth via hole V18. In an exemplary embodiment, the third connection electrode 53 interconnects the second electrode of the third transistor T3, the second electrode of the seventh transistor T7, and the second electrode plate 12 (upper electrode) of the first capacitor, forming a third node N3 of the pixel driving circuit. In an exemplary embodiment, the third connection electrode 53 is configured to be connected to a subsequently formed anode connection electrode.

[0289] In an exemplary embodiment, the fourth connection electrode 54 may be in a block shape (e.g., a rectangle). A first end of the fourth connection electrode 54 is connected to the second region of the second active layer via a third via V3, and a second end of the fourth connection electrode 54 is connected to the plate connection block 15 via a sixteenth via V16. Because the plate connection block 15 is connected to the first plate 11 and the third plate 13, the fourth connection electrode 54 interconnects the second electrode of the second transistor T2, the first plate 11 (lower plate) of the first capacitor, and the third plate 13 (lower plate) of the second capacitor, forming a fourth node N4 of the pixel driving circuit.

[0290] In this exemplary embodiment, since the first plate 11 and the third plate 13 are interconnected and connected to the second electrode of the second transistor T2 via the fourth connection electrode 54, the first plate 11 and the third plate 13 have a potential of the fourth node N4 in the pixel driving circuit. Since the second plate 12 is connected to the second electrode of the third transistor T3 and the second electrode of the seventh transistor T7 via the third connection electrode 53, the second plate 12 has a potential of the third node N3 in the pixel driving circuit. Since the fourth plate 14 is connected to the second electrode of the fourth transistor T4 and the second electrode of the sixth transistor T6 via the second connection electrode 52, the fourth plate 14 has a potential of the second node N2 in the pixel driving circuit. Thus, the first plate 11 having a potential of the fourth node N4 and the second plate 12 having a potential of the third node N3 form a first capacitor, and the third plate 13 having a potential of the fourth node N4 and the fourth plate 14 having a potential of the second node N2 form a second capacitor.

[0291] In an exemplary embodiment, the shape of the fifth connection electrode 55 can be a strip shape with a main portion extending along the first direction X, the first end of the fifth connection electrode 55 is connected to the first region of the fourth active layer through the fourth via hole V4, and the second end of the fifth connection electrode 55 extends in a direction away from the fourth transistor T4, and the second end of the fifth connection electrode 55 is configured to be connected to a data signal line formed subsequently.

[0292] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first data connection line 81. The first data connection line 81 may be in the shape of a straight line or a broken line extending along the first direction X and may be disposed in the horizontal routing space between some adjacent unit rows.

[0293] In an exemplary embodiment, a first break K1 may be provided on at least one first data link line 81 , and the first break K1 may cut off the first data link line 81 , so that the first data link lines 81 on both sides of the first break K1 are insulated from each other.

[0294] In an exemplary embodiment, the first data connection line 81 may include a first connection sub-line 81-1 and a second connection sub-line 81-2 respectively located on both sides of the first break K1 in the first direction X, the first connection sub-line 81-1 is configured to be connected to the data signal line in the display area, and the second connection sub-line 81-2 is configured as a first dummy line.

[0295] In one exemplary embodiment, the first connecting sub-wire 81-1 may be located on one side of the first break K1 in the first direction X, and the second connecting sub-wire 81-2 may be located on the side of the first break K1 in the opposite direction of the first direction X. In another exemplary embodiment, the first connecting sub-wire 81-1 may be located on one side of the first break K1 in the opposite direction of the first direction X, and the second connecting sub-wire 81-2 may be located on one side of the first break K1 in the first direction X.

[0296] In an exemplary embodiment, a data connection block 83 and a data connection electrode 84 may be provided on at least one first connection sub-line 81-1. The data connection block 83 may be in the shape of a strip extending along the second direction Y, and the data connection electrode 84 may be in the shape of a block (such as a rectangle). The data connection block 83 and the data connection electrode 84 may be provided on one side of the first connection sub-line 81-1 in the second direction Y, and the data connection block 83 is provided between the first connection sub-line 81-1 and the data connection electrode 84. A first end of the data connection block 83 is connected to the first connection sub-line 81-1, and a second end of the data connection block 83 is connected to the data connection electrode 84. The data connection electrode 84 is configured to be connected to a second data connection line formed subsequently.

[0297] In an exemplary embodiment, the data connection block 83 and the data connection electrode 84 may be disposed in the vertical wiring space between some adjacent cell columns. For example, the data connection block 83 and the data connection electrode 84 may be located in the vertical wiring space between the Nth cell column and the N+1th cell column. For another example, the data connection block 83 and the data connection electrode 84 may be located in the vertical wiring space between the N+1th cell column and the N+2th cell column.

[0298] In an exemplary embodiment, the first connection sub-line 81 - 1 , the data connection block 83 , and the data connection electrode 84 may be an integral structure connected to each other.

[0299] In an exemplary embodiment, the fourth conductive layer may further include at least one dummy electrode 85. The dummy electrode 85 may be in the shape of a block (e.g., a rectangle) and may be disposed in the vertical wiring space between some adjacent cell columns. The dummy electrode 85 is configured to be connected to a second data connection line formed subsequently. For example, the dummy electrode 85 may be located in the vertical wiring space between the Nth cell column and the N+1th cell column. For another example, the dummy electrode 85 may be located in the vertical wiring space between the N+1th cell column and the N+2th cell column.

[0300] In an exemplary embodiment, the position and shape of the dummy electrode 85 in the circuit unit can be substantially the same as the position and shape of the data connection electrode 84 in the circuit unit. The difference is that the dummy electrode 85 is isolated and is neither connected to the first data connection line 81 nor to any other electrode. In an exemplary embodiment, the dummy electrode 85 and the data connection electrode 84 have the same morphology and via connection structure. The identical design of the transition area not only improves the uniformity of the subsequent etching process, but also enables different areas to achieve the same display effect under both transmitted and reflected light, effectively achieving shadow elimination, effectively avoiding poor appearance of the display substrate, and improving display quality.

[0301] In an exemplary embodiment, in the first direction X, the data connection electrode 84 and the dummy electrode 85 may be disposed between two adjacent first power connection blocks 68 - 1 in the first direction X. In the second direction Y, positions of the data connection electrode 84 and the dummy electrode 85 may be substantially flush with positions of the first power connection block 68 - 1 .

[0302] In an exemplary embodiment, in a cell row, the fourth conductive layers of two adjacent circuit cells (excluding the first data connection line and the data connection block) can be symmetrically arranged with respect to the column center line. For example, the fourth conductive layers of the Nth cell column and the N+1th cell column can be symmetrically arranged with respect to the column center line. For another example, the fourth conductive layers of the N+1th cell column and the N+2th cell column can be symmetrically arranged with respect to the column center line.

[0303] In an exemplary embodiment, the fourth conductive layers (except the first data link lines and the data connection blocks) in adjacent cell rows may be substantially the same.

[0304] (17) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 15 .

[0305] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0306] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first power connection block 68-1 on the substrate, the first flat layer in the twenty-first via V21 is removed, exposing the surface of the first power connection block 68-1, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the first power connection block 68-1 through the via.

[0307] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the second end of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-second via hole V22 is removed, exposing the surface of the second end of the fifth connecting electrode 55, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the second end of the fifth connecting electrode 55 through the via hole.

[0308] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-third via hole V23 is removed, exposing the surface of the third connecting electrode 53, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the third connecting electrode 53 through the via hole.

[0309] In an exemplary embodiment, the plurality of via holes on the first planar layer may further include a twenty-fourth via hole V24 and a twenty-fifth via hole V25 .

[0310] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is within the range of the orthographic projection of the data connection electrode 84 on the substrate. The first planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the data connection electrode 84. The twenty-fourth via hole V24 is configured to connect a third connection sub-line of a subsequently formed second data connection line to the data connection electrode 84 through the via hole. In an exemplary embodiment, the twenty-fourth via hole V24 can be referred to as a data transfer via hole.

[0311] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the dummy electrode 85 on the substrate, the first flat layer in the twenty-fifth via hole V25 is removed to expose the surface of the dummy electrode 85, and the twenty-fifth via hole V25 is configured to connect the fourth connecting sub-line in the subsequently formed second data connecting line to the dummy electrode 85 through the via hole.

[0312] In an exemplary embodiment, in the first direction X, the twenty-fourth via hole V24 and the twenty-fifth via hole V25 may be disposed between two adjacent twenty-first via holes V21 in the first direction X. In the second direction Y, the positions of the twenty-fourth via hole V24 and the twenty-fifth via hole V25 may be substantially flush with the position of the twenty-first via hole V21, i.e., both the twenty-fourth via hole V24 and the twenty-fifth via hole V25 are disposed within the circuit unit. By designing the data transfer vias to be hidden within the circuit unit, the present disclosure effectively achieves shadow elimination, effectively avoiding a poor appearance of the display substrate and improving display quality.

[0313] (18) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG16A and FIG16B , where FIG16B is a planar schematic diagram of the fifth conductive layer in FIG16A . In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0314] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least a first power line 71 , a second power line 72 , a data signal line 73 , and an anode connection electrode 74 .

[0315] In an exemplary embodiment, the first power line 71 may be in the shape of a straight line or a zigzag line, with its main portion extending along the second direction Y. The first power line 71 is connected to the first power connection block 68-1 through the twenty-first via V21. Since the first power connection block 68-1 is connected to the first power connection line 68, and the first power connection line 68 is connected to the first region of the fifth active layer, the first power line 71 is connected to the first electrode of the fifth transistor T5. The first power line 71 can write the first power signal to the first electrode of the fifth transistor T5.

[0316] In an exemplary embodiment, since the first power line 71 is connected to the first power connection line 68, the first power connection line 68 extending along the first direction X of the main body and the first power line 71 extending along the second direction Y of the main body are connected to each other. The first power line 71 and the first power connection line 68 form a mesh structure on the display substrate for transmitting the first power signal with a mesh-like interconnected structure. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0317] In an exemplary embodiment, the first power connection line 68 in the fourth conductive layer can be arranged in each unit row, and the first power line 71 in the fifth conductive layer can be arranged in each unit column. Multiple first power lines 71 are respectively connected to multiple first power connection lines 68 to form a mesh structure for transmitting the first power signal.

[0318] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projections of the first active layer, the fourth active layer, and the sixth active layer on the substrate, that is, the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projections of the first transistor T1, the fourth transistor T4, and the sixth transistor T6 on the substrate. The first power line 71 can block the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the first transistor T1, the fourth transistor T4, and the sixth transistor T6 of the oxide, thereby preventing the characteristics of the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.

[0319] In an exemplary embodiment, the second power line 72 may be in a straight line or a zigzag line shape with a main portion extending along the second direction Y, and may be disposed between the first power line 71 and the data signal line 73 .

[0320] In an exemplary embodiment, the orthographic projection of the second power line 72 on the substrate at least partially overlaps with the orthographic projections of the third active layer, the fifth active layer, and the seventh active layer on the substrate, that is, the orthographic projection of the second power line 72 on the substrate at least partially overlaps with the orthographic projections of the third transistor T3, the fifth transistor T5, and the seventh transistor T7 on the substrate. The second power line 72 can block the light emitted by the light-emitting device and the light reflected by the film layer from irradiating the third oxide transistor T3, the fifth transistor T5, and the seventh oxide transistor T7, thereby preventing the characteristics of the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.

[0321] In an exemplary embodiment, the width of the second power line 72 may be greater than the width of the first power line 71 , and the width may be a dimension in the first direction X. The present disclosure, by providing a second power line 72 with a relatively wide wiring, not only effectively reduces the resistance of the second power line 72 and reduces the voltage drop when transmitting the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves display uniformity, and improves display quality and display quality.

[0322] In an exemplary embodiment, the data signal line 73 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 73 is connected to the second end of the fifth connection electrode 55 through the twenty-second via hole V22. Since the first end of the fifth connection electrode 55 is connected to the first region of the fourth active layer through the via hole, the data signal line 73 can write a data signal to the first electrode of the fourth transistor T4.

[0323] In an exemplary embodiment, the orthographic projection of the data signal line 73 on the substrate does not overlap with the orthographic projections of the channel region of the first transistor T1 to the channel region of the seventh transistor T7 on the substrate, thereby avoiding signal crosstalk caused by the data voltage jump of the data signal line 73 and the influence of the data voltage jump on the first transistor T1 to the seventh transistor T7, thereby improving the operating stability of the pixel driving circuit and the display effect.

[0324] In an exemplary embodiment, the anode connection electrode 74 may be block-shaped (e.g., rectangular) and connected to the third connection electrode 53 via a twenty-third via hole V23. The anode connection electrode 74 is configured to be connected to a subsequently formed anode. Since the third connection electrode 53 is connected to the second region of the third active layer (also the second region of the seventh active layer) via the via hole, the pixel driving circuit can output a driving current to the light-emitting device.

[0325] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second data link line 82 .

[0326] In an exemplary embodiment, the second data connection line 82 may be in the shape of a straight line or a broken line with a main portion extending along the second direction Y, and may be disposed in a vertical routing space between some adjacent unit columns.

[0327] In an exemplary embodiment, the second data connection line 82 can be arranged between the first power lines 71 of adjacent cell columns. For example, the second data connection line 82 can be arranged between the first power line 71 of the Nth cell column and the first power line 71 of the N+1th cell column. In another example, the second data connection line 82 can be arranged between the first power line 71 of the N+2th cell column and the first power line 71 of the N+3th cell column. By arranging the second data connection line 82 between two first power lines 71, the first power line 71 with a constant voltage signal can serve as a shielding line, preventing data voltage jumps from affecting the pixel driving circuit, improving the operating stability of the pixel driving circuit, and enhancing the display effect.

[0328] In an exemplary embodiment, a second break K2 may be provided on at least one second data connection line 82 , and the second break K2 may cut off the second data connection line 82 , so that the second data connection lines 82 on both sides of the second break K2 are insulated from each other.

[0329] In an exemplary embodiment, the second data connection line 82 may include a third connection sub-line 82-3 and a fourth connection sub-line 82-4 respectively located on both sides of the second break K2 in the second direction Y, the third connection sub-line 82-3 is configured to be connected to the data lead in the binding area, and the fourth connection sub-line 82-4 is configured as a second dummy line.

[0330] In an exemplary embodiment, the third connecting sub-line 82-3 can be located on the side of the second break K2 in the second direction Y (the side close to the binding area), and the fourth connecting sub-line 82-4 can be located on the side of the second break K2 in the opposite direction of the second direction Y (the side away from the binding area).

[0331] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one reference signal line 66 on the substrate, or the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one initial signal line 67 on the substrate.

[0332] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate can be within the range of the orthographic projection of at least one reference signal line 66 on the substrate. The reference signal line 66 can be used to cushion the second break K2, effectively eliminating film layer differences between different regions and preventing a poor appearance of the display substrate. Alternatively, the orthographic projection of at least one second break K2 on the substrate can be within the range of the orthographic projection of at least one initial signal line 67 on the substrate. The initial signal line 67 can be used to cushion the second break K2, effectively eliminating film layer differences between different regions and preventing a poor appearance of the display substrate.

[0333] In an exemplary embodiment, the third connection sub-line 82-3 may be connected to the data connection electrode 84 through the twenty-fourth via hole V24. Since the data connection electrode 84 is connected to the first connection sub-line 81-1 of the first data connection lines 81 through the data connection block 83, the first data connection line 81 extending in the first direction X and the second data connection line 82 extending in the second direction Y are interconnected. Since the first connection sub-line 81-1 of the first data connection lines 81 is configured to connect to the data signal lines in the display area, and the third connection sub-line 82-3 is configured to connect to the data leads in the binding area, the interconnection between the first connection sub-line 81-1 and the third connection sub-line 82-3 connects the data leads in the binding area to the data signal lines in the display area through the first data connection line 81 and the second data connection line 82.

[0334] In an exemplary embodiment, the fourth connection sub-line 82-4 may be connected to the dummy electrode 85 through the twenty-fifth via hole V25. In an exemplary embodiment, since the dummy electrode has substantially the same morphology as the data connection electrode 84, and the twenty-fifth via hole V25 has substantially the same morphology as the twenty-fourth via hole V24, the connection structure between the third connection sub-line 82-3 and the data connection electrode 84 through the via hole and the connection structure between the fourth connection sub-line 82-4 and the dummy electrode 85 through the via hole are substantially the same. This not only improves the uniformity of the subsequent etching process, but also enables different regions to achieve the same display effect under both transmitted and reflected light, effectively achieving shadow elimination, effectively avoiding poor appearance of the display substrate, and improving display quality.

[0335] In an exemplary embodiment, the orthographic projection of at least one first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate, or the orthographic projection of at least one second power line 72 on the substrate may include the orthographic projection of the first break K1 on the substrate.

[0336] In an exemplary embodiment, the orthographic projection of at least one first break K1 on the substrate can be within the range of the orthographic projection of at least one first power line 71 on the substrate, that is, the first break K1 is covered by the first power line 71. Using the first power line 71 to shield the first break K1 can effectively eliminate film layer differences between different regions, thereby preventing a poor appearance of the display substrate. Alternatively, the orthographic projection of at least one first break K1 on the substrate can be within the range of the orthographic projection of at least one second power line 72 on the substrate, that is, the first break K1 is covered by the second power line 72. Using the second power line 72 to shield the first break K1 can effectively eliminate film layer differences between different regions, thereby preventing a poor appearance of the display substrate.

[0337] The subsequent preparation process may include forming a second flat layer, on which an anode via is provided, the anode via exposing the surface of the anode connection electrode 74 , and the anode via is configured to connect a subsequently formed anode to the anode connection electrode 74 through the via.

[0338] At this point, the drive circuit layer of this embodiment is completed on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a reference signal line, an initial signal line, a first power line, a second power line, and a data signal line connected to the pixel drive circuit.

[0339] In a plane perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer, which are sequentially arranged on the base. The first conductive layer may include at least a first plate of a first capacitor and a third plate of a second capacitor, the second conductive layer may include at least a second plate of the first capacitor, a fourth plate of the second capacitor, a first shielding line, a second shielding line, and a plurality of bottom gate electrodes, the semiconductor layer may include at least active layers of a plurality of transistors, the third conductive layer may include at least a second scanning signal line, a light-emitting signal line, and a plurality of top gate electrodes, the fourth conductive layer may include at least a first scanning signal line, a third scanning signal line, a fourth scanning signal line, a reference signal line, an initial signal line, a first power connection line, and a plurality of connection electrodes, and the fifth conductive layer may include at least a first power line, a second power line, and a data signal line.

[0340] In an exemplary embodiment, the fourth conductive layer may further include a first data link line, and the fifth conductive layer may further include a second data link line.

[0341] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0342] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or may be made of an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure such as Ti / Al / Ti. The first planarizing layer and the second planarizing layer may be made of an organic material such as a resin or polyimide.

[0343] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer, and an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0344] The exemplary embodiments of the present disclosure provide a display substrate that creatively combines oxide pixel drive circuit technology with data connection line technology located in the display area, so that the display substrate has the advantages of both a narrow frame and a new circuit architecture. The present disclosure adopts a new pixel drive circuit of an oxide transistor, which can effectively reduce leakage current, which is conducive to achieving low-frequency display. By setting a first data connection line and a second data connection line in the display area, the data lead line of the binding area is connected to the data signal line through the first data connection line and the second data connection line, so that there is no need to set a fan-shaped oblique line in the lead line area, which effectively reduces the length of the lead line area, greatly reduces the width of the lower frame, and improves the screen-to-body ratio, which is conducive to achieving full-screen display.

[0345] The embodiment of the present disclosure can effectively improve the driving performance of the pixel driving circuit and the display quality by setting the width-to-length ratio of the oxide driving transistor in the pixel driving circuit under the corresponding process and pixel architecture.

[0346] In the embodiment of the present disclosure, by setting the data signal line and the channel region of the first transistor T1 to the seventh transistor T7 to not overlap, signal crosstalk caused by the data voltage jump of the data signal line 73 can be avoided, and the influence of the data voltage jump on the first transistor T1 to the seventh transistor T7 can be avoided, thereby improving the working stability of the pixel driving circuit and improving the display effect.

[0347] In the embodiment of the present disclosure, by using the first power line to block the first transistor T1, the fourth transistor T4 and the sixth transistor T6, and by using the second power line to block the third transistor T3, the fifth transistor T5 and the seventh transistor T7, the light emission of the light-emitting device and the light reflected by the film layer can be blocked from irradiating the oxide transistor, thereby preventing the characteristics of the oxide transistor from drifting due to light, and improving the electrical characteristics of the oxide transistor.

[0348] In the embodiment of the present disclosure, by setting the second data connection line between the two first power lines, the first power line with a constant voltage signal can be used as a shielding line to prevent the data voltage jump from affecting the pixel driving circuit, thereby improving the working stability of the pixel driving circuit and improving the display effect.

[0349] The disclosed embodiment hides the data transfer via connecting the first data connection line and the second data connection line in the circuit unit, thereby effectively achieving shadow elimination, effectively avoiding poor appearance of the display substrate, and improving display quality.

[0350] The embodiment of the present disclosure sets the first break to overlap with the second source-drain metal layer (such as the first power line or the second power line), and the second source-drain metal layer can be used to shield the first break, which can effectively eliminate the film layer differences in different areas and avoid poor appearance of the display substrate.

[0351] The embodiment of the present disclosure sets the second fracture to overlap with the first source-drain metal layer (such as a reference signal line or an initial signal line), and can use the first source-drain metal layer to pad the second fracture, which can effectively eliminate the film layer differences in different areas and avoid poor appearance of the display substrate.

[0352] The embodiment of the present disclosure arranges dummy electrodes in the circuit units. The morphology and connection structure of the dummy electrodes are substantially the same as those of the data connection electrodes, so that different circuit units have substantially the same transfer connection structure, which can effectively achieve shadow elimination, effectively avoid the poor appearance of the display substrate, and improve the display quality.

[0353] In the embodiment of the present disclosure, a first power connection line extending along a first direction X and a first power line extending along a second direction Y are provided in the main portion, and the first power lines are connected to each other, so that the first power lines and the first power connection lines form a mesh structure on the display substrate for transmitting a first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves display uniformity, and improves display quality and display quality.

[0354] By providing a second power line within the display area, the disclosed embodiment implements a VSS-in-pixel structure. This significantly reduces the width of the frame power lead, significantly reducing the width of the left and right frame widths, improving the screen-to-body ratio, and facilitating full-screen display. By providing a second power line with a wider routing, the disclosed embodiment not only effectively reduces the resistance of the second power line and the voltage drop during transmission of the second power signal, but also effectively improves the uniformity of the second power signal within the display substrate, effectively improving display uniformity and enhancing display quality.

[0355] The embodiment of the present disclosure effectively reduces the resistance of the scan signal lines and the voltage drop of the scan signals by setting the first scan signal line, the third scan signal line and the fourth scan signal line in the first source-drain metal layer, thereby increasing the compensation speed and improving the display quality.

[0356] The pixel drive circuit of the disclosed embodiment uses seven oxide transistors. Through a mirror-symmetrical design, the bottom gate electrodes and top gate electrodes of the transistors in adjacent circuit units are interconnected as an integrated structure and share the same gate connection block and gate connection via. This not only effectively reduces the space occupied by the pixel drive circuit, facilitating high-resolution (PPI) display, but also facilitates the compression of circuit units. Two unit columns are compressed to create a vertical routing space for the second data connection line, and four unit rows are compressed to create a horizontal routing space for the first data connection line. The disclosed circuit unit compression structure can achieve high transmittance and is suitable for sensor recognition.

[0357] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0358] In some other embodiments, the drive circuit layer of the display substrate may further include a third source / drain metal layer (SD3). The third source / drain metal layer may be disposed on a side of the second planar layer away from the substrate. A third planar layer may be disposed on a side of the third source / drain metal layer away from the substrate. In an exemplary embodiment, the data signal line and the second data connection line may be disposed in the third source / drain metal layer, or the data signal line, the second data connection line, and the second power supply line may be disposed in the third source / drain metal layer. This is not limited in the present disclosure.

[0359] Figure 17 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure. This is an enlarged view of area A in Figure 7B, illustrating the structure of a circuit unit comprising one circuit row and four circuit columns. The display substrate structure of this embodiment is substantially the same as that shown in Figure 8 , except that the data signal line 73 can be in the form of a zigzag line extending along the second direction Y.

[0360] In an exemplary embodiment, in at least one circuit unit, the data signal line 73 may include at least one straight segment and at least one bent segment connected to each other, and the bent segment is configured to increase an extended length of the data signal line.

[0361] As shown in FIG17 , at least one data signal line 73 may include a first straight segment 73-1, a second straight segment 73-2 and a bending segment 73-3, wherein a first end of the bending segment 73-3 is connected to the first straight segment 73-1, and a second end of the bending segment 73-3 is connected to the second straight segment 73-2.

[0362] In an exemplary embodiment, the bend section 73-3 may include a first bend portion 73A, a second bend portion 73B, and an extension portion 73C. The first end of the first bend portion 73A is connected to the first straight segment 73-1. The second end of the first bend portion 73A extends toward the second power line 72 and is then connected to the first end of the extension portion 73C. The second end of the extension portion 73C extends along the second direction Y and is then connected to the first end of the second bend portion 73B. The second end of the second bend portion 73B extends away from the second power line 72 and is then connected to the second straight segment 73-2.

[0363] In an exemplary embodiment, the first bending portion 73A has a first angle α1 with the second direction Y, which may be approximately 20 to 60 degrees. The second bending portion 73B has a second angle α2 with the second direction Y, which may be approximately 20 to 60 degrees.

[0364] In an exemplary embodiment, the extension lengths of the first bending portion 73A, the second bending portion 73B, and the extension portion 73C can be set according to actual needs, and the present disclosure does not limit them herein.

[0365] In an exemplary embodiment, a portion of the data signal lines in the display area (which may be referred to as FIP lines) are connected to the data lead lines in the binding area via first and second data connection lines, while another portion of the data signal lines (which may be referred to as normal lines) are directly connected to the data lead lines in the binding area. Therefore, the data signal transmission distance of the FIP lines is greater than that of the normal lines. By providing a bend in the data signal lines of the normal lines and compensating for the data signal transmission distance through the line bend, the present disclosure can make the data signal transmission distance of the FIP lines substantially the same as that of the normal lines, thereby improving the driving performance of the pixel driving circuit and enhancing the display effect.

[0366] This embodiment provides a display substrate, which not only has the technical effects of the display substrate shown in Figure 8, but also provides a bending section on the data signal line of the normal routing and compensates for the data signal transmission distance through routing bending processing. This can make the data signal transmission distance of the FIP routing substantially the same as that of the normal routing, thereby improving the driving performance of the pixel driving circuit and enhancing the display effect.

[0367] Figure 18 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. This is an enlarged view of area A in Figure 7B and illustrates the structure of a circuit unit comprising one circuit row and four circuit columns. The display substrate structure of this embodiment is substantially the same as that shown in Figure 8 , except that an auxiliary cathode is provided on the side of the second power line away from the substrate.

[0368] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display substrate may include at least a drive structure layer disposed on a base and a light-emitting structure layer disposed on a side of the drive structure layer away from the base. The drive structure layer may include multiple circuit units, at least one of which may include a pixel drive circuit; the light-emitting structure layer may include multiple light-emitting units, at least one of which may include a light-emitting device, and at least one light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, with the anode being connected to the pixel drive circuit of the corresponding circuit unit.

[0369] As shown in FIG18 , the light-emitting structure layer of this embodiment may further include at least one auxiliary cathode 90. The auxiliary cathode 90 may be provided in the same layer as the anode. Thus, the auxiliary cathode 90 is provided on a side of the second power line 72 away from the substrate. The orthographic projection of the auxiliary cathode 90 on the substrate at least partially overlaps with the orthographic projection of the second power line 72 on the substrate, and the auxiliary cathode 90 is connected to the second power line 72 via an auxiliary via V30. The auxiliary cathode 90 is configured to be connected to a subsequently formed cathode.

[0370] In an exemplary embodiment, after forming the organic light emitting layer, a connection hole exposing the auxiliary cathode 90 may be formed by laser drilling, so that the cathode is connected to the auxiliary cathode 90 through the connection hole.

[0371] In an exemplary embodiment, a plurality of auxiliary cathodes 90 may be periodically arranged along the first direction X and the second direction Y to form a mesh structure for transmitting the second power signal on the display substrate with a mesh-like interconnected structure. This not only effectively reduces the resistance of the second power line and reduces the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0372] In the exemplary embodiment, the second power line 72 of the present disclosure is relatively wide, which facilitates the arrangement of the auxiliary cathodes 90, thereby minimizing the voltage drop of the second power signal. For example, in the first direction X, an auxiliary cathode 90 may be provided every three circuit units. For another example, in the second direction Y, an auxiliary cathode 90 may be provided every one circuit unit.

[0373] In an exemplary embodiment, the plurality of anodes in the light emitting structure layer may be arranged in an RGBG manner, or may be arranged in a real RGB manner, which is not limited in the present disclosure.

[0374] In some other embodiments, the display substrate may not be provided with the auxiliary cathode 90 , and the cathode in the light emitting structure layer is directly connected to the second power line 72 via a connection hole, which is not limited in the present disclosure.

[0375] Figure 19 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. This is an enlarged view of area A in Figure 7B, illustrating the structure of a circuit unit comprising one circuit row and four circuit columns. The display substrate structure of this embodiment is substantially the same as that shown in Figure 8, except that the second data connection line is disposed between the two data signal lines.

[0376] 19 , the second data connection line 82 of this embodiment may be disposed between adjacent data signal lines 73 in the first direction X. For example, the second data connection line 82 may be disposed between the data signal line 73 in the N+1th unit column and the data signal line 73 in the N+2th unit column.

[0377] In an exemplary embodiment, the shape of the first power connection line 68 can be a straight line or a broken line extending along the first direction X, and can be arranged discontinuously in a unit row. The first power connection lines 68 of two circuit units adjacent in the first direction X can be an integrated structure connected to each other.

[0378] In an exemplary embodiment, a first power connection block 68-1 can be connected to the first power connection line 68, and the first power connection block 68-1 can be set in the middle position of the first power connection line 68 of the integrated structure, so that the first power connection lines 68 of the two circuit units share the same first power connection block 68-1.

[0379] In an exemplary embodiment, the first power lines 71 of two adjacent circuit units may be connected to each other as an integral structure, and thus the width of the first power line 71 in this embodiment may be greater than the width of the first power line 71 in the embodiment shown in FIG. 8 .

[0380] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0381] (21) A first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer pattern are sequentially formed, as shown in FIG20A and FIG20B . FIG20B is a schematic plan view of the fourth conductive layer in FIG20A . In this exemplary embodiment, the patterns of the first conductive layer, the second conductive layer, the semiconductor layer, the third conductive layer, and the fourth insulating layer are substantially the same as those in the embodiment shown in FIG8 and are not further described herein.

[0382] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a first scanning signal line 61, a third scanning signal line 63, a fourth scanning signal line 64, a reference signal line 66 and an initial signal line 67, and the above structure is basically the same as the embodiment shown in Figure 8.

[0383] In an exemplary embodiment, the fourth conductive layer of each circuit unit may further include a first power connection line 68. The first power connection line 68 may be in the shape of a straight line or a broken line extending along the first direction X, and may be intermittently provided in a cell row. The first power connection line 68 is connected to the first region of the fifth active layer through a fifth via V5.

[0384] In an exemplary embodiment, the first power connection lines 68 of two circuit units adjacent in the first direction X may be interconnected as an integral structure. For example, the first power connection lines 68 of the Nth unit column and the N+1th unit column may be interconnected as an integral structure, and the first power connection lines 68 of the N+2th unit column and the N+3th unit column may be interconnected as an integral structure, but there is a gap between the first power connection lines 68 in the Nth unit column and the N+1th unit column and the first power connection lines 68 in the N+2th unit column and the N+3th unit column.

[0385] In an exemplary embodiment, a first power connection block 68 - 1 may be connected to the first power connection line 68 , and the first power connection block 68 - 1 is configured to be connected to a first power line formed subsequently.

[0386] In an exemplary embodiment, the first power connection block 68-1 can be set in the middle position of the first power connection line 68 of the integrated structure, that is, between two adjacent circuit units in the first direction X, so that the first power connection lines 68 of the two circuit units share the same first power connection block 68-1, which can effectively reduce the occupied space of the pixel driving circuit and is conducive to the compression of the circuit unit while ensuring the display resolution (PPI).

[0387] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first data connection line 81. The shape of the first data connection line 81 may be a straight line or a broken line extending along the first direction X, and may be arranged between partially adjacent unit rows. A first break K1 may be provided on the first data connection line 81, and a first connection sub-line 81-1 and a second connection sub-line 81-2 are formed on both sides of the first break K1.

[0388] In an exemplary embodiment, a data connection block 83 and a data connection electrode 84 may be provided on at least one first connection sub-line 81-1, a first end of the data connection block 83 is connected to the first connection sub-line 81-1, and a second end of the data connection block 83 is connected to the data connection electrode 84. The first connection sub-line 81-1, the data connection block 83 and the data connection electrode 84 may be an integrated structure connected to each other.

[0389] In an exemplary embodiment, unlike the embodiment shown in FIG. 8 , the data connection block 83 and the data connection electrode 84 of this embodiment may be disposed between the N+1th unit column and the N+2th unit column, and may be located between the first power connection lines 68 that are intermittently disposed.

[0390] In an exemplary embodiment, the fourth conductive layer may further include at least one dummy electrode 85, and the dummy electrode 85 may be located between the intermittently arranged first power connection lines 68. The position and shape of the dummy electrode 85 in the circuit unit may be substantially the same as the position and shape of the data connection electrode 84 in the circuit unit.

[0391] In an exemplary embodiment, in a cell row, the fourth conductive layers of two adjacent circuit cells (excluding the first data connection line and the data connection block) can be symmetrically arranged with respect to the column center line. For example, the fourth conductive layers of the Nth cell column and the N+1th cell column can be symmetrically arranged with respect to the column center line. For another example, the fourth conductive layers of the N+1th cell column and the N+2th cell column can be symmetrically arranged with respect to the column center line.

[0392] In an exemplary embodiment, the fourth conductive layers (except the first data link lines and the data connection blocks) in adjacent cell rows may be substantially the same.

[0393] (22) Sequentially forming a first flat layer and a fifth conductive layer pattern. In an exemplary embodiment, sequentially forming the first flat layer and the fifth conductive layer pattern may include: first forming a first flat layer covering the fourth conductive layer pattern, with the twenty-first to twenty-fifth via holes V21 to V25 provided on the first flat layer; and then forming a fifth conductive layer on the first flat layer, as shown in FIG21A and FIG21B , where FIG21B is a plan view schematic diagram of the fifth conductive layer in FIG21A .

[0394] In an exemplary embodiment, the positions of the twenty-first vias V21 to the twenty-fifth vias V25 are substantially the same as those in the embodiment shown in FIG8 , except that, since the first power connection lines 68 of two adjacent circuit units in the first direction X share the same first power connection block 68 - 1, the two circuit units share the same twenty-first via V21.

[0395] In an exemplary embodiment, the fifth conductive layer of each circuit cell may include at least a first power line 71, a second power line 72, a data signal line 73, and an anode connection electrode 74. The above structure is substantially the same as the embodiment shown in FIG8 , except that the first power lines 71 of two adjacent circuit cells may be interconnected as a single unit. For example, the first power lines 71 of the Nth and N+1th cell columns may be interconnected as a single unit, and the first power lines 71 of the N+2 and N+3th cell columns may be interconnected as a single unit.

[0396] In an exemplary embodiment, since the first power lines 71 of two adjacent circuit units are connected to each other as an integral structure, the width of the first power line 71 in this embodiment may be greater than the width of the first power line 71 in the embodiment shown in FIG. 8 .

[0397] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second data connection line 82. The shape of the second data connection line 82 may be a straight line or a broken line with the main portion extending along the second direction Y. It may be arranged between some adjacent unit columns. A second break K2 may be provided on the second data connection line 82, and a third connection sub-line 82-3 and a fourth connection sub-line 82-4 may be formed on both sides of the second break K2.

[0398] In an exemplary embodiment, unlike the embodiment shown in FIG8 , the second data connection line 82 of this embodiment can be disposed between some of the data signal lines 73 adjacent in the first direction X. For example, the second data connection line 82 can be disposed between the data signal line 73 of the N+1th unit column and the data signal line 73 of the N+2th unit column. By disposing the second data connection line 82 between two data signal lines 73, the present disclosure can make the first power lines 71 of two adjacent circuit units an interconnected, integrated structure, thereby increasing the width of the first power line 71. By providing a wider first power line 71, the present disclosure not only effectively reduces the resistance of the first power line 71 and reduces the voltage drop when transmitting the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity, and improving display quality and display quality.

[0399] In an exemplary embodiment, the orthographic projection of at least one first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate, or the orthographic projection of at least one second power line 72 on the substrate may include the orthographic projection of the first break K1 on the substrate.

[0400] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one reference signal line 66 on the substrate, or the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one initial signal line 67 on the substrate.

[0401] This embodiment provides a display substrate, which not only has the technical effects of the display substrate shown in Figure 8, but also, by arranging the second data connection line between the two data signal lines, can make the first power lines of two adjacent circuit units an integrated structure connected to each other, and increase the width of the first power line, which not only effectively reduces the resistance of the first power line and reduces the voltage drop of transmitting the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0402] Figure 22 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. This is an enlarged view of area A in Figure 7B , illustrating the structure of a circuit unit comprising one circuit row and four circuit columns. The display substrate structure of this embodiment is substantially the same as that shown in Figure 8 , except that some adjacent circuit units can share active vias.

[0403] As shown in FIG22 , in this embodiment, the first active layers 31 of some adjacent circuit units in the first direction X are interconnected as an integrated structure, and the seventh active layers 37 of some adjacent circuit units in the first direction X are interconnected as an integrated structure.

[0404] In this exemplary embodiment, because the first active layers 31 of two adjacent circuit cells in the first direction X are interconnected as a single unit, the two circuit cells share the same first via V1 as the first active via. For example, the first active layers 31 of the Nth and N+1th cell columns can be interconnected as a single unit, and the circuit cells of the Nth and N+1th cell columns share the same first via V1. For another example, the first active layers 31 of the N+2th and N+3th cell columns can be interconnected as a single unit, and the circuit cells of the N+2th and N+3th cell columns can share the same first via V1.

[0405] In an exemplary embodiment, since the seventh active layers 27 of two adjacent circuit units in the first direction X are interconnected as an integral structure, the two circuit units share the same seventh via V7 serving as the seventh active via. For example, the seventh active layers 37 of the (N+1)th and (N+2)th cell columns may be interconnected as an integral structure, and the circuit units of the (N+1)th and (N+2)th cell columns may share the same seventh via V7.

[0406] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0407] (31) Forming a first conductive layer pattern. In an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a first electrode plate 11 of a first capacitor, a third electrode plate 13 of a second capacitor, and a plate connecting block 15. The above structure is substantially the same as that of the embodiment shown in FIG8 , except that the shape of the first electrode plate 11 is different, as shown in FIG23 .

[0408] (32) Forming a second conductive layer pattern. In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second electrode plate 12 of a first capacitor, a fourth electrode plate 14 of a second capacitor, a first bottom gate electrode 21, a second bottom gate electrode 22, a fourth bottom gate electrode 24, a sixth bottom gate electrode 26, a first shielding line 27, and a second shielding line 28. The above structure is substantially the same as that of the embodiment shown in FIG8, except that the shape of the second electrode plate 12 is different, as shown in FIG24.

[0409] (33) Forming a semiconductor layer pattern. In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include a first active layer 31, a second active layer 32, a third active layer 33, a fourth active layer 34, a fifth active layer 35, a sixth active layer 36, and a seventh active layer 37. The above structure is substantially the same as that of the embodiment shown in FIG8, except that the active layers of some adjacent circuit units are interconnected as an integrated structure, as shown in FIG25.

[0410] In an exemplary embodiment, the first regions 31-1 of the first active layers of some adjacent circuit cells in the first direction X may be interconnected, such that the first active layers 31 of some adjacent circuit cells in the first direction X are interconnected as a single unit. For example, the first active layers 31 of the Nth unit column and the N+1th unit column may be interconnected as a single unit. For another example, the first active layers 31 of the N+2th unit column and the N+3th unit column may be interconnected as a single unit.

[0411] In an exemplary embodiment, since the first active layer 31, the second active layer 32, the fourth active layer 34 and the sixth active layer 36 in the circuit unit are interconnected as an integrated structure, the first active layer 31, the second active layer 32, the fourth active layer 34 and the sixth active layer 36 of the adjacent circuit units in part of the first direction X are interconnected as an integrated structure.

[0412] In an exemplary embodiment, the first regions 37 - 1 of the seventh active layers of some adjacent circuit cells in the first direction X may be connected to each other, so that the seventh active layers 37 of some adjacent circuit cells in the first direction X are connected to each other as an integrated structure. For example, the seventh active layers 37 of the (N+1)th cell column and the (N+2)th cell column may be connected to each other as an integrated structure.

[0413] In an exemplary embodiment, since the third active layer 33, the fifth active layer 35 and the seventh active layer 37 in the circuit unit are interconnected as an integrated structure, the third active layer 33, the fifth active layer 35 and the seventh active layer 37 of the adjacent circuit units in part of the first direction X are interconnected as an integrated structure.

[0414] (34) Forming a third conductive layer pattern. In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a first top gate electrode 41, a second top gate electrode 42, a third top gate electrode 43, a fourth top gate electrode 44, a sixth top gate electrode 46, a second scanning signal line 62, and a light-emitting signal line 65. The above structure is substantially the same as that of the embodiment shown in FIG8, as shown in FIG26.

[0415] (35) Forming a fourth insulating layer pattern. In an exemplary embodiment, the plurality of vias on the fourth insulating layer covering the third conductive layer may include at least first to eighteenth vias V1 to V18. The via structure is substantially the same as that in the embodiment shown in FIG8 , except that some adjacent circuit units share the same active via, as shown in FIG27 .

[0416] In this exemplary embodiment, because the first active layers of two adjacent circuit units in the first direction X are interconnected and integrated, these two circuit units share the same first via V1, which serves as the first active via. This effectively reduces the space occupied by the pixel driver circuit and facilitates the compactness of the circuit units. For example, the circuit units in the Nth and N+1th unit columns share the same first via V1. For another example, the circuit units in the N+2th and N+3th unit columns share the same first via V1.

[0417] In this exemplary embodiment, because the seventh active layers of two adjacent circuit units in the first direction X are interconnected and integrated, the two circuit units share the same seventh via V7, which serves as the seventh active via. This effectively reduces the space occupied by the pixel driving circuit and facilitates the compactness of the circuit units. For example, the circuit units in the (N+1)th and (N+2)th unit columns share the same seventh via V7.

[0418] (36) Forming a fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a first scan signal line 61, a third scan signal line 63, a fourth scan signal line 64, a reference signal line 66, an initial signal line 67, and a first power connection line 68. The above structure is substantially the same as the embodiment shown in FIG8, as shown in FIG28.

[0419] In an exemplary embodiment, the reference signal line 66 is connected to the first region of the first active layer of the two circuit units through the first via V1 shared by the two circuit units, thereby enabling the reference signal line 66 to simultaneously write the reference signal into the first electrode of the first transistor T1 and the first electrode of the second transistor T2 of the two circuit units.

[0420] In an exemplary embodiment, the initial signal line 67 is connected to the first region of the seventh active layer in the two circuit units through the seventh via hole V7 shared by the two circuit units, thereby enabling the initial signal line 67 to write the initial signal into the first electrode of the seventh transistor T7 of the two circuit units.

[0421] In an exemplary embodiment, the structures of the first data connection line 81 , the first break K1 , the data connection block 83 , the data connection electrode 84 , and the dummy electrode 85 are substantially the same as those in the embodiment shown in FIG. 8 .

[0422] (37) The patterns of the first flat layer and the fifth conductive layer are formed in sequence. The via structure on the first flat layer and the structure of the fifth conductive layer are basically the same as those in the embodiment shown in FIG8 and are not described again here.

[0423] This embodiment provides a display substrate that not only has the technical effects of the display substrate shown in Figure 8, but also effectively reduces the space occupied by the pixel driving circuit by arranging the active layers of some adjacent circuit units into an interconnected integrated structure so that two circuit units share the same active via, which is beneficial to the compression of the circuit units.

[0424] FIG29 is a schematic structural diagram of another display substrate of an exemplary embodiment of the present disclosure, which is an enlarged view of area A in FIG7B , illustrating the structure of a circuit unit with one circuit row and eight circuit columns, wherein the pixel driving circuit in the circuit unit has a non-mirror structure.

[0425] As shown in FIG29 , in an exemplary embodiment, multiple circuit units on a display substrate can be compressed horizontally and vertically to create routing space. The routing space is configured to accommodate first data connection lines 81 and second data connection lines 82. Specifically, four unit columns can be grouped together, and a vertical routing space can be compressed horizontally to create a second data connection line 82 for every four unit columns. Two unit rows can be grouped together, and a horizontal routing space can be compressed vertically to create a first data connection line 81 for every three unit rows.

[0426] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0427] (41) A first conductive layer pattern is formed. The first conductive layer pattern of each circuit unit may include at least a first plate of a first capacitor, a third plate of a second capacitor, and a plate connecting block, as shown in FIG30 .

[0428] In example embodiments, the first conductive layers in adjacent cell columns may be substantially the same, and the first conductive layers in adjacent cell rows may be substantially the same.

[0429] (42) A second conductive layer pattern is formed. The second conductive layer pattern of each circuit unit may include at least the second plate of the first capacitor, the fourth plate of the second capacitor, the first bottom gate electrode, the second bottom gate electrode, the fourth bottom gate electrode, the sixth bottom gate electrode, the first shielding line and the second shielding line, as shown in FIG31.

[0430] In example embodiments, the second conductive layers in adjacent cell columns may be substantially the same, and the second conductive layers in adjacent cell rows may be substantially the same.

[0431] (43) A semiconductor layer pattern is formed. The semiconductor layer pattern of each circuit unit may include at least a first active layer, a second active layer, a third active layer, a fourth active layer, a fifth active layer, a sixth active layer, and a seventh active layer, as shown in FIG. 32 .

[0432] In example embodiments, semiconductor layers in adjacent cell columns may be substantially the same, and semiconductor layers in adjacent cell rows may be substantially the same.

[0433] (34) A third conductive layer pattern is formed. The third conductive layer pattern of each circuit unit may include at least a first top gate electrode, a second top gate electrode, a third top gate electrode, a fourth top gate electrode, a sixth top gate electrode, a second scanning signal line, and a light-emitting signal line, as shown in FIG33 .

[0434] (35) A fourth insulating layer and a fourth conductive layer pattern are formed, wherein the fourth insulating layer of each circuit unit includes a plurality of vias, and the fourth conductive layer of each circuit unit includes at least a first connecting electrode, a second connecting electrode, a third connecting electrode, a fourth connecting electrode, a fifth connecting electrode, a first scanning signal line, a third scanning signal line, a fourth scanning signal line, a reference signal line, an initial signal line, and a first power supply connecting line, as shown in FIG34 .

[0435] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first data connection line 81 , and the first data connection line 81 may be provided with a data connection electrode 84 and a first break K1 .

[0436] In an exemplary embodiment, the fourth conductive layers (except the first data link line and the data link electrode) in adjacent cell columns may be substantially the same, and the fourth conductive layers (except the first data link line and the data link electrode) in adjacent cell rows may be substantially the same.

[0437] (36) A first flat layer and a fifth conductive layer pattern are formed, wherein the first flat layer of each circuit unit includes a plurality of vias, and the fifth conductive layer may include at least: a first power line, a second power line, a data signal line, and an anode connection electrode, as shown in FIG29 .

[0438] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second data connection line 82, which may be disposed between the first power line and the data signal line adjacent in the first direction X, and the second data connection line 82 may be connected to the data connection electrode through a via.

[0439] In an exemplary embodiment, a second break K2 may be provided on at least one second data connection line 82 , and the second break K2 may cut off the second data connection line 82 .

[0440] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one reference signal line on the substrate, or the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one initial signal line on the substrate.

[0441] In an exemplary embodiment, the orthographic projection of at least one first power line on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate, or the orthographic projection of at least one second power line on the substrate may include the orthographic projection of the first break K1 on the substrate.

[0442] This embodiment provides a display substrate that uses a pixel driving circuit with a non-mirror structure and also has the technical effects of the display substrate shown in FIG. 8 .

[0443] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, the first break on the first data connection line can be set below the anode, and the orthographic projection of the first break on the substrate can be located within the range of the orthographic projection of the anode on the substrate. The anode is used to block the first break, eliminating the difference in film layers in different regions. For another example, the second break on the second data connection line can be set below the anode, and the orthographic projection of the second break on the substrate can be located within the range of the orthographic projection of the anode on the substrate. The anode is used to block the second break, eliminating the difference in film layers in different regions. For another example, the first break and the second break are both set below the anode, and the present disclosure does not limit this.

[0444] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0445] The present disclosure also provides a method for manufacturing a display substrate, for manufacturing the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along a second direction, wherein at least one first data connection line has one end connected to the data signal line and the other end connected to the second data connection line, and the first direction and the second direction intersect. The manufacturing method may include:

[0446] A pixel driving circuit is formed in at least one circuit unit, and the pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light-emitting control transistor, a first capacitor and a second capacitor, the first capacitor including a first plate and a second plate, and the second capacitor including a third plate and a fourth plate; the first electrode of the first reset transistor is connected to the reference signal line, the second electrode of the first reset transistor is connected to the gate electrode of the driving transistor, the first electrode of the light-emitting control transistor is connected to the first power line, the second electrode of the light-emitting control transistor is connected to the first electrode of the driving transistor, the second electrode of the driving transistor is connected to the second plate of the first capacitor, the first electrode of the data writing transistor is connected to the data signal line, the second electrode of the data writing transistor is connected to the fourth plate of the second capacitor, and the first plate of the first capacitor is connected to the third plate of the second capacitor; the driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is 1.25 to 2.67.

[0447] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0448] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate includes a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect. At least one circuit unit includes a pixel driving circuit, and the pixel driving circuit at least includes a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate. The first pole of the first reset transistor is connected to a reference signal line, the second pole of the first reset transistor is connected to the gate electrode of the driving transistor, the first pole of the light emitting control transistor is connected to a first power supply line, the second pole of the light emitting control transistor is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the second electrode plate of the first capacitor, the first pole of the data writing transistor is connected to the data signal line, the second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, and the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor. The driving transistor is an oxide transistor, and the width-to-length ratio of the driving transistor is 1.25 to 2.

67.

2. The display substrate according to claim 1, wherein The positive projection of the data signal line on the substrate does not overlap with the positive projections of the channel regions of the driving transistor, the first reset transistor, the data writing transistor, and the light emitting control transistor on the substrate.

3. The display substrate according to claim 1, wherein, In at least one circuit unit, the data signal line includes at least one straight segment and at least one bent segment, and the bent segment is configured to increase the extension length of the data signal line.

4. The display substrate according to claim 1, wherein, At least one second data connection line is disposed between two adjacent first power supply lines in the first direction, or at least one second data connection line is disposed between two adjacent data signal lines in the first direction.

5. The display substrate according to claim 1, wherein, In at least one circuit unit and the circuit unit adjacent to it in the first direction, the first power supply lines of the two circuit units are an integrally connected structure.

6. The display substrate according to claim 1, wherein, At least one circuit unit further includes a first power connection line extending along the first direction. The shape of the first power supply line is a straight line or a broken line extending along the second direction. The first power supply line is connected to the first power connection line to form a mesh structure for transmitting the first power signal.

7. The display substrate according to claim 1, wherein, At least one circuit unit further includes a second power supply line, and the width of the second power supply line is greater than the width of the first power supply line, and the width is the dimension in the first direction.

8. The display substrate according to claim 7, wherein The display substrate further includes a plurality of auxiliary cathodes, which are disposed on a side of the second power line away from the substrate, and at least one auxiliary cathode has a positive projection on the substrate that at least partially overlaps with a positive projection of the second power line on the substrate. The auxiliary cathode is connected to the second power line through an auxiliary via hole, and the auxiliary cathode is configured to be connected to a cathode of a light-emitting device.

9. The display substrate according to claim 7, wherein, A positive projection of the first power line on the substrate at least partially overlaps with positive projections of the first reset transistor and the data writing transistor on the substrate, and a positive projection of the second power line on the substrate at least partially overlaps with positive projections of the driving transistor and the light-emitting control transistor on the substrate.

10. The display substrate according to claim 1, wherein, At least one circuit unit further includes a data connection electrode, which is connected to the first data connection line, and the second data connection line is connected to the data connection electrode through a via hole; at least one circuit unit further includes a dummy electrode, and the second data connection line is connected to the dummy electrode through a via hole. A position and a shape of the dummy electrode in one circuit unit are the same as a position and a shape of the data connection electrode in another circuit unit.

11. The display substrate according to claim 1, wherein, In a direction perpendicular to the substrate, the display substrate at least includes a first source-drain metal layer and a second source-drain metal layer sequentially disposed along a direction away from the substrate, and the first data connection line is disposed in the first source-drain metal layer; At least one first data connection line is provided with a first break, which truncates the first data connection line, and a positive projection of the first break on the substrate at least partially overlaps with a positive projection of the second source-drain metal layer on the substrate.

12. The display substrate according to claim 1, wherein, In a direction perpendicular to the substrate, the display substrate at least includes a first source-drain metal layer and a second source-drain metal layer sequentially disposed along a direction away from the substrate, and the second data connection line is disposed in the second source-drain metal layer; At least one second data connection line is provided with a second break, which truncates the second data connection line, and a positive projection of the second break on the substrate at least partially overlaps with a positive projection of the first source-drain metal layer on the substrate.

13. The display substrate according to any one of claims 1 to 12, wherein, The pixel driving circuit further includes a second reset transistor, a third reset transistor, and a data control transistor; a first pole of the second reset transistor is connected to a reference signal line, and a second pole of the second reset transistor is connected to a first electrode plate of the first capacitor and a third electrode plate of the second capacitor; a first pole of the third reset transistor is connected to an initial signal line, and a second pole of the third reset transistor is connected to a second pole of the driving transistor; a first pole of the data control transistor is connected to a gate electrode of the driving transistor, and a second pole of the data control transistor is connected to a second pole of the data writing transistor; the first reset transistor, the second reset transistor, the third reset transistor, the data writing transistor, the light-emitting control transistor, and the data control transistor are oxide transistors.

14. The display substrate according to claim 13, wherein, The first reset transistor includes at least a first bottom gate electrode and a first top gate electrode. Among at least one circuit unit and the circuit units adjacent to it in the first direction, the first bottom gate electrodes in two circuit units are an integrally connected structure, and the first top gate electrodes in two circuit units are an integrally connected structure; and / or, the data writing transistor includes at least a fourth bottom gate electrode and a fourth top gate electrode. Among at least one circuit unit and the circuit units adjacent to it in the first direction, the fourth bottom gate electrodes in two circuit units are an integrally connected structure, and the fourth top gate electrodes in two circuit units are an integrally connected structure; and / or, the data control transistor includes at least a sixth bottom gate electrode and a sixth top gate electrode. Among at least one circuit unit and the circuit units adjacent to it in the first direction, the sixth bottom gate electrodes in two circuit units are an integrally connected structure, and the sixth top gate electrodes in two circuit units are an integrally connected structure.

15. The display substrate according to claim 14, wherein, A first bottom gate connection block is provided on the first bottom gate electrode, and a first top gate connection block is provided on the first top gate electrode. The first bottom gate connection block is configured to be connected to the first scan signal line through a first bottom gate connection via hole, and the first top gate connection block is configured to be connected to the first scan signal line through a first top gate connection via hole. Among at least one circuit unit and the circuit units adjacent to it in the first direction, two circuit units share the first bottom gate connection via hole, and two circuit units share the first top gate connection via hole; and / or, a fourth bottom gate connection block is provided on the fourth bottom gate electrode, and a fourth top gate connection block is provided on the fourth top gate electrode. The fourth bottom gate connection block is configured to be connected to the third scan signal line through a fourth bottom gate connection via hole, and the fourth top gate connection block is configured to be connected to the third scan signal line through a fourth top gate connection via hole. Among at least one circuit unit and the circuit units adjacent to it in the first direction, two circuit units share the fourth bottom gate connection via hole, and two circuit units share the fourth top gate connection via hole; and / or, a sixth bottom gate connection block is provided on the sixth bottom gate electrode, and a sixth top gate connection block is provided on the sixth top gate electrode. The sixth bottom gate connection block is configured to be connected to the fourth scan signal line through a sixth bottom gate connection via hole, and the sixth top gate connection block is configured to be connected to the fourth scan signal line through a sixth top gate connection via hole. Among at least one circuit unit and the circuit units adjacent to it in the first direction, two circuit units share the sixth bottom gate connection via hole, and two circuit units share the sixth top gate connection via hole.

16. The display substrate according to claim 13, wherein, The second reset transistor includes at least a second bottom gate electrode and a second top gate electrode. In at least one circuit unit, the first bottom gate electrode and the second bottom gate electrode are an integrally connected structure, and the first top gate electrode and the second top gate electrode are an integrally connected structure.

17. The display substrate according to claim 13, wherein The first reset transistor includes at least a first active layer. Among at least one circuit unit and a circuit unit adjacent to the first direction, the first active layers in the two circuit units are integrally connected to each other.

18. The display substrate according to claim 17, wherein, The reference signal line is connected to a first region of the first active layer through a first active via. Among at least one circuit unit and a circuit unit adjacent to the first direction, the two circuit units share the first active via.

19. The display substrate according to claim 13, wherein, The third reset transistor includes at least a seventh active layer. Among at least one circuit unit and a circuit unit adjacent to the first direction, the seventh active layers in the two circuit units are integrally connected to each other.

20. The display substrate according to claim 19, wherein, The initial signal line is connected to a first region of the seventh active layer through a seventh active via. Among at least one circuit unit and a circuit unit adjacent to the first direction, the two circuit units share the seventh active via.

21. A display device, comprising the display substrate according to any one of claims 1 to 20.

22. A method for manufacturing a display substrate, the display substrate including a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect; the manufacturing method includes: Forming a pixel driving circuit in at least one circuit unit. The pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light emission control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate. A first pole of the first reset transistor is connected to a reference signal line, a second pole of the first reset transistor is connected to a gate electrode of the driving transistor, a first pole of the light emission control transistor is connected to a first power supply line, a second pole of the light emission control transistor is connected to a first pole of the driving transistor, a second pole of the driving transistor is connected to the second electrode plate of the first capacitor, a first pole of the data writing transistor is connected to the data signal line, a second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor; the driving transistor is an oxide transistor, and a width-to-length ratio of the driving transistor is 1.25 to 2.67.

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