Dram cell structure and operation method therefor, dram array structure and operation method therefor, and manufacturing method

Abstract

The present disclosure provides a dynamic random access memory (DRAM) cell structure and an operation method therefor, a DRAM array structure and an operation method therefor, and a manufacturing method. The DRAM cell structure according to the present disclosure comprises: a storage capacitor, comprising a first electrode, and a second electrode connected to a source line; and a selection transistor comprising: a vertically extending active region, comprising a first source / drain region, a channel region and a second source / drain region, arranged in sequence from bottom to top along a vertical direction, one of the first source / drain region and the second source / drain region being connected to a bit line, and the other being connected to the first electrode of the storage capacitor; and first to fourth gate structures, the first gate structure and the second gate structure being arranged from bottom to top along the vertical direction at a first side of the channel region, and the third gate structure and the fourth gate structure being arranged from bottom to top along the vertical direction at a second side of the channel region opposite the first side. On the basis of the DRAM cell structure and the operation method thereof of the present disclosure, selection transistor leakage current can be reduced, thereby improving switching characteristics.

Description

DRAM cell structure and operation method thereof, DRAM array structure and operation method thereof and manufacturing method thereof Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a dynamic random access memory (DRAM) cell structure and an operating method thereof, as well as a DRAM array structure and an operating method and a manufacturing method thereof. Background Art

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a selection transistor and a storage capacitor (1T1C structure) for storing charge. In a DRAM cell structure that uses a conventional planar horizontal transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), to implement the selection transistor, the transistor's source, gate, and drain are arranged horizontally parallel to the substrate surface. Because the transistor's source, gate, and drain each occupy independent areas in the horizontal direction, the scaling of the DRAM cell circuit structure is limited by gate length and contact size, making it impossible to meet the continued scaling requirements of DRAM devices. This in turn limits the integration density and bandwidth of DRAM devices.

[0004] Therefore, a vertical DRAM cell structure has been proposed in recent years, in which the source, gate and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is conducive to the miniaturization of the DRAM array structure.

[0005] However, in existing DRAM cell circuit structures based on vertical channel transistors (VCTs), the metal gate wraps the entire channel, requiring additional area for isolation between word lines formed by the metal gate connection. This limits the scaling of VCT transistors used as gate transistors in DRAM cell circuits. Furthermore, the resistance of metal deposited by atomic layer deposition (ALD) increases significantly as its thickness decreases. This, combined with the additional area required by the metal and gate oxide thickness compared to planar structures, limits further reductions in word line spacing.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel dynamic random access memory (DRAM) cell structure and an operating method thereof, as well as a DRAM array structure and an operating method and a manufacturing method thereof.

[0008] According to one aspect of the present disclosure, a DRAM cell structure is provided, which includes: a storage capacitor, including a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a selection transistor, including: a vertically extending active region, including a first source / drain region, a channel region, and a second source / drain region arranged in sequence from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to a bit line, and the other of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged on a first side of the channel region from bottom to top in the vertical direction, and the third gate structure and the fourth gate structure are arranged on a second side of the channel region opposite to the first side from bottom to top in the vertical direction.

[0009] According to another aspect of the present disclosure, there is provided an operating method for the above-mentioned DRAM cell structure, comprising: turning on or off a gate transistor by controlling voltages applied to a first gate structure and a fourth gate structure.

[0010] According to another aspect of the present disclosure, there is provided an operating method for the above-mentioned DRAM cell structure, comprising: turning on or off a gate transistor by controlling voltages applied to a second gate structure and a third gate structure.

[0011] The DRAM cell structure and operating method disclosed herein reduce leakage current in the gate transistor by providing upper and lower gate structures on either side of the vertical channel region and controlling the voltage applied to these four gate structures to turn the gate transistor on or off, thereby improving switching characteristics. Consequently, the DRAM cell structure and operating method disclosed herein extend data storage time, reduce the frequency of interruptions due to refresh operations, and thus reduce power consumption.

[0012] According to one aspect of the present disclosure, a dynamic random access memory (DRAM) array structure is provided, comprising: a plurality of DRAM cell structures arranged in M ​​rows and N columns, wherein M and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: a storage capacitor comprising a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a gate transistor comprising: a vertically extending active region comprising a first source / drain region, a channel region, and a second source / drain region arranged in sequence from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor ; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged on a first side of the channel region from bottom to top in the vertical direction, and the third gate structure and the fourth gate structure are arranged on a second side of the channel region opposite to the first side from bottom to top in the vertical direction; N bit lines, respectively connected to the first source / drain region and the other of the second source / drain region of the selection transistor in the N columns of DRAM cell structures; M+1 first word lines, respectively connected to the second gate structure and the third gate structure of the M rows of DRAM cell structures; and M+1 second word lines, respectively connected to the first gate structure and the fourth gate structure of the M rows of DRAM cell structures.

[0013] According to another aspect of the present disclosure, a method for operating the above-mentioned DRAM array structure is provided, comprising: controlling the turning on and off of the gate transistors in the plurality of DRAM cell structures by applying a voltage to the first word line.

[0014] According to another aspect of the present disclosure, a method for operating the above-mentioned DRAM array structure is provided, comprising: controlling the turning on and off of the gate transistors in the plurality of DRAM cell structures by applying a voltage to the second word line.

[0015] According to another aspect of the present disclosure, a method for manufacturing the above-mentioned DRAM array structure is provided, comprising: providing a sacrificial layer and an active layer on a substrate; forming a plurality of bit line grooves extending along a column direction in the active layer to define the size of the active area of ​​each DRAM cell structure in a row direction; removing the sacrificial layer through the plurality of bit line grooves and filling them with a conductive material to form a bit line below the active area of ​​each DRAM cell structure; forming a plurality of word line grooves extending along a row direction in the active layer to define the size of the active area of ​​each DRAM cell structure in a column direction; forming a gate dielectric, a first word line, a second word line and an isolation dielectric in the plurality of word line grooves; and sequentially forming a contact portion and a storage capacitor above the active area of ​​each DRAM cell structure.

[0016] According to another aspect of the present disclosure, a method for manufacturing the above-mentioned DRAM array structure is provided, comprising: providing a sacrificial layer and an active layer on a substrate; forming a plurality of bit line grooves extending along a column direction in the active layer to define the size of the active area of ​​each DRAM cell structure in a row direction; removing the sacrificial layer through the plurality of bit line grooves and filling a conductive material to form bit lines below the active area of ​​each DRAM cell structure; forming a plurality of alternating first word line grooves and second word line grooves extending along a row direction in the active layer to define the size of the active area of ​​each DRAM cell structure in the row direction; forming a gate dielectric, a first word line, a second word line and an isolation dielectric in the first word line groove; forming a gate dielectric, a second word line, a first word line and an isolation dielectric in the second word line groove; and sequentially forming a contact portion and a storage capacitor above the active area of ​​each DRAM cell structure.

[0017] According to the DRAM array structure and its operation method and manufacturing method disclosed in the present invention, by using vertical transistors with four gate structures as selection transistors of the DRAM cell structure and making adjacent DRAM cell structures share word lines in the column direction, the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors is eliminated, thereby achieving further size reduction.

[0018] According to one aspect of the present disclosure, a dynamic random access memory (DRAM) array structure is provided, comprising: a plurality of DRAM cell structures arranged in M ​​rows and N columns, wherein M and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: a storage capacitor comprising a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a gate transistor comprising: a vertically extending active region comprising a first source / drain region, a channel region, and a second source / drain region arranged in sequence from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the storage capacitor. A first electrode; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged on a first side of the channel region from bottom to top in a vertical direction, and the third gate structure and the fourth gate structure are arranged on a second side of the channel region opposite to the first side from bottom to top in a vertical direction; N bit lines, respectively connected to the other of the first source / drain region and the second source / drain region of the selection transistor in the N columns of DRAM cell structures; M+1 word lines, respectively connected to the second gate structure and the third gate structure of the M rows of DRAM cell structures; and control lines, commonly connected to the first gate structure and the fourth gate structure of the DRAM cell structure.

[0019] According to another aspect of the present disclosure, a dynamic random access memory (DRAM) array structure is provided, comprising: a plurality of DRAM cell structures arranged in M ​​rows and N columns, wherein M and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: a storage capacitor comprising a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a gate transistor comprising: a vertically extending active region comprising a first source / drain region, a channel region, and a second source / drain region arranged in sequence from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the storage capacitor. A first electrode; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged on a first side of the channel region from bottom to top in a vertical direction, and the third gate structure and the fourth gate structure are arranged on a second side of the channel region opposite to the first side from bottom to top in a vertical direction; N bit lines, respectively connected to the other of the first source / drain region and the second source / drain region of the selection transistor in the N columns of DRAM cell structures; M+1 word lines, respectively connected to the first gate structure and the fourth gate structure of the M rows of DRAM cell structures; and control lines, commonly connected to the second gate structure and the third gate structure of the DRAM cell structure.

[0020] According to another aspect of the present disclosure, a method for operating the above-mentioned DRAM array structure is provided, comprising: applying a bias voltage to a control line or floating it; and controlling the on and off of the selection transistors in the multiple DRAM cell structures by applying a voltage to the word line.

[0021] According to the DRAM array structure and operation method thereof disclosed in the present invention, by using vertical transistors with four gate structures as selection transistors of the DRAM cell structure and making adjacent DRAM cell structures share word lines in the column direction, the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors is eliminated, thereby achieving further size reduction.

[0022] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0024] FIG. 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0025] FIG. 2 is a schematic perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0026] FIG. 3 is a schematic top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0027] FIG. 4 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to an embodiment of the present disclosure.

[0028] FIG. 5 is a schematic diagram illustrating an operating method of a DRAM cell structure according to an embodiment of the present disclosure.

[0029] FIG. 6 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0030] FIG. 7 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0031] FIG. 8 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0032] FIG. 9 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0033] FIG. 10 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0034] 11A and 11B are schematic top views illustrating DRAM cell structures according to other embodiments of the present disclosure.

[0035] FIG. 12 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in FIG. 1 according to an embodiment of the present disclosure.

[0036] 13A and 13B are top views of a DRAM array structure respectively illustrating a DRAM cell structure including a VCT transistor according to the related art and a transistor having four gate structures sharing a word line according to an embodiment of the present disclosure.

[0037] FIG. 14 is a schematic diagram illustrating an operating method of a DRAM array structure according to an embodiment of the present disclosure.

[0038] 15A to 15Q are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure.

[0039] FIG. 16 is a vertical cross-sectional view illustrating a DRAM cell structure according to another embodiment of the present disclosure.

[0040] FIG. 17 is a vertical cross-sectional view illustrating a DRAM cell structure according to another embodiment of the present disclosure.

[0041] 18A to 18G are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure.

[0042] FIG. 19 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in FIG. 1 according to one embodiment of the present disclosure.

[0043] FIG. 20 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in FIG. 1 according to another embodiment of the present disclosure.

[0044] FIG. 21 is a schematic diagram illustrating an operating method of a DRAM array structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0046] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0047] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0048] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0049] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "a" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "comprising" mean that there are stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the text, the same reference numerals represent the same components. Furthermore, in the drawings, for clarity of illustration, the components are not necessarily drawn to ratio, and the ratios and sizes of the components may be exaggerated.

[0052] FIG1 shows an equivalent circuit diagram of a dynamic random access memory (DRAM) cell structure 100 according to an embodiment of the present disclosure. FIG2 also shows a schematic perspective view of the DRAM cell structure 100 according to an embodiment of the present disclosure, FIG3 shows a schematic top view of the DRAM cell structure 100 according to an embodiment of the present disclosure, and FIG4 shows a schematic vertical cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure. It should be noted that FIG4 is a schematic vertical cross-sectional view taken along line AA′ in FIG3 .

[0053] As shown in FIG1 , a DRAM cell structure 100 according to an embodiment of the present disclosure may include a storage capacitor C and a gate transistor T (as shown in a dotted box). As shown in FIG1 to FIG4 , according to an embodiment of the present disclosure, the gate transistor T may include a vertically extending active region 101, which includes a first source / drain region 102, a channel region 103, and a second source / drain region 104 arranged in sequence from bottom to top along the vertical direction, wherein the first source / drain region 102 may be connected to a bit line BL, and the second source / drain region may be connected to one electrode (lower electrode) CP1 of the storage capacitor C. According to an embodiment of the present disclosure, the other electrode (upper electrode) CP2 of the storage capacitor C may be connected to a source line SL.

[0054] Although FIG1 shows that the bit line BL, the gate transistor T, the storage capacitor C, and the source line SL are arranged in a vertical direction from bottom to top, the configuration of the DRAM cell structure 100 is not limited thereto. According to an alternative embodiment of the present disclosure, the source line SL, the storage capacitor C, the gate transistor T, and the bit line may also be arranged in a vertical direction from bottom to top. In this embodiment, the second source / drain region 102 may be connected to the bit line BL, the first source / drain region 102 may be connected to the upper electrode CP2 of the storage capacitor C, and the lower electrode CP1 of the storage capacitor C may be connected to the source line SL.

[0055] As shown in Figures 1 to 4, according to an embodiment of the present disclosure, the selection transistor T may further include a first gate structure G1 105, a second gate structure G2 106, a third gate structure G3 107 and a fourth gate structure G4 108, wherein the first gate structure G1 105 and the second gate structure G2 106 may be arranged from bottom to top along a vertical direction on a first side of the channel region 103, and the third gate structure G3 107 and the fourth gate structure G4 108 may be arranged from bottom to top along a vertical direction on a second side of the channel region 103 opposite to the first side.

[0056] As shown in Figure 4, according to an embodiment of the present disclosure, the selection transistor T can be a junction-less device, that is, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with the same type. For example, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with a first doping type. According to an embodiment of the present disclosure, the first doping type can be N-type doping, and the second doping type can be P-type doping. However, the present disclosure is not limited to this. According to an alternative embodiment of the present disclosure, the first doping type can be P-type doping, and the second doping type can be N-type doping. According to an embodiment of the present disclosure, the doping concentration of the first source / drain region 102 and the second source / drain region 104 can be higher than the doping concentration of the channel region 103.

[0057] Furthermore, according to an embodiment of the present disclosure, the gate transistor T may also be a junction-type device. That is, different types of doping may be performed on the first source / drain region 102, the channel region 103, and the second source / drain region 104. For example, the first source / drain region 102 and the second source / drain region 104 may be doped with a first doping type, and the channel region 103 may be doped with a second doping type. This will be described in more detail below with reference to FIG. 6 and FIG. 7 .

[0058] As shown in FIG1 , according to an embodiment of the present disclosure, the first source / drain region 102 can be connected to a bit line BL, and the second source / drain region 104 can be connected to one electrode or lower electrode CP1 of the storage capacitor C. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is in a write period, the bit line BL can be connected to a voltage representing data 0 (e.g., ground voltage VSS) or a voltage representing data 1 (e.g., power supply voltage VDD) to store the voltage representing the corresponding data in the storage capacitor C. When the DRAM cell structure 100 is not in a write period, the bit line BL can be connected to an equalization voltage VBLQ. According to an embodiment of the present disclosure, the equalization voltage VBLQ can be, for example, a voltage at the intersection of a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 0 (e.g., ground voltage VSS) and a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 1 (e.g., power supply voltage VDD) (e.g., typically approximately (VDD+VSS) / 2).

[0059] Furthermore, as shown in FIG1 , according to an embodiment of the present disclosure, the other electrode or upper electrode CP2 of the storage capacitor C can be connected to a source line SL. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, the source line SL can be connected to a fixed voltage VFF. For example, according to an embodiment of the present disclosure, the fixed voltage VFF can be used as a reference voltage, which is typically half of the power supply voltage VDD, i.e., VFF = 1 / 2 VDD.

[0060] For clarity, the storage capacitor C, the bit line BL, and the source line SL are not shown in FIG. 2 to FIG. 4 .

[0061] Furthermore, as described above, with reference to Figures 1 to 4 , according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a first gate structure G1 105, a second gate structure G2 106, a third gate structure G3 107, and a fourth gate structure G4 108. According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 are vertically arranged from bottom to top on a first side of the channel region 103 (e.g., the left side as shown in Figures 2 and 4 ), and the third gate structure G3 107 and the fourth gate structure G4 108 are vertically arranged from bottom to top on a second side of the channel region 103 opposite the first side (e.g., the right side as shown in Figures 2 and 4 ). Herein, the first gate structure G1 105 and the third gate structure G3 107 may also be referred to as a lower gate structure, and the second gate structure G2 106 and the fourth gate structure G4 108 may also be referred to as an upper gate structure.

[0062] According to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may be formed of the same conductive material. According to an embodiment of the present disclosure, examples of conductive materials used to form the first to fourth gate structures G1 105 to G4 108 may include: metals or alloys, such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), palladium (Pd), or alloys of the above metals; metal nitrides, such as titanium nitride (TiN); or polysilicon. In addition, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may include a high work function material, a low work function material, or a combination thereof. The low work function material may have a low work function of approximately 4.5 eV or less, and the high work function material may have a high work function of approximately 4.5 eV or more. For example, the low work function material may include N-type doped polysilicon, and the high work function material may include tungsten, titanium nitride, or a combination thereof. According to an alternative embodiment of the present invention, the first to fourth gate structures G1 105 to G4 108 may have a dual work function structure in which a low work function material and a high work function material are combined.

[0063] According to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 can be formed of different conductive materials. For example, the lower gate structure, namely the first gate structure G1 105 and the third gate structure G3 107, can be formed of a metal-based material such as titanium nitride or tungsten, while the upper gate structure, namely the second gate structure G2 106 and the fourth gate structure G4 108, can be formed of polysilicon. According to an embodiment of the present disclosure, by forming the first to fourth gate structures G1 105 to G4 108 with different conductive materials, the work function can be adjusted, thereby adjusting the threshold voltage of the gate transistor T.

[0064] In addition, as more clearly shown in Figures 3 and 4, according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a gate dielectric 109 disposed between the first gate structure G1105 to the fourth gate structure G4 108 and the channel region 103. According to an embodiment of the present disclosure, the gate dielectric 109 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide may have a dielectric constant of approximately 3.9, and the gate dielectric 109 may include a high-k material having a dielectric constant of approximately 4 or greater. As the gate dielectric 109, the high-k material may have a dielectric constant of approximately 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to an alternative embodiment of the present invention, the gate dielectric 109 may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

[0065] Furthermore, as shown in Figures 2 to 4 , according to embodiments of the present disclosure, the first gate structure G1 105 to the fourth gate structure G4 108 may be separated from each other by an isolation dielectric 110. As shown in Figure 3 , according to embodiments of the present disclosure, the two upper gate structures, namely, the second gate structure G2 106 and the fourth gate structure G4 108, may be separated from each other in the horizontal direction using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as the isolation dielectric 110. Similarly, although not shown, according to embodiments of the present disclosure, the two lower gate structures, namely, the first gate structure 105 and the third gate structure 107, may be separated from each other in the horizontal direction using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as the isolation dielectric 110.

[0066] 4 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 disposed on the first side of the channel region 103 may be vertically separated from each other using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as an isolation dielectric 110. Furthermore, the third gate structure G3 107 and the fourth gate structure G4 108 disposed on the second side of the channel region 103 may be vertically separated from each other using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as an isolation dielectric 110. According to an embodiment of the present disclosure, the isolation dielectric 110 may be formed of the same material as or a different material from the gate dielectric 109.

[0067] According to an embodiment of the present disclosure, the first gate structure G1 105, the second gate structure G2 106, the third gate structure G3 107, and the fourth gate structure G4 108 may have the same size and structure. In addition, as shown in Figures 2 and 4, according to an embodiment of the present disclosure, the first gate structure G1 105 and the third gate structure G3 107 may be aligned with each other in the vertical direction, and the second gate structure G2 106 and the fourth gate structure G4 108 may be aligned with each other in the vertical direction.

[0068] As shown in FIG4 , according to an embodiment of the present disclosure, the vertical distance d1 between the upper end of the first gate structure G1 105 and the lower end of the second gate structure G2 106 can be equal to the vertical distance d2 between the upper end of the third gate structure G3 107 and the lower end of the fourth gate structure G4 108, i.e., d1 = d2. According to an embodiment of the present disclosure, the distances d1 and d2 can be greater than the horizontal thickness d3 of the gate dielectric 109 between the first gate structure G1 105 to the fourth gate structure G4 108 and the channel region 103, and preferably greater than twice the horizontal thickness d3 of the gate dielectric 109 between the first gate structure G1 105 to the fourth gate structure G4 108 and the channel region 103, to reduce the impact of parasitic capacitance formed between the first gate structure G1 105 and the second gate structure G2 106, and between the third gate structure G3 107 and the fourth gate structure G4 108.

[0069] In addition, according to an embodiment of the present disclosure, although not shown, a work function adjustment layer may be formed between the gate dielectric 109 and the first to fourth gate structures G1 105 to G4 108 to further adjust the threshold voltage of the gate transistor T.

[0070] Furthermore, according to an embodiment of the present disclosure, although not shown, a doping concentration adjustment layer may be formed at the surface of the channel region 103 overlapping the first to fourth gate structures G1 105 to G4 108 to reduce fluctuations in the threshold voltage of the gate transistor T.

[0071] As shown in FIG3 , according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may be formed to have a “[”-shaped cross-section in the horizontal direction to obtain a larger control area between the gate structure and the channel region 103. In addition, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may also be formed to have a “|”-shaped or “L”-shaped cross-section in the horizontal direction.

[0072] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, the gate transistor T can be equivalent to two dual-gate transistors connected in series, wherein the lower dual-gate transistor (hereinafter referred to as the “lower dual-gate transistor”) uses the first gate structure G1 105 and the third gate structure G3 107 as gates, and the upper dual-gate transistor (hereinafter referred to as the “upper dual-gate transistor”) uses the second gate structure G2 106 and the fourth gate structure G4 108 as gates. Therefore, according to an embodiment of the present disclosure, the gate transistor T is turned on only when both the upper dual-gate transistor and the lower dual-gate transistor are turned on. In addition, according to an embodiment of the present disclosure, the gate transistor T is turned off when at least one of the upper dual-gate transistor and the lower dual-gate transistor is turned off.

[0073] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, by controlling the voltage applied to the first gate structure G1 105 to the fourth gate structure G4 108, the conduction and shutoff of the selection transistor T can be controlled, thereby realizing the read, write and refresh operations of the DRAM cell structure, which will be described in more detail below in conjunction with FIG5 .

[0074] FIG. 5 is a schematic diagram illustrating an operating method of the DRAM cell structure 100 according to an embodiment of the present disclosure.

[0075] In a traditional 1T1C DRAM cell structure, a single transistor is used as a gate transistor to control the formation of a conduction path between the bit line and the storage capacitor. According to an embodiment of the present disclosure, the gate transistor T can be equivalent to two NMOS depletion-type dual-gate transistors (i.e., a lower dual-gate transistor and an upper dual-gate transistor) connected in series to form a logic AND unit. In other words, only when the upper and lower dual-gate transistors are turned on at the same time, a conduction path is formed between the storage capacitor C and the bit line BL, thereby performing read, write and refresh operations on the DRAM cell structure. According to an embodiment of the present disclosure, when one of the upper and lower dual-gate transistors of the gate transistor T is turned on, a conduction path is not formed. In other words, when at least one of the upper and lower dual-gate transistors of the gate transistor T is turned off, a conduction path is not formed. In addition, according to an embodiment of the present disclosure, when the upper and lower dual-gate transistors of the gate transistor T are turned off at the same time, leakage is minimized, and data is continuously retained in the storage capacitor C in the form of charge.

[0076] As shown in FIG2 to FIG4, when the gate transistor T is a junction-less device, that is, the active region 101 is entirely formed of the first doping type semiconductor, when no voltage is applied to the first gate structure G1 105 to the fourth gate structure G4 108, the gate transistor T is in the on state.

[0077] As shown in FIG. 5 , according to an embodiment of the present disclosure, the gate transistor T may be turned on or off by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107 .

[0078] Specifically, as shown in FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is not selected, low voltages VGL1 to VGL4 may be applied to the first to fourth gate structures G1 105 to G4 108 of the gate transistor T, respectively, to ensure that the gate transistor T is turned off. According to an embodiment of the present disclosure, each of the low voltages VGL1 to VGL4 may be a negative voltage, so that the portion of the channel region 103 between the first gate structure G1 105 and the third gate structure G3 107, as well as the portion of the channel region 103 between the second gate structure G2 106 and the fourth gate structure G4 108, are completely pinched off. This ensures that the gate transistor T is turned off while reducing or eliminating leakage current in the off state of the gate transistor T. According to an embodiment of the present disclosure, the low voltages VGL1 to VGL4 applied to the first to fourth gate structures G1 105 to G4 108 may be the same as or different from each other.

[0079] 5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, the second gate structure G2 106 and the third gate structure G3 107 of the gate transistor T can be applied with high voltages VGH2 and VGH3, respectively, and the first gate structure G1 105 and the fourth gate structure G4 108 can remain connected to low voltages VGL1 and VGL4, respectively. According to an embodiment of the present disclosure, each of the high voltages VGH2 and VGH3 can be the ground voltage VSS or a positive voltage, so that the channel region 103 forms a conductive path near the surface overlapping with the second gate structure G2 106 and the third gate structure G3 107. That is, as shown in FIG5 , according to an embodiment of the present disclosure, by applying high voltages VGH2 and VGH3, respectively, to the second gate structure G2 106 and the third gate structure G3 107 of the gate transistor T, an "S"-shaped conduction path can be formed near the surface of the channel region 103 overlapping with the second gate structure G2 106 and the third gate structure G3 107, as shown by arrows in FIG5 , thereby turning on the gate transistor T. According to an embodiment of the present disclosure, the high voltages VGH2 and VGH3, respectively applied to the second gate structure G2 106 and the third gate structure G3 107, can be the same as or different from each other.

[0080] According to an embodiment of the present disclosure, when the gate transistor T is turned on or off by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107, the first gate structure G1 105 and the fourth gate structure G4 108 can be constantly connected to the low voltages VGL1 and VGL4, respectively. In addition, according to an embodiment of the present disclosure, the first gate structure G1 105 and the fourth gate structure G4 108 can also be connected individually or collectively to a bias voltage that prevents the channel region 103 from forming a conductive path near the surface overlapping with the first gate structure G1 105 and the fourth gate structure G4 108, or the first gate structure G1 105 and the fourth gate structure G4 108 can be individually or collectively floated.

[0081] Although FIG5 describes an embodiment of the present disclosure by taking the example of turning on or off the selection transistor T by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107, those skilled in the art should recognize that the selection transistor T can also be turned on or off by controlling the voltage applied to the first gate structure G1 105 and the fourth gate structure G4 108, which can also achieve the technical effects of the present disclosure.

[0082] Specifically, according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, the first gate structure G1 105 and the fourth gate structure G4 108 of the gate transistor T can be applied with high voltages VGH1 and VGH4, respectively, and the second gate structure G2 106 and the third gate structure G3 107 can remain connected to low voltages VGL2 and VGL3, respectively. At this time, an "S"-shaped conduction path can be formed near the surface of the channel region 103 that overlaps with the first gate structure G1 105 and the fourth gate structure G4 108. This "S"-shaped conduction path is mirror-symmetrical to the conduction path indicated by the arrow in FIG. 5 .

[0083] According to an alternative embodiment of the present disclosure, when the gate transistor T is turned on or off by controlling the voltage applied to the first gate structure G1 105 and the fourth gate structure G4 108, the second gate structure G2 106 and the third gate structure G3 107 can be constantly connected to the low voltages VGL2 and VGL3, respectively. In addition, according to an embodiment of the present disclosure, the second gate structure G2 106 and the third gate structure G3 107 can also be connected individually or collectively to a bias voltage that prevents the channel region 103 from forming a conductive path near the surface overlapping with the second gate structure G2 106 and the third gate structure G3 107, or the second gate structure G2 106 and the third gate structure G3 107 can be individually or collectively floated.

[0084] According to an embodiment of the present disclosure, the low voltages VGL1 to VGL4 may be identical to one another and collectively represented as VGL, and the high voltages VGH1 to VGH4 may be identical to one another and collectively represented as VGH.

[0085] FIG6 shows a schematic vertical cross-sectional view of a DRAM cell structure 200 according to another embodiment of the present disclosure. Components in FIG6 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG6 , the DRAM cell structure 200 shown in FIG6 is substantially identical to the DRAM cell structure 100 shown in FIG4 , except that the gate transistor T is a junction-type device.

[0086] Specifically, as shown in FIG6 , according to an embodiment of the present disclosure, the first source / drain region 102 and the second source / drain region 104 of the active region 101 of the gate transistor T of the DRAM cell structure 200 are formed of a first doping type semiconductor, and the channel region 103 can be formed of a second doping type semiconductor. According to an embodiment of the present disclosure, the first doping type can be N-type doping, and the second doping type can be P-type doping. In this case, the gate transistor T can be an NMOS enhancement-mode transistor.

[0087] The operating method of the DRAM cell structure 100 described above with reference to FIG5 can also be applied to the DRAM cell structure 200 shown in FIG6 , that is, the high voltages VGH2 and VGH3 can be applied to the second gate structure G2 106 and the third gate structure G3 107, respectively, and the first gate structure G1 105 and the fourth gate structure G4 108 are respectively maintained at the low voltages VGL1 and VGL4 (or individually or collectively connected to the bias voltage or floating), so that the selection transistor T is turned on (as shown by the arrow in FIG6 ).

[0088] In addition, although not shown in FIG6 , similar to FIG5 , according to an embodiment of the present disclosure, the selection transistor T may be turned on by applying high voltages VGH1 and VGH4 to the first gate structure G1 105 and the fourth gate structure G4 108, respectively, and maintaining the second gate structure G2 106 and the third gate structure G3 107 at low voltages VGL1 and VGL4, respectively (or individually or collectively connected to a bias voltage or floating).

[0089] Unlike the DRAM cell structure 100 shown in FIG4 , the gate transistor T in the DRAM cell structure 200 of FIG6 is a junction-type device. Therefore, when no voltage is applied to the first to fourth gate structures G1 105 to G4 108, the gate transistor T is in an off state. Therefore, in the DRAM cell structure 200 shown in FIG6 , each of the low voltages VGL1 to VGL4 can be, for example, the ground voltage VSS, and each of the high voltages VGH1 to VGH4 can be a positive voltage greater than a threshold voltage.

[0090] In addition, as shown in Figure 6, according to an embodiment of the present disclosure, in order to ensure that the inversion zone formed near the lower end of the second gate structure G2 106 in the channel region 103 overlaps with the inversion zone formed near the upper end of the third gate structure G3 107 (as shown in the shaded area in Figure 6), thereby forming a conductive path in the region corresponding to the spacings d1 and d2 in the channel region 103, at least one of the following conditions should be met: the spacings d1 and d2 are sufficiently small, the high voltages VGH2 and VGH3 applied to the second gate structure G2 106 and the third gate structure G3 107, respectively, are sufficiently large, and the size w of the channel region 103 in the horizontal direction is sufficiently small.

[0091] FIG7 shows a schematic vertical cross-sectional view of a DRAM cell structure 300 according to another embodiment of the present disclosure. Components in FIG7 identical to those shown in FIG6 are denoted by the same reference numerals. As shown in FIG7 , the DRAM cell structure 300 shown in FIG7 is substantially identical to the DRAM cell structure 200 shown in FIG6 , except that a third source / drain region 111 formed of a semiconductor of the first doping type is provided in the channel region 103 of the gate transistor T at portions corresponding to the spacings d1 and d2. In this case, the active region 101 includes a first source / drain region 102, a second source / drain region 104, a third source / drain region 111 disposed between the first source / drain region 102 and the second source / drain region 104, and a channel region 103. According to an embodiment of the present disclosure, the first doping type may be N-type doping, and the second doping type may be P-type doping. In this case, as shown in FIG7 , the gate transistor T can be considered to be composed of two NMOS enhancement-mode transistors connected in series.

[0092] The operating method of the DRAM cell structure 100 described above with reference to FIG5 can also be applied to the DRAM cell structure 300 shown in FIG7 , that is, the high voltages VGH2 and VGH3 can be applied to the second gate structure G2 106 and the third gate structure G3 107, respectively, and the first gate structure G1 105 and the fourth gate structure G4 108 are respectively maintained at the low voltages VGL1 and VGL4 (or individually or collectively connected to the bias voltage or floating), so that the selection transistor T is turned on (as shown by the arrow in FIG7 ).

[0093] In addition, although not shown in FIG. 7 , similar to FIG. 5 , according to an embodiment of the present disclosure, the selection transistor T may be turned on by applying high voltages VGH1 and VGH4 to the first gate structure G1 105 and the fourth gate structure G4 108, respectively, and maintaining the second gate structure G2 106 and the third gate structure G3 107 at low voltages VGL2 and VGL4, respectively (or individually or collectively connected to a bias voltage or floating).

[0094] Unlike the DRAM cell structure 100 shown in FIG4 , the gate transistor T in the DRAM cell structure 300 of FIG7 is a junction-type device. Therefore, when no voltage is applied to the first to fourth gate structures G1 105 to G4 108, the gate transistor T is in an off state. Therefore, in the DRAM cell structure 4 shown in FIG7 , each of the low voltages VGL1 to VGL4 can be, for example, the ground voltage VSS, and each of the high voltages VGH1 to VGH4 can be a positive voltage greater than a threshold voltage.

[0095] In addition, as shown in Figure 7, according to an embodiment of the present disclosure, since an N-type doped third source / drain region 111 is provided in the portion corresponding to the vertical spacings d1 and d2 in the channel region 103, even if the conditional restrictions for forming a conductive path described above in conjunction with Figure 6 are not met, a conductive path can be formed in the channel region 103 via the third source / drain region 111 (as shown by the arrow in Figure 7).

[0096] Furthermore, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 of the gate transistor T of the DRAM cell structure 100 may have an asymmetric configuration.

[0097] FIG8 illustrates a schematic vertical cross-sectional view of a DRAM cell structure 400 according to another embodiment of the present disclosure. Components in FIG8 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG8 , the DRAM cell structure 400 shown in FIG8 is substantially identical to the DRAM cell structure 100 shown in FIG4 , except that the first through fourth gate structures G1 105 through G4 108 have an asymmetric configuration.

[0098] In particular, unlike the configuration shown in FIG4 in which the first gate structure G1 105 is aligned with the third gate structure G3 107 in the vertical direction and the second gate structure G2 106 is aligned with the fourth gate structure G4 108 in the vertical direction, as shown in FIG8 , according to an embodiment of the present disclosure, the first gate structure G1 105 can be staggered with the third gate structure G3 107 in the vertical direction, and the second gate structure G2 106 can be staggered with the fourth gate structure G4 108 in the vertical direction.

[0099] Specifically, as shown in FIG8 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 400, the first gate structure G1 105 disposed on the first side of the channel region 103 is not vertically aligned with the third gate structure G3 107 disposed on the second side of the channel region 103, but is instead lower than the third gate structure G3 107. Furthermore, correspondingly, as shown in FIG8 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 400, the second gate structure G2 106 disposed on the first side of the channel region 103 is not vertically aligned with the fourth gate structure G4 108 disposed on the second side of the channel region 103, but is instead lower than the fourth gate structure G4 108. In other words, according to an embodiment of the present disclosure, compared to the RAM cell structure 100 shown in FIG4 , in the selection transistor T of the DRAM cell structure 400 shown in FIG8 , the first gate structure G1 105 and the second gate structure G2 106 arranged on the first side of the channel region 103 are relatively moved downward as a whole in the vertical direction, while the third gate structure G3 107 and the fourth gate structure G4 108 arranged on the second side of the channel region 103 are relatively moved upward as a whole in the vertical direction.

[0100] According to an embodiment of the present disclosure, in the selection transistor T of the DRAM cell structure 400 shown in FIG8 , by applying high voltages VGH2 and VGH3 to the second gate structure G2 106 relatively downwardly shifted in the vertical direction and the third gate structure G3 107 relatively upwardly shifted (such that the second gate structure G2 106 and the third gate structure 107 are close to each other in the vertical direction), and maintaining the first gate structure G1 105 and the fourth gate structure G4 108 at low voltages VGL1 and VGL4, respectively (either individually or collectively connected to a bias voltage or floating), a larger on-state current can be obtained when the selection transistor T is turned on.

[0101] Similarly, although not shown in FIG8 , according to an embodiment of the present disclosure, when the first gate structure G1 105 and the fourth gate structure G4 108 are used to control the on and off of the selection transistor T, that is, when high voltages VGH1 and VGH4 are applied to the first gate structure G1 105 and the fourth gate structure G4 108, respectively, and the second gate structure G2 106 and the third gate structure G3 107 are maintained at low voltages VGL2 and VGL3, respectively (or are individually or collectively connected to a bias voltage or are floating) so that the selection transistor T is turned on, the first gate structure G1 105 and the second gate structure G2 106 can be relatively moved upward as a whole in the vertical direction, and the third gate structure G3 107 and the fourth gate structure G4 108 can be relatively moved downward as a whole in the vertical direction, so that the first gate structure G1 105 and the fourth gate structure G4 108 are close to each other in the vertical direction.

[0102] Furthermore, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 of the gate transistor T of the DRAM cell structure 100 may have sizes different from each other.

[0103] FIG9 illustrates a schematic vertical cross-sectional view of a DRAM cell structure 500 according to another embodiment of the present disclosure. Components in FIG9 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG9 , the DRAM cell structure 500 shown in FIG9 is substantially identical to the DRAM cell structure 100 shown in FIG4 , except that the sizes of the first through fourth gate structures G1 105 through G4 108 are different.

[0104] 4 , the first to fourth gate structures G1 105 to G4 108 have the same size as each other. As shown in FIG. 9 , according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may have different sizes along the vertical direction.

[0105] Specifically, as shown in FIG9 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 500, the vertical dimension of the first gate structure G1 105 disposed on the first side of the channel region 103 may be smaller than the vertical dimension of the second gate structure G2 106, and the vertical dimension of the fourth gate structure G4 108 disposed on the second side of the channel region 103 may be smaller than the vertical dimension of the third gate structure G3 107. Furthermore, as shown in FIG9 , according to an embodiment of the present disclosure, the vertical dimension of the first gate structure G1 105 may be equal to the vertical dimension of the fourth gate structure G4 108, and the vertical dimension of the second gate structure G2 106 may be equal to the vertical dimension of the third gate structure G3 107.

[0106] According to an embodiment of the present disclosure, in the pass transistor T of the DRAM cell structure 500 shown in FIG9 , when the pass transistor T is turned on by applying high voltages VGH2 and VGH3, respectively, to the second gate structure G2 106 and the third gate structure G3 107, which have relatively large dimensions in the vertical direction, and by maintaining the first gate structure G1 105 and the fourth gate structure G4 108 at low voltages VGL1 and VGL4, respectively (or individually or collectively connected to a bias voltage or floating), a larger on-state current can be obtained.

[0107] Similarly, although not shown in FIG9 , according to an embodiment of the present disclosure, when the first gate structure G1 105 and the fourth gate structure G4 108 are used to control the on and off of the selection transistor T, that is, when the selection transistor T is turned on by applying high voltages VGH1 and VGH4 to the first gate structure G1 105 and the fourth gate structure G8 108, respectively, and maintaining the second gate structure G2 106 and the third gate structure G3 107 at low voltages VGL2 and VGL3, respectively (or individually or collectively connected to a bias voltage or floating), the first gate structure G1 105 and the fourth gate structure G4 108 can be formed to have a size in the vertical direction that is larger than the size of the second gate structure G2 106 and the third gate structure G3 107 in the vertical direction.

[0108] In addition, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may also have different sizes in the horizontal direction.

[0109] Furthermore, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 of the gate transistor T of the DRAM cell structure 100 may have different structures from each other.

[0110] FIG10 illustrates a schematic vertical cross-sectional view of a DRAM cell structure 600 according to another embodiment of the present disclosure. Components in FIG10 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG10 , the DRAM cell structure 600 shown in FIG10 is identical to the DRAM cell structure 100 shown in FIG4 , except that the structures of the first through fourth gate structures G1 105 through G4 108 are different.

[0111] As shown in FIG10 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 600, the lower gate structure, namely the first gate structure G1 105 and the third gate structure G3 107, can have a uniform structure, i.e., all formed of the same material, such as polysilicon, while the upper gate structure, namely the second gate structure G2 106 and the fourth gate structure G4 108, can have a stacked structure. As shown in FIG10 , according to an embodiment of the present disclosure, the second gate structure G2 106 and the fourth gate structure G4 108 can respectively include two layers of gate material, for example, the lower gate material can be formed of polysilicon, and the upper gate material can be formed of titanium nitride. This configuration can adjust the work function, thereby adjusting the threshold voltage of the gate transistor T.

[0112] In addition, those skilled in the art will recognize that, although not shown in FIG10 , according to embodiments of the present disclosure, the upper gate structure, i.e., the second gate structure G2 106 and the fourth gate structure G4 108, may be formed to have a uniform structure, and the lower gate structure, i.e., the first gate structure G1 105 and the third gate structure G3 107, may be formed to have a stacked structure; alternatively, the first gate structure G1 105 and the fourth gate structure G4 108 may be formed to have a uniform structure, and the second gate structure G2 106 and the third gate structure G3 107 may be formed to have a stacked structure; alternatively, the second gate structure G2 106 and the third gate structure G3 107 may be formed to have a uniform structure, and the first gate structure G1 105 and the fourth gate structure G4 108 may be formed to have a stacked structure. All of these variations are intended to be within the scope of the present disclosure.

[0113] 11A and 11B illustrate schematic top views of DRAM cell structures according to other embodiments of the present disclosure. Components in FIG. 11A and FIG. 11B identical to those shown in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 11A and FIG. 11B , the DRAM cell structure shown in FIG. 11A and FIG. 11B is identical to the DRAM cell structure 100 shown in FIG. 3 , except for the horizontal cross-sectional shapes of the second gate structure G2 106 and the fourth gate structure G4 108.

[0114] As shown in FIG11A , unlike the second gate structure G2 106 and the fourth gate structure G4 108 shown in FIG3 which are formed to have a “[”-shaped cross section in the horizontal direction, the second gate structure G2 106 and the fourth gate structure G4 108 in FIG11A are formed to have a “|”-shaped cross section in the horizontal direction.

[0115] 11B , unlike the second gate structure G2 106 and the fourth gate structure G4 108 shown in FIG3 which are formed to have a “[”-shaped cross section in the horizontal direction, the second gate structure G2 106 and the fourth gate structure G4 108 in FIG11B are formed to have an “L”-shaped cross section in the horizontal direction.

[0116] Those skilled in the art should recognize that, although the cross-sections of the first gate structure G1 105 and the third gate structure G3 107 in the horizontal direction are not shown in Figures 11A and 11B , for the purpose of simplifying the process, the cross-section of the first gate structure G1 105 in the horizontal direction may be the same as the cross-section of the second gate structure G2 106 in the horizontal direction shown in Figures 11A and 11B , and the cross-section of the third gate structure G3 107 in the horizontal direction may be the same as the cross-section of the fourth gate structure G4 108 in the horizontal direction shown in Figures 11A and 11B .

[0117] According to the DRAM cell structure and its operation method of the present disclosure, the leakage current of the select transistor can be reduced, thereby improving the switching characteristics.

[0118] FIG. 12 shows an equivalent circuit diagram of a DRAM array structure 700 formed by the DRAM cell structure 100 shown in FIG. 1 according to an embodiment of the present disclosure. As shown in FIG. 12, according to an embodiment of the present disclosure, the DRAM array structure 700 may include a plurality of DRAM cell structures 100 shown in FIG. 1, and some reference numerals inside each DRAM cell structure 100 are omitted for clarity.

[0119] According to an embodiment of the present disclosure, the plurality of DRAM cell structures included in the DRAM array structure 700 may be arranged in an array of M rows and N columns, where M and N are natural numbers greater than 1. According to an embodiment of the present disclosure, the row selection operation of the plurality of DRAM cell structures included in the DRAM array structure 700 may be performed by M + 1 first word lines or M + 1 second word lines, and the column selection operation may be performed by N bit lines.

[0120] It should be noted that for ease of description, FIG. 12 only shows the nth column DRAM cell structure of the DRAM array structure 700 that can be selected through the nth bit line BLn (n is a positive integer, and 0 < n ≤ N). As shown in FIG. 12, according to an embodiment of the present disclosure, the nth column DRAM cell structure of the DRAM array structure 700 may include M DRAM cell structures CELL1n to CELLMn, where each DRAM cell CELLmn includes a storage capacitor Cmn and a select transistor Tmn (m is a positive integer, and 0 < m ≤ M; n is a positive integer, and 0 < n ≤ N).

[0121] According to an embodiment of the present disclosure, a row selection operation of the M DRAM cell structures CELL1n through CELLMn of the nth column of DRAM cell structures can be performed via M+1 first word lines WL1m (m is an integer, and 0≤m≤M). As shown in FIG. 12 , according to an embodiment of the present disclosure, the M+1 first word lines WL10 through WL1M are respectively connected to the second gate structure G2 and the third gate structure G3 of the nth column of DRAM cell structures. Specifically, as shown in Figure 12, the first word line WL10 is connected to the second gate structure G2 of the selection transistor T1n of the DRAM cell structure CELL1n, the first word line WL11 is connected to the third gate structure G3 of the selection transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and the first word line WL12 is connected to the second gate structure G2 of the selection transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n, and so on. The first word line WL1M is connected to the second gate structure G2 of the selection transistor TMn of the DRAM cell structure CELLMn.

[0122] Alternatively, according to an embodiment of the present disclosure, the row selection operation of the M DRAM cell structures CELL1n to CELLMn in the nth column of the DRAM cell structure can also be performed via M+1 second word lines WL2m (m is an integer, and 0≤m≤M). As shown in FIG. 12 , according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M are respectively connected to the first gate structure G1 and the fourth gate structure G4 of the nth column of the DRAM cell structure. Specifically, as shown in Figure 12, the second word line WL20 is connected to the first gate structure G1 of the selection transistor T1n of the DRAM cell structure CELL1n, the second word line WL21 is connected to the fourth gate structure G4 of the selection transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and the second word line WL22 is connected to the first gate structure G1 of the selection transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n, and so on. The second word line WL2M is connected to the first gate structure G1 of the selection transistor TMn of the DRAM cell structure CELLMn.

[0123] According to an embodiment of the present disclosure, N columns of DRAM cell structures can be connected together through M+1 first word lines WL10 to WL1M and M+1 second word lines WL20 to WL2M, thereby forming a DRAM array structure 700 including M rows and N columns, i.e., M×N DRAM cell structures.

[0124] As shown in FIG12 , according to an embodiment of the present disclosure, the M×N DRAM cell structures included in the DRAM array structure 700 can be arranged in mirror-symmetry along the column direction. That is, as shown in FIG12 , each DRAM cell structure is mirror-symmetric relative to its adjacent DRAM cell structure in the column direction. Taking the DRAM cell structure CELL2n shown in FIG12 as an example, its gate transistor T2n is mirror-symmetric with the gate transistor T1n of the adjacent DRAM cell structure CELL1n. That is, the third gate structure G3 of the gate transistor T2n is adjacent to the third gate structure G3 of the gate transistor T1n, and the fourth gate structure G4 of the gate transistor T2n is adjacent to the fourth gate structure G4 of the gate transistor T1n. In addition, the gate transistor T2n of the DRAM cell structure CELL2n is also mirror-symmetrical with the gate transistor T3n of the adjacent DRAM cell structure CELL3n, that is, the first gate structure G1 of the gate transistor T2n is adjacent to the first gate structure G1 of the gate transistor T3n, and the second gate structure G2 of the gate transistor T2n is adjacent to the second gate structure G2 of the gate transistor T3n.

[0125] According to an embodiment of the present disclosure, DRAM cell structures in adjacent rows are configured such that they share a first word line WL1m and a second word line WL2m in the column direction. For example, as shown in FIG12 , in the column direction, a DRAM cell structure CELL2n shares a first word line WL11 and a second word line WL21 with an adjacent DRAM cell structure CELL1n, and shares a first word line WL12 and a second word line WL22 with an adjacent DRAM cell structure CELL3n. In other words, as shown in FIG12 , according to an embodiment of the present disclosure, in the column direction, the first gate structure of the first side of the gate transistor of the DRAM cell structure shares a second word line with the first gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, the second gate structure of the first side of the gate transistor of the DRAM cell structure shares a first word line with the second gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, the third gate structure of the second side of the gate transistor of the DRAM cell structure shares a first word line with the third gate structure of the second side of the gate transistor of its adjacent DRAM cell structure, and the fourth gate structure of the second side of the gate transistor of the DRAM cell structure shares a second word line with the fourth gate structure of the second side of the gate transistor of its adjacent DRAM cell structure. In particular, according to an embodiment of the present disclosure, each DRAM cell structure of the DRAM cell array 700 is connected to two first word lines and two second word lines.

[0126] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share word lines (first word lines and second word lines), the isolation between word lines formed by the gate structures connecting adjacent DRAM cell structures can be omitted. Therefore, compared with the vertical channel transistor (VCT) of the prior art, the size miniaturization of the DRAM array structure can be further improved.

[0127] 13A and 13B respectively illustrate top views of a DRAM array structure including a VCT transistor according to the prior art and a DRAM cell structure of a transistor having four gate structures sharing a bit line according to an embodiment of the present disclosure.

[0128] As shown in FIG13A , in the column direction, word lines formed by connecting gate structures of VCT transistors according to the prior art require isolation dielectrics, which occupy additional area. In contrast, as shown in FIG13B , in the column direction, transistors with four gate structures according to an embodiment of the present disclosure share word lines with adjacent transistors with four gate structures, thereby eliminating isolation between word lines. Consequently, the DRAM array structure shown in FIG13B achieves further size reduction compared to the DRAM array structure shown in FIG13A .

[0129] In fact, according to the embodiment of the present disclosure, compared with the DRAM array structure implemented by the VCT transistor according to the prior art, the DRAM array structure implemented by the transistor with four gate structures according to the embodiment of the present disclosure changes the word line isolation in the horizontal direction to the word line isolation in the vertical direction, thereby achieving further size reduction.

[0130] The following describes the operating method of the DRAM array structure 700 according to an embodiment of the present disclosure based on Figure 12 in combination with Figure 5 and Figure 14. Figure 14 shows a schematic diagram of the operating method of the DRAM array structure 700 according to an embodiment of the present disclosure.

[0131] According to an embodiment of the present disclosure, the gate transistor in each DRAM cell structure in the DRAM array structure 700 is a transistor having a four-gate structure, which, as described above, can be equivalent to two dual-gate transistors connected in series. As described above with reference to FIG5 , by controlling the voltages applied to the four gate structures of the gate transistor, the gate transistor can be controlled to be turned on and off, thereby connecting or disconnecting the conductive path from the bit line of the corresponding DRAM cell structure to the storage capacitor.

[0132] 5 , 12 and 14 , according to an embodiment of the present disclosure, for each DRAM cell structure in the DRAM array structure 700, as described above, the conduction and shutoff of the selection transistor can be controlled by controlling the voltage applied to the second gate structure and the third gate structure of the selection transistor in the DRAM cell structure, that is, the voltage applied to the two first word lines connected thereto.

[0133] 5 , 12 and 14 , taking the case where the DRAM cell structure CELL2n in the 2nd row and nth column shown in FIG12 is selected as an example, when the DRAM cell structure CELL2n is selected, a high voltage VGH is applied to the first word lines WL12 and WL11 of the second gate structure G2 and the third gate structure G3 respectively connected to the selection transistor T2n in the DRAM cell structure CELL2n, so that the selection transistor T2n is turned on (as indicated by the arrow in the DRAM cell structure CELL2n in FIG12 ).

[0134] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share the first and second word lines, the third gate structure G3 of the gate transistor T1n of the DRAM cell structure CELL1n in the 1st row and nth column, which is also connected to the first word line WL11, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T1n of the DRAM cell structure CELL1n, which is close to the third gate structure G3 (as indicated by the arrow in the DRAM cell structure CELL1n in FIG12 ). However, as shown in FIG14 , according to an embodiment of the present disclosure, since the first word line WL10 and the second word line WL21, which are respectively connected to the second gate structure G2 and the fourth gate structure G4 of the DRAM cell structure CELL1n, are applied with a low voltage VGL, the upper dual-gate transistor of the gate transistor T1n is turned off, and the gate transistor T1n of the DRAM cell structure CELL1n as a whole remains turned off.

[0135] Similarly, according to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share the first and second word lines, the second gate structure G2 of the gate transistor T3n of the DRAM cell structure CELL3n in the 3rd row and nth column, which is also connected to the first word line WL12, is also applied with the high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T3n of the DRAM cell structure CELL3n, which is close to the second gate structure G2 (as indicated by the arrow in the DRAM cell structure CELL3n in FIG12 ). However, as shown in FIG14 , according to an embodiment of the present disclosure, since the second word line WL22 and the first word line WL13, which are respectively connected to the first gate structure G1 and the third gate structure G3 of the DRAM cell structure CELL3n, are applied with the low voltage VGL, the lower dual-gate transistor of the gate transistor T3n is turned off, and thus the gate transistor T3n of the DRAM cell structure CELL3n as a whole remains turned off.

[0136] 12 and 14 , according to an embodiment of the present disclosure, by controlling the voltages applied to the first word lines WL11 and WL12 , the DRAM cell structure CELL2 n can be turned on and off without affecting the operations of other DRAM cell structures.

[0137] Therefore, as shown in Figures 12 and 14, according to the embodiments of the present disclosure, the conduction and shutoff of the gate transistor in the DRAM cell structure can be controlled by the voltage applied to the first word line. Specifically, according to the embodiments of the present disclosure, for each DRAM cell structure in the DRAM array structure 700, the conduction and shutoff of the gate transistor of the DRAM cell structure can be controlled by controlling the voltages applied to its second gate structure and third gate structure via the two first word lines.

[0138] According to an embodiment of the present disclosure, in order to ensure that the selection transistors of adjacent DRAM cell structures in the column direction will not be erroneously turned on, in the selection transistors of each DRAM cell structure in the DRAM array structure 700, the gate structures arranged on the same side of the channel region (for example, the first gate structure and the second gate structure arranged on the first side or the third gate structure and the fourth gate structure arranged on the second side) will never be applied with a high voltage VGH at the same time.

[0139] Furthermore, as shown in FIG. 12 and FIG. 14 , according to an embodiment of the present disclosure, M+1 second word lines WL20 to WL2M may be commonly connected to the low voltage VGL.

[0140] Alternatively, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M may be commonly connected to a bias voltage different from VGL or floated to adjust switching characteristics of gate transistors of all DRAM cell structures.

[0141] Alternatively, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M can also be connected to corresponding bias voltages or floated in groups (for example, by storage area (Bank)) or individually, so as to adjust the switching characteristics of the selection transistors of the corresponding DRAM cell structures in groups or individually.

[0142] Specifically, according to the embodiments of the present disclosure, by setting the bias voltage at a lower voltage, the gate transistor including the gate structure connected to the second word line (i.e., the first gate structure and the fourth gate structure) can have a lower leakage current, thereby reducing the power consumption of the corresponding DRAM cell structure. In addition, by setting the bias voltage at a higher voltage, the gate transistor including the gate structure connected to the second word line can have a higher on-state current, thereby improving the read and write speed of the corresponding DRAM cell structure.

[0143] According to the embodiments of the present disclosure, adjusting the bias voltage can provide a greater degree of adjustment than adjusting the switching characteristics of the gate transistor by adjusting the work function of the gate structure alone. Furthermore, according to the embodiments of the present disclosure, adjusting the bias voltage can enable the DRAM array structure to operate in different operating modes, such as a high-performance operating mode and a low-power operating mode.

[0144] Those skilled in the art will appreciate that the operating method of the DRAM array structure according to the present disclosure is not limited to the embodiments described above with reference to FIG. 12 and FIG. 14 .

[0145] For example, according to another embodiment of the present disclosure, the on / off state of the gate transistor in the DRAM cell structure can be controlled by applying voltages to the M+1 second word lines, that is, by controlling the voltages applied to the first gate structure and the fourth gate structure. Accordingly, according to this embodiment of the present disclosure, bias voltages can be applied to the M+1 first word lines collectively, in groups, and / or individually, or they can be left floating.

[0146] The following describes a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure in conjunction with Figures 15A to 15Q. Figures 15A to 15Q respectively show schematic cross-sectional views of various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure. It should be noted that Figures 15A to 15G are cross-sectional views taken in the row direction of the DRAM array structure, i.e., the word line direction, wherein the bit line direction is perpendicular to the paper plane and the word line direction is parallel to the paper plane, while Figures 15H to 15Q are cross-sectional views taken in the column direction of the DRAM array structure, i.e., the bit line direction, wherein the word line direction is perpendicular to the paper plane and the bit line direction is parallel to the paper plane.

[0147] In the following description, the materials for each layer are exemplified. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description of "selectively etching B (relative to A)" indicates that the etching recipe used can primarily affect B, with little or no effect on A or other material layers exposed to the etching recipe when etching B (in the absence of explicit mention of A or only a portion of such material layers). Based on this description, those skilled in the art will understand how to select the materials for each layer, and are not limited to the materials exemplified herein.

[0148] As shown in FIG15A , according to an embodiment of the present disclosure, a substrate 1501 may be provided, and a well region 1502 may be formed on the substrate 1501 by, for example, an ion implantation process. According to an embodiment of the present disclosure, the substrate 1501 may be a P-type silicon substrate, and the well region 1502 may be an N-type well region. However, according to an embodiment of the present disclosure, the substrate 1501 may also be a substrate of other forms, including but not limited to a bulk semiconductor material substrate such as a bulk silicon substrate, a semiconductor on insulator (SOI) substrate, a compound semiconductor substrate such as a silicon germanium (SiGe) substrate, etc. Alternatively, the substrate 401 may also be an N-type silicon substrate, and the well region 402 may be a P-type well region.

[0149] Subsequently, as shown in FIG15B , according to an embodiment of the present disclosure, a sacrificial layer 1503 and an active layer 1504 may be sequentially grown on the well region 1502 by, for example, an epitaxial process. According to an embodiment of the present disclosure, the sacrificial layer 1503 may be formed of a silicon-germanium material having an etch selectivity, such as silicon-germanium (SiGe) or germanium (Ge). According to an embodiment of the present disclosure, the sacrificial layer 1503 may be used to form a conductor line serving as a bit line in a subsequent process step. According to an embodiment of the present disclosure, the active layer 1504 may include a semiconductor material, such as silicon (Si).

[0150] According to an embodiment of the present disclosure, the active layer 1504 may be in-situ doped when grown, for example, by an epitaxial process. It should be noted that according to an embodiment of the present disclosure, the active layer 1504 may be used to form, in subsequent process steps, the active region 101 of the gate transistor T of the DRAM cell structure 100 described above with reference to FIG. 2 to FIG. 4 , which may include the first source / drain region, the second source / drain region, and a channel region therebetween.

[0151] As described above, according to embodiments of the present disclosure, the gating transistor T can be a junctionless device, in which case the active layer 1504 can be doped with the same type of doping, such as N-type doping. Furthermore, according to embodiments of the present disclosure, the gating transistor T can also be a junction-type device, in which case the active layer 1504 can be doped with different types of doping. For example, the lower and upper portions of the active layer 1504 can be doped with N-type to form the first source / drain region and the second source / drain region of the gating transistor T, respectively, and the middle portion of the active layer 1504 can be doped with P-type to form the channel region. For clarity, this description is based on the example of a junctionless device in the gating transistor T.

[0152] Alternatively, although not shown, the active layer 1504 may also include a plurality of semiconductor material layers sequentially disposed on the sacrificial layer 1504, such as a first semiconductor layer for forming a first source / drain region of the gate transistor T, a second semiconductor layer for forming a channel region of the gate transistor T, and a third semiconductor layer for forming a second source / drain region of the gate transistor T. These semiconductor layers may be doped with different types or concentrations as needed.

[0153] Subsequently, as shown in FIG15C , according to an embodiment of the present disclosure, a hard mask layer may be formed on the active layer 1504 by, for example, a deposition process, and then patterned and etched to form a first hard mask stopper 1507. According to an embodiment of the present disclosure, the first hard mask stopper 1507 may include, for example, silicon oxide, silicon nitride, silicon glass, polysilicon, amorphous silicon, or a combination thereof. It should be noted that the first hard mask stopper 1507 shown in FIG15C extends in the column direction (i.e., perpendicular to the paper), i.e., in the bit line direction.

[0154] Subsequently, according to an embodiment of the present disclosure, a first spacer 1505 can be formed on both sides of the first hard mask barrier 1507 through a spacer process to expose a portion of the upper surface of the active layer 1504. It should be noted that, similar to the first hard mask barrier 1507, the first spacer 1505 also extends in the column direction (i.e., perpendicular to the paper), i.e., the bit line direction. According to an embodiment of the present disclosure, the first spacer 1505, which serves as a mask for self-aligned etching in subsequent process steps, can be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the row direction.

[0155] Subsequently, according to an embodiment of the present disclosure, the active layer 1504, the sacrificial layer 1503, the well region 1502, and / or a portion of the substrate 1501 may be sequentially self-alignedly etched using, for example, the first hard mask barrier 1507 and the first spacer 1505 as masks through an etching process to form a first trench G1 extending into the substrate 1501. According to an embodiment of the present disclosure, the first trench G1 may extend vertically into the substrate 1501. It should be noted that, according to an embodiment of the present disclosure, the first trench G1 also extends along the column direction (i.e., a direction perpendicular to the paper), i.e., the bit line direction.

[0156] 15D , according to an embodiment of the present disclosure, a first isolation dielectric 1506 may be filled in the first trench G1 by, for example, a deposition process, and the upper surfaces of the first hard mask barrier 1507, the first isolation dielectric 1506, and the first spacer 1505 may be planarized by, for example, a grinding process or an etching process. According to an embodiment of the present disclosure, the first isolation dielectric 1506 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof.

[0157] Subsequently, as shown in FIG15E , according to an embodiment of the present disclosure, the first hard mask stopper 1507 can be removed by, for example, an etching process, and the active layer 1504 can be self-alignedly etched using the first spacer 1505 as a mask to form a second trench G2 that exposes the sacrificial layer 1503. It should be noted that according to an embodiment of the present disclosure, similar to the first trench G1, the second trench G2 also extends along the column direction (i.e., perpendicular to the paper), i.e., the bit line direction. In other words, the first trench G1 is parallel to the second trench G2.

[0158] According to an embodiment of the present disclosure, although not shown, after forming the second groove G2, a protective layer may be formed along the inner surface of the second groove G2 to protect the active area of ​​the gate transistor of the DRAM cell structure in subsequent process steps. According to an embodiment of the present disclosure, the protective layer may include an oxide, such as silicon oxide.

[0159] According to an embodiment of the present disclosure, the first groove G1 and the second groove G2 may be formed respectively by performing two self-aligned etching steps using the first spacer 1505 as a mask.

[0160] Subsequently, according to an embodiment of the present disclosure, the sacrificial layer 1503 may be removed through the second groove G2 by, for example, an etching process.

[0161] Subsequently, as shown in FIG15F , according to an embodiment of the present disclosure, a conductive material layer can be conformally formed along the inner surface of the second groove G2 and the upper surface of the entire semiconductor structure (i.e., the DRAM array structure) by, for example, a deposition process (e.g., atomic layer deposition (ALD)). According to an embodiment of the present disclosure, the conductive material layer can include a metal or alloy, such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), palladium (Pd), or alloys of the above metals. In particular, according to an embodiment of the present disclosure, the conductive material layer can include, for example, titanium nitride (TiN).

[0162] Subsequently, according to an embodiment of the present disclosure, a portion of the conductive material layer may be removed by, for example, an etching process to bury a conductor line 1509 in the space left by removing the sacrificial layer 1503 below the active layer 1504. As shown in FIG15F , according to an embodiment of the present disclosure, the conductor line 1509 may be formed into a structure having a mirrored “[”-shaped cross-section. According to an embodiment of the present disclosure, as shown in FIG15F , the opening of the “[”-shaped cross-section of the conductor line formed using the second groove G2 faces the second groove G2, that is, the openings of the “[”-shaped cross-section of the conductor line formed using the same second groove G2 face each other. However, the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the conductor line 1509 may also be formed into a structure having a solid rectangular cross-section.

[0163] According to an alternative embodiment of the present disclosure, when the conductive material layer includes metal, silicidation can be performed by, for example, an annealing process, so that metal silicide is formed below the active layer 1504 in the space left by removing the sacrificial layer 1503 through the second groove G2, so that these metal silicides can form conductor lines used as, for example, bit lines.

[0164] According to an embodiment of the present disclosure, the first spacer 1505 used as a mask for self-aligned etching may further define a dimension of a conductor line 1509 used as a bit line in a row direction.

[0165] Subsequently, as shown in FIG15G , according to an embodiment of the present disclosure, the well region 1502 and / or a portion of the substrate 1501 can be etched downward through the second trench G2, for example, by an etching process, so that the second trench G2 extends into the substrate 1501. The second trench G2 can then be filled with a second isolation dielectric 1510, for example, by a deposition process. According to an embodiment of the present disclosure, since the first trench G1 and the second trench G2 are formed in different etching process steps, the bottom ends of the first trench G1 and the second trench G2 may or may not be aligned in the vertical direction. According to an embodiment of the present disclosure, the second isolation dielectric 1510 can fill the recessed portion of the conductor line 1509 having a "["-shaped cross-section formed by the second trench G2. According to an embodiment of the present disclosure, the second isolation dielectric 1510 can include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the second isolation medium 1510 may be formed of the same material as the first isolation medium 1506 , or may be formed of a different material from the first isolation medium 1506 .

[0166] According to an embodiment of the present disclosure, first trench G1 and second trench G2 extend into substrate 1501 and are respectively filled with non-conductive first isolation dielectric 1506 and second isolation dielectric 1510. Furthermore, a PN junction formed between N-type well region 1502 and P-type substrate 1501 below conductor lines 1509 can isolate conductor lines 1509 from one another from below, reducing the effects of parasitic capacitance between conductor lines 1509. In an embodiment of the present disclosure, buried conductor lines 1509 serving as bit lines are formed by first trench G1 and second trench G2. Therefore, first trench G1 and second trench G2 may also be collectively referred to herein as bit line trenches.

[0167] Through the process steps shown in Figures 15A to 15G, a first groove G1 and a second groove G2 can be formed by two self-aligned etchings using the first sidewall 1505 (and the first hard mask blocking portion 1507) as a mask, so that a buried conductor line 1509 serving as a bit line extending along the column direction (i.e., the direction perpendicular to the paper surface of Figures 15A to 15G) is formed in the DRAM array structure composed of vertical DRAM cell structures, and the size of the active area of ​​the selection transistor of each DRAM cell structure of the DRAM array structure in the row direction is also limited.

[0168] It should be noted that FIG. 15H to FIG. 15Q illustrate cross-sectional views of the DRAM array structure taken along line BB′ of FIG. 15G , ie, cross-sectional views in the row direction of the DRAM array structure, ie, in the word line direction.

[0169] Specifically, as shown in FIG15H , according to an embodiment of the present disclosure, a second hard mask stopper 1511 extending in the row direction (i.e., the direction perpendicular to the paper), i.e., the word line direction, is formed on the first spacer 1505, the first isolation dielectric 1506, and the second isolation dielectric 1510 (not shown in FIG15H ). According to an embodiment of the present disclosure, the second hard mask stopper 1511 may include, for example, silicon oxide, silicon nitride, silicon glass material, polysilicon, amorphous silicon, or a combination of the above materials. According to an embodiment of the present disclosure, the second hard mask stopper 1511 may have an etching selectivity different from that of the first spacer 1505 thereunder. According to an embodiment of the present disclosure, the second hard mask stopper 1511 may be used to limit the size of the active area 101 described above with reference to FIG2 to FIG4 in the column direction.

[0170] Subsequently, as shown in FIG15I , according to an embodiment of the present disclosure, the first spacer 1505 and the active layer 1504 can be self-alignedly etched sequentially using the second hard mask barrier 1511 as a mask, for example, through an etching process to form a third trench G3. According to an embodiment of the present disclosure, the third trench G3 is used to define the position of the subsequently formed word line, and therefore, the third trench may also be referred to herein as a word line trench, which is horizontally perpendicular to the bit line trench. According to an embodiment of the present disclosure, the etching depth of the third trench G3 can be controlled so that its lower end does not extend into the metal bit line 1509 below.

[0171] Subsequently, as shown in FIG. 15J , according to an embodiment of the present disclosure, a third isolation dielectric 1512 a may be formed at the bottom of the third trench G3 by, for example, a deposition process.

[0172] 15K , according to an embodiment of the present disclosure, a gate dielectric 1513 a may be formed, for example, by a deposition process, along the surface of the third trench G3 and the upper surface of the second hard mask barrier 1511. According to an embodiment of the present disclosure, the gate dielectric 1513 a may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG. 2 to FIG. 4 .

[0173] Subsequently, as shown in FIG15L , according to an embodiment of the present disclosure, a lower conductor line 1514 serving as both a word line and a gate structure can be formed in the third trench G3 through, for example, a deposition process and an etching process, wherein the lower conductor line 1514 is separated from the active layer 1504 by a gate dielectric 1513 a. According to an embodiment of the present disclosure, the lower conductor line 1514 can simultaneously serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , and as the first word line or the second word line described above in conjunction with FIG12 .

[0174] Subsequently, as shown in Figure 15M, according to an embodiment of the present disclosure, a third isolation dielectric 1512b can be again filled in the bottom of the third groove G3 (i.e., on the gate dielectric 1513a and the lower conductor line 1514) through, for example, a deposition process to achieve isolation between the lower conductor line 1514 and the subsequently formed upper conductor line 1515 (see Figure 15N).

[0175] Subsequently, as shown in FIG15N , according to an embodiment of the present disclosure, a gate dielectric 1513 b and an upper conductor line 1515 can be formed in the third trench G3 above the lower conductor line 1514 by repeating the steps described above with reference to FIG15K and FIG15L , wherein the upper conductor line 1515 is separated from the active layer 1504 by the gate dielectric 1513 b. According to an embodiment of the present disclosure, the upper conductor line 1515 can also serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line or the second word line described above in conjunction with FIG12 . According to an embodiment of the present disclosure, the dielectric material and thickness of the gate dielectrics 1513 a and 1513 b can be the same or different.

[0176] According to an embodiment of the present disclosure, the method for forming the lower conductor line 1514 and the upper conductor line 1515 in the third trench G3 is not limited to the method described above. For example, according to an alternative embodiment of the present disclosure, after forming the gate dielectric 1513a in the third trench G3 as shown in FIG15K , the lower conductor line 1514, the third isolation dielectric 1512b, and the upper conductor line 1515 can be sequentially formed in the third trench G3 from bottom to top. In this case, the gate dielectric 1513a used to isolate the lower conductor line 1514 from the active layer 1504 and the gate dielectric 1513b used to isolate the upper conductor line 1515 from the active layer 1504 are connected together. All of these alternative embodiments are also within the scope of the present disclosure.

[0177] Subsequently, as shown in FIG15O , according to an embodiment of the present disclosure, the third trench G3 may be filled with a third isolation dielectric 1512 c, for example, by a deposition process. According to an embodiment of the present disclosure, the third isolation dielectrics 1512 a, 1512 b, and 1512 c may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination thereof. The third isolation dielectrics 1512 a, 1512 b, and 1512 c may be formed of the same material as the first isolation dielectric 1506 and / or the second isolation dielectric 1510, or may be formed of a different material than the first isolation dielectric 1506 and / or the second isolation dielectric 1510. Although collectively referred to as the third isolation dielectric, the dielectric material and thickness of the third isolation dielectrics 1512 a, 1512 b, and 1512 c may be the same or different.

[0178] Subsequently, as shown in FIG. 15P , according to an embodiment of the present disclosure, the remaining second hard mask barrier 1511 and the first spacer 1505 may be removed by, for example, an etching process to expose the active layer 1504 .

[0179] Through the process steps shown in Figures 15H to 15P, a DRAM array structure is formed having two layers of conductor lines serving as the first word line and the second word line, namely, the lower conductor line 1514 and the upper conductor line 1515, extending along the row direction (i.e., the direction perpendicular to the paper surface of Figures 15H to 15P), and the size of the active area of ​​the selection transistor of each DRAM unit structure of the DRAM array structure in the column direction is limited by the second hard mask blocking portion 1511.

[0180] Subsequently, as shown in FIG15Q , according to an embodiment of the present disclosure, a contact 1516 may be formed on the active layer 1504, and a storage capacitor may be formed on the contact 1516, thereby forming a DRAM array structure. Since the process steps for forming the storage capacitor are well known to those skilled in the art, they will not be described in further detail herein for the sake of brevity.

[0181] As shown in FIG15Q , since adjacent DRAM cell structures in the column direction share word lines (first word line and second word line), the area overhead for isolating the word lines can be omitted, thereby further achieving size reduction of the DRAM array structure.

[0182] Returning to FIG. 1 to FIG. 4 , according to an embodiment of the present disclosure, the first to fourth gate structures 105 to 108 of the gate transistor T of the DRAM cell structure 100 may have different positions from each other.

[0183] FIG16 illustrates a vertical cross-sectional view of a DRAM cell structure 800 according to another embodiment of the present disclosure. Components in FIG16 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG16 , the DRAM cell structure 800 shown in FIG16 is substantially identical to the DRAM cell structure 100 shown in FIG4 , except that the first through fourth gate structures G1 105 through G4 108 have an asymmetric configuration.

[0184] In particular, unlike the configuration shown in Figure 4 in which the first gate structure G1 105 is aligned with the third gate structure G3 107 in the vertical direction and the second gate structure G2 106 is aligned with the fourth gate structure G4 108 in the vertical direction, as shown in Figure 16, according to an embodiment of the present disclosure, the first gate structure G1 105 can be staggered with the third gate structure G3 107 in the vertical direction, and the second gate structure G2 106 can be staggered with the fourth gate structure G4 108 in the vertical direction.

[0185] Specifically, as shown in FIG16 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 800, the first gate structure G1 105 disposed on the first side of the channel region 103 is not vertically aligned with the third gate structure G3 107 disposed on the second side of the channel region 103, but is instead lower than the third gate structure G3 107. Furthermore, correspondingly, as shown in FIG16 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 800, the second gate structure G2 106 disposed on the first side of the channel region 103 is not vertically aligned with the fourth gate structure G4 108 disposed on the second side of the channel region 103, but is instead lower than the fourth gate structure G4 108. In other words, according to an embodiment of the present disclosure, compared to the RAM cell structure 100 shown in FIG4 , in the selection transistor T of the DRAM cell structure 800 shown in FIG16 , the first gate structure G1 105 and the second gate structure G2 106 arranged on the first side of the channel region 103 are relatively moved downward as a whole in the vertical direction, while the third gate structure G3 107 and the fourth gate structure G4 108 arranged on the second side of the channel region 103 are relatively moved upward as a whole in the vertical direction.

[0186] According to an embodiment of the present disclosure, in the selection transistor T of the DRAM cell structure 800 shown in Figure 16, when the conduction of the selection transistor T is controlled by applying a high voltage VGH to the second gate structure 106 that moves downward in the vertical direction and the third gate structure 107 that moves upward (so that the second gate structure 106 and the third gate structure 107 are close to each other in the vertical direction), and maintaining the first gate structure 105 and the fourth gate structure 108 at a low voltage VHL, a larger on-state current can be obtained.

[0187] Similarly, although not shown in FIG16 , according to an embodiment of the present disclosure, when the conduction of the selection transistor T is controlled by applying a high voltage VGH to the first gate structure 105 and the fourth gate structure 108, and maintaining the second gate structure 106 and the third gate structure 107 at a low voltage VHL, the first gate structure 105 and the second gate structure 106 can be moved upward as a whole in the vertical direction, and the third gate structure 107 and the fourth gate structure 108 can be moved downward as a whole in the vertical direction, so that the first gate structure 105 and the fourth gate structure 108 are close to each other in the vertical direction.

[0188] Furthermore, according to an embodiment of the present disclosure, the first to fourth gate structures 105 to 108 of the gate transistor T of the DRAM cell structure 100 may have sizes different from each other.

[0189] FIG17 shows a vertical cross-sectional view of a DRAM cell structure 900 according to another embodiment of the present disclosure. Components in FIG17 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG17 , the DRAM cell structure 900 shown in FIG17 is identical to the DRAM cell structure 100 shown in FIG4 , except that the sizes of the first to fourth gate structures 105 to 108 are different.

[0190] 4 , the first to fourth gate structures G1 105 to G4 108 have the same size as each other. As shown in FIG. 17 , according to an embodiment of the present disclosure, the first to fourth gate structures 105 to 108 may have different sizes in the vertical direction.

[0191] Specifically, as shown in FIG17 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 900, the vertical dimension of the first gate structure 105 disposed on the first side of the channel region 103 may be smaller than the vertical dimension of the second gate structure 106, and the vertical dimension of the fourth gate structure 108 disposed on the second side of the channel region 103 may be smaller than the vertical dimension of the third gate structure 107. Furthermore, as shown in FIG17 , according to an embodiment of the present disclosure, the vertical dimension of the first gate structure 105 may be equal to the vertical dimension of the fourth gate structure 108, and the vertical dimension of the second gate structure 106 may be equal to the vertical dimension of the third gate structure 107.

[0192] According to an embodiment of the present disclosure, in the selection transistor T of the DRAM cell structure 900 shown in Figure 17, when the conduction of the selection transistor T is controlled by applying a high voltage VGH to the second gate structure 106 and the third gate structure 107 with relatively large dimensions in the vertical direction, and maintaining the first gate structure 105 and the fourth gate structure 108 at a low voltage VHL, a larger on-state current can be obtained.

[0193] Similarly, although not shown in FIG17 , according to an embodiment of the present disclosure, when the conduction of the selection transistor T is controlled by applying a high voltage VGH to the first gate structure 105 and the fourth gate structure 108 and maintaining the second gate structure 106 and the third gate structure 107 at a low voltage VHL, the first gate structure 105 and the fourth gate structure 108 may be formed to have a size in the vertical direction that is larger than a size in the vertical direction of the second gate structure 106 and the third gate structure 107.

[0194] By appropriately adjusting the manufacturing method of the DRAM array structure according to the embodiment of the present disclosure described above with reference to Figures 15A to 15Q, a DRAM array structure formed of multiple DRAM cell structures described above with reference to Figures 16 and 17 can be manufactured.

[0195] 18A to 18G illustrate schematic cross-sectional views of various process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure.

[0196] For the sake of brevity, the components in Figures 18A to 18G that are identical to those in Figures 15A to 15Q are denoted by the same reference numerals, and the corresponding descriptions are omitted.

[0197] FIG18A may be continued from FIG15G, that is, the process steps prior to the process steps shown in FIG18A may be the same as the process steps described above with reference to FIG15A to FIG15G. Furthermore, similar to FIG15H to FIG15Q, FIG18A to FIG18G are cross-sectional views taken along the column direction of the DRAM array structure, i.e., the bit line direction.

[0198] As shown in FIG18A , according to an embodiment of the present disclosure, a third hard mask stopper 1518 and a second spacer 1517 are formed on the first spacer 1505, the first isolation dielectric 1506, and the second isolation dielectric 1510 (not shown in FIG18A ), extending in the row direction (i.e., perpendicular to the paper), i.e., the word line direction. According to an embodiment of the present disclosure, the third hard mask stopper 1518 may include, for example, silicon oxide, silicon nitride, silicon glass, polycrystalline silicon, amorphous silicon, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the third hard mask stopper 1518 may have a different etch selectivity than the first spacer 1505 and the second spacer 1517 below it. According to an embodiment of the present disclosure, the second spacer 1517 may have a different etch selectivity than the first spacer 1505. According to an embodiment of the present disclosure, the second spacer 1517 is used to limit the size of the active area 101 in the column direction described above with reference to FIG2 to FIG4 .

[0199] Subsequently, as shown in FIG18B , according to an embodiment of the present disclosure, the first spacer 1505 and the active layer 1504 can be etched using the second spacer 1517 as a mask, for example, by an etching process to form a fourth trench G4. According to an embodiment of the present disclosure, the fourth trench G4 is used to subsequently form a portion of the word lines (e.g., odd-numbered word lines or even-numbered word lines) of the DRAM array structure. Therefore, the fourth trench G4 can also be referred to as the first word line trench herein, which is horizontally perpendicular to the bit line trench. According to an embodiment of the present disclosure, the etching depth of the fourth trench G4 can be controlled so that its lower end does not extend into the metal bit line 1509 below.

[0200] Subsequently, as shown in FIG18C , according to an embodiment of the present disclosure, a third isolation dielectric 1512 a, a gate dielectric 1513 a, a lower conductor line 1514, a third isolation dielectric 1512 b, a gate dielectric 1513 b, an upper conductor line 1515, and a third isolation dielectric 1512 c can be sequentially formed from bottom to top in the fourth trench G4, for example, by the process described above with reference to FIG15J to FIG15O . In other words, the gate structure and word line on one side of each DRAM cell structure are formed in the fourth trench G4.

[0201] Subsequently, as shown in Figure 18D, according to an embodiment of the present disclosure, the third isolation medium 1512c above can be removed by, for example, a grinding process to expose the third hard mask blocking portion 1518, and the third hard mask blocking portion 1518 and the first side wall 1505 thereunder can be removed by, for example, an etching process using the second side wall 1517 as a mask to expose the active layer 1504.

[0202] Subsequently, as shown in FIG18E , according to an embodiment of the present disclosure, the active layer 1504 exposed by the process step shown in FIG18D can be etched using the second sidewall 1517 as a mask, for example, by an etching process to form a fifth groove G5. According to an embodiment of the present disclosure, the fifth groove G5 is used to subsequently form the remaining word lines (e.g., even-numbered word lines or odd-numbered word lines) of the DRAM array structure. Therefore, the fifth groove G5 can also be referred to as a second word line groove in this article, which is parallel to the first word line groove in the horizontal direction and perpendicular to the bit line groove. According to an embodiment of the present disclosure, the etching depth of the fifth groove G5 can be controlled so that its lower end does not extend into the metal bit line 1509 below. In addition, according to an embodiment of the present disclosure, the depth of the fifth groove G5 in the vertical direction can be different from that of the fourth groove G4. In particular, as shown in FIG18E , the depth of the fifth groove G5 can be less than that of the fourth groove G4.

[0203] Subsequently, as shown in FIG18F , according to an embodiment of the present disclosure, a fourth isolation dielectric 1522 a, a gate dielectric 1523 a, a lower conductor line 1524, a fourth isolation dielectric 1522 b, a gate dielectric 1523 b, an upper conductor line 1525, and a fourth isolation dielectric 1522 c can be sequentially formed from bottom to top in the fifth trench G5, for example, by the process described above with reference to FIG15J to FIG15O . In other words, the gate structure and word lines on the other side of each DRAM cell structure are formed in the fifth trench G5. According to an embodiment of the present disclosure, the materials of the fourth isolation medium 1522a, the gate dielectric 1523a, the lower conductor line 1524, the fourth isolation medium 1522b, the gate dielectric 1523b, the upper conductor line 1525 and the fourth isolation medium 1522c may be the same as or different from the materials of the third isolation medium 1512a, the gate dielectric 1513a, the lower conductor line 1514, the third isolation medium 1512b, the gate dielectric 1513b, the upper conductor line 1515 and the third isolation medium 1512c, respectively.

[0204] As shown in FIG. 18F , according to an embodiment of the present disclosure, the first gate structure of each DRAM cell structure may be staggered with the third gate structure in the vertical direction, and the second gate structure may be staggered with the fourth gate structure in the vertical direction.

[0205] Furthermore, according to an embodiment of the present disclosure, by adjusting the vertical dimensions of the gate structures formed in the fourth trench G4 and the fifth trench G5 , the first to fourth gate structures of each DRAM cell structure may have different vertical dimensions.

[0206] Subsequently, as shown in Figure 18G, according to an embodiment of the present disclosure, the remaining second sidewall 1517 can be removed by, for example, a grinding process and an etching process to expose the active layer 1504, a contact portion 1516 is formed on the active layer 1504, and a storage capacitor is formed on the contact portion 1516, thereby forming a DRAM array structure.

[0207] As shown in FIG18G , since adjacent DRAM cell structures in the column direction share word lines, the area overhead for isolating the word lines can be omitted, thereby further achieving size reduction of the DRAM array structure.

[0208] According to the embodiment of the present disclosure, since the gate structures and word lines on both sides of each DRAM cell structure are formed in different grooves (i.e., the fourth groove G4 (first word line groove) and the fifth groove G5 (second word line groove)), their sizes and positions can be controlled, so that the DRAM cell structure that can be finally formed can have a cross-section as shown in Figure 16 or Figure 17.

[0209] According to the DRAM array structure, operation method, and manufacturing method of the present disclosure, by using a vertical transistor with four gate structures as the select transistor of the DRAM cell structure and sharing word lines between adjacent DRAM cell structures in the column direction, the inherent spacer region between word lines in the conventional ring-gate transistor-based DRAM array structure is eliminated, thereby achieving further size scaling.

[0210] FIG. 19 shows an equivalent circuit diagram of a DRAM array structure 1000 formed by the DRAM cell structure 100 shown in FIG. 1 according to an embodiment of the present disclosure. FIG. 20 shows an equivalent circuit diagram of a DRAM array structure 1100 formed by the DRAM cell structure 100 shown in FIG. 1 according to another embodiment of the present disclosure. As shown in FIGS. 19 and 20, according to an embodiment of the present disclosure, the DRAM array structures 1000 and 1100 may include a plurality of DRAM cell structures 100 shown in FIG. 1, where some reference numerals inside each DRAM cell structure 100 are omitted for clarity.

[0211] According to an embodiment of the present disclosure, the plurality of DRAM cell structures included in the DRAM array structures 1000 and 1100 may be arranged in an array of M rows and N columns, where M and N are natural numbers greater than 1. According to an embodiment of the present disclosure, the row selection operation of the plurality of DRAM cell structures included in the DRAM array structures 1000 and 1100 may be performed by M + 1 word lines, and the column selection operation may be performed by N bit lines.

[0212] It should be noted that for ease of description, FIGS. 19 and 20 only show the nth column DRAM cell structures of the DRAM array structures 1000 and 1100 that can be selected by the nth bit line BLn (n is a positive integer, and 0 < n ≤ N). As shown in FIGS. 19 and 20, according to an embodiment of the present disclosure, the nth column DRAM cell structures of the DRAM array structures 1000 and 1100 may include M DRAM cell structures CELL1n to CELLMn, where each DRAM cell CELLmn includes a storage capacitor Cmn and a select transistor Tmn (m is a positive integer, and 0 < m ≤ M; n is a positive integer, and 0 < n ≤ N).

[0213] According to an embodiment of the present disclosure, the row selection operation of the M DRAM cell structures CELL1n to CELLMn in the nth column DRAM cell structure may be performed by M + 1 word lines WLm (m is an integer, and 0 ≤ m ≤ M).

[0214] As shown in FIG19 , according to an embodiment of the present disclosure, M+1 word lines WL0 through WLM can be connected to the second gate structure G2 and the third gate structure G3 of the nth column of DRAM cell structures, respectively. Specifically, as shown in FIG19 , word line WL0 is connected to the second gate structure G2 of the gate transistor T1n of DRAM cell structure CELL1n, word line WL1 is connected to the third gate structure G3 of the gate transistors T1n and T2n of DRAM cell structures CELL1n and CELL2n, and word line WL2 is connected to the second gate structure G2 of the gate transistors T2n and T3n of DRAM cell structures CELL2n and CELL3n. Similarly, word line WLM is connected to the second gate structure G2 of the gate transistor TMn of DRAM cell structure CELLMn. As shown in FIG19 , in this embodiment, the control line CL is commonly connected to the first gate structure G1 and the fourth gate structure G4 of each DRAM cell structure in the DRAM array structure 1000.

[0215] Alternatively, as shown in FIG20 , according to an embodiment of the present disclosure, the M+1 word lines WL0 through WLM may also be connected to the first gate structure G1 and the fourth gate structure G4 of the nth column of DRAM cell structures, respectively. Specifically, as shown in FIG20 , word line WL0 is connected to the first gate structure G1 of the gate transistor T1n of the DRAM cell structure CELL1n, word line WL1 is connected to the fourth gate structure G4 of the gate transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and word line WL2 is connected to the first gate structure G1 of the gate transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n. Similarly, word line WLM is connected to the first gate structure G1 of the gate transistor TMn of the DRAM cell structure CELLMn. As shown in FIG20 , in this embodiment, the control line CL is commonly connected to the second gate structure G2 and the third gate structure G3 of each DRAM cell structure in the DRAM array structure 1100.

[0216] As shown in Figures 19 and 20, according to an embodiment of the present disclosure, N columns of DRAM cell structures can be connected together through M+1 word lines WL0 to WLM and a control line CL, thereby forming a DRAM array structure 1000 including M rows and N columns, i.e., M×N DRAM cell structures.

[0217] As shown in Figures 19 and 20, according to an embodiment of the present disclosure, the M×N DRAM cell structures included in the DRAM array structures 1000 and 1100 can be arranged in mirror-symmetry along the column direction. That is, as shown in Figures 19 and 20, each DRAM cell structure is mirror-symmetric with respect to its adjacent DRAM cell structure in the column direction. Taking the DRAM cell structure CELL2n shown in Figures 19 and 20 as an example, its gate transistor T2n is mirror-symmetric with the gate transistor T1n of the adjacent DRAM cell structure CELL1n, that is, the third gate structure G3 of the gate transistor T2n is adjacent to the third gate structure G3 of the gate transistor T1n, and the fourth gate structure G4 of the gate transistor T2n is adjacent to the fourth gate structure G4 of the gate transistor T1n. In addition, the gate transistor T2n of the DRAM cell structure CELL2n is also mirror-symmetrical with the gate transistor T3n of the adjacent DRAM cell structure CELL3n, that is, the first gate structure G1 of the gate transistor T2n is adjacent to the first gate structure G1 of the gate transistor T3n, and the second gate structure G2 of the gate transistor T2n is adjacent to the second gate structure G2 of the gate transistor T3n.

[0218] According to an embodiment of the present disclosure, such a configuration enables adjacent rows of DRAM cell structures to share a word line WLm in the column direction. For example, as shown in Figures 19 and 20, in the column direction, DRAM cell structure CELL2n shares a word line WL1 with the adjacent DRAM cell structure CELL1n, and shares a word line WL2 with the adjacent DRAM cell structure CELL3n. In other words, as shown in Figure 19, according to an embodiment of the present disclosure, in the column direction, the second gate structure of the first side of the gate transistor of the DRAM cell structure shares a word line with the second gate structure of the first side of the gate transistor of the adjacent DRAM cell structure, and the third gate structure of the second side of the gate transistor of the DRAM cell structure shares a word line with the third gate structure of the second side of the gate transistor of the adjacent DRAM cell structure. Alternatively, as shown in FIG20 , according to an embodiment of the present disclosure, in the column direction, the first gate structure of the first side of the gate transistor of the DRAM cell structure shares a word line with the first gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, and the fourth gate structure of the second side of the gate transistor of the DRAM cell structure shares a word line with the fourth gate structure of the second side of the gate transistor of its adjacent DRAM cell structure. In particular, according to an embodiment of the present disclosure, as shown in FIG19 and FIG20 , each DRAM cell structure of the DRAM cell arrays 1000 and 1100 is connected to two word lines on both sides.

[0219] According to the embodiments of the present disclosure, since adjacent DRAM cell structures in the column direction share word lines, the isolation between word lines formed by connecting the gate structures of adjacent DRAM cell structures can be omitted, thereby further improving the size miniaturization of the DRAM array structure compared to the vertical channel transistor (VCT) of the prior art.

[0220] In fact, according to the embodiment of the present disclosure, compared with the DRAM array structure implemented by the VCT transistor according to the prior art, the DRAM array structure implemented by the transistor with four gate structures according to the embodiment of the present disclosure changes the word line isolation in the horizontal direction to the word line isolation in the vertical direction, thereby achieving further size reduction.

[0221] The following describes the operating method of the DRAM array structure 1000 according to an embodiment of the present disclosure based on Figure 19 in combination with Figure 5 and Figure 21. Figure 21 shows a schematic diagram of the operating method of the DRAM array structure 1000 according to an embodiment of the present disclosure.

[0222] According to an embodiment of the present disclosure, the gate transistor in each DRAM cell structure in the DRAM array structure 1000 is a transistor having a four-gate structure, which, as described above, can be equivalent to two dual-gate transistors connected in series. As described above with reference to FIG5 , by controlling the voltages applied to the four gate structures of the gate transistor, the gate transistor can be controlled to be turned on and off, thereby connecting or disconnecting the conductive path from the bit line to the capacitor of the corresponding DRAM cell structure.

[0223] 5, 19, and 21, according to an embodiment of the present disclosure, the control line CL may be connected to a low voltage VGL or floated. Alternatively, the control line CL may be connected to other bias voltages for adjusting the off state of the DRAM cell structure.

[0224] Specifically, according to the embodiments of the present disclosure, by setting the bias voltage at a lower voltage, the gate transistor including the gate structure connected to the word line (i.e., the first gate structure and the fourth gate structure) can have a lower leakage current, thereby reducing the power consumption of the corresponding DRAM cell structure. In addition, by setting the bias voltage at a higher voltage, the gate transistor including the gate structure connected to the word line can have a higher on-state current, thereby improving the read and write speed of the corresponding DRAM cell structure.

[0225] According to the embodiments of the present disclosure, adjusting the bias voltage can provide a greater degree of adjustment than adjusting the switching characteristics of the gate transistor by adjusting the work function of the gate structure alone. Furthermore, according to the embodiments of the present disclosure, adjusting the bias voltage can enable the DRAM array structure to operate in different operating modes, such as a high-performance operating mode and a low-power operating mode.

[0226] In addition, referring to Figures 5, 19 and 21, according to an embodiment of the present disclosure, for each DRAM cell structure in the DRAM array structure 1000, as described above, the conduction and shutoff of the selection transistor can be controlled by controlling the voltage applied to the second gate structure and the third gate structure of the selection transistor in the DRAM cell structure, that is, the voltage applied to the two word lines connected thereto.

[0227] 5 , 19 and 21 , taking the case where the DRAM cell structure CELL2n in the 2nd row and nth column shown in FIG19 is selected as an example, when the DRAM cell structure CELL2n is selected, a high voltage VGH is applied to the word lines WL2 and WL1 respectively connected to the second gate structure G2 and the third gate structure G3 of the selection transistor T2n in the DRAM cell structure CELL2n, so that the selection transistor T2n is turned on (as indicated by the arrow in the DRAM cell structure CELL2n in FIG19 ).

[0228] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share a word line, the third gate structure G3 of the gate transistor T1n of the DRAM cell structure CELL1n in the 1st row and nth column, which is also connected to the word line WL1, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T1n of the DRAM cell structure CELL1n, which is close to the third gate structure G3 (as indicated by the arrow in the DRAM cell structure CELL1n in FIG19 ). However, as shown in FIG21 , according to an embodiment of the present disclosure, since the word line WL0 connected to the second gate structure G2 of the DRAM cell structure CELL1n is applied with a low voltage VGL and the control line CL connected to the fourth gate structure G4 of the DRAM cell structure CELL1n is applied with a bias voltage VCL for turning off the gate transistor T1n (e.g., low voltage VGL), the upper dual-gate transistor of the gate transistor T1n is turned off, and the gate transistor T1n of the DRAM cell structure CELL1n as a whole remains turned off.

[0229] Similarly, according to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share a word line, the second gate structure G2 of the gate transistor T3n of the DRAM cell structure CELL3n in the 3rd row and nth column, which is also connected to the word line WL2, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T3n of the DRAM cell structure CELL3n, which is close to the second gate structure G2 (as indicated by the arrow in the DRAM cell structure CELL3n in FIG19 ). However, as shown in FIG21 , according to an embodiment of the present disclosure, since the word lines WL3 connected to the third gate structures G3 of the DRAM cell structure CELL3n are respectively applied with a low voltage VGL and the control line CL connected to the first gate structure G1 of the DRAM cell structure CELL3n is applied with a bias voltage VCL for turning off the gate transistor T3n (e.g., the low voltage VGL), the lower dual-gate transistor of the gate transistor T3n is turned off, and the gate transistor T3n of the DRAM cell structure CELL3n as a whole remains turned off.

[0230] 19 and 21 , according to an embodiment of the present disclosure, by controlling the voltages applied to the word lines WL1 and WL2 , the DRAM cell structure CELL2 n can be turned on and off without affecting the operations of other DRAM cell structures.

[0231] Therefore, as shown in Figures 19 and 21, according to embodiments of the present disclosure, the conduction and shutoff of the gate transistor in the DRAM cell structure can be controlled by the voltage applied to the word line. Specifically, according to embodiments of the present disclosure, for each DRAM cell structure in the DRAM array structure 1000, the conduction and shutoff of the gate transistor of the DRAM cell structure can be controlled by controlling the voltages applied to its second gate structure and third gate structure via two word lines.

[0232] Those skilled in the art will appreciate that the operating method of the DRAM array structure according to the present disclosure is not limited to the embodiments described above with reference to FIG. 19 and FIG. 21 .

[0233] For example, according to another embodiment of the present disclosure as shown in FIG20 , the on / off state of the gate transistor in the DRAM cell structure can be controlled by controlling the voltages applied to the first gate structure and the fourth gate structure. Aside from the different connection relationships between the control lines and the word lines, the operating method based on the DRAM array structure 1100 shown in FIG20 is substantially the same as the operating method described above with reference to FIG19 and FIG21 . Therefore, for the sake of brevity, no further detailed description is given here.

[0234] According to the DRAM array structure and operation method thereof disclosed in the present invention, by using vertical transistors with four gate structures as selection transistors of the DRAM cell structure and making adjacent DRAM cell structures share word lines in the column direction, the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors is eliminated, thereby achieving further size reduction.

[0235] For illustrative purposes, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0236] Although this document contains many details, these details should not be construed as limitations on the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated as such, in some cases one or more features in a combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

Claims

1. A dynamic random access memory (DRAM) cell structure, comprising: A storage capacitor, including a first electrode and a second electrode, wherein the second electrode is connected to a source line; and A select transistor, including: A vertically extending active region, including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to a bit line, and the other of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and First to fourth gate structures, wherein the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side.

2. The DRAM cell structure according to claim 1, Among them, The first to fourth gate structures are formed of the same or different materials.

3. The DRAM cell structure according to claim 1, Among them, The first to fourth gate structures have the same or different sizes.

4. The DRAM cell structure according to claim 1, Among them, The first gate structure is aligned or offset with the third gate structure in the vertical direction, and wherein the second gate structure is aligned or offset with the fourth gate structure in the vertical direction.

5. The DRAM cell structure according to claim 1, Among them, The active region is formed of a semiconductor of a first doping type, and wherein the doping concentrations of the first source / drain region and the second source / drain region are greater than or equal to the doping concentration of the channel region.

6. The DRAM cell structure according to claim 1, Among them, The first and second source / drain regions are formed of a semiconductor of a first doping type, and the channel region is formed of a semiconductor of a second doping type.

7. The DRAM cell structure according to claim 6, Among them, The active region further includes a third source / drain region located between the first source / drain region and the second source / drain region in the vertical direction, and the third source / drain region is formed of a semiconductor of a first doping type.

8. The DRAM cell structure according to claim 1, Among them, The first to fourth gate structures have a "[", "|", or "L" - shaped cross - section in the horizontal direction.

9. An operation method for the DRAM cell structure according to any one of claims 1 to 8, comprising: Turning on or off the select transistor by controlling the voltages applied to the first gate structure and the fourth gate structure.

10. An operation method for the DRAM cell structure according to any one of claims 1 to 8, comprising: Turning on or off the select transistor by controlling the voltages applied to the second gate structure and the third gate structure.

11. A dynamic random access memory (DRAM) array structure, comprising: A plurality of DRAM cell structures arranged in M rows and N columns, wherein M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures includes: A storage capacitor, comprising a first electrode and a second electrode, wherein the second electrode is connected to a source line; and A select transistor, comprising: A vertically extending active region, comprising a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and First to fourth gate structures, wherein the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side; N bit lines, respectively connected to the other of the first source / drain region and the second source / drain region of the select transistor in N columns of DRAM cell structures; M + 1 first word lines, respectively connected to the second gate structure and the third gate structure of M rows of DRAM cell structures; and M + 1 second word lines, respectively connected to the first gate structure and the fourth gate structure of M rows of DRAM cell structures.

12. The DRAM array structure according to claim 11, Among them, The M rows of DRAM cell structures are arranged in mirror symmetry in the column direction, such that the DRAM cell structures in adjacent rows share a first word line and a second word line in the column direction.

13. The DRAM array structure according to claim 11, Among them, In each of the plurality of DRAM cell structures, the active region is formed of a semiconductor of a first doping type, and the doping concentrations of the first source / drain region and the second source / drain region are greater than or equal to the doping concentration of the channel region.

14. The DRAM array structure according to claim 11, Among them, In the active region of each of the plurality of DRAM cell structures, the first and second source / drain regions are formed of a semiconductor of a first doping type, and the channel region is formed of a semiconductor of a second doping type.

15. A method for operating the DRAM array structure according to any one of claims 11 to 14, comprising: Controlling the on and off of the select transistor in the plurality of DRAM cell structures by a voltage applied to the first word line.

16. The method according to claim 15, further comprising: Commonly, in groups, and / or individually applying a bias voltage to or floating the M + 1 second word lines.

17. A method for operating the DRAM array structure according to any one of claims 11 to 14, comprising: Controlling the on and off of the select transistor in the plurality of DRAM cell structures by a voltage applied to the second word line.

18. The method according to claim 17, further comprising: Commonly, in groups, and / or individually applying a bias voltage to or floating the M + 1 first word lines.

19. A method for manufacturing the DRAM array structure according to any one of claims 11 to 14, comprising: Providing a sacrificial layer and an active layer on a substrate; A plurality of bit grooves extending in the column direction are formed in the active layer to define the size of the active region of each DRAM cell structure in the row direction; The sacrificial layer is removed through the plurality of bit grooves and filled with a conductive material to form the bit line under the active region of each DRAM cell structure; A plurality of word grooves extending in the row direction are formed in the active layer to define the size of the active region of each DRAM cell structure in the column direction; A gate dielectric, a first word line, a second word line, and an isolation dielectric are formed in the plurality of word grooves; And A contact portion and the storage capacitor are sequentially formed above the active region of each DRAM cell structure.

20. A method for manufacturing a DRAM array structure according to any one of claims 11 to 14, comprising: A sacrificial layer and an active layer are provided on a substrate; A plurality of bit grooves extending in the column direction are formed in the active layer to define the size of the active region of each DRAM cell structure in the row direction; The sacrificial layer is removed through the plurality of bit grooves and filled with a conductive material to form the bit line under the active region of each DRAM cell structure; A plurality of alternately arranged first word grooves and second word grooves extending in the row direction are formed in the active layer to define the size of the active region of each DRAM cell structure in the row direction; A gate dielectric, a first word line, a second word line, and an isolation dielectric are formed in the first word groove; A gate dielectric, a second word line, a first word line, and an isolation dielectric are formed in the second word groove; And A contact portion and the storage capacitor are sequentially formed above the active region of each DRAM cell structure.

21. A dynamic random access memory DRAM array structure, comprising: A plurality of DRAM cell structures arranged in M rows and N columns, where M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures includes: A storage capacitor including a first electrode and a second electrode, where the second electrode is connected to a source line; and A select transistor including: An active region extending vertically, including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, where one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and First to fourth gate structures, where the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side; N bit lines respectively connected to the other of the first source / drain region and the second source / drain region of the select transistors in N columns of DRAM cell structures; M + 1 word lines respectively connected to the second gate structures and the third gate structures of the DRAM cell structures in M rows; and Control lines commonly connected to the first gate structure and the fourth gate structures of the DRAM cell structures.

22. A dynamic random access memory DRAM array structure, comprising: Multiple DRAM cell structures are arranged in M rows and N columns, where M and N are natural numbers greater than 1. Each of the multiple DRAM cell structures includes: A storage capacitor including a first electrode and a second electrode, where the second electrode is connected to a source line; and A select transistor including: A vertically extending active region including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, where one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and First to fourth gate structures, where the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side; N bit lines are respectively connected to the other of the first source / drain region and the second source / drain region of the select transistors in N columns of DRAM cell structures; M + 1 word lines are respectively connected to the first gate structure and the fourth gate structure of M rows of DRAM cell structures; and Control lines are commonly connected to the second gate structure and the third gate structure of the DRAM cell structures.

23. The DRAM array structure according to claim 21 or 22, Among them, The M rows of DRAM cell structures are arranged in mirror symmetry in the column direction such that the DRAM cell structures in adjacent rows share a word line in the column direction.

24. The DRAM array structure according to claim 21 or 22, Among them, In each of the multiple DRAM cell structures, the active region is formed of a semiconductor of a first doping type, and the doping concentrations of the first source / drain region and the second source / drain region are greater than or equal to the doping concentration of the channel region.

25. The DRAM array structure according to claim 21 or 22, Among them, In the active region of each of the multiple DRAM cell structures, the first and second source / drain regions are formed of a semiconductor of a first doping type, and the channel region is formed of a semiconductor of a second doping type.

26. The DRAM array structure according to claim 21 or 22, Among them, In each of the multiple DRAM cell structures, the first to fourth gate structures are formed of the same or different materials.

27. The DRAM array structure according to claim 21 or 22, Among them, In each of the multiple DRAM cell structures, the first to fourth gate structures have the same or different sizes.

28. The DRAM array structure according to claim 21 or 22, Among them, In each of the multiple DRAM cell structures, the first gate structure is aligned or offset with the third gate structure in the vertical direction, and the second gate structure is aligned or offset with the fourth gate structure in the vertical direction.

29. The DRAM array structure according to claim 21 or 22, Among them, In each of the multiple DRAM cell structures, the first to fourth gate structures have a "[", "|", or "L" shaped cross-section in the horizontal direction.

30. A method for operating a DRAM array structure according to any one of claims 21 to 29, comprising: Applying a bias voltage to or floating the control line; And Controlling the conduction and cutoff of the strobe transistors in the plurality of DRAM cell structures by a voltage applied to the word line.

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