A quantum dot qubit structure, a manufacturing method and uses for such

Abstract

There is provided a quantum dot qubit structure comprising a base layer (100) configured to form a base for the quantum dot qubit structure, a first dielectric layer (104) arranged onto the base layer (100), and a seed layer (102) comprising silicon, arranged onto the dielectric layer (104) and configured to form a seed for epitaxial growth of a carrier layer (103). The carrier layer (103) is configured to host one or more quantum dots (112), wherein the hosted one or more quantum dots being operable as one or more quantum dot qubits. The quantum dot qubit structure further comprises a second dielectric layer arranged onto the carrier layer (103) and at least one gate electrode (108) arranged onto the second dielectric layer (105). The device may further comprise side gates (106). The substrate is an SOI substate with a natural silicon seed layer, whereas carrier layer (103) comprises 28-silicon enriched silicon grown onto the seed layer.

Description

TITLEA quantum dot qubit structure, a manufacturing method and uses for suchTECHNICAL FIELD

[0001] There is presented a quantum dot qubit structure, a manufacturing method for a quantum dot qubit structure and uses for a quantum dot qubit structure.BACKGROUND

[0002] Silicon is one used material for providing qubits for quantum computing purposes. Qubits enable superposition of multiple possible states.

[0003] Natural silicon, Si, has nuclear spins, which tend to couple to spin qubits and cause decoherence. Silicon-28 isotope, Si-28, is a most abundant and stable isotope having zero nuclear spin. Natural silicon comprises about 92.23 % of Si-28. Also, isotopes Si-29 and Si-30 are stable. Natural silicon may be purified to comprise isotope Si-28 of a purity grade of over 99 %.SUMMARY

[0004] Aim is to provide a quantum dot qubit structure, which is electrically operable, and applicable for variety of applications.

[0005] The invention is defined by the features of the independent claims. Some embodiments are defined in the dependent claims.

[0006] According to a first aspect of the present application, there is provided a quantum dot qubit structure comprising a base layer configured to form a base for the quantum dot qubit structure, a first dielectric layer arranged on the base layer, and a seed layer comprising silicon, arranged on the dielectric layer and configured to form a seed for epitaxial growth of a carrier layer. The carrier layer is configured to host one or more quantum dots, wherein the hosted one or more quantum dots being operable as one or more spin qubits. The quantum dot qubit structure further comprises a second dielectric layer arranged on the carrier layer and at least one gate electrode arranged on the second dielectric layer.

[0007] The base layer may comprise natural silicon, doped natural silicon, doped silicon, locally doped silicon arranged to form electrically conducting patterns, fully doped conductive silicon, bulk material, a silicon on insulator, SOI, a silicon wafer, and / or other buried oxide wafers. The first dielectric layer may comprise silicon oxide, aluminium oxide, hafnium oxide, silicon nitride, zirconium oxide, transition metal oxides or any combination of such. The seed layer may comprise natural silicon and / or silicon oxide. The carrier layer may comprise silicon 28 isotope, Si-28, or silicon 30 isotope Si-30. Si-28 isotope may have purity of at least 99 %, preferably at least 99.99 %, or more preferably at least 99.9999%. The carrier layer may comprise silicon and germanium, Ge, layers, Si-28 / Ge or Si-30 / Ge. The second dielectric layer may comprise Si-28 oxide, Si-28 nitride, Si-30 oxide or Si-30 nitride.

[0008] Various embodiments quantum dot qubit may be based on one or more quantum dots. The quantum dot qubit structure may comprise electric means for controlling the quantum dot qubits, optionally by an electromagnetic field. The at least gate electrode may comprise electrically conducting material. Means for applying an electromagnetic field over the carrier layer enables controlling the quantum dot qubits at the carrier layer between the seed layer and the second dielectric layer, and / or towards the second dielectric layer and away from the seed layer, and / or, along the carrier layer at least partly perpendicular to the direction between the seed and carrier layers, for example along slanted edges of the carrier layer. Means for applying an electromagnetic field to the base layer enable to move the one or more quantum dot qubits away from the seed layer, towards an interface between the carrier layer and the second dielectric layer.

[0009] According to a second aspect of the present application, there is provided a method for manufacturing a quantum dot qubit structure, comprising: providing a base layer configured to form a base for the qubit structure, providing a first dielectric layer on the base layer and providing a seed layer on the dielectric layer. The method comprises epitaxially growing a carrier layer on the seed layer, hosting at the carrier layer one or more quantum dots, wherein the hosted one or more quantum dots being operable as one or more quantum dot qubits. The method further comprises providing a second dielectric layer on the carrier layer and providing at least one gate electrode arranged on the second dielectric layer.

[0010] Various embodiments the method may comprise controlling the one or more quantum dot qubits electronically, and / or providing electromagnetic field via a base layerand / or via the at least one gate layer in order to control the one or more quantum dot qubits. Applying an electromagnetic field over the carrier layer may enable to move the one or more quantum dot qubits at the carrier layer between the seed layer and the second dielectric layer; and / or at the carrier layer towards the second dielectric layer and optionally away from the seed layer; and / or along the carrier layer at least partly perpendicular to the direction between the seed layer and the carrier layer, for example along slanted edges of the carrier layer. The method may comprise applying an electromagnetic field to the base layer, i.e. back gate, in order to move the one or more quantum dot qubits away from the seed layer, towards an interface between the carrier layer and the second dielectric layer. The method may comprise epitaxially growing the second dielectric layer on the carrier layer.

[0011] According to a third aspect of the present application, there is provided use of the quantum dot qubit structure for making one or more quantum dot qubit structures, or quantum processing units.

[0012] According to a fourth aspect of the present application there is provided a quantum processing unit comprising one or more quantum dot qubit structures.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the following embodiments are discussed in more detail with reference to the attached drawings, of which:

[0014] Figure 1 illustrates, by way of an example, a quantum dot qubit structure.

[0015] Figure 2 illustrates, by way of an example, a quantum dot qubit structure.

[0016] Figure 3 illustrates, by way of an example, a quantum dot qubit structure.

[0017] Figure 4a illustrates, by way of an example, a side view of a quantum dot qubit structure having spacer gates between two quantum dots.

[0018] Figure 4b illustrates, by way of an example, a side view of a quantum dot qubit structure having spacer gates between two quantum dots.

[0019] Figure 5 illustrates, by way of an example, a side view of a quantum dot qubit structure.

[0020] Figures 6a, 6b and 6c illustrate, by way of an example, a quantum dot.

[0021] Figure 7a illustrates, by way of an example, a top view of a quantum dot qubit structure.

[0022] Figures 7b and 7c illustrate, by way of an example, a side view of a quantum dot qubit structure.

[0023] Figure 8a illustrates, by way of an example, a top view of a quantum dot structure.

[0024] Figures 8b and 8c illustrate, by way of an example, a side view of a quantum dot structure.

[0025] Figure 9a illustrates, by way of an example, a top view of quantum dots.

[0026] Figure 9b illustrates, by way of an example, a top view of a nanowire without gate electrodes.

[0027] Figure 10 illustrates, by way of an example, a top view of a quantum dot qubit structure.

[0028] Figure 11 illustrates, by way of an example, a quantum dot qubit architecture.

[0029] Figure 12 illustrates, by way of an example, a quantum dot qubit architecture.

[0030] Figure 13 illustrates, by way of an example, a quantum dot qubit architecture.

[0031] Figure 14 illustrates, by way of an example, a quantum dot qubit architecture.

[0032] Figure 15 illustrates, by way of an example, a quantum dot qubit architecture.

[0033] Figure 16 illustrates, by way of an example, a method for manufacturing a quantum dot qubit structure.

[0034] Figures are presented as illustrative examples and embodiments may not be limited solely to the illustrated parts, but modifications may be made under the scope as defined in the claims. Figures that may not fully present the claimed invention, aim to provide better understanding on the context and relating technical field.DESCRIPTION OF EMBODIMENTS

[0035] There is provided a dual layer structure on top of a dielectric material for providing a structure for quantum dots in order to form qubits. One layer of the dual layer structure comprises a seed layer, which may comprise natural silicon. A carrier layer of the dual layer structure is epitaxially grown on the seed layer. The carrier layer may comprise silicon-28 isotope, Si-28, and / or silicon-30 isotope, Si-30. A qubit or a quantum dot is arranged on the carrier layer and it may be defined electronically. A qubit may be electrostatically moved between the seed layer and an opposing surface of the carrier layer. This may be implemented by applying a suitable electrostatic potential, which induces an electromagnetic field, between a layer beneath the dielectric layer, and / or to gate electrodes onto a dielectric layer arranged on top of the carrier layer. The layer beneath the dielectric layer, on which the dielectric material and the dual layer structure may be introduced, may comprise a silicon on insulator, SOI, or other buried oxide wafers, which may be used as a growth base. The dual layer structure enables simplified fabrication process for wafers with one or more carrier layer on top of a dielectric layer. Current manufacturing processes are limited to handle exchange technique and / or similar demanding and material wasting methods.

[0036] A carrier layer may comprise Si-30 throughout the application, for example instead of Si-28. As Si-28, Si-30 has zero spin. Difference is that Si-30 has a lower concentration in a natural silicon compared to Si-28.

[0037] A quantum dot refers to physical unit, from which a qubit may be formed. A qubit refers to a two-state quantum-mechanical system that may be used for quantum computing or quantum information storage similarly to classical bits in traditional computing. Qubits may be used as sensitive detectors. Quantum dots may host other quantum systems, such as qutrits with three possible quantum states that may be used similarly. For the sake of simplicity, all such elements suitable for quantum computing will be referred as qubits in this application. Qubits may be formed using a single or multiple quantum dot. The qubit refers to an application of a unit of a quantum dot. Quantum dot structure can be used as a qubit. The qubit can be a spin qubit or a charge qubit, for example. The provided quantum dot qubit structure is controllable electrically, for example by inducing an electric or an electromagnetic field. Electrical may include microwaves or any electromagnetic radiation. The structure comprises layers, which may comprise material,like silicon. A layer may comprise essentially or mainly of the mentioned material, wherein essentially or mainly refers to most, i.e. over half of the weight percent of the layer.

[0038] Fig. 1 illustrates, by way of an example, a quantum dot qubit structure. The qubit structure comprises a base layer 100 and on top of the base layer 100, a first dielectric layer 101. On top of the first dielectric layer 101 the qubit structure comprises a seed layer 102, and on top of the seed layer 102, a carrier layer 103. The seed layer 102 is insulated from the base layer 100 by a first dielectric layer 101. The carrier layer 103 is epitaxially grown on the seed layer 102. The carrier layer 103 hosts or contains one or more quantum dots and / or one or more ions, being referred as 112 in Fig. 1. The ions comprise impurity ions. The hosted one or more quantum dots and / or one or more ions 112 are operable as spin qubits. The qubit structure is controlled electrically. The quantum dots may react to an optical signal.

[0039] On top of the carrier layer 103, the qubit structure comprises a second dielectric layer 105, and on top of the second dielectric layer 105, gate electrodes 108. Spin qubits of Fig. 1 may be operable electrically. The spin qubits may be electrically defined.

[0040] Fig. 1 illustrates the structure from a side, the layers on top of each other such that surfaces of neighbouring layers face each other. Throughout this application, a layer refers to a layer unit, which may comprise a multilayer. A layer may consist of one, or one kind of material, compound or substance. A seed layer may not consist fully of one material, as long as it comprises sufficient monocrystal region(s), as seed material for crystal formation. A dual layer refers to structure with two layers, or layer units, each comprising, or consisting of, one single material, compound or substance, respectively. A multilayer refers to a structure having multiple layers, or layer units, each comprising, or consisting of, a single material, compound or substance, respectively. Layers may have different amounts of material and different thicknesses, for example. Thickness direction is illustrated with z, and surfaces of the layers are on xy-plane in Fig. 1.

[0041] The base layer 100 may comprise silicon, for example natural silicon, doped silicon, partially doped silicon or complementarily doped silicon. The base layer 100 may comprise, or consist of, bulk material, a SOI, a silicon wafer, or other buried oxide wafers. The base layer 100 may have thickness from hundreds of nanometers to thousands of micrometers.

[0042] The first dielectric layer 101 and the second dielectric layer 105 have poor or none electric conductivity, so those form insulators. The first dielectric layer 101 may be polarized by applying an electric field over the first dielectric layer 101. The first dielectric layer 101 and the second dielectric layer 105 may comprise, or comprise mainly, silicon oxide. The first dielectric layer 101 may comprise aluminium oxide, hafnium oxide, silicon nitride, zirconium oxide, transition metal oxides, or any combination of such. Combination of oxides may comprise hafnium-zirconium oxide, for example. Stoichiometry of combination of oxides may vary. The first dielectric layer 101 may have thickness of 10-500 nm.

[0043] The seed layer 102 comprises at least one of: silicon, natural silicon, or silicon oxide. The seed layer 102 may have thickness from few nanometers to few tens of nanometers, for example 1-50 nm. The seed layer 102 is used as a seed layer for growth of a carrier layer 103. The seed layer 102 may not comprise fully of one material, or be fully continuous, as long as there is sufficient seed for the crystal formation, which may comprise sufficiently wide monocrystalline region.

[0044] The carrier layer 103 is grown on the seed layer 102 of silicon. The carrier layer 103 may comprise Si-28 or Si-30. Forming a carrier layer 103 may include an epitaxial growth. In epitaxial growth a grating structure or epithelium is multiplied. For example, crystal growth of the carrier layer 103 may progress laterally on the seed surface of an amorphous silicon oxide using reduced pressure chemical vapour deposition. Similar growth may be used to directly grow Si-28 (or Si-30) nanowires for spin qubits. The carrier layer 103 may comprise silicon 30 isotope or silicon 28 isotope, having purity over 99 %, preferably over 99.99 %, or 99.9999 %, or even closer to 100 %, or 100 %. The carrier layer 103 may have thickness from tens to few hundreds of nanometers, for example 10-150 nm.

[0045] A second dielectric layer 105 may comprise silicon oxide, SiCh. It may be grown on the carrier layer 102 of Si-28. The second silicon layer 105 of silicon oxide may be formed by oxidation, without complex phases. Spins of Si-28 have shown to be favourable for use in the second dielectric layer 105. Si-29 consists approximately 4.7 % of natural Si and has a nuclear spin, whereas Si-28 does not have a nuclear spin. A nuclear spin may interfere with an electron or a hole spin.

[0046] The gate electrodes 108 comprise electrically conducting material. The gate electrodes 108 may comprise in a thickness direction z, multiple layers, which are isolatedby dielectric layers. The gate electrodes 108 are isolated from each other and from the carrier layer 103. One or more of the layers may comprise, or consist of, doped polysilicon, metal, Niobium nitride, NbN, Titanium nitride, TiN, or any other electrically conducting material. The gate electrodes 108 enable electrostatic formation of a quantum dot 112.

[0047] Fig. 1 illustrates a quantum dot 112. The quantum dot 112 may be based on a potential well, where electrons or holes can be accumulated. A number of, even thousands or millions, quantum dots 112 may be arranged on a carrier layer 103. The quantum dot(s) 112 may be operable as a spin qubit. Operable refers to the quantum dots 112 being used as spin qubits, enabling utilizing the states of the spin qubits, for example controlling by applying an electromagnetic field. The quantum dots operable as qubits may be called quantum dot qubits.

[0048] The base layer 100 may be locally doped or fully doped, i.e. conductive. A doped base layer 100, of silicon for example, is arranged to form electrically conducting patterns. The first dielectric layer 101 enables using the base layer 100, i.e. a back side, as a back gate for back side gating. The back side gating is implemented by electrically connecting through the back side (base layer 100). A front side gating is implemented electrically connecting an electrode (of the gate electrodes 108) through the front-side. A fully doped base layer 100 substrate entails global gating of all spin qubits (based on quantum dots 112). A locally doped base layer 100 substrate, which is individually electrically connected, allows gating of individual spin qubits.

[0049] As an example, epitaxial growth of a carrier layer, like Si-28, may be implemented using chemical vapour deposition, CVD, or molecular beam epitaxy, MBE. CVD is used in semiconductor industry to produce thin films. A seed layer or a substrate, is exposed to volatile precursors which react or decompose on the substrate surface to produce a desired deposit. In MBE crystal growth or material deposition, in which new crystalline layers are formed with one or more well-defined orientations with respect to the crystalline seed layer. MBE is used for thin film deposition of single crystals, and it allows films to grow epitaxially. With high vacuum conditions and in absence of carrier gases, it enables providing very high purity of the grown films. The CVD and MBE may be used for epitaxial growth of the carrier layer, as discussed in this application.

[0050] An impure semiconductor is known as a doped semiconductor. Doping refers to a process of adding an impurity into the semiconductor crystal. Doping has effect ofmodifying or increasing electric conductivity. Silicon may be doped, for example with boron or phosphorous. Boron has three valence electrons, while phosphorous has five. Silicon doped with boron has a hole lacking an electron, forming a p-type semiconductor. The fifth valence electron of phosphorous acts as a free charge carrier in doped silicon, forming an n- type semiconductor. Doping may be done locally. A heavily doped region has high concentration of ions.

[0051] Fig. 2 illustrates, by way of an example, a quantum dot qubit structure. The layers correspond to those presented in Fig. 1, and the same reference numbers are used for corresponding layers. In Fig. 2, negative or positive bias has been applied to the back gate, which corresponds to the back layer 100. This is configured to drive a quantum dot 112 (based on an electron or a hole) in the carrier layer 103, away from the seed layer 102, towards opposing surface of the carrier layer 103, and / or towards a surface of the second dielectric layer 105. Electric charge applied to the base layer 100 or to the gate electrodes 108 induces a potential difference between the two. Due to the induced potential difference, and caused electromagnetic field, between the back gate of the base layer 100 and front gate of the gate electrodes 108, the quantum dot 112 at the carrier layer 103 shifts away from the lower seed layer 102, towards the upper second dielectric layer 105. Using the base layer 100 as a back gate enables to move the quantum dot qubit 112 away from the seed layer 102, towards interface of the carrier layer 103 and the second dielectric layer 105. This enables to reduce an effect of seed layer 102 silicon, like Si-29, to operation of the one or more quantum dot qubits 112.

[0052] The base layer 100 may comprise gate patterns, or implanted wires. This enables adjusting areas electrostatically. Conductive areas effect on controlling a quantum dot 112. A back gate and / or patterned, implanted areas in the base layer 100 may be used to control the quantum dot 112. By applying an electromagnetic field, the quantum dot may be controlled to move in the carrier layer 103, in z-direction, between the seed layer 102 and the second dielectric layer 105.

[0053] Quantum dots may be formed in potential wells that are electrostatically defined in a semiconductor crystal. Such quantum dot may host one or more electron or hole that are trapped to the potential well. Charged particles inside the quantum dot repulse each other because of Coulomb repulsion and adding a particle requires energy, creating a system with multiple energy levels. Effective size of a quantum dot may be from a few to hundredsof nanometers in size depending on the semiconductor material. Charge transport through a quantum dot can only occur when the electrons or holes have sufficient energy to overcome or tunnel through the potential well. This effect may be used, for example, to determine the change of the charge level of a quantum dot that is coupled capacitively to another quantum dot by measuring current through it. This may be used, for example, to read out a qubit state.

[0054] In an alternative, the carrier layer 103 may comprise silicon and germanium, Si / Ge, layers, for example Si-28 / Ge or Si-30 / Ge This enables forming quantum dots, which are operable as spin qubits. Use of Si / Ge enables to create 2D (2-dimensional) electron or hole gas due to strain modulated valence and conduction bands at an interface of the Si / Ge material layers. Gate layers may be used to confine charge carriers of the 2D electron or hole gas to form quantum dots. The quantum dots may be operated as qubits.

[0055] Si-28 has an enhanced thermal conductivity. This enables an enhanced thermalisation of devices at low temperatures. This causes less thermal noise due to smaller temperature gradients within and between devices. In addition, an enhanced thermal conductivity enables use of added power dissipating in the components without significantly increasing the temperature gradients. At low temperatures thermal conductivity of Si-28 may exceed the thermal conductivity of natural silicon up to 8 times. The thermal conductivity of Si-28 reaches a maximum at approximately 26 kelvins. The maximum value depends on sample shape and on a degree of isotope enrichment.

[0056] Spin qubits are operated in low temperatures, maximum of 5 K. Such low temperatures are reached by cryogenic apparatus. Commercially available cryostats may operate, for example, by Helium 4, He4, compressor and pulse tube or utilising liquid He4.

[0057] A semiconductive silicon is sensitive to light when the photon energy exceeds the band gap of the semiconductor. This enables utilization in fotonics, for example for creating photo detectors, photo emitters and / or waveguides.

[0058] Fig. 3 illustrates, by way of an example, a quantum dot qubit structure. The quantum dot qubit structure of Fig. 3 comprises spacer gates 106 and a top gate formed by a gate electrode 108. In Fig. 3 buried oxide is arranged as a dielectric 10 Ion a surface of a base layer 100, called a substrate 100. A seed layer 102 is called a silicon device layer. A carrier layer 103 formed of Si-28 (or Si-30) is arranged on the silicon device layer (102). Silicon oxide 104, like Si-28 oxide, is arranged on the carrier layer (103), around Si-28 (orSi-30). Spacer gates 106 are arranged next to silicon oxide 104, on two opposing sides. Gate electrode 108 is isolated from the carrier layer 103, surrounded by Si oxide and the spacer gates 106, by a second dielectric layer 105 and dielectric 107. The gate electrode 108 is connected to a voltage Vi and the substrate 100 is connected to a voltage V4. The spacer gates 106 are connected to voltages V2 and V3 correspondingly. Potential difference causes an electromagnetic field, to which electrons react. The electromagnetic field is controlled by the potential difference.

[0059] Figures 4a and 4b illustrate, by way of an example, a side view of a quantum dot qubit structure having spacer gates 106 between two quantum dots. The structure comprises a base layer 100, which may be called a substrate 100. A layer of buried oxide 102 is arranged onto the substrate 100. The substrate 100 and the buried oxide 102 form a continuous layer. Next layers, arranged onto the continuous layer of substrate 100 and buried oxide 101, have been arranged as separate units or enclaves (a, b), having a trench between those. A silicon device layer or a seed layer 102a (102b) is arranged on a surface of a layer of buried oxide 101. A carrier layer 103a (103b), comprising Si-28 or Si-30, is arranged on the silicon device layer (102a, 102b). The carrier layer 103a, 103b may be called a nanowire. The carrier layer 103 a (103b) is surrounded by a Si oxide 104a (104b), which isolates the carrier layer 103a (103b) from a gate electrode 108a (108b). A trench is arranged between two separate units a, b. A layer of buried oxide 101 is arranged to form bottom of the trench. Layers of silicon oxide 104a, 104b, surrounding the carrier layer (of Si-28 or Si-30) 103a, 103b correspondingly, are arranged to form sides of the trench. Spacer gates 106 are arranged into the trench. The base layer 100 (substrate) is connected to a voltage V4. The gate electrode 108a is connected to a voltage Vi and the gate electrode 108b is connected to a voltage V5. In Fig. 4a two spacer gates 106 are arranged into the trench, next to the silicon oxide 104a, 104b at the sides of the trench. The two spacer gates 106 are connected to voltages V2 and V3 correspondingly. In Fig. 4b the trench is filled with a spacer gate 106. The spacer gate 106 is connected to a voltage V2.

[0060] A potential difference arranged on a structures of Fig. 4a or Fig. 4b causes an electromagnetic field, which enables to control a quantum dot qubit in the carrier layer 103 a (103b), which may be called a nanowire. By applying a voltage Vi to a gate electrode 108b and / or a voltage V4 to the substrate 100, a quantum dot in a carrier layer 103b may be moved along upright-, y-direction. Similarly, by applying a voltage V5 to a gate electrode 108a and / or a voltage V4 to the substrate 100, a quantum dot in a carrier layer 103a may be movedalong upright-, y-direction. By applying voltages V2 and / or V3 to the two spacer gates 106 of Fig. 4a, a quantum dot in a carrier layer (103a, 103b) may be moved in a side direction, along x-axis, in the carrier layer 103.

[0061] Fig. 5 illustrates, by way of an example, a side view of a quantum dot qubit structure. A substrate 100 is connected to a voltage V3. A layer of Si oxide 104 is arranged onto the substrate 100, and is arranged to surround a Si seed layer (seed layer 102), onto which a nanowire (Si-28 layer) 103 is arranged. Two spacer gates 106 are arranged on opposite sides of the nanowire 103. Gate electrode layer 108 is arranged onto the layer of Si oxide 104. The gate electrode layer 108 is connected to a voltage Vi. At least one of the spacer gates 106 is connected to a voltage V2. The same potential V2 may be applied to both spacer gates 106, or only to one of those. The two spacer gates 106 may be connected to potentials, which differ from one another. Potential difference between the two spacer gates 106, and an electromagnetic field caused by it, may be used to push or squeeze the quantum dot 112. This may have effect on shape or placement of the quantum dot 112 in the nanowirel03. The spacer gates 106 may be used to push or align the quantum dot 112 in the middle of the nano wire 103. This may enable reducing effect of non-optimal surfaces. Surfaces or interfaces may include non-idealities, like traps or interface charges, which affect a quantum dot, for example causing reduction of a life time, or a coherence time, of quantum dots. By applying voltage V3 to the substrate 100, such as a SOI, the quantum dot 112 is controlled in z-direction. For example, quantum dots 112, such as idle quantum dots, may be moved along z-direction. Idle quantum dot refers to a formed quantum dot, which is not being manipulated at the moment. Alternatively, or in addition, shaping of the quantum dot 112 may have effect on modifying coupling of the quantum dot 112 to the gate electrodes 108.

[0062] Voltages, like V1-V5 of Figs. 2-5, applicable to the quantum dot qubit structure depend on a thickness of a dielectric layer, or layers, that are between the conductor where the potential is applied and the carrier layer, on geometry of the conductor layer, and on the carrier layer material properties. The applicable voltages may vary from -100 V to 100 V, or from -10 V to 10 V, for example. Voltages may be constant or vary in relation to time. Voltages may comprise direct-current voltage(s) and / or time dependent voltage(s), for example microwave signals. Voltages applied to different layers and / or components of the quantum dot qubit structure may vary among each other. Different kinds of voltages anddifferent amounts of voltages may be applied to different parts of the quantum dot qubit structure in a constant and / or time dependent manner.

[0063] Figures 6a, 6b and 6c illustrate, by way of an example, a quantum dot. The quantum dot 112 is presented in a nanowire. In Fig. 6a the quantum dot 112 has been shaped in an elliptic form. The elliptic form of the quantum dot 112 is such that the longer axis of the elliptic form is along x-axis, and difference between dimensions of the quantum dot in x-direction and z-direction is relatively small. In Fig. 6b the quantum dot 112 has been squeezed in an elliptic form. The elliptic form of the quantum dot 112 is such that the longer axis of the elliptic form is along z-axis, and difference between dimensions of the quantum dot in x-direction and z-direction is substantially bigger compared to that of Fig. 6a. In Fig. 6c two quantum dots 112 are induces on sides of nano wire 103 in x-direction. The quantum dot of Fig. 6b is squeezed on sides in x-direction by attracting charge carriers. In Fig. 6a one quantum dot 112 is induced on sides of the nanowire 103 in x-direction. Using voltages, by inducing potential difference, which causes an electromagnetic field, enables to move and shape a quantum dot 112. The quantum dots may be squeezed, pushes and reshaped. The voltages, potential difference, and / or an electromagnetic field may be used to attract electrons to form two quantum dots 112 within the nanowire 103, as illustrated in Fig. 6c.

[0064] Fig. 7a illustrates, by way of an example, a top view of a quantum dot qubit structure. The top view illustrates gate electrodes 108 and second gate electrodes 110 arranged on a Si oxide 104. Spacer gates 106 are arranged on sides of the Si oxide 104. At ends, doped areas 111 are illustrated.

[0065] Fig. 7b illustrates, by way of an example, a side view of a quantum dot qubit structure. The structure is illustrated as seen on a bottom side, in a yz-plane, of Fig. 7a. The base 100 forms a continuous base structure of substrate and buried oxide 101. Si seed layer 102 is arranged on the base structure 100. Si-28-, carrier layer 103, or a nanowire, is arranged on the Si seed layer 102. Quantum dots 112 are arranged in the nanowire. The Si seed layer 102 and the Si-28 layer 103 have been surrounded on top and sides by Si-28 oxide. Spacer gates 106 are arranged onto the base structure 100, at sides of the Si-28 oxide (nanowire). Gate electrodes 108 are arranged onto base structure 100, continuing on the Si-28 oxide 104 along a dielectric layer 105, which isolates the gate electrodes 108 from the spacer gates 106. The gate electrodes 108 are separated from second gate electrodes 110 by a dielectric layer 107.

[0066] Fig. 7c illustrates, by way of an example, a side view of a quantum dot qubit structure. The structure is illustrated as seen on a right side, in a xz-plane, of Fig. 7a. A substrate 100 and buried oxide 101 from a continuous base structure. Si device or a seed layer 102 is arranged between doped areas 111. The doped areas act as source / drain for the charge carriers, i.e. electrons or holes. The quantum dots 112 are arranged in the nanowire, or Si-28 layer 103, which is arranged onto Si seed layer 102. Gate electrodes 108 and second gate electrodes 110 are arranged next to each other, as illustrated, and separated by a dielectric layer 105.

[0067] In the following Figs. 8a, 8b and 8c, the same reference numbers as in the previous Figs. 7a, 7b and 7c have been used. Fig. 8a illustrate, by way of an example, a top view of a quantum dot qubit structure. Fig. 8a corresponds to Fig. 7a with an addition to a third gate electrodes 113. The third gate electrodes 113 are separated from the second gate electrodes 108 by a dielectric layer 109, as illustrated in a side view of Fig. 8b in yz-plane. Fig. 8c illustrates a bottom side view of Fig. 8a in a xz-plane, showing the third gate electrodes 113 from a bottom side.

[0068] The gate electrodes 108, 110, 113 enable to control the quantum dots (qubits) 112. The gate electrodes 108, forming a first layer of the gate electrodes, may be coupled to individual quantum dots 112. The gate electrodes 110 between neighbouring quantum dots 112, may control coupling between the adjacent quantum dots 112. The gate electrodes may be called control electrodes. The control electrodes may be arranged to isolate or couple two neighbouring quantum dots 112. While the gate electrodes 108, 110, 113 are arranged to reshape or move the quantum dots 112 in a z-direction, the spacer gates 106 enable to reshape or move the quantum dots 112 in a x-direction, which is perpendicular to the z-direction. Use of both the gate electrodes 108, 110, 113 and spacer gates 106 enables to move and reshape the quantum dots 112 in two dimensions.

[0069] Fig. 9a illustrates, by way of an example, a top view of quantum dots. The structure illustrates a top view without any gate electrodes. Quantum dots 112 are formed on edges of a rectangular part of a nanowire 103, surrounded by a Si-28 oxide 104. Spacer gates 106 are arranged on sides of the nanowire, and surrounded by a dielectric 105. The quantum dots 112 are formed on edges, because an electrostatic potential is stronger in the comers of the rectangular part of the nanowire 103. Other geometries maybe utilized correspondingly, for example a polygon, stellated or star form structure. An interior angle shall be sharpenough in order to enable forming a potential well by an electric field. An example of another geometry is illustrated in the following Fig. 9b.

[0070] Fig. 9b illustrates, by way of an example, a top view of a nanowire without gate electrodes. Square edges have been introduced to a one-dimensional nanowire 103. Si- 28 oxide layer 104 surrounds the nanowire 103 and spacer gate 106 surrounds the Si-28 oxide layer 104. Dielectric 105 is arranged next to the spacer gate 106. A zigzag form of the nano wire can be interpreted to contain multiple rectangles and quantum dots 112 are arranged into edges, as in Fig. 9a. Shape of the nanowire 103 enables to control placement of quantum dots 112. Different examples of gate architectures may be utilized in accordance to the use and / or purpose of the structure and quantum dots.

[0071] Fig. 10 illustrates, by way of an example, a top view of a quantum dot qubit structure. A two-dimensional array of four example quantum dots is shown. A dielectric layer 101 is overlayed by a carrier layer 103 comprising quantum dots under gate electrode layer 108, and surrounded by a spacer gate layer 106. Spacer gates are used to control coupling between two neighbouring quantum dot qubits. The neighbouring quantum dot qubits refer to the quantum dot qubits that are arranged closest to each other(s). Quantum dot qubit structure of Fig. 10 has applications in neural network devices in addition to qubit devices. Different geometries, for example triangular or rectangular, may be utilized to form a network.

[0072] Fig. 11 illustrates, by way of an example, a quantum dot qubit architecture. A buried oxide 101 is arranged on a surface of a base layer 100. Seed areas 102 of Si are arranged on a buried oxide 101. Carrier material 103 of Si-28 is grown on seed areas 102 and covered by Si-28 oxide 104 on its sides other than the seed area 102. Quantum dots 112 are arranged on the carrier material 103. Carrier material 103 volumes surrounded by Si-28 oxide and seed area 102 on the bottom, are separated from each other by spacer gates 106. On top of each carrier material 103 volume there is arranged a gate electrode 108. Gate electrodes 108 are connected to metal or doped polysilicon 108a. The spacer gates 106 enable to reduce cross-talk between neighbouring quantum dots 112.

[0073] Fig. 12 illustrates, by way of an example, a quantum dot qubit architecture. Buried oxide 101 is arranged on a surface of a base layer 100. A seed layer 102, or a Si device layer, is arranged on a surface of the buried oxide 101. A carrier layer 103 is arranged on a surface of a seed layer 102. Quantum dots 112 are on a carrier layer. Gate electrodes108, 110 are separated from the carrier layer 103 by a dielectric layer 103. Two independent gate layers 108 and 110 are illustrated in Fig. 12. The two gate layers 108, 110 enable fully overlapping gates on the carrier layer 103 covered by the Si-oxide layer 104. Lithography requirements may be relaxed with the presented structure. When electrodes are formed in two layers, a line width may be larger than in a case, where both electrodes are patterned in the same layer. A gap of an order of a minimum line width is utilized between two electrodes in the same layer.

[0074] In the spin qubit architectures of Fig. 11 and 12 quantum dots (qubits) 112 are arranged in two dimensional arrays. Spacer gates 106 separate the quantum dot 112 carrier areas 103. The spacer gates 106 are arranged to shape or squeeze the quantum dots 112 via a voltage induced to the one or more spacer gates 106. The gate electrodes 108, 110 are arranged to create barriers; or induce / deplete the quantum dots 112 locally. Back gate is arranged to control positions of the quantum dots 112 in a z-direction.

[0075] Fig. 13 illustrates, by way of an example, a quantum dot qubit architecture. The architecture of Fig. 13 is scalable. A two-dimensional array of quantum dots 112 is arranged similarly as in Fig. 11 , but in Fig. 13 spacer gates 106 are arranged between slanted edges of the carrier areas 103 covered by dielectric 104. The spacer gates 106 are arranged to form the quantum dots 112. Gate electrodes 108 are arranged to create barriers, or induce / deplete the quantum dots 112 locally. Controlling the quantum dots 112 in a z- direction is enabled. The base layer 100 may comprise SOI or bulk material. The gate electrodes 108 enable tuning the coupling between the quantum dots 112 by changing the location of the quantum dots 112 on the z-plane. The same applies with the second gate electrodes 110 and with the third gate electrodes 113. The spacer gates 106 enable tuning the coupling between the quantum dots 112 by changing the location of the quantum dots 112 on the x-plane. The slanted geometry of silicon enables controlled coupling between neighbour quantum dots 112. Position, and distance between quantum dots, is controllable by applied electric or electromagnetic field. This has effect on distance between quantum dots, which in turn has effect on coupling between the quantum dots.

[0076] Fig. 14 illustrates, by way of an example, a quantum dot qubit architecture. Two-dimensional array of quantum dots 112 is controlled by gate electrodes 108, 110, 113 and by spacer gates 106 in z- and x-direction correspondingly. Sloped edges of silicon 104 and the spacer gates 106 induced quantum dots 112 enable electric controlling of thequantum dots 112. The quantum dots 112 are movable along x-axis. This enables to control the interaction between the quantum dots. The gate electrodes 108, 110, 113 are connected to metal routing layers via metal or polysilicon 108a. The metal routing layers may be connectable or connected to units 114, such as multiplexers, MUXs, amplifiers, signal generators, or alike.

[0077] Fig. 15 illustrates, by way of an example, a quantum dot qubit architecture. Fig. 15 illustrates a two-dimensional array of quantum dots 112 on a carrier layer 103, which is arranged onto a seed layer 102. Number of gate electrodes 108, 110 are arranged in order to enable movement of quantum dots 112 in multiple ways, for example along z- and x-axis. Interaction of the quantum dots 112 with each other can be tuned. Added freedom of movement is provided by multiple gate electrodes 108, 110. Figs. 14 and 15 illustrate the same architecture such that Fig. 15 is a y-directional cross section of Fig. 14. Fig. 15 shows gate electrodes of layer 110, which are behind gate electrodes 108 in Fig. 14. Fig. 14 shows split gate electrodes 108, which are not visible in Fig. 15.

[0078] Figure 16 illustrates, by way of an example, a method for manufacturing a quantum dot qubit structure. The method comprises providing a base layer (1601) configured to form a base for the quantum dot qubit structure, providing a first dielectric layer (1602) onto the base layer, providing a seed layer (1603) onto the dielectric layer, and growing a carrier layer (1604) onto the seed layer. The method comprises hosting at the carrier layer one or more quantum dots, wherein the hosted one or more quantum dots being operable as one or more quantum dot qubits. The method comprises providing a second dielectric layer (1605) on the carrier layer, and providing at least one gate electrode (1606) on the second dielectric layer.

[0079] The method may further comprise controlling the one or more quantum dot qubits electrically. The method may further comprise providing an electromagnetic field via a base layer or via the at least one gate electrode in order to control the one or more quantum dot qubits. The method may comprise applying an electromagnetic field over the carrier layer in order to control at least one of the following: moving the one or more quantum dot qubits at the carrier layer (103) between the seed layer (102) and the second dielectric layer (105); moving the one or more quantum dot qubits at the carrier layer (103) towards the second dielectric layer (105), and optionally away from the seed layer (102), and moving the one or more quantum dot qubits at the carrier layer (103) along slanted edges of the carrierlayer (102). The method may comprise epitaxially growing the second dielectric layer on the carrier layer (103).

[0080] The manufacturing method is simplified compared to known manufacturing methods for qubit structures.

[0081] In the previous description and figures a two layered structure, comprising a seed layer, like Si layer, and a carrier layer, like Si-30 or Si-28 layer, epitaxially grown on the seed layer. Total silicon layer of the structure includes both the seed layer and the carrier layer. This enables simplified manufacturing process for Si-30 or Si-28 based quantum dot qubit structure. This leads to cost savings, thus enabling wider use of spin qubits by providing those available. Further, the discussed structure enables better performance compared to current commercial process.

[0082] It is to be understood that aspects, examples and embodiments disclosed are not limited to the particular structures, process steps, or materials disclosed herein, but are extended to equivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting.

[0083] The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the previous description, numerous specific details are provided, such as examples of structures, lengths, widths, shapes, etc., to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that embodiments can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0084] While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the invention. Accordingly, it is not intended that the invention be limited, except as by the claims set forth below.

[0085] The verbs “to comprise” and “to include” are used in this document as open limitations that neither exclude nor require the existence of also un-recited features. Thefeatures recited in depending claims are mutually freely combinable unless otherwise explicitly stated. Furthermore, it is to be understood that the use of “a” or “an”, i.e. a singular form, throughout this document does not exclude a plurality

Claims

CLAIMS:

1. A quantum dot qubit structure, comprising a base layer (100) configured to form a base for the quantum dot qubit structure, a first dielectric layer (101) arranged onto the base layer (100), a seed layer ( 102) comprising silicon, arranged onto the dielectric layer (101) and configured to form a seed for epitaxial growth of a carrier layer (103), the carrier layer (103) configured to host one or more quantum dots, wherein the hosted one or more quantum dots being operable as one or more quantum dot qubits, a second dielectric layer (105) arranged onto the carrier layer (102), and at least one gate electrode (108) arranged onto the second dielectric layer (105), wherein the quantum dot qubits are electrically defined, and wherein the seed layer (102) comprises a thickness of 1-50 nm.

2. The quantum dot qubit structure according to claim 1, wherein the base layer (100) comprises one of the following: natural silicon, doped natural silicon, doped silicon, locally doped silicon arranged to form electrically conducting patterns, fully doped conductive silicon, bulk material, a silicon on insulator, SOI, a silicon wafer, or other buried oxide wafers.

3. The quantum dot qubit structure according to any of the previous claims, wherein the first dielectric layer (101) comprises at least one of: silicon oxide, aluminium oxide, hafnium oxide, silicon nitride, zirconium oxide, transition metal oxides, or any combination of such oxides.

4. The quantum dot qubit structure according to any of the previous claims, wherein the seed layer (102) comprises at least one of the following: natural silicon, and silicon oxide.

5. The quantum dot qubit structure according to any of the previous claims, wherein the carrier layer (103) comprises silicon 30 isotope, Si-30, or silicon 28 isotope, Si-28, wherein optionally Si-28, having purity of at least 99 %, preferably at least 99.99 %, or more preferably at least 99.9999 %.

6. The quantum dot qubit structure according to any of the previous claims, wherein the carrier layer (103) comprises a multilayer of alternating silicon, Si, and germanium, Ge, layers, comprising at least one of Si-28 / Ge and Si-30 / Ge.

7. The quantum dot qubit structure according to any of the previous claims, wherein the second dielectric layer (105) comprises silicon 28 isotope.

8. The quantum dot qubit structure according to any of the previous claims, comprising quantum dot qubits based on the one or more quantum dots, and electric means for controlling the quantum dot qubits, optionally by an electromagnetic field.

9. The quantum dot qubit structure according to any of the previous claims, wherein the at least one gate electrode (108) comprises electrically conducting material.

10. The quantum dot qubit structure according to any of the previous claims, comprising means for applying an electromagnetic field over the carrier layer (102) in order to control at least one of: the one or more quantum dot qubits at the carrier layer (103) between the seed layer (102) and the second dielectric layer (105), the one or more quantum dot qubits at the carrier layer (103) towards the second dielectric layer (105), and away from the seed layer (102) the one or more quantum dot qubits along the carrier layer (102), at least partly perpendicular to the direction between the seed layer and the carrier layer.

11. The quantum dot qubit structure according to any of the previous claims, comprising means for applying an electromagnetic field to the base layer (100) in order to move the one or more quantum dot qubits away from the seed layer (102), towards an interface between the carrier layer (103) and the second dielectric layer (105).

12. A method for manufacturing a quantum dot qubit structure, comprising- providing a base layer (1601) configured to form a base for the quantum dot qubit structure,providing a first dielectric layer (1602) onto the base layer,- providing a seed layer (1603) onto the dielectric layer, epitaxially growing a carrier layer (1604) onto the seed layer, hosting at the carrier layer (1604) one or more quantum dots, wherein the hosted one or more quantum dots being operable as one or more quantum dot qubits, providing a second dielectric layer (1605) onto the carrier layer, and- providing at least one gate electrode (1606) arranged onto the second dielectric layer, wherein the quantum dot qubits are electrically defined, and wherein the seed layer comprises a thickness of 1-50 nm.

13. The method according to claim 12, comprising controlling the one or more quantum dot qubits electrically.

14. The method according to claim 12 or 13, comprising providing an electromagnetic field via a base layer or via the at least one gate electrode (108) in order to control the one or more quantum dot qubits.

15. The method according to any of claims 12-14, comprising at least one of: applying an electromagnetic field over the carrier layer in order to control at least one of the following: o moving the one or more quantum dot qubits at the carrier layer (103) between the seed layer (102) and the second dielectric layer (105); o Moving the one or more quantum dot qubits at the carrier layer (103) towards the second dielectric layer (105), and optionally away from the seed layer (102), and o moving the one or more quantum dot qubits at the carrier layer along the carrier layer (103), at least partly perpendicular to the direction between the seed layer (102) and the carrier layer (103); and applying an electromagnetic field to the base layer ( 100) in order to move the one or more quantum dot qubits away from the seed layer (102), towards an interface between the carrier layer (103) and the second dielectric layer (105).

16. The method according to any of claims 12-15, comprising epitaxially growing the second dielectric layer on the carrier layer.

17. A use of the quantum dot qubit structure according to any of claims 1-11 for making one or more quantum dot qubits.

18. A use of the quantum dot qubit structure according to any of claims 1-11 for making quantum processing units using the one or more quantum dot qubits.

19. A quantum processing unit comprising one or more quantum dot qubit structure according to any of claims 1-11.

Images