Circuit board and semiconductor package comprising same

Abstract

The circuit board according to an embodiment may comprise: a first insulating layer; a second insulating layer disposed on the first insulating layer; at least one electronic element disposed on the second insulating layer; a connection member disposed on the second insulating layer and overlapping the electronic element in the horizontal direction; a first via electrode disposed on the second insulating layer and disposed over the electronic element; and a second via electrode disposed on the second insulating layer and disposed over the connection member, wherein a horizontal width of the first via electrode is different from a horizontal width of the second via electrode.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiments relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple semiconductor devices across multiple substrates have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005]

[0006] Recently, research is being conducted on technologies that embed electronic components that consume, store, and release power supplied to the motherboard of electronic devices into package substrates. For example, various passive components such as capacitors, inductors, and resistors are required to operate active components such as memory, APs, or RF semiconductors. Furthermore, package substrate technologies are being developed to embed electronic components such as Deep Trench Capacitors (DTCs) to achieve high capacity and high performance due to the high integration and multi-functionality of circuit boards.

[0007] Meanwhile, in conventional circuit boards, electronic components are placed within the core layer to enhance the rigidity of the circuit board. However, placing electronic components within the core layer increases the distance between the additional external chips placed on the circuit board and the electronic components placed within the core layer, leading to signal transmission loss.

[0008] One of the technical challenges of the embodiment is to prevent signal transmission loss between the electronic component and the external chip.

[0009] Additionally, one of the technical challenges of the embodiment is to reduce the thickness of the circuit board.

[0010] Additionally, one of the technical challenges of the embodiment is to prevent warping of the circuit board.

[0011] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0012] A circuit board according to an embodiment includes a first insulating layer and a second insulating layer disposed on the first insulating layer; one or more electronic components disposed on the second insulating layer; a connecting member disposed on the second insulating layer and overlapping the electronic components in a horizontal direction; a first via electrode disposed on the second insulating layer and disposed on the electronic components; and a second via electrode disposed on the second insulating layer and disposed on the connecting member; and a horizontal width of the first via electrode may be different from a horizontal width of the second via electrode.

[0013] Additionally, in the embodiment, the horizontal width of the first via electrode may be greater than the horizontal width of the second via electrode.

[0014] Additionally, in the embodiment, the height of the upper surface of the first via electrode may be the same as the height of the upper surface of the second insulating layer.

[0015] Additionally, in the embodiment, the content of the reinforcing member of the second insulating layer may be less than the content of the reinforcing member of the first insulating layer.

[0016] In addition, the embodiment further includes a first insulating layer including a trench region on an upper surface, the second insulating layer overlapping the first insulating layer in a horizontal direction and including a protrusion disposed in the trench region of the first insulating layer, and the electronic device can be disposed in the trench region.

[0017] Additionally, the embodiment may further include a protective layer disposed on the second insulating layer and in contact with the first via electrode.

[0018] In addition, the embodiment further includes a third insulating layer disposed between the second insulating layer and the protective layer, and the content of the reinforcing member of the third insulating layer may be greater than the content of the reinforcing member of the second insulating layer.

[0019] Additionally, the embodiment may further include a post bump disposed within the second insulating layer and overlapping the electronic component in a horizontal direction.

[0020] Additionally, in an embodiment, the sum of the horizontal width of the first via electrode and the horizontal width of the second via electrode may be smaller than the horizontal width of the post bump.

[0021] Additionally, in the embodiment, the height of the upper surface of the first via electrode may be the same as the height of the upper surface of the post bump.

[0022] A semiconductor package according to an embodiment includes any one of the circuit boards described above.

[0023] A circuit board according to an embodiment and a semiconductor package including the same have a technical effect of preventing signal transmission loss between an electronic component and an external chip.

[0024] For example, embodiments may prevent signal loss as the electronic components are positioned within a second insulating layer adjacent to the outermost layer of the circuit board, thereby reducing the distance over which they are electrically connected to external components or the board.

[0025] In addition, the embodiment has a technical effect of controlling the horizontal width of the via electrode of the electronic component and the connecting member to control signal transmission with an external chip connected to each.

[0026] For example, referring to FIG. 2, the embodiment can control signal transmission with an external chip connected to each by forming the first width of the first via electrode of the electronic component and the second width of the second via electrode of the connecting member differently.

[0027] Additionally, the embodiment has a technical effect that can reduce the thickness of a circuit board.

[0028] For example, referring to FIG. 3, the thickness of the second insulating layer may be reduced as the electronic components and connecting members are placed in the recessed area, thereby reducing the thickness of the circuit board.

[0029] Additionally, the embodiment has a technical effect that can prevent the problem of warping of a circuit board.

[0030] For example, referring to FIG. 4, the embodiment includes a fifth insulating layer disposed between the second insulating layer and the first protective layer, and the fifth insulating layer has a higher content of reinforcing material than the second insulating layer, thereby preventing warpage of the circuit board.

[0031] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0032] Fig. 1 is a cross-sectional view of a circuit board (100) according to the first embodiment.

[0033] Figure 2 is a detailed view of one area (A1) of Figure 1.

[0034] Figure 3 is a cross-sectional view of a circuit board (101) according to the second embodiment.

[0035] Figure 4 is a cross-sectional view of a circuit board (102) according to the third embodiment.

[0036] Fig. 5 is a cross-sectional view of a semiconductor package (103) according to an embodiment.

[0037] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0038] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0039] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0040] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0041] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0042] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0043] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0044] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0045] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0046] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0047] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0048]

[0049] (Example)

[0050] Fig. 1 is a cross-sectional view of a circuit board (100) according to an embodiment.

[0051] Referring to FIG. 1, a circuit board (100) according to an embodiment includes a build-up structure (110) and an electronic component (150). The build-up structure (110) includes a build-up insulator (112), a build-up wiring body, and a protective layer (125, 126). The build-up structure (110) can function as a laminated circuit for connecting to an electronic component / main board, etc.

[0052] The build-up insulator (112) includes a single or multiple laminated insulating layers and provides insulating properties between the build-up wiring bodies. The build-up insulator (112) may include, but is not limited to, a first insulating layer (115), a second insulating layer (116), a third insulating layer (117), and a fourth insulating layer (118).

[0053] One of the insulating layers of the build-up insulator (112) may be a molding layer. For example, the second insulating layer (116) positioned on the upper side of the build-up insulator (112) may be a molding layer, but is not limited thereto.

[0054] Additionally, one of the insulating layers of the build-up insulator (112) may be a core layer. The third insulating layer (117) located at the center of the build-up insulator (112) may be a core layer, but is not limited thereto.

[0055]

[0056] The core layer can function to ensure the overall mechanical rigidity of the circuit board, thereby suppressing warpage. Because it can suppress both warpage occurring during processing and during product operation, the core layer can improve circuit board yield and reliability.

[0057] The core layer may include a reinforcing member such as glass fiber extending horizontally and a resin covering the reinforcing member, and the mechanical rigidity may be controlled according to the density of the reinforcing member. The reinforcing members of the core layer may be laminated and spaced apart from each other in the vertical direction and provided within the resin layer. According to another embodiment, the core layer may be provided with glass. When provided with glass, there is an effect that the density of via electrodes penetrating the core layer can be increased, and the spacing between via electrodes can be easily controlled. In addition, it may have an advantage of being able to make the circuit board thinner due to higher mechanical rigidity than a resin including glass fiber. The core layer is not limited to the above-described material in consideration of yield, price, etc., and any material that can secure mechanical rigidity may be freely selected and used.

[0058] The build-up insulator (112) may include an upper build-up insulator disposed on the upper surface of the core layer and a lower build-up insulator disposed on the lower surface of the core layer. For example, the build-up insulator (112) may include a third insulating layer (117) which is the core layer, a first insulating layer (115) and a second insulating layer (116) which are upper build-up insulators disposed on the upper surface of the core layer, and a fourth insulating layer (118) which is a lower build-up insulator disposed on the lower surface of the core layer.

[0059] The upper build-up insulator and the lower build-up insulator each have a function of arranging a wiring layer or via electrode of a build-up wiring body, securing insulation between circuits, and controlling impedance or insertion loss due to the circuit, and include an insulating layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film, taking into account dielectric constant, mechanical rigidity, and processability.

[0060] For example, the insulating layer of the build-up insulator (112) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0061] Also, for example, the insulating layer of the build-up insulator (112) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0062] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0063] Additionally, the insulating layer of the build-up insulator (112) may include an optically isotropic film, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0064] Additionally, the insulation layer of the build-up insulator (112) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0065]

[0066] Next, the build-up wiring body of the circuit board (100) includes a wiring layer (131) arranged on the surface of each insulating layer and a via electrode (132) for vertically connecting each wiring layer (131). The wiring layer (131) can have the function of transmitting signals and / or power to semiconductor elements arranged on the circuit board (100) and can have an impedance matching function. The wiring layer (131) can be referred to as a wiring pattern layer, a metal wiring, or a wiring portion.

[0067] The via electrode (132) is formed in a through hole that penetrates each insulating layer, and the through hole can be formed by any one of mechanical processing, laser processing, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When formed by laser processing, a UV or CO2 laser method can be used, and for chemical processing, a chemical agent including aminosilane, ketones, etc. can be used.

[0068]

[0069] A via electrode (132) can be formed by forming a through hole penetrating the insulating layers and filling the inside of the formed through hole with a conductive material.

[0070] Once the through hole is formed, the inside of the through hole can be filled with a conductive material to form a via electrode (132). The metal material forming the via electrode (132) can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the filling of the conductive material can utilize any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0071]

[0072] The build-up wiring body can be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring body can be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0073]

[0074] Next, the circuit board according to the embodiment includes a via electrode (132) and a wiring layer (131) connected to the electrode.

[0075] The wiring layer (131) includes pads and / or traces (or connection patterns) for connecting to via electrodes (132) and / or semiconductor elements and / or capacitors. The traces may be signal wiring lines connecting between a plurality of pads.

[0076] At this time, the pad of the wiring layer (131) includes a connection pad or a connecting pad. The connection pad may be a mounting pad on which an electronic component or semiconductor chip is mounted, or a terminal pad connected to an external substrate. The connection pad is a contact portion that comes into contact with a via electrode, and may include a lateral extension portion with a horizontal width greater than that of the trace for alignment margin.

[0077] The wiring layer (131) can be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0078]

[0079] Next, the circuit board according to the embodiment includes a protective layer (125, 126) disposed on a wiring layer of the uppermost or lowermost insulating layer. For example, the protective layer (125, 126) may include a first protective layer (125) disposed on a second insulating layer (116) and a second protective layer (126) disposed under a fourth insulating layer (118).

[0080] The protective layer (125, 126) can prevent problems such as oxidation or peeling of the build-up structure due to penetration of moisture and / or external contaminants. In addition, the protective layer is formed of a material with low solder wettability to prevent short circuits between adjacent solders when connecting the build-up structure and electronic components or a main board, thereby preventing bridging short circuits between adjacent solders.

[0081] The protective layer (125, 126) includes an insulating material, and the protective layer (125, 126) includes various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. The protective layer (125, 126) may be a resist layer, and for example, the protective layer (125, 126) may be a solder resist layer that includes an organic polymer material. As an example, the protective layer (125, 126) includes an epoxy acrylate series resin. In detail, the protective layer (125, 126) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, etc. However, the embodiment is not limited thereto, and the protective layer (125, 126) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0082]

[0083] Meanwhile, the electronic component may be placed within the third insulating layer (117) that functions as a core layer. Additionally, an external component or substrate may be connected to the build-up structure (110). An additional build-up layer is placed between the electronic component and the external component or substrate, which may increase the distance between the electronic component and the external component or substrate, potentially resulting in signal loss during transmission.

[0084] To solve the above problem, in the circuit board (100) according to the embodiment, the electronic component (150) may be disposed within a second insulating layer (116) disposed on a build-up insulator. For example, in the case of an embodiment including a core layer, the second insulating layer (116) may be disposed on an upper build-up layer. For convenience of explanation, when the uppermost surface of the upper build-up layer is provided as the upper surface of the first insulating layer (115), the electronic component (150) may be disposed within the second insulating layer (116) disposed on the first insulating layer (115). The second insulating layer (116) may not include a reinforcing member such as glass fiber. In addition, the second insulating layer (116) may have a lower content of the reinforcing member than the first insulating layer (115) or the third insulating layer (117). In addition, the second insulating layer (116) may be a molding layer, but is not limited thereto.

[0085] Additionally, a first adhesive layer (157) may be disposed on the upper surface of the first insulating layer (115). The first adhesive layer (157) may fix the mounted electronic component (150) and may buffer stress applied to the electronic component (150) when an external component or substrate is mounted on the build-up structure (110). The electronic component (150) may be disposed within the second insulating layer (116) and may include a first electronic component (150a) and a second electronic component (150b) that are disposed spaced apart from each other.

[0086] Referring briefly to FIG. 2, the electronic component (150) has a first-first pad (161) on its upper surface, and a first via electrode (162) may be disposed on the first-first pad (161). In addition, a first-second pad (163) may be disposed on the first via electrode (162). The first-second pad (163) is connected to a first connection portion (164), so that the electronic component (150) may be electrically connected to an external component or a substrate.

[0087] The circuit board (100) according to the embodiment has a technical effect of preventing signal loss as the distance electrically connected to an external element or substrate is reduced by placing the electronic element (150) within the second insulating layer (116) adjacent to the outermost layer of the build-up structure (110).

[0088]

[0089] Referring again to FIG. 1, the embodiment may further include a connecting member (155) disposed within the second insulating layer (116). The connecting member (155) may be disposed to overlap the electronic element (150) in a horizontal direction. The connecting member (155) may be disposed between the first electronic element (150a) and the second electronic element (150b).

[0090] The connecting member (155) may be a bridge substrate connecting a plurality of semiconductor elements arranged on the circuit board (100), may be a semiconductor element laminated on a silicon substrate, and may be an organic substrate including an insulating layer, a circuit layer, a via, and a protective layer made of the same material as the material provided on the circuit board (100), but is not limited thereto. The connecting member (155) may include finer circuits at a higher density than the build-up wiring body of the circuit board (100), and may not only minimize signal transmission loss between chips connected through the connecting member (155), but may also facilitate signal transmission between semiconductor elements, thereby allowing a plurality of semiconductor elements to operate as a single semiconductor element. The electronic element (150) and the connecting member (155) may be molded by a second insulating layer (116).

[0091] A second-1 pad (166) may be arranged on the upper surface of the connecting member (155). A second via electrode (167) may be arranged on the second-1 pad (166). In addition, a second-2 pad (168) may be arranged on the second via electrode (167). The second-2 pad (168) may be connected to the second connecting portion (169) so that the connecting member (155) may be electrically connected to an external element or a substrate.

[0092] In addition, a post bump (145) connected to the via electrode (132) may be disposed within the second insulating layer (116). The post bump (145) may overlap the electronic component (150) and the connecting member (155) in the horizontal direction. Therefore, the post bump (145) may operate to smoothly transmit power and / or signals when another upper circuit board (not shown) is disposed on the semiconductor component and / or circuit board (100), thereby enabling the electronic component (150) and / or the connecting member (155) to operate smoothly. In addition, a third pad (138) may be disposed on the post bump (145), and the third pad (138) may be connected to a third connection portion (139).

[0093]

[0094] Next, FIG. 2 is a detailed drawing of one area (A1) of the circuit board (100) according to the embodiment of FIG. 1.

[0095] Referring to FIG. 2, a first protective layer (125) may be disposed on the second insulating layer (116). As described above, the first protective layer (125) takes into account the wettability of the solder and has the function of protecting the circuit board (100) from external moisture or contaminants. Therefore, if the second insulating layer (116) performs the function described above, the first protective layer (125) may not be disposed. However, although it is illustrated in the embodiment for the convenience of explanation, the present invention is not limited thereto, and the first protective layer (125) may not be provided depending on the function and necessity of the second insulating layer (116).

[0096] Referring back to FIG. 2, a second insulating layer (116) may be disposed on the first insulating layer (115). A first adhesive layer (157) and a second adhesive layer (159) may be disposed on the upper surface of the first insulating layer (115) to prevent misalignment of the position of the electronic component (150) and / or the connecting member (155). In addition, the electronic component (150) may be disposed on the first adhesive layer (157). A first-first pad (161) may be disposed on the upper surface of the electronic component (150). In addition, a first via electrode (162) may be disposed on the first-first pad (161). A first-second pad (163) may be disposed on the first via electrode (162).

[0097] Additionally, a connecting member (155) may be placed on the second adhesive layer (159). A second-1 pad (166) may be placed on the upper surface of the connecting member (155). A second via electrode (167) may be placed on the second-1 pad (166). Additionally, a second-2 pad (168) may be placed on the second via electrode (167).

[0098] In addition, the electronic component (150) and the connecting member (155) may be arranged to overlap in the horizontal direction. By positioning the electronic component (150) and the connecting member (155) at the same height based on the bottom surface of the build-up structure on the upper part of the circuit board (100), the integrity of the signal and / or power transmission of the circuit board (100) can be improved. In addition, for the purpose of insulation, the thickness of the electronic component (150) and the connecting member (155) may be smaller than the thickness of the second insulating layer (116).

[0099] Meanwhile, the horizontal width of the first width (W1) of the first via electrode (162) connected to the electronic component (150) and the horizontal width of the second width (W2) of the second via electrode (167) connected to the connecting member (155) may be different from each other. In detail, the first width (W1) of the first via electrode (162) may be larger than the second width (W2) of the second via electrode (167). Accordingly, the embodiment has a technical effect of controlling the horizontal widths of the via electrodes of the electronic component and the connecting member differently to control signal transmission with an external chip connected to each and improve connectivity with an external terminal.

[0100]

[0101] In addition, in order to secure an alignment margin, the horizontal width of the 1-1 pad (161) connected to the 1st via electrode (162) may be different from the horizontal width of the 2-1 pad (166) connected to the 2nd via electrode (167). In addition, the horizontal width of the 1-2 pad (163) connected to the 1st via electrode (162) may be different from the horizontal width of the 2-2 pad (168) connected to the 2nd via electrode (167). The horizontal width of the 1-2 pad (163) may be greater than the horizontal width of the 2-2 pad (168).

[0102] The height of the upper surface of the first via electrode (162) may be the same as the height of the upper surface of the second insulating layer (116). In addition, the height of the upper surface of the second via electrode (167) may be the same as the height of the upper surface of the second insulating layer (116). The height of the upper surface of the first via electrode (162) may be the same as the height of the upper surface of the second via electrode (167).

[0103] Additionally, the first-second pad (163) and the second-second pad (168) may be placed on the upper surface of the second insulating layer (116). The height of the lower surface of the first-second pad (163) and the second-second pad (168) may be the same as the height of the upper surface of the second insulating layer (116).

[0104] Here, height should be understood to mean the vertical length based on the bottom surface of the build-up structure for convenience of explanation.

[0105]

[0106] In addition, a post bump (145) may be disposed within the second insulating layer (116). The post bump (145) may include copper, but is not limited thereto. The post bump (145) may overlap the electronic component (150) and the connecting member (155) in the horizontal direction. The height of the upper surface of the post bump (145) may be the same as the height of the upper surface of the second insulating layer (116). The post bump (145) may be used as a passage for electrically connecting the build-up wiring body and an external component or substrate. A third pad (138) may be disposed on the post bump (145), and the third pad (138) may be disposed on the upper surface of the second insulating layer (116).

[0107] Meanwhile, the third width (W3) in the horizontal direction of the post bump (145) may be larger than the first width (W1) of the first via electrode (162) of the electronic component (150). In addition, the third width (W3) in the horizontal direction of the post bump (145) may be larger than the second width (W2) of the second via electrode (167) of the connecting member (155).

[0108] Additionally, the third width (W3) of the post bump (145) may be greater than the sum of the first width (W1) of the first via electrode (162) and the second width (W2) of the second via electrode (167). The post bump (145) may be provided to have the horizontal width described above in consideration of securing the integrity of signal and / or power transmission, mechanical rigidity, and stress with the build-up structure.

[0109]

[0110] Next, Fig. 3 is a cross-sectional view of a circuit board (101) according to a second embodiment. The second embodiment may adopt the technical features of the first embodiment. For example, in the second embodiment, the horizontal width of the first via electrode (162) arranged on the electronic component (150) may be different from the horizontal width of the second via electrode (167) arranged on the connecting member (155) in which the fine pattern is employed at a high density.

[0111] Next, referring to FIG. 3, the build-up insulator (112) may include a first insulating layer (115c), a third insulating layer (115b), and a fourth insulating layer (115a) that are sequentially arranged from top to bottom. In addition, a second insulating layer (116) is arranged on the first insulating layer (115c), and the first insulating layer (115c) may be in contact with the second insulating layer (116).

[0112] In addition, the build-up insulator (112) may include a trench region (115T) on its upper surface. The above-described trench region (115T) may penetrate at least a portion of the build-up insulator from the upper surface of the build-up insulator toward the lower surface of the build-up insulator. In the embodiment, the trench region (115T) is illustrated as penetrating the first insulating layer (115c), but is not limited thereto, and may be implemented to penetrate up to a portion of the first insulating layer (115c) and the third insulating layer (115b), or to penetrate only up to a portion of the first insulating layer (115c).

[0113] According to an embodiment, a trench region (115T) may be formed on an upper surface of a build-up insulator, and a second insulating layer (116) may be arranged to fill the trench region (115T). Accordingly, the second insulating layer (116) may include a horizontal portion (116-1) arranged on the first insulating layer (115c) and a protrusion (116-2) that overlaps the first insulating layer (115c) in a horizontal direction. The protrusions (116-2) may be included in multiple numbers and may be spaced apart from each other. The protrusions (116-2) of the second insulating layer (116) may be arranged within the trench region (115T) of the build-up insulator (112).

[0114] In addition, an electronic component (150) may be disposed within the trench region (115T). In addition, a connecting member (155) may be disposed within a horizontal portion (116-1) of the second insulating layer (116). In addition, the connecting member (155) may be disposed on the first insulating layer (115c). The electronic component (150) may be disposed to overlap with the first insulating layer (115c) in a horizontal direction. The electronic component (150) may not overlap with the first insulating layer (115c) in a vertical direction. Accordingly, the second embodiment has a technical effect in that the thickness of the second insulating layer (116) covering the electronic component (150) may be reduced as the electronic component (150) is disposed within the trench region (115T), thereby reducing the thickness of the build-up structure (110).

[0115] In addition, the post bump (145) may be arranged to vertically overlap with the first insulating layer (115c). When the thickness of the second insulating layer (116) covering the electronic device (150) is reduced, the thickness of the post bump (145) may also be reduced. Accordingly, the second embodiment has a technical effect of reducing the thickness of the post bump (145) and preventing signal transmission loss as the electronic device (150) is arranged within the trench region (115T).

[0116] In addition, the second embodiment has a technical effect that the degree of freedom of the chip can be improved because the thickness of the electronic component (150) can be increased by being covered by the second insulating layer (116) as the electronic component (150) is placed within the trench region (115T).

[0117]

[0118] Figure 4 is a cross-sectional view of a circuit board (102) according to the third embodiment.

[0119] Referring to FIG. 4, the third embodiment may further include a fifth insulating layer (119) disposed on the second insulating layer (116). The fifth insulating layer (119) may be disposed between the second insulating layer (116) and the first protective layer (125). The fifth insulating layer (119) may include a first-first via electrode (162-1) disposed on the first via electrode (162). The horizontal width of the first-first via electrode (162-1) may be the same as the horizontal width of the first via electrode (162), but is not limited thereto. In addition, the fifth insulating layer (119) may include a second-first via electrode (167-1) disposed on the second via electrode (167). The horizontal width of the 2-1 via electrode (167-1) may be the same as the horizontal width of the 2nd via electrode (167), but is not limited thereto.

[0120] Meanwhile, the fifth insulating layer (119) may have a higher density of reinforcing members compared to the second insulating layer (116). In addition, the thickness of the fifth insulating layer (119) may be smaller than the thickness of the second insulating layer (116). Accordingly, the third embodiment has a technical effect of preventing a warping problem that may occur on the upper surface of the build-up structure (110) by placing the fifth insulating layer (119) further including a reinforcing member on the second insulating layer (116) on which the electronic device is placed.

[0121] In addition, although the fifth insulating layer (119) is illustrated as a single layer in FIG. 4, the fifth insulating layer (119) may include multiple insulating layers. The multiple insulating layers of the fifth insulating layer (119) may include multiple wiring bodies, and the multiple wiring bodies may be electrically connected to at least one of the first-first via electrode (162-1), the second-first via electrode (167-1), and the post bump (145).

[0122] Referring back to FIG. 2, the horizontal width of the 2-1 pad (166) and the 2nd via electrode (167) arranged on the connecting member is different from the horizontal width of the 1-1 pad (161) and the 1st via electrode (162) arranged on the electronic component. Accordingly, the amount of current applied during the plating process may be different, or the upper surface of the 1-2 pad (163) and the upper surface of the 2-2 pad (168) may have different thicknesses depending on the process conditions such as the amount of penetration of the plating solution. As described above, when a semiconductor component is mounted on pads having different thicknesses, a problem may arise in which the connection reliability between the semiconductor component and the circuit board (100) is lowered. In order to prevent this problem, as illustrated in FIG. 4, a 5th insulating layer (119) may be laminated to prevent the plating deviation problem.

[0123] If the width of the second via electrode (167) arranged on the connecting member is smaller than the width of the first via electrode (162) arranged on the electronic component, the second-second pad (168) arranged on the lower surface of the fifth insulating layer (119) may be extended in the horizontal direction to implement a second-first via electrode (167-1) having the same width as the via arranged on the electronic component. Here, the same width means a width at which the plating deviation is small, and if the plating deviation does not cause distortion during mounting of the semiconductor component, the widths between the vias may be designed to be somewhat different from each other.

[0124]

[0125] Fig. 5 is a cross-sectional view of a semiconductor package (103) according to an embodiment.

[0126] The embodiment may include, but is not limited to, a circuit board (100) having a build-up structure (110) of FIG. 1, and may also include a circuit board illustrated in FIG. 3 or FIG. 4.

[0127] Referring to FIG. 5, a semiconductor package (103) according to an embodiment includes a first-second pad (163) disposed on a bottom surface of an electronic device (150), and a first connection portion (164) may be disposed on the first-second pad (163). In addition, a second-second pad (168) may be disposed on a connecting member (155), and a second connection portion (169) may be disposed on the second-second pad (168). In addition, a third pad (138) may be disposed on a post bump (145), and a third connection portion (139) may be disposed on the third pad (138). The first connection portion (164), the second connection portion (169), and the third connection portion (139) may include a spherical shape. For example, the cross-sections of the first connection portion (164), the second connection portion (169), and the third connection portion (139) may include a circular shape or a semicircular shape. The first connection portion (164), the second connection portion (169), and the third connection portion (139) may be solder balls, but are not limited thereto.

[0128] In addition, the circuit board may further include a bonding portion on the first protective layer (125). The bonding portion may be disposed on the upper surface of the first protective layer (125) to perform thermal compression bonding with the semiconductor element, and may be used when it is difficult to implement with the existing solder bonding when the pitch of the first-second pads (163) of the semiconductor element becomes fine. The semiconductor package (103) according to the embodiment may include a chip (200) or an element (200) disposed on the build-up structure (110). The chip (200) may be a processor chip. For example, the chip (200) may be an application processor (AP) chip of any one of a central processor (e.g., a CPU), a graphic processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal (205) may be included on the lower surface of the chip (200), and the terminal (205) may include a plurality of terminals. For example, the terminal (205) may include a first terminal (205a), a second terminal (205b), a third terminal (205c), and a fourth terminal (205d). The first terminal (205a) may be electrically connected to the second-second pad (168) of the build-up structure (110) through the first connection portion (164). In addition, the second terminal (205b) may be electrically connected to the second-second pad (168) through the second connection portion (169). In addition, the third terminal (205c) may be electrically connected to the first-second pad (163) through the first connection portion (164). In addition, the fourth terminal (205d) may be electrically connected to the third pad (138) through the third connection portion (139).

[0129] Meanwhile, the semiconductor package (103) of the embodiment may include a plurality of chips that are horizontally spaced apart from each other and arranged on a single circuit board. For example, the chip (200) may also include a first chip (201) and a second chip (202). The first chip (201) and the second chip (202) may be different types of application processor (AP) chips. Accordingly, the plurality of second-second pads (168) of the connecting member (155) may be connected to the first chip (201) and the second chip (202), respectively, to electrically connect the first chip (201) and the second chip (202).

[0130] In addition, the semiconductor package (103) of the embodiment may additionally have a connection portion arranged on the lower surface of the fourth wiring layer (131-4), and the connection portion may be for connecting to a main board (or motherboard) of an external device.

[0131]

[0132] (semiconductor package)

[0133] A semiconductor package including a circuit board of an embodiment will be described. The semiconductor package includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be electrically connected to the circuit board of the embodiment. Various components may be mounted on the circuit board.

[0134] For example, a circuit board may be mounted with memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), an antenna chip, a digital signal processor, an encryption processor, a microprocessor, a microcontroller, and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC).

[0135] For example, a circuit board may be mounted with at least one of various types of passive components and active components.

[0136] At this time, the semiconductor package may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, it is not limited to these, and of course, it may be any other electronic device that processes data.

[0137] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integrity or technical interoperability with each other.

[0138] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0139] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0140] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0141] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0142] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A first insulating layer and a second insulating layer disposed on the first insulating layer; One or more electronic elements arranged in the second insulating layer; A connecting member that overlaps the electronic component in a horizontal direction and is arranged on the second insulating layer; A first via electrode disposed on the second insulating layer and disposed on the electronic component; and A second via electrode is disposed on the second insulating layer and is disposed on the connecting member; A circuit board, wherein the horizontal width of the first via electrode is different from the horizontal width of the second via electrode.

2. In paragraph 1, A circuit board, wherein the horizontal width of the first via electrode is greater than the horizontal width of the second via electrode.

3. In paragraph 1, A circuit board wherein the height of the upper surface of the first via electrode is the same as the height of the upper surface of the second insulating layer.

4. In paragraph 1, A circuit board, wherein the content of the reinforcing member of the second insulating layer is smaller than the content of the reinforcing member of the first insulating layer.

5. In paragraph 1, The first insulating layer includes a trench region on the upper surface, and the second insulating layer further includes a protrusion that overlaps the first insulating layer in a horizontal direction and is arranged in a part of the trench region. A circuit board wherein the electronic components are arranged in different regions of the trench region.

6. In paragraph 1, A circuit board further comprising a protective layer disposed on the second insulating layer and in contact with the first via electrode.

7. In paragraph 6, It further includes a third insulating layer disposed between the second insulating layer and the protective layer, A circuit board, wherein the content of the reinforcing member of the third insulating layer is greater than the content of the reinforcing member of the second insulating layer.

8. In paragraph 1, A circuit board further comprising a post bump disposed within the second insulating layer and overlapping the electronic component in a horizontal direction.

9. In paragraph 8, A circuit board, wherein the sum of the horizontal width of the first via electrode and the horizontal width of the second via electrode is smaller than the horizontal width of the post bump.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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