Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment of the present invention may comprise: a core portion including a first core layer and a second core layer disposed on the first core layer; a first insulating layer disposed between the first core layer and the second core layer; and a via penetrating the core portion and the first insulating layer. The via includes a first via region horizontally overlapping the first core layer and a second via region vertically connected to the first via region and horizontally overlapping the first insulating layer, and the horizontal width of the second via region may be different from the horizontal width of the first via region.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] Meanwhile, the circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, the circuit board may mean that a mounting position of each semiconductor device is predetermined for mounting at least one semiconductor device, and a build-up wiring body connected to the semiconductor device is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005] On the other hand, in semiconductor packages being studied internally, vias penetrating multiple insulating layers are provided with at least one pad between vias spaced apart from each other in the thickness direction. Accordingly, circuit boards according to the prior art may experience problems such as increased signal transmission distance and increased signal transmission loss due to pads provided in the vias. Furthermore, the formation of vias may reduce the rigidity of the circuit board, resulting in warpage, or may cause the vias to be formed too small, resulting in reduced electrical performance.

[0006] Meanwhile, FCBGA circuit boards for servers and vehicles have electronic components embedded in the core layer, and the thickness of the core layer comprising glass fiber is formed thicker than the thickness of the electronic components in consideration of the rigidity of the circuit board, etc. However, when manufacturing an embedded core, the size of the electronic components becomes smaller compared to the volume of the core layer cavity or opening for embedding the electronic components, and there is a problem that voids or blisters occur in the resin due to insufficient insulating layer resin to fill the core layer cavity, or rotation defects occur in the electronic components.

[0007] One of the technical challenges of the embodiment is to improve the signal transmission speed of the semiconductor package.

[0008] Additionally, one of the technical challenges of the embodiment is to improve the design freedom of via holes.

[0009] Additionally, one of the technical challenges of the embodiment is to simplify the via formation process.

[0010] In addition, the embodiment aims to secure the rigidity of the circuit board when implementing a circuit board of an embedded core, while preventing the occurrence of voids or blisters in the resin or rotation defects of electronic components due to insufficient insulating layer resin for filling the core layer cavity.

[0011] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0012] A circuit board according to an embodiment may include a core portion having a first core layer and a second core layer disposed on the first core layer; a first insulating layer disposed between the first core layer and the second core layer; and a via penetrating the core portion and the first insulating layer. The via includes a first via region horizontally overlapping the first core layer and a second via region vertically connected to the first via region and horizontally overlapping the first insulating layer, and a horizontal width of the second via region may be different from a horizontal width of the first via region.

[0013] In addition, a circuit board according to an embodiment includes a core portion having a first core layer and a second core layer disposed on the first core layer, a first insulating layer disposed between the first core layer and the second core layer, an upper build-up insulator disposed on the first core layer, a lower build-up insulator disposed under the second core layer, and a via penetrating the core portion and the first insulating layer, wherein the via can penetrate at least a portion of the upper build-up insulator and at least a portion of the lower build-up insulator.

[0014] The above via may include a first via region horizontally overlapping the first core layer and a second via region vertically connected to the first via region and horizontally overlapping the first insulating layer.

[0015] The horizontal width of the second via area may be different from the horizontal width of the first via area.

[0016] The horizontal width of the second via area may be greater than the horizontal width of the first via area.

[0017] The first insulating layer may have a lower content of reinforcing material than the first core layer or the second core layer.

[0018] The first insulating layer includes a first insulating layer disposed on the first core layer; and a first insulating layer disposed on the first insulating layer; and the first insulating layer may include an extension portion whose width increases in the horizontal direction between the first insulating layer and the first insulating layer.

[0019] The above via may include a 2-2 via region protruding into the interface between the 1-1 insulating layer and the 1-2 insulating layer.

[0020] The horizontal width of the above-mentioned 2-2 via area may be greater than the horizontal width of the above-mentioned 1st via area.

[0021] The horizontal width of the above-mentioned 2-2 via area may be greater than the horizontal width of the above-mentioned 2nd via area.

[0022] The above 2-2 via region may have a vertical thickness that becomes smaller as it moves in the horizontal direction of the first insulating layer.

[0023] The side surface of the second via region may include a curved surface.

[0024] The curvature of the side surface of the second via area may be greater than the curvature of the side surface of the first via area.

[0025] The embodiment may further include an electronic element disposed within the second core layer.

[0026] Additionally, the semiconductor package according to the embodiment may include any one of the circuit boards described above.

[0027] The circuit board according to the embodiment and the semiconductor package including the same have a technical effect of providing a semiconductor package with improved signal transmission speed.

[0028] For example, in forming a via penetrating a core portion, the embodiment secures rigidity by including a reinforcing member between a plurality of spaced core layers, while the first insulating layer interposed between the core layers does not include glass fiber, thereby blocking the possibility of migration due to contact between the via and the glass fiber. Accordingly, there is a technical effect of improving electrical characteristics, for example, increasing signal transmission speed.

[0029] In addition, the embodiment has a technical effect of increasing the diameter of a via or improving the design freedom of a via hole.

[0030] For example, the embodiment can increase the diameter of a via disposed in a first insulating layer interposed between core layers while ensuring rigidity by including a reinforcing member between multiple spaced core layers. Accordingly, the embodiment can enhance the design freedom of via holes, such as increasing the diameter of the via, without concern for a reduction in the rigidity of the circuit board.

[0031] In addition, the embodiment has a technical effect that the via formation process can be simplified.

[0032] For example, the embodiment can efficiently form via holes through drilling or laser without major damage to the circuit board since the multiple spaced core layers include a reinforcing member, and the via formation process can be simplified because there is no need to place pads for via connection at the interface of each layer.

[0033] In addition, according to an embodiment, while implementing an embedded core, the rigidity of the circuit board can be secured, and the occurrence of voids or blisters in the resin or rotation defects of electronic components due to insufficient insulating layer resin for filling the core layer cavity can be prevented.

[0034] For example, referring to FIGS. 1, 2a, 6 and 7a, an embedded core is implemented by embedding an electronic element (150) in one of the core portions (110) of the embodiment, for example, a second core layer (112), while the first core layer (111) and the second core layer (112) including glass fibers are provided so as to secure the rigidity of the circuit board, and further, since the thickness of the second core layer (112) in which the electronic element is embedded is comparable to that of the electronic element, voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the cavity of the second core layer can be prevented, thereby providing a complex technical effect.

[0035] Also, referring to FIGS. 1, 2b, 6, and 7b, the first thickness (T1) of the first core layer (111) in which the electronic element is not embedded can be controlled to be greater than the second thickness (T2) of the second core layer (112) in which the electronic element is embedded. Accordingly, while sufficiently securing the rigidity of the core portion (110), the thickness of the second core layer (112) in which the electronic element is embedded is controlled to be thin enough to correspond to the thickness of the electronic element, thereby implementing an embedded core, while securing the rigidity of the circuit board, and at the same time preventing the occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the core layer cavity. The technical effects of the embodiment are not limited to those described in this item, but include those that can be understood through the description of the invention.

[0036] Figure 1 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0037] Fig. 2a is a cross-sectional view showing a detailed area of ​​Fig. 1.

[0038] Figure 2b is another cross-sectional view showing a detailed area of ​​Figure 1.

[0039] Fig. 3 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0040] Fig. 4 is a cross-sectional view showing a detailed area of ​​Fig. 3.

[0041] FIGS. 5A to 5D are process diagrams showing a manufacturing process of a part of a semiconductor package according to the second embodiment.

[0042] Fig. 6 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0043] Figure 7a is a first cross-sectional view showing in detail one area of ​​Figure 6.

[0044] Fig. 7b is a second cross-sectional view showing in detail one area of ​​Fig. 6.

[0045] Figure 7c is a third cross-sectional view showing in detail one area of ​​Figure 6.

[0046] Fig. 8 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0047] Figure 9a is a first cross-sectional view showing in detail one area of ​​Figure 8.

[0048] Figure 9b is a second cross-sectional view showing in detail one area of ​​Figure 8.

[0049] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0050] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0051] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0052] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0053] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0054] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0055] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0056] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0057] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0058] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0059] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0060] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0061]

[0062] (Example)

[0063] Fig. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. Referring to Fig. 1, the first embodiment includes a core portion (110), a first insulating layer (121), an upper build-up insulator (117), a lower build-up insulator (118), a via portion (130V), and a wiring portion (160). The upper build-up insulator (117) may be disposed on the core portion (110), and the lower build-up insulator (118) may be disposed below the core portion (110). In addition, a first insulating layer (121) may be interposed between the core portions (110).

[0064] A semiconductor package according to the first embodiment may include an electronic element (150) built into a core portion (110). The characteristics of each main component will be described in detail below.

[0065]

[0066] The core portion (110) includes a first core layer (111) and a second core layer (112) that are sequentially arranged. The first core layer (111) and the second core layer (112) may include a reinforcing member, and the reinforcing member may be a reinforcing fiber or glass fiber, etc.

[0067] The first core layer (111) and the second core layer (112) may be arranged spaced apart from each other. A first insulating layer (121) may be arranged between the first core layer (111) and the second core layer (112). The first insulating layer (121) interposed between the first core layer (111) and the second core layer (112) may not include a reinforcing member in the form of glass fiber, but is not limited thereto.

[0068]

[0069] The first core layer (111) and the second core layer (112) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. In addition, the first core layer (111) and the second core layer (112) may include a strengthened or flexible plastic such as polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC).

[0070] Meanwhile, the first insulating layer (121) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, for example, Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Ltd. may be used. In addition, the first insulating layer (121) may be formed using a photocurable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern. In addition, the first insulating layer (121) may include an optically isotropic film, for example, a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA). In addition, the first insulating layer (121) may have a structure in which an inorganic filler such as silica or alumina is arranged in a thermosetting resin or a thermoplastic resin. In addition, the first insulating layer (121) may include a prepreg, thereby having a strength of a certain level or higher that can improve the bending characteristics of the circuit board. The prepreg constituting the first insulating layer (121) may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0071]

[0072] Next, an upper build-up insulator (117) may be placed on the core portion (110), and a lower build-up insulator (118) may be placed below the core portion (110).

[0073] The upper build-up insulator (117) may include a second insulating layer (122) disposed on the core portion (110), and a third insulating layer (123) disposed on the second insulating layer (122). In addition, the lower build-up insulator (118) may include a fourth insulating layer (124), a fifth insulating layer (125), and a sixth insulating layer (126) disposed under the core portion (110). In addition, an upper protective layer (128) may be disposed to partially cover a wiring layer disposed on the third insulating layer (123). In addition, a lower protective layer (129) may be disposed to partially cover a wiring layer disposed under the sixth insulating layer (126).

[0074] The second insulating layer (122) to the sixth insulating layer (126) may have a structure in which an inorganic filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin. In addition, the insulating layer (120) may use a thermosetting insulating material containing an inorganic filler in the resin, for example, Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. In addition, the insulating layer (120) may use a photocurable insulating material (Photo Imageable Dielectric, PID). In addition, the insulating layer (120) may include an optically isotropic film, for example, a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0075] The second insulating layer (122) to the sixth insulating layer (126) may include a prepreg, and may have a strength of a certain level or higher that can improve the bending characteristics of the circuit board. The prepreg constituting the second insulating layer (122) to the sixth insulating layer (126) may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like.

[0076]

[0077] Next, the second core layer (112) may include a cavity (115), and an electronic element (150) may be placed within the cavity (115). An area within the cavity (115) where the electronic element (150) is not placed may be formed of the same material as the first insulating layer (121). Accordingly, a portion of the first insulating layer (121) may overlap the second core layer (112) in a horizontal direction.

[0078]

[0079] Additionally, a device pad (152) may be arranged on the upper surface of the electronic device (150). Additionally, a second via (132) may be arranged on the device pad (152). The electronic device (150) may be electrically connected to the first wiring portion (166) through the second via (132). The electronic device (150) may be an active device or a passive device.

[0080] The wiring section (160) may include a first wiring section (166) disposed on the core section (110) and a second wiring section (168) disposed under the core section (110). The first wiring section (166) and the second wiring section (168) each include pads and traces (or connection patterns) according to their functions. The pads may be mounting pads on which components or chips are mounted or terminal pads connected to an external substrate. The traces may be long signal wiring lines connecting between a plurality of pads. The traces are micropatterns having a width smaller than the pads. The first and second wiring sections (166, 168) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the wiring portion (160) may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0081]

[0082] Next, the via section (130V) includes a first via (130) arranged in a vertical through hole integrally penetrating the core section (110) and the first insulating layer (121), the second insulating layer (122) and the fourth insulating layer (124), a second via (132) arranged on the element pad (152) of the electronic element (150), a third via (134) arranged on the first via (130), and a fourth via (136) arranged under the first via (130).

[0083] The first via (130) may overlap with the electronic element (150) in the horizontal direction. In addition, the first via (130) may be connected to the first wiring portion (166) disposed on the upper surface of the core portion (110) and the second wiring portion (168) disposed on the lower surface of the core portion (110).

[0084] The via (130V) can be formed by filling the inside of the through hole with a conductive material. The metal material forming the via (130V) can be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling can utilize any one of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0085] Meanwhile, the circuit board being studied internally formed a through electrode by forming a via in each of the core and insulating layers and providing a pad for via connection at the interface of each layer. In addition, as the rigidity decreased when forming the via hole, the problem of warpage was caused by the decrease in rigidity, so the rigidity was secured by filling the inside of the via hole with resin. Accordingly, the circuit board had a problem in that the signal transmission distance increased due to the pad provided in the via, and the signal transmission loss increased. In addition, when forming the via hole, it was difficult to perform the drilling process due to damage to the circuit board, and since it was formed through etching on the upper and lower parts of the core layer or the insulating layer, there was a problem in that the horizontal width in the middle of the via became narrow and an hourglass shape was formed, which increased the electrical resistance.

[0086] On the other hand, the embodiment can interpose a first insulating layer (121) between a first core layer (111) and a second core layer (112) spaced apart from each other, and embed an electronic element (150) in the second core layer (112). Accordingly, the core portion (110) has a first core layer (111) and a second core layer (112) including glass fibers to secure rigidity, while forming a vertical first via (130) as an integral part through a drilling or laser process, etc., and since a pad for via connection does not need to be provided at the interface of each layer, the transmission distance of a signal flowing through the first via (130) can be reduced, and thus there is a technical effect of minimizing signal transmission loss. In addition, since the first via (130) is formed integrally through a drilling or laser process, the via formation process is simplified, and the problem of the width in the middle of the via being reduced is prevented, thereby providing a technical effect of preventing an increase in electrical resistance.

[0087] In addition, when the first insulating layer (121) through which the first via (130) penetrates does not have glass fiber, the possibility of migration due to contact between the first via (130) and the glass fiber can be blocked due to not having glass fiber, and thus there is a technical effect of improving electrical characteristics, for example, improving signal transmission speed.

[0088] In addition, according to an embodiment, an embedded core is implemented by embedding an electronic element (150) in one of the core portions (110), for example, a second core layer (112), and the rigidity of the circuit board can be secured by providing a first core layer (111) and a second core layer (112) including glass fiber, and further, since the thickness of the second core layer (112) is comparable to that of the electronic element (150), there is a composite technical effect of preventing occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the second core layer cavity.

[0089] Additionally, the first via (130) is connected to the first wiring portion (166) arranged on the core portion (110), and the first wiring portion (166) can be connected to the third via (134).

[0090] .

[0091] A pad may be formed on the third via (134), for example, a first pad (137a) may be formed on the third via (134) overlapping the first via (130), and a second pad (137b) may be formed on the third via (134) overlapping the electronic element (150).

[0092] A connecting member that electrically connects to an external element or substrate can be formed on the first pad (137a) and the second pad (137b).

[0093] For example, a post bump (201P) may be formed of a conductive metal such as Cu on a first pad (137a) formed on a third via (134) overlapping a first via (130).

[0094] The post bump (201P) of the embodiment operates to facilitate power and / or signal transmission when another upper circuit board is placed on the semiconductor device and / or circuit board, thereby facilitating the operation of the electronic device and / or connecting member.

[0095] Furthermore, according to the embodiment, by erecting a post bump (201P) on the first pad (137a), a space for mounting a semiconductor chip on a circuit board can be secured. Accordingly, heat generated from the semiconductor package can be more efficiently dissipated, and higher performance can be achieved by using a more integrated chip.

[0096] In addition, according to the embodiment, by erecting a post bump (201P) on the first pad (137a), the solder volume for mounting a semiconductor chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0097] In addition, an upper solder portion (201S) is disposed on a second pad (137b) formed on a third via (134) overlapping with an electronic component (150), and the upper solder portion (201S) can be electrically connected to an external component or a substrate. In addition, it can be connected to a second wiring portion (168) disposed under the first via (130) core portion (110). The second wiring portion (168) can be connected to a fourth via (136). In addition, a lower solder portion (202) can be disposed under the fourth via (136).

[0098]

[0099] Next, Fig. 2a is a cross-sectional view showing in detail one region (R1) of Fig. 1. Referring to Fig. 2a, in the first embodiment, the first via (130) can penetrate at least one of the first, second, and fourth insulating layers (121, 122, 124) and at least one of the core portion (110).

[0100] Additionally, the first via (130) can penetrate from the upper surface to the lower surface of the build-up structure including the insulating layer and the core portion (110).

[0101] In addition, in the embodiment, the via pad connected to the first via (130) at each interface of the first, second, and fourth insulating layers (121, 122, 124) and the core portion (110) may not be included. In the embodiment, since the core portion (110) includes a reinforcing member, there is a technical effect of being able to efficiently form a vertical through via through a drilling or laser process without causing damage to the circuit board.

[0102] Meanwhile, the first via (130) may include a first via region (130a) that overlaps the first core layer (111) in the horizontal direction and a second via region (130b) that overlaps the first insulating layer (121).

[0103] A desmear solution is used to remove smear generated when forming a via hole. The desmear solution not only etches the smear but also partially etches the side surfaces of the core portion (110) and the first, second, and fourth insulating layers (121, 122, 124), so that an expansion portion, which is an area where the width of the via hole is expanded, can be formed in the core portion (110) and the first, second, and fourth insulating layers (121, 122, 124).

[0104] Meanwhile, the etching degrees of the first core layer (111), the second core layer (112) and the first insulating layer (121) in the core portion (110) may be different. Specifically, the first insulating layer (121) may have a larger area etched by the desmear solution than the first core layer (111) and the second core layer (112) due to a lower content of the reinforcing member or no glass fiber content than the first core layer (111) and the second core layer (112). Accordingly, the horizontal width (W2) of the second via region (130b) may be larger than the horizontal width (W1) of the first via region (130a). In addition, the second via region (130b) may include a shape in which the side surface has a curvature. In addition, the curvature of the side surface of the second via region (130b) may be larger than the curvature of the side surface of the first via region (130a).

[0105]

[0106] Next, Fig. 2b is a second cross-sectional view showing in detail one area (R1) of Fig. 1.

[0107] As previously described, in conventional FCBGA circuit boards for servers and vehicles, electronic components can be embedded in the core layer. In this case, the core layer, which comprises glass fiber, is formed thicker than the thickness of the electronic components, taking into account the rigidity of the circuit board, etc.

[0108] However, when manufacturing an embedded core, as the size of the electronic component becomes smaller compared to the volume of the core layer cavity or opening for embedding the electronic component, there is a problem in that resin voids or resin blisters occur inside the resin due to insufficient insulating layer resin to fill the cavity of the core layer, or rotational defects of the electronic component occur.

[0109]

[0110] Referring to FIG. 1 and FIG. 2b together, an embedded core can be implemented by embedding an electronic element (150) in one of the core portions (110) of the embodiment, for example, a second core layer (112), while the rigidity of the circuit board can be secured by having a first core layer (111) having a first thickness (T1) and a second core layer (112) having a second thickness (T2) including glass fiber.

[0111] In addition, the embodiment has a composite technical effect that can prevent occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the cavity of the second core layer (112) as the second thickness (T2) of the second core layer (112) has a thickness comparable to that of the electronic element (150).

[0112] In addition, the first thickness (T1) of the first core layer (111) in which the electronic element is not embedded can be controlled to be greater than the second thickness (T2) of the second core layer (112) in which the electronic element is embedded, and accordingly, while sufficiently securing the rigidity of the core portion (110), the thickness of the second core layer (112) in which the electronic element is embedded is controlled to be thin enough to correspond to the thickness of the electronic element, thereby implementing an embedded core, while securing the rigidity of the circuit board, and at the same time, preventing the occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the core layer cavity. This has a special technical effect.

[0113] In addition, the third thickness (T3) of the first insulating layer (121) may be thinner than the thickness of the core portion (110). In detail, the third thickness (T3) of the first insulating layer (121) may be thinner than the first thickness (T1) of the first core layer (111). In addition, the third thickness (T3) of the first insulating layer (121) may be thinner than the second thickness (T2) of the second core layer (112). By controlling the first thickness (T1) and the second thickness (T2) of the core portion (110) to be greater than the third thickness (T3) of the first insulating layer (121), the rigidity of the core portion (110) can be sufficiently secured, and when forming the first via (130) by drilling, there is a technical effect in which damage to the circuit board can be prevented based on the rigidity of the core portion (110).

[0114]

[0115] Next, Fig. 3 is a cross-sectional view illustrating a semiconductor package according to a second embodiment. The second embodiment may employ the technical features of the first embodiment, and the following description will focus on the features of the second embodiment.

[0116] Referring to FIG. 3, the first insulating layer (121) may include a plurality of layers. For example, the first insulating layer (121) may include a 1-1 insulating layer (121a) and a 1-2 insulating layer (121b) disposed on the 1-1 insulating layer (121a). The 1-1 insulating layer (121a) may be disposed on the first core layer (111). The 1-2 insulating layer (121b) may be disposed under the 2nd core layer (112).

[0117]

[0118] Next, Fig. 4 is a second cross-sectional view showing in detail one area (R2) of Fig. 3.

[0119] Referring to FIG. 4, the first via (130) can be arranged to penetrate the first insulating layer (121), the second insulating layer (122), the fourth insulating layer (124), and the core portion (110).

[0120] The first via (130) may include a first via region (130a) overlapping the first insulating layer (121) and a second via region (130b) overlapping the first insulating layer (121).

[0121] The first insulating layer (121) may include a first-first insulating layer (121a) and a first-second insulating layer (121b), and when a via hole is formed, a desmear liquid may penetrate into the interface where the first-first insulating layer (121a) and the first-second insulating layer (121b) come into contact.

[0122] Accordingly, the first insulating layer (121) can have an extension formed between the first-first insulating layer (121a) and the first-second insulating layer (121b) in which the width of the through hole is expanded in the horizontal direction.

[0123] Additionally, the first via (130) may include a second-second via region (130b2) disposed between the first-first insulating layer (121a) and the first-second insulating layer (121b). The second-second via region (130b2) may include a protrusion extending into an extension between the first-first insulating layer (121a) and the first-second insulating layer (121b).

[0124] In addition, the horizontal width (W3) of the 2-2 via area (130b2) may be greater than the horizontal width (W1) of the 1st via area (130a). In addition, the horizontal width (W3) of the 2-2 via area (130b2) may be greater than the horizontal width (W2) of the 2nd via area (130b). In addition, the thickness of the protrusion of the 2-2 via area (130b2) in the vertical direction in the horizontal direction of the 1st insulating layer (121) may be reduced.

[0125] Accordingly, according to the first and second embodiments, when the first insulating layer (121) does not include glass fiber, the possibility of migration due to contact between the first via (130T) and the glass fiber can be blocked, and the horizontal width of the second via area (130b) overlapping the first insulating layer (121) can be secured wide, thereby further improving the electrical characteristics, which has the technical effect.

[0126]

[0127] Next, FIGS. 5a to 5d are process diagrams showing a manufacturing process of a part of a semiconductor package according to the second embodiment.

[0128] First, referring to FIG. 5a, the core portion (110) may include a first core layer (111) and a second core layer (112). In addition, a first insulating layer (121) may be disposed between the first core layer (111) and the second core layer (112). In addition, a second insulating layer (122) may be disposed on the second core layer (112). In addition, a fourth insulating layer (124) may be disposed under the first core layer (111). In addition, the first insulating layer (121) may include a first-first insulating layer (121a) and a first-second insulating layer (121b).

[0129] The first via hole (180) may penetrate at least one of the core portion (110) and at least one of the insulating layers. For example, the first via hole (180) may be a via hole that penetrates from the upper surface to the lower surface of the build-up structure including the core portion (110) and the insulating layer. The first via hole (180) may be formed by drilling, laser processing, or the like, but is not limited thereto. In this case, a smear (170) may occur on the side surface of the first via hole (180).

[0130] Next, referring to FIG. 5b, a desmear process may be performed to remove a smear formed on the side surface of the first via hole (180). The desmear process may utilize a desmear solution or a photodesmear solution. Meanwhile, when a desmear solution is utilized, not only the smear but also a portion of the side surface of the via hole may be etched. Accordingly, an expansion portion may be formed in the area where the first via hole (180) is formed in the core portion (110) and the insulating layer.

[0131] Meanwhile, the etching degree of the core layer and the first insulating layer may be different. Specifically, the first core layer (111) and the second core layer (112) may have a smaller etched area than the insulating layer due to a higher content of the reinforcing material than the first, second, and fourth insulating layers (121, 122, 124). In addition, the first, second, and fourth insulating layers (121, 122, 124) may have a larger etched area than the core layer due to a lower content of the reinforcing material than the core layer or due to the presence of a glass fiber material.

[0132] For example, the first via hole (180) may include a first via hole region (180a) overlapping the first core layer (111) and a second via hole region (180b) overlapping the first insulating layer (121). The horizontal width (W2) of the second via hole region (180b) may be greater than the horizontal width (W1) of the first via hole region (180a).

[0133] In addition, in the desmear process, the desmear liquid can penetrate into the interface between the first-first insulating layer (121a) and the first-second insulating layer (121b). Accordingly, the first insulating layer (121) can include an extension between the first-first insulating layer (121a) and the first-second insulating layer (121b). The first via hole (180) can include a third via hole region (180c) overlapping the interface between the first-first insulating layer (121a) and the first-second insulating layer (121b). The third via hole region (180c) can have a shape that protrudes from the extension between the first-first insulating layer (121a) and the first-second insulating layer (121b) into the first insulating layer (121). The horizontal width (W3) of the third via hole region (180c) may be greater than the width (W1) of the first via hole region (180a) and the width (W2) of the second via hole region (180b). In addition, the vertical thickness of the third via hole region (180c) may become smaller as it goes horizontally along the first insulating layer (121).

[0134]

[0135] Next, referring to FIG. 5c, a seed layer (185) can be formed within the first via hole (180). The seed layer (185) can be formed on the inner walls of the core portion (110) and the first, second, and fourth insulating layers (121, 122, 124). The seed layer (185) can fill the first via hole (180) and the expansion portion formed on the inner side of the core portion (110).

[0136]

[0137] Next, referring to FIG. 5d, a first via (130) can be formed through a plating process of a seed layer formed on the inside of the first via hole (180).

[0138] Meanwhile, the first via (130) may include a first via region (130a) overlapping the first core layer (111) and a second via region (130b) overlapping the first insulating layer (121). The horizontal width (W2) of the second via region (130b) may be greater than the horizontal width (W1) of the first via region (130a).

[0139] Additionally, the first via (130) may include a second-second via region (130b2) at the interface where the first-first insulating layer (121a) and the first-second insulating layer (121b) come into contact.

[0140] The second-second via region (130b2) may be located within the second via region (130b). The second-second via region (130b2) may include a shape that protrudes from the center of the first via (130) to the interface between the first-first insulating layer (121a) and the first-second insulating layer (121b). The vertical thickness of the second-second via region (130b2) may decrease from the center of the first via (130) toward the first insulating layer (121).

[0141] The horizontal width (W3) of the second-second via area (130b2) may be greater than the horizontal width (W1) of the first via area (130a). In addition, the horizontal width (W3) of the second-second via area (130b2) may be greater than the horizontal width (W2) of the second via area (130b).

[0142]

[0143] The circuit board according to the embodiment and the semiconductor package including the same have a technical effect of providing a semiconductor package with improved signal transmission speed.

[0144] For example, in forming a via penetrating a core portion, the embodiment can secure rigidity by including a reinforcing member between a plurality of spaced core layers, while blocking the possibility of migration due to contact between the via and the glass fiber by not including glass fiber in the first insulating layer interposed between the core layers. This can have the technical effect of improving electrical characteristics, for example, increasing signal transmission speed.

[0145] In addition, the embodiment has a technical effect of increasing the diameter of a via or improving the design freedom of a via hole.

[0146] For example, the embodiment can increase the diameter of a via disposed in a first insulating layer interposed between core layers while ensuring rigidity by including a reinforcing member between multiple spaced core layers. Accordingly, the embodiment can enhance the design freedom of via holes, such as increasing the diameter of the via, without concern for a reduction in the rigidity of the circuit board.

[0147] In addition, the embodiment has a technical effect that the via formation process can be simplified.

[0148] For example, the embodiment can efficiently form via holes through drilling or laser without major damage to the circuit board since the multiple spaced core layers include a reinforcing member, and the via formation process can be simplified because there is no need to place pads for via connection at the interface of each layer.

[0149] In addition, according to an embodiment, while implementing an embedded core, the rigidity of the circuit board can be secured, and the occurrence of voids or blisters in the resin or rotation defects of electronic components due to insufficient insulating layer resin for filling the core layer cavity can be prevented.

[0150]

[0151] Next, Fig. 6 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0152] The third embodiment may adopt the technical features of the first or second embodiment, and the main features of the third embodiment will be described below.

[0153] Referring to FIG. 6, a semiconductor package according to a third embodiment includes a core portion (110), a first insulating layer (121), an upper build-up insulator (117), a lower build-up insulator (118), a via portion (130V), and a wiring portion (160). The upper build-up insulator (117) may be disposed on the core portion (110), and the lower build-up insulator (118) may be disposed below the core portion (110). In addition, a first insulating layer (121) may be interposed between the core portions (110). The semiconductor package according to the third embodiment may include an electronic device (150) embedded in the core portion (110).

[0154] The core portion (110) includes a first core layer (111) and a second core layer (112) that are sequentially arranged. The first core layer (111) and the second core layer (112) may include a reinforcing member, and the reinforcing member may be a reinforcing fiber or glass fiber, etc.

[0155] The first core layer (111) and the second core layer (112) may be arranged vertically spaced apart from each other. A first insulating layer (121) may be arranged between the first core layer (111) and the second core layer (112).

[0156] An upper build-up insulator (117) may be placed on the core portion (110), and a lower build-up insulator (118) may be placed below the core portion (110).

[0157] The upper build-up insulator (117) may include a second insulating layer (122) disposed on the core portion (110), and a third insulating layer (123) disposed on the second insulating layer (122). In addition, the lower build-up insulator (118) may include a fourth insulating layer (124), a fifth insulating layer (125), and a sixth insulating layer (126) disposed under the core portion (110).

[0158] Next, the second core layer (112) may include a cavity (115), and an electronic element (150) may be placed within the cavity (115).

[0159] Additionally, a device pad (152) may be arranged on the upper surface of the electronic device (150). Additionally, a second via (132) may be arranged on the device pad (152). The electronic device (150) may be electrically connected to a wiring portion (160) through the second via (132). The electronic device (150) may be an active device or a passive device.

[0160] The wiring section (160) may include a first wiring section (166) arranged on the core section (110) and a second wiring section (168) arranged under the core section (110).

[0161] The via section (130V) includes a first via (130T) arranged in a vertical through hole integrally penetrating the core section (110) and the first insulating layer (121), the second insulating layer (122) and the fourth insulating layer (124), a second via (132) arranged on the element pad (152) of the electronic element (150), a third via (134) arranged on the first via (130T), and a fourth via (136) arranged under the first via (130T).

[0162]

[0163] In the third embodiment, a first insulating layer (121) is interposed between a first core layer (111) and a second core layer (112) that are spaced apart from each other, and an electronic element (150) can be embedded in the second core layer (112).

[0164] Accordingly, the core part (110) has a first core layer (111) and a second core layer (112) including glass fibers to secure rigidity, and a vertical first via (130T) can be integrally formed through a drilling or laser process, etc., and since a pad for via connection does not need to be provided at the interface of each layer, the transmission distance of a signal flowing through the first via (130T) can be reduced, and thus there is a technical effect of minimizing signal transmission loss.

[0165] In addition, since the first via (130T) is formed integrally through a drilling or laser process, the via formation process is simplified, and the problem of the width in the middle of the via being reduced is prevented, thereby providing a technical effect of preventing an increase in electrical resistance.

[0166] In addition, when the first insulating layer (121) through which the first via (130T) penetrates does not have glass fiber, the possibility of migration due to contact between the first via (130T) and the glass fiber can be blocked, and thus, there is a technical effect of improving electrical characteristics, for example, improving signal transmission speed.

[0167] In addition, according to an embodiment, an embedded core is implemented by embedding an electronic element (150) in one of the core portions (110), for example, a second core layer (112), and the rigidity of the circuit board can be secured by providing a first core layer (111) and a second core layer (112) including glass fiber, and further, since the thickness of the second core layer (112) is comparable to that of the electronic element (150), there is a composite technical effect of preventing occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the second core layer cavity.

[0168] Additionally, the first via (130T) is connected to the first wiring portion (166) arranged on the core portion (110), and the first wiring portion (166) can be connected to the third via (134).

[0169] A pad may be formed on the third via (134), for example, a first pad (137a) may be formed on the third via (134) overlapping the first via (130T), and a second pad (137b) may be formed on the third via (134) overlapping the electronic element (150).

[0170] A connecting member that electrically connects to an external element or substrate can be formed on the first pad (137a) and the second pad (137b).

[0171] For example, a post bump (201P) may be formed of a conductive metal such as Cu on a first pad (137a) formed on a third via (134) overlapping a first via (130T).

[0172] The post bump (201P) of the embodiment operates to facilitate power and / or signal transmission when another upper circuit board is placed on the semiconductor device and / or circuit board, thereby facilitating the operation of the electronic device and / or connecting member.

[0173] Furthermore, according to the embodiment, by erecting a post bump (201P) on the first pad (137a), a space for mounting a semiconductor chip on a circuit board can be secured. Accordingly, heat generated from the semiconductor package can be more efficiently dissipated, and higher performance can be achieved by using a more integrated chip.

[0174] In addition, according to the embodiment, by erecting a post bump (201P) on the first pad (137a), the solder volume for mounting a semiconductor chip can be reduced, and the reduced solder volume can prevent a short circuit due to a solder bridge, thereby improving electrical reliability, and by reducing the risk of an electrical short, a finer bump pitch design is possible, thereby providing a high-performance semiconductor package.

[0175] In addition, an upper solder portion (201S) is disposed on a second pad (137b) formed on a third via (134) overlapping with an electronic component (150), and the upper solder portion (201S) can be electrically connected to an external component or a substrate. In addition, it can be connected to a second wiring portion (168) disposed under the first via (130T) core portion (110). The second wiring portion (168) can be connected to a fourth via (136). In addition, a lower solder portion (202) can be disposed under the fourth via (136).

[0176]

[0177] Next, Fig. 7a is a cross-sectional view showing in detail one area (R3) of Fig. 6.

[0178] Referring to FIG. 7a, in the third embodiment, the first via (130T) can penetrate at least one of the first, second, and fourth insulating layers (121, 122, 124) and at least one of the core portion (110).

[0179] Additionally, the first via (130T) can penetrate from the upper surface to the lower surface of the build-up structure including the insulating layer and the core portion (110).

[0180] Additionally, in the embodiment, the pad for the via connected to the first via (130T) may not be included at each interface of the first, second, and fourth insulating layers (121, 122, 124) and the core portion (110).

[0181] Accordingly, the embodiment has a core portion (110) having a first core layer (111) and a second core layer (112) including glass fibers to secure rigidity, and by integrally forming a vertical first via (130T), there is no need to provide a pad for via connection at the interface of each layer, thereby reducing the transmission distance of a signal flowing through the first via (130T), and thus has a technical effect of minimizing signal transmission loss.

[0182] In the embodiment, the core portion (110) includes a reinforcing member, thereby providing a technical effect of efficiently forming a vertical through-via through a drilling or laser process without causing damage to the circuit board.

[0183] Meanwhile, the first via (130T) may include a first via region (130Ta) that overlaps the first core layer (111) in the horizontal direction and a second via region (130Tb) that overlaps the first insulating layer (121).

[0184] According to an embodiment, a desmear solution is used to remove smear generated when forming a via hole, and the desmear solution partially etches not only the smear but also the side surfaces of the core portion (110) and the first, second, and fourth insulating layers (121, 122, 124), so that an expansion portion, which is an area where the width of the via hole is expanded, can be formed in the core portion (110) and the first, second, and fourth insulating layers (121, 122, 124).

[0185] Meanwhile, the etching degrees of the first core layer (111), the second core layer (112) and the first insulating layer (121) in the core portion (110) may be different. Specifically, the first insulating layer (121) may have a larger area etched by the desmear solution than the first core layer (111) and the second core layer (112) due to a lower content of the reinforcing member or no glass fiber content than the first core layer (111) and the second core layer (112). Accordingly, the horizontal width (W2) of the second via region (130Tb) may be larger than the horizontal width (W1) of the first via region (130Ta). In addition, the second via region (130Tb) may include a shape in which the side surface has a curvature. In addition, the curvature of the side surface of the second via region (130Tb) may be larger than the curvature of the side surface of the first via region (130Ta).

[0186] Additionally, the first via (130T) can penetrate at least a portion of the upper build-up insulator and at least a portion of the lower build-up insulator.

[0187] Accordingly, the first via (130T) may include a third via region (130Tc) that overlaps the second insulating layer (122) in the horizontal direction and a fourth via region (130Td) that overlaps the fourth insulating layer (124).

[0188]

[0189] Next, a seed layer (not shown) can be formed within the via hole. The seed layer can be formed on the inner walls of the core portion (110) and the first, second, and fourth insulating layers (121, 122, 124). Next, a first via electrode (130T1) can be formed through a plating process of the seed layer formed on the inner side of the via hole.

[0190] The first via (130T) of the embodiment may include an insulating member (130T2) within the through hole. The insulating member (130T2) may be provided to fill a portion of the through hole penetrating the core layer. The insulating member (130T2) may also be referred to as a hole plugging member. The insulating member (130T2) may include an insulating material provided within the through hole of the core layer. For example, the insulating member (130T2) may include a paste of an insulating ink material. For example, the insulating member (130T2) may include a plugging ink, but the embodiment is not limited thereto. For example, the insulating member (130T2) may include a conductive material. Specifically, the insulating member (130T2) may include a conductive paste containing a conductive metal powder.

[0191]

[0192] As described above, the first via (130T) may include a first via region (130Ta) overlapping the first core layer (111) and a second via region (130Tb) overlapping the first insulating layer (121). The horizontal width (W2) of the second via region (130Tb) may be greater than the horizontal width (W1) of the first via region (130Ta).

[0193] Additionally, the horizontal width (W2) of the third via area (130Tc) may be greater than the horizontal width (W1) of the first via area (130Ta).

[0194] Additionally, the horizontal width (W2) of the fourth via area (130Td) may be greater than the horizontal width (W1) of the first via area (130Ta).

[0195]

[0196] Accordingly, according to the embodiment, when the first insulating layer (121) does not include glass fiber, the possibility of migration due to contact between the first via (130T) and the glass fiber can be blocked, and the horizontal width of the second via area (130Tb) overlapping the first insulating layer (121) can be secured wide, thereby further improving the electrical characteristics.

[0197] In addition, according to the embodiment, when the first insulating layer (121) does not have glass fiber, the possibility of migration due to contact between the first via (130T) and the glass fiber can be blocked, and the horizontal width of the third via area (130Tc) and the fourth via area (130Td) overlapping the second insulating layer and the fourth insulating layer, respectively, can be secured wide, thereby providing a technical effect that the electrical characteristics can be further improved.

[0198]

[0199] Next, Fig. 7b is a second cross-sectional view showing in detail one area (R3) of Fig. 6.

[0200] As previously described, in conventional FCBGA circuit boards for servers and vehicles, electronic components can be embedded in the core layer. In this case, the core layer, which comprises glass fiber, is formed thicker than the thickness of the electronic components, taking into account the rigidity of the circuit board, etc.

[0201] However, when manufacturing an embedded core, as the size of the electronic component becomes smaller compared to the volume of the core layer cavity or opening for embedding the electronic component, there is a problem in that resin voids or resin blisters occur inside the resin due to insufficient insulating layer resin to fill the cavity of the core layer, or rotational defects of the electronic component occur.

[0202]

[0203] Referring to FIGS. 6 and 7b together, an embedded core can be implemented by embedding an electronic element (150) in one of the core portions (110) of the embodiment, for example, a second core layer (112), while the rigidity of the circuit board can be secured by having a first core layer (111) having a first thickness (T1) and a second core layer (112) having a second thickness (T2) including glass fiber.

[0204] In addition, the embodiment has a composite technical effect that can prevent occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the cavity of the second core layer (112) as the second thickness (T2) of the second core layer (112) has a thickness comparable to that of the electronic element (150).

[0205] In addition, the first thickness (T1) of the first core layer (111) in which the electronic element is not embedded can be controlled to be greater than the second thickness (T2) of the second core layer (112) in which the electronic element is embedded, and accordingly, while sufficiently securing the rigidity of the core portion (110), the thickness of the second core layer (112) in which the electronic element is embedded is controlled to be thin enough to correspond to the thickness of the electronic element, thereby implementing an embedded core, while securing the rigidity of the circuit board, and at the same time, preventing the occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the core layer cavity. This has a special technical effect.

[0206] In addition, the third thickness (T3) of the first insulating layer (121) may be thinner than the thickness of the core portion (110). In detail, the third thickness (T3) of the first insulating layer (121) may be thinner than the first thickness (T1) of the first core layer (111). In addition, the third thickness (T3) of the first insulating layer (121) may be thinner than the second thickness (T2) of the second core layer (112). By controlling the first thickness (T1) and the second thickness (T2) of the core portion (110) to be greater than the third thickness (T3) of the first insulating layer (121), the rigidity of the core portion (110) can be sufficiently secured, and when forming the first via (130T) by drilling, there is a technical effect in which damage to the circuit board can be prevented based on the rigidity of the core portion (110).

[0207]

[0208] Next, Fig. 7c is a third cross-sectional view showing in detail one area (R2) of Fig. 6.

[0209] Referring to FIG. 7c, the first via (130T) can be arranged to penetrate the first insulating layer (121), the second insulating layer (122), the fourth insulating layer (124), and the core portion (110).

[0210] The first via (130T) may include a first via region (130Ta) overlapping the first insulating layer (121) and a second via region (130Tb) overlapping the first insulating layer (121).

[0211] The first insulating layer (121) may include a plurality of insulating layers, for example, a first-first insulating layer (121a) and a first-second insulating layer (121b), and when a via hole is formed, a desmear liquid may penetrate into the interface where the first-first insulating layer (121a) and the first-second insulating layer (121b) come into contact.

[0212] Accordingly, the first insulating layer (121) can have an extension formed between the first-first insulating layer (121a) and the first-second insulating layer (121b) in which the width of the through hole is expanded in the horizontal direction.

[0213] Additionally, the first via (130T) may include a second-second via region (130Tb2) disposed between the first-first insulating layer (121a) and the first-second insulating layer (121b). The second-second via region (130Tb2) may include a protrusion extending into an extension between the first-first insulating layer (121a) and the first-second insulating layer (121b).

[0214] In addition, the horizontal width (W3) of the 2-2 via area (130Tb2) may be larger than the horizontal width (W1) of the 1st via area (130Ta). In addition, the horizontal width (W3) of the 2-2 via area (130Tb2) may be larger than the horizontal width (W2) of the 2nd via area (130Tb). In addition, the thickness of the protrusion of the 2-2 via area (130Tb2) in the vertical direction in the horizontal direction of the 1st insulating layer (121) may be reduced.

[0215] Accordingly, according to the embodiment, when the first insulating layer (121) does not have glass fiber, the possibility of migration due to contact between the first via (130T) and the glass fiber can be blocked, and further, there is a technical effect that the horizontal width of the second via area (130Tb) overlapping the first insulating layer (121) can be secured wider than the horizontal width (W1) of the first via area (130Ta), thereby further improving the electrical characteristics.

[0216]

[0217] Next, FIG. 8 is a cross-sectional view showing a semiconductor package according to the fourth embodiment, FIG. 9a is a first cross-sectional view (R4a) showing in detail one area (R4) of FIG. 8, and FIG. 9b is a second cross-sectional view (R4b) showing in detail one area (R4) of FIG. 8.

[0218] The semiconductor package according to the fourth embodiment can adopt the technical features of the semiconductor package according to the third embodiment, and the main features of the fourth embodiment will be described below.

[0219]

[0220] Referring to FIG. 8, a semiconductor package according to the fourth embodiment includes a core portion (110), a first insulating layer (121), an upper build-up insulator (117), a lower build-up insulator (118), a via portion (130V), and a wiring portion (160). The upper build-up insulator (117) may be disposed on the core portion (110), and the lower build-up insulator (118) may be disposed below the core portion (110). In addition, a first insulating layer (121) may be interposed between the core portions (110).

[0221] A semiconductor package according to the fourth embodiment may include an electronic element (150) built into a core portion (110).

[0222] In the fourth embodiment, the second via portion (130V2) includes a first-second via (130TB) arranged in a vertical through hole integrally penetrating the core portion (110) and the first insulating layer (121), a third via (134) arranged on the element pad (152) of the electronic element (150), and a fourth via (136) arranged under the first-second via (130TB).

[0223] Unlike the first via (130T) in the third embodiment, the first-second via (130TB) in the fourth embodiment can integrally penetrate the first core portion (111), the second core portion (112), and the first insulating layer (121) interposed therebetween.

[0224] The first-second via (130TB) may overlap with the electronic element (150) in the horizontal direction. In addition, the first-second via (130TB) may be electrically connected to the first wiring portion (166) disposed on the upper surface of the core portion (110) and the second wiring portion (168) disposed on the lower surface of the core portion (110).

[0225]

[0226] Next, Fig. 9a is a first cross-sectional view (R4a) showing in detail one area (R4) of Fig. 8.

[0227] Referring to FIG. 9a, in the fourth embodiment, the first-second via (130TB) may penetrate the first insulating layer (121) and the core portion (110). In addition, in the embodiment, a pad for a via connected to the first-second via (130TB) may not be included at each interface of the first insulating layer (121) and the core portion (110).

[0228] Accordingly, the embodiment has a core portion (110) having a first core layer (111) and a second core layer (112) including glass fibers to secure rigidity, and by integrally forming the vertical first-second via (130TB), there is no need to provide a pad for via connection at the interface of each layer, thereby reducing the transmission distance of a signal flowing through the first-second via (130TB), and thus has a technical effect of minimizing signal transmission loss.

[0229] In the embodiment, the core portion (110) includes a reinforcing member, thereby providing a technical effect of efficiently forming a vertical through-via through a drilling or laser process without causing damage to the circuit board.

[0230] Meanwhile, the first-second via (130TB) may include a first via region (130Ta) that overlaps the first core layer (111) in the horizontal direction and a second via region (130Tb) that overlaps the first insulating layer (121).

[0231] According to an embodiment, a desmear solution is used to remove smear generated when forming a via hole, and the desmear solution etches not only the smear but also a portion of the side surface of the core portion (110) and the first insulating layer (121), so that an expansion portion, which is an area where the width of the via hole is expanded, can be formed in the core portion (110) and the first insulating layer (121).

[0232] Meanwhile, the etching degrees of the first core layer (111), the second core layer (112) and the first insulating layer (121) in the core portion (110) may be different. Specifically, the first insulating layer (121) may have a larger area etched by the desmear solution than the first core layer (111) and the second core layer (112) due to a lower content of the reinforcing member or no glass fiber content than the first core layer (111) and the second core layer (112). Accordingly, the horizontal width (W2) of the second via region (130Tb) may be larger than the horizontal width (W1) of the first via region (130Ta). In addition, the second via region (130Tb) may include a shape in which the side surface has a curvature. In addition, the curvature of the side surface of the second via region (130Tb) may be larger than the curvature of the side surface of the first via region (130Ta).

[0233] In addition, the first-second via (130TB) of the embodiment may include an insulating member (130T2) within the through hole. The insulating member (130T2) may be provided to fill a portion of the through hole penetrating the core layer. The insulating member (130T2) may also be referred to as a hole plugging member. The insulating member (130T2) may include an insulating material provided within the through hole of the core layer. For example, the insulating member (130T2) may include a paste of an insulating ink material. For example, the insulating member (130T2) may include a plugging ink, but the embodiment is not limited thereto. For example, the insulating member (130T2) may include a conductive material. Specifically, the insulating member (130T2) may include a conductive paste containing a conductive metal powder.

[0234]

[0235] According to the fourth embodiment, when the first insulating layer (121) does not include glass fiber, the possibility of migration due to contact between the first-second via (130TB) and the glass fiber can be blocked, and the horizontal width of the second via area (130Tb) overlapping the first insulating layer (121) can be secured wide, thereby further improving the electrical characteristics. This has the technical effect.

[0236]

[0237] Continuing with reference to FIG. 9a, an embedded core can be implemented by embedding an electronic element (150) in one of the core portions (110) of the embodiment, for example, a second core layer (112), while the rigidity of the circuit board can be secured by having a first core layer (111) having a first thickness (T1) and a second core layer (112) having a second thickness (T2) including glass fiber.

[0238] In addition, the embodiment has a composite technical effect that can prevent occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the cavity of the second core layer (112) as the second thickness (T2) of the second core layer (112) has a thickness comparable to that of the electronic element (150).

[0239] In addition, the first thickness (T1) of the first core layer (111) in which the electronic element is not embedded can be controlled to be greater than the second thickness (T2) of the second core layer (112) in which the electronic element is embedded, and accordingly, while sufficiently securing the rigidity of the core portion (110), the thickness of the second core layer (112) in which the electronic element is embedded is controlled to be thin enough to correspond to the thickness of the electronic element, thereby implementing an embedded core, while securing the rigidity of the circuit board, and at the same time, preventing the occurrence of voids or blisters in the resin or rotation defects of the electronic element due to insufficient insulating layer resin for filling the core layer cavity. This has a special technical effect.

[0240] In addition, the third thickness (T3) of the first insulating layer (121) may be thinner than the thickness of the core portion (110). In detail, the third thickness (T3) of the first insulating layer (121) may be thinner than the first thickness (T1) of the first core layer (111). In addition, the third thickness (T3) of the first insulating layer (121) may be thinner than the second thickness (T2) of the second core layer (112). By controlling the first thickness (T1) and the second thickness (T2) of the core portion (110) to be greater than the third thickness (T3) of the first insulating layer (121), the rigidity of the core portion (110) can be sufficiently secured, and when the first-second via (130TB) is formed by drilling, damage to the circuit board can be prevented based on the rigidity of the core portion (110).

[0241]

[0242] Next, Fig. 9b is a second cross-sectional view (R4b) showing in detail one area (R4) of Fig. 8.

[0243] Referring to FIG. 9b, the first-second via (130TB) can be arranged to penetrate the first insulating layer (121) and the core portion (110).

[0244] The first-second via (130TB) may include a first via region (130Ta) overlapping the first insulating layer (121) and a second via region (130Tb) overlapping the first insulating layer (121).

[0245] The first insulating layer (121) may include a plurality of insulating layers, for example, a first-first insulating layer (121a) and a first-second insulating layer (121b), and when a via hole is formed, a desmear liquid may penetrate into the interface where the first-first insulating layer (121a) and the first-second insulating layer (121b) come into contact.

[0246] Accordingly, the first insulating layer (121) can have an extension formed between the first-first insulating layer (121a) and the first-second insulating layer (121b) in which the width of the through hole is expanded in the horizontal direction.

[0247] Additionally, the first-second via (130TB) may include a second-second via region (130Tb2) disposed between the first-first insulating layer (121a) and the first-second insulating layer (121b). The second-second via region (130Tb2) may include a protrusion extending into an extension between the first-first insulating layer (121a) and the first-second insulating layer (121b).

[0248] In addition, the horizontal width (W3) of the 2-2 via area (130Tb2) may be larger than the horizontal width (W1) of the 1st via area (130Ta). In addition, the horizontal width (W3) of the 2-2 via area (130Tb2) may be larger than the horizontal width (W2) of the 2nd via area (130Tb). In addition, the thickness of the protrusion of the 2-2 via area (130Tb2) in the vertical direction in the horizontal direction of the 1st insulating layer (121) may be reduced.

[0249] Accordingly, according to the fourth embodiment, when the first insulating layer (121) does not have glass fiber, the possibility of migration due to contact between the first-second via (130TB) and the glass fiber can be blocked, and further, the horizontal width of the second via area (130Tb) overlapping the first insulating layer (121) can be secured wider than the horizontal width (W1) of the first via area (130Ta), thereby providing a technical effect of further improving electrical characteristics.

[0250]

[0251] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0252] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0253] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0254] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A core portion having a first core layer and a second core layer disposed on the first core layer; A first insulating layer disposed between the first core layer and the second core layer; and A via penetrating the core portion and the first insulating layer; The above via, It includes a first via region that horizontally overlaps the first core layer and a second via region that is vertically connected to the first via region and horizontally overlaps the first insulating layer. A circuit board, wherein the horizontal width of the second via region is different from the horizontal width of the first via region.

2. A core portion having a first core layer and a second core layer disposed on the first core layer; A first insulating layer disposed between the first core layer and the second core layer; An upper build-up insulator disposed on the first core layer; a lower build-up insulator disposed under the second core layer; and A via penetrating the core portion and the first insulating layer; The above via penetrates at least a portion of the upper build-up insulator and at least a portion of the lower build-up insulator, The above via, It includes a first via region that horizontally overlaps the first core layer and a second via region that is vertically connected to the first via region and horizontally overlaps the first insulating layer. A circuit board, wherein the horizontal width of the second via region is different from the horizontal width of the first via region.

3. In paragraph 1 or 2, A circuit board, wherein the horizontal width of the second via area is greater than the horizontal width of the first via area.

4. In paragraph 1 or 2, A circuit board, wherein the first insulating layer has a lower content of reinforcing material than the first core layer or the second core layer.

5. In paragraph 1 or 2, The above first insulating layer is, A first-first insulating layer disposed on the first core layer; and Including a 1-2 insulating layer disposed on the 1-1 insulating layer; A circuit board, wherein the first insulating layer includes an extension portion whose width increases in the horizontal direction between the first-first insulating layer and the first-second insulating layer.

6. In paragraph 5, The above via, It includes a 2-2 via region protruding into the interface between the 1-1 insulating layer and the 1-2 insulating layer, A circuit board, wherein the horizontal width of the above-mentioned 2-2 via area is greater than the horizontal width of the above-mentioned first via area.

7. In paragraph 6, A circuit board, wherein the horizontal width of the above-mentioned 2-2 via area is greater than the horizontal width of the above-mentioned 2nd via area.

8. In paragraph 6, A circuit board, wherein the vertical thickness of the above-mentioned 2-2 via region becomes smaller as it goes in the horizontal direction of the first insulating layer.

9. In paragraph 1, The side surface of the second via region includes a curved surface, A circuit board, wherein the curvature of the side surface of the second via area is greater than the curvature of the side surface of the first via area.

10. A semiconductor package including a circuit board according to claim 1 or 2.

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