Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment may comprise: an insulating layer including a through-hole penetrating an upper surface and a lower surface; a circuit layer disposed on the upper surface of the insulating layer; and a metal layer disposed between the circuit layer and the upper surface of the insulating layer. The circuit layer may include a wiring portion disposed on the upper surface of the insulating layer, and a via portion extending from the wiring portion, disposed inside the through-hole of the insulating layer, and overlapping the insulating layer in the horizontal direction. The metal layer may include an extension portion extending into the through-hole to vertically overlap at least a portion of the via portion and not in contact with the inner sidewall of the through-hole.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] A circuit board includes an insulating layer and a circuit layer disposed on the insulating layer, and may refer to a substrate on which semiconductor devices are mounted. For example, a circuit board may refer to a substrate in which at least one semiconductor device is mounted, with a mounting location for each semiconductor device determined, and a circuit layer connected to the semiconductor device disposed on the insulating layer. The circuit layer may include a through electrode (or via) and a circuit pattern layer (or metal wiring). The semiconductor device is mounted on the circuit board, and can transmit and receive signals through the circuit layer.

[0003] Meanwhile, in the process of forming a through-hole electrode in a conventional circuit board, there is a process of forming a through-hole in a copper-clad laminate (CCL) in which copper foil is laminated to an insulating layer such as prepreg (PPG), epoxy, or polyimide, and forming a through-hole electrode in the through-hole. For example, in the conventional technology, a through-hole is formed through a laser drilling process using CO2 while the copper foil is bonded, and a through-hole electrode is formed through a plating process.

[0004] However, when the copper foil of a copper-clad laminate is thicker than approximately 6 ㎛, the energy absorption rate is low at approximately 5%, making CO2 laser drilling difficult. Therefore, in conventional technology, the copper foil at the location of the through-hole formation is etched away using a photolithography process, such as the DES (Developing-Etching-Striping) process, and then laser drilling is performed on the exposed insulating layer.

[0005] Accordingly, the circuit layer formation process of the conventional copper-clad laminate requires a photo process on the copper foil, which increases the process production delivery L / T (Lead Time) and also increases the manufacturing cost.

[0006] In addition, in the conventional technology, the copper foil of the copper-clad laminate is removed by etching, so the copper foil side of the entrance of the through hole may be smooth as if cut with a knife, which may reduce the plating process in the subsequent plating process.

[0007] One of the technical challenges of the embodiment is to provide a circuit board and a semiconductor package including the same, which can partially remove copper foil without involving a photo process in a circuit layer forming process using a copper-clad laminate.

[0008] In addition, one of the technical tasks of the embodiment is to improve the plating processability according to the plating process performed after the copper foil of the copper-clad laminate is partially removed.

[0009] The technical problems of the embodiment are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0010] A circuit board according to an embodiment may include an insulating layer including a through hole penetrating an upper surface and a lower surface, a circuit layer disposed on an upper surface of the insulating layer, and a metal layer disposed between the circuit layer and the upper surface of the insulating layer.

[0011] The circuit layer may include a wiring portion arranged on the upper surface of the insulating layer and a via portion extended from the wiring portion and arranged inside the through hole of the insulating layer and overlapping the insulating layer in a horizontal direction.

[0012] The metal layer may include an extension extending inwardly of the through hole, vertically overlapping at least a portion of the via portion, and not in contact with the inner wall of the through hole.

[0013] The side roughness of the extension of the metal layer may be different from the roughness of the inner wall of the through hole formed in the insulating layer.

[0014] The length by which the extension of the metal layer extends inside the through hole may be less than half of the horizontal width of the upper side of the through hole provided in the insulating layer.

[0015] The upper surface of the metal layer in contact with the wiring portion may include a surface treatment area.

[0016] The above metal layer may be arranged at a level equal to or higher than the through hole of the above insulating layer.

[0017] The thickness of the above wiring portion may be thicker than the thickness of the above metal layer.

[0018] In an embodiment, the circuit layer may further include a second metal layer disposed on a lower surface of the insulating layer.

[0019] The second metal layer may vertically overlap the wiring portion and the via portion.

[0020] The lower surface of the second metal layer may include a surface treatment region.

[0021] The side slope of the extension of the metal layer may correspond to the slope of the inner wall of the through hole formed in the insulating layer.

[0022] A semiconductor package according to an embodiment may include any one of the circuit boards described above.

[0023] According to the circuit board and the semiconductor package including the same according to the embodiment, there is a feature that a through hole can be formed in an insulating layer while partially removing the copper foil without involving a photo process in a circuit layer formation process using a copper-clad laminate. Accordingly, since the photo process that was involved in the prior art to partially remove the copper foil in forming a through electrode of a copper-clad laminate is omitted, the process production delivery L / T (Lead Time) can be shortened and manufacturing costs can be reduced.

[0024] In addition, according to an embodiment, the processability of the plating process performed after forming a through hole in a copper-clad laminate can be improved, thereby improving the physical reliability and electrical reliability of the through electrode and the circuit pattern layer (metal wiring).

[0025] For example, referring to FIGS. 2A and 2B, the physical reliability of the circuit layer including the first via portion (251v) can be improved by having the first metal layer (255) have an extension portion (255P) that vertically overlaps at least a portion of the first via portion (251v) and does not contact the inner wall of the first through hole (210H).

[0026] In addition, since the extension portion (255P) of the first metal layer has a side roughness (255R), the plating processability of the plating process can be improved, thereby improving the physical reliability and electrical reliability of the through electrode and wiring portion.

[0027] The technical effects of the embodiments are not limited to those described in this article, but include those that can be understood through the description of the invention.

[0028] Fig. 1 is a cross-sectional view of a circuit board (200) according to an embodiment.

[0029] FIG. 2a is a detailed view of a first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 1.

[0030] FIG. 2b is a detailed view of a second area (A2) of a first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 2a.

[0031] FIG. 2c is a microscopic photograph of an area corresponding to the first area (A1) of a circuit board (200) according to an embodiment.

[0032] FIGS. 3A to 3D are manufacturing process diagrams of a first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 2A.

[0033] Fig. 4 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0034] Fig. 5 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0035] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the specific embodiments described, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0036] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as “and (and) at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0037] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0038] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0039] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0040]

[0041] (Example)

[0042] Hereinafter, a circuit board and a semiconductor package according to an embodiment will be specifically described. Here, a circuit board may refer to a board before electronic components are mounted. In addition, a circuit board may refer to an auxiliary board (e.g., an interposer) connected to another board on which electronic components are mounted. In addition, a semiconductor package may refer to a package in which electronic components are mounted on a circuit board. In this case, the product group to which the circuit board of the embodiment is applied may include, but is not limited to, FC-BGA (Flip Chip-Ball Grid Array) or FC-CSP (Flip Chip-Chip Scale Package).

[0043]

[0044] Fig. 1 is a cross-sectional view of a circuit board (200) according to an embodiment.

[0045] Referring to FIG. 1, the circuit board (200) of the embodiment includes an insulating layer (290), a circuit layer (250), and a protective layer (280). The insulating layer (290) includes a first insulating layer (210), a second insulating layer (220), and a third insulating layer (230). The circuit layer (250) includes a first circuit layer (251), a second circuit layer (252), and a third circuit layer (253). In addition, the circuit layer (250) includes a via portion (250V) arranged in a through hole of the insulating layer and a wiring portion (250W) arranged on an upper or lower surface of the insulating layer. The via portion (250V) may be referred to as a 'through electrode' or a 'via', and the wiring portion (250W) may be referred to as a 'circuit pattern layer' or a 'metal wiring'.

[0046]

[0047] First, the circuit board (200) of the embodiment includes a single or multiple insulating layers (290). For example, the insulating layers (290) of the embodiment include, but are not limited to, a first insulating layer (210), a second insulating layer (220), and a third insulating layer (230). For example, the embodiment may have two or fewer insulating layers, or four or more insulating layers.

[0048] The circuit board (200) of the embodiment includes an inner insulating layer and an outer insulating layer. The inner insulating layer may refer to an insulating layer located on the inner side in a laminated structure of multiple insulating layers. The outer insulating layer may refer to an insulating layer located on the outer side in a plurality of insulating layers. For example, the first insulating layer (210) may be an inner insulating layer, and the second insulating layer (220) and the third insulating layer (230) may be outer insulating layers.

[0049] At least one of the insulating layers (290) of the embodiment may be rigid or flexible. For example, at least one of the insulating layers (290) may include glass or plastic. For example, at least one of the insulating layers (290) may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. In addition, the insulating layer (210) may include a strengthened or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

[0050] Additionally, at least one of the insulating layers (290) may include an optically isotropic film. For example, at least one of the insulating layers (290) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0051] Additionally, at least one of the insulating layers (290) may be formed of a material including an inorganic filler and an insulating resin. For example, at least one of the insulating layers (290) may be formed of ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), etc.

[0052] In addition, at least one of the insulating layers (290) may include a prepreg, thereby having a strength of a certain level or higher that can improve the bending characteristics of the circuit board. The prepreg constituting the insulating layer (290) may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like. In this case, in the embodiment, the first insulating layer (210), the second insulating layer (220), and the third insulating layer (230) may all be composed of prepreg, or alternatively, the second insulating layer (220) and / or the third insulating layer (230), excluding the first insulating layer (210), may be composed of prepreg.

[0053]

[0054] Next, the circuit board (200) of the embodiment includes a circuit layer (250). The circuit layer (250) includes a via portion (250V) and a wiring portion (250W).

[0055] The circuit layer (250) includes a single or multiple circuit layers. For example, the circuit layer (250) includes first to third circuit layers (251, 252, 253). For example, the circuit layer (250) includes a first circuit layer (251) disposed on a first insulating layer (210), a second circuit layer (252) disposed on a second insulating layer (220), and a third circuit layer (253) disposed on a third insulating layer (230).

[0056] The circuit layer (250) includes a via portion (250V) penetrating the insulating layer and a wiring portion (250W) arranged on the upper or lower surface of the insulating layer. The via portion (250V) includes first to third via portions (251v, 252v, 253v) penetrating the first insulating layer (210), the second insulating layer (220), and the third insulating layer (230). The wiring portion (250W) includes first to third wiring portions (251w, 252w, 253w) arranged on the surfaces of the first insulating layer (210), the second insulating layer (220), and the third insulating layer (230).

[0057] The first circuit layer (251) includes a first via portion (251v) and a first wiring portion (251w). In addition, the second circuit layer (252) includes a second via portion (252v) and a second wiring portion (252w). In addition, the third circuit layer (253) includes a third via portion (253v) and a third wiring portion (253w). The third wiring portion (253w) may be arranged on the upper and lower sides of the third via portion (253v), respectively.

[0058] The via portion (250V) of the embodiment includes first to third via portions (251v, 252v, 253v) arranged in through holes penetrating the first insulating layer (210), the second insulating layer (220), and the third insulating layer (230), respectively.

[0059] For example, the first via portion (251v) can penetrate the first insulating layer (210) and connect between the first wiring portion (251w) and the third wiring portion (253w).

[0060] For example, the second via portion (252v) can penetrate the second insulating layer (220) and connect between the first wiring portion (251w) and the second wiring portion (252w).

[0061] For example, the third via (253v) can penetrate the third insulating layer (230) and connect between the upper third wiring portion (253w) and the lower third wiring portion (253w).

[0062] The first via portion (251v), the second via portion (252v), and the third via portion (253v) can be formed by filling a through hole (not shown) penetrating at least one of the first insulating layer (210), the second insulating layer (220), and the third insulating layer (230) with a conductive material.

[0063] For example, the metal material forming the via (250V) may be any one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The conductive material filling may utilize one or more of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing.

[0064] At least one of the vias (250V) may have a different shape. For example, the first via (251v) and the second via (252v) may have different shapes than the third via (253v), but this is not limited thereto.

[0065]

[0066] Next, the wiring section (250W) of the embodiment includes first to third wiring sections (251w, 252w, 253w) arranged on the surfaces of the first insulating layer (210), the second insulating layer (220), and the third insulating layer (230).

[0067] The wiring section (250W) is a wiring section that transmits an electrical signal and may be formed of a metal material with high electrical conductivity. To this end, the wiring section (250W) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn).

[0068] The wiring section (250W) includes traces and wiring pads. A trace refers to a line-shaped wiring that transmits electrical signals. A wiring pad may be a mounting pad on which a component such as a chip is mounted, a core pad or BGA pad for connection to an external board, or an electrode pad connected to a through-hole electrode.

[0069] The wiring portion (250W) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength. The wiring portion (250W) may be manufactured using a method such as an additive process, a subtractive process, a semi-additive process (SAP), or a modified semi-additive process (MSAP), which are manufacturing processes for printed circuit boards.

[0070]

[0071] Next, the circuit board (200) of the embodiment includes a protective layer (280). For example, the protective layer (280) includes a first protective layer (281) disposed on the upper surface of the second insulating layer (220) and a second protective layer (282) disposed on the lower surface of the third insulating layer (230).

[0072] The protective layer (280) may be a resist layer. For example, the protective layer (280) may be a solder resist layer including an organic polymer material. For example, the protective layer (280) includes an epoxy acrylate series resin. Specifically, the protective layer (280) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, and the like. However, the embodiment is not limited thereto, and the protective layer (280) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0073] The protective layer (280) may include at least one opening. For example, the first protective layer (281) may include an opening that vertically overlaps the second wiring portion (252w). Additionally, the second protective layer (282) may include an opening that vertically overlaps the lower third wiring portion (253w).

[0074]

[0075] Next, FIG. 2a is a detailed view of a first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 1, FIG. 2b is a detailed view of a second area (A2) of the first area (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 2a, and FIG. 2c is a microscopic photograph of an area corresponding to the first area (A1) of a circuit board (200) according to the embodiment.

[0076]

[0077] As described above, one of the technical challenges of the present invention is to provide a circuit board and a semiconductor package including the same, which can partially remove copper foil without involving a photo process in a circuit layer formation process using a copper-clad laminate. Furthermore, one of the technical challenges of the present invention is to improve the quality of a through-electrode formed by a plating process performed after the copper foil of the copper-clad laminate is partially removed.

[0078] The technical features of a circuit board (200) according to an embodiment for solving the technical problems of the following embodiments will be described in detail based on FIGS. 2a to 2c.

[0079]

[0080] The circuit board (200) of the embodiment includes an insulating layer including a through hole penetrating the upper surface and the lower surface, a circuit layer disposed on the upper surface of the insulating layer, and a first metal layer (255) disposed between the circuit layer and the upper surface of the insulating layer.

[0081] For example, referring to FIG. 2, the circuit board (200) of the embodiment includes a first insulating layer (210) including a first through hole (210H) penetrating the upper surface and the lower surface, a first circuit layer (251) disposed on the upper surface of the first insulating layer (210), and a first metal layer (255) disposed between the first circuit layer (251) and the upper surface of the first insulating layer (210). In addition, the circuit board (200) of the embodiment may include, but is not limited to, a second metal layer (256) disposed on the lower surface of the first insulating layer (210).

[0082] The first metal layer (255) or the second metal layer (256) may be any one material selected from a conductive metal, for example, copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), but is not limited thereto.

[0083] The first circuit layer (251) includes a first wiring portion (251w) disposed on the upper surface of the first insulating layer (210) and a first via portion (251v) extending from the first wiring portion (251w) and disposed inside the first through hole (210H) of the first insulating layer (210) and overlapping the first insulating layer (210) in a horizontal direction.

[0084] At this time, the first metal layer (255) includes an extension portion (255P) that extends toward the inside of the first through hole (210H) and vertically overlaps at least a portion of the first via portion (251v) and does not contact the inner wall of the first through hole (210H).

[0085] The first metal layer (255) and the second metal layer (256) respectively disposed on the upper and lower sides of the first insulating layer (210) may be copper foil, but are not limited thereto.

[0086] The first metal layer (255) may be in a form in which the area corresponding to the first via portion (251v) is removed, and the second metal layer (256) may be in a form in which the area corresponding to the first via portion (251v) is not removed, but is not limited thereto.

[0087] The surface of the first metal layer (255) or the second metal layer (256) includes a surface treatment region. For example, the upper surface of the first metal layer (255) includes a first surface treatment region (ST1). The lower surface of the second metal layer (256) includes a second surface treatment region (ST2).

[0088]

[0089] Next, referring to FIG. 2b, the first metal layer (255) includes an extension portion (255P) that extends inwardly of the first through hole (210H) and vertically overlaps at least a portion of the first via portion (251v) and does not contact the inner wall of the first through hole (210H).

[0090] At this time, the side roughness (255R) of the extension (255P) of the first metal layer may be different from the side roughness (210R) of the first through hole (210H) formed in the first insulating layer (210).

[0091] For example, the side roughness (255R) of the extension (255P) of the first metal layer may be about 1.0 to 1.5 μm, and the side roughness (210R) of the first through hole (210H) formed in the first insulating layer (210) may be about 1.0 to 3.0 μm, but is not limited thereto.

[0092] According to an embodiment, since the extension portion (255P) of the first metal layer has a side roughness (255R), the plating processability of the plating process can be improved, thereby improving the physical reliability and electrical reliability of the through-electrode.

[0093] In addition, since the first metal layer (255) has an extension (255P) that vertically overlaps at least a portion of the first via portion (251v) and does not come into contact with the inner wall of the first through hole (210H), it can serve as an anchoring element, thereby improving the physical reliability of the circuit layer including the first via portion (251v) and the first wiring portion (251w).

[0094] In the embodiment, the slope of the side surface of the extension portion (255P) of the first metal layer may correspond to the slope of the side surface of the first through hole (210H) formed in the first insulating layer (210). For example, according to the embodiment, in the process of forming a circuit layer using a copper-clad laminate, the through hole is formed in the presence of the copper foil without involving a photo process, so the slope of the side surface of the extension portion (255P) of the first metal layer may correspond to the slope of the side surface of the first through hole (210H) formed in the first insulating layer (210).

[0095]

[0096] Next, referring to FIG. 2c, the first horizontal length (L1) of the extension portion (255P) extending inwardly of the first through hole (210H) of the first metal layer (255) may be smaller than half the first horizontal width (D1) of the upper side of the first through hole (210H) provided in the first insulating layer (210). For example, the first horizontal length (L1) of the extension portion (255P) of the first metal layer (255) may be smaller than 1 / 4 of the first horizontal width (D1) of the upper side of the first through hole (210H).

[0097] In addition, the extension portion (255P) of the first metal layer (255) may extend horizontally from the upper surface of the first insulating layer (210) toward the inside of the first through hole (210H). Accordingly, the extension portion (255P) of the first metal layer (255) of the embodiment may be distinguished from a protrusion or extension portion in which a via portion or a through electrode located inside the first through hole (210H) partially protrudes toward the inner wall of the through hole.

[0098]

[0099] According to an embodiment, there is a feature that allows for the formation of through holes in an insulating layer by partially removing the copper foil without involving a photo process in a circuit layer formation process using a copper-clad laminate. Accordingly, since the photo process that was involved in the prior art to partially remove the copper foil in the formation of through electrodes in a copper-clad laminate is omitted, the process production delivery L / T (Lead Time) can be shortened and manufacturing costs can be reduced.

[0100] In addition, according to an embodiment, the processability of the plating process performed after forming a through hole in a copper-clad laminate can be improved, thereby improving the physical reliability and electrical reliability of the through electrode and the circuit pattern layer (metal wiring).

[0101] For example, the physical reliability of the circuit layer including the first via portion (251v) can be improved by having the first metal layer (255) have an extension portion (255P) that vertically overlaps at least a portion of the first via portion (251v) and does not contact the inner wall of the first through hole (210H).

[0102] In addition, since the extension portion (255P) of the first metal layer has a side roughness (255R), the plating processability of the plating process can be improved, thereby improving the physical reliability and electrical reliability of the through electrode and wiring portion.

[0103]

[0104] Next, FIGS. 3A to 3D are manufacturing process diagrams of a first region (A1) of a circuit board (200) according to the embodiment illustrated in FIG. 2A. Hereinafter, the manufacturing process of a circuit board (200) including the first metal layer (255) illustrated in FIG. 2A will be described with reference to FIGS. 3A to 3D.

[0105] First, as shown in Fig. 3a, a first insulating layer (210) is prepared in which a first base metal layer (255a) and a second base metal layer (256a) are bonded to the upper and lower sides, respectively. The first insulating layer (210) includes a resin (210a) and glass fiber (210g). In addition, the first insulating layer (210) may be formed of a material including an inorganic filler and an insulating resin. In addition, the first insulating layer (210) may include a prepreg, and the prepreg may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with an epoxy resin or the like. In addition, the first insulating layer (210) may include glass or plastic. Additionally, the first insulating layer (210) may include a reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0106] The first base metal layer (255a) or the second base metal layer (256a) may be any one material selected from a conductive metal, for example, copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), but is not limited thereto.

[0107]

[0108] Next, as shown in Fig. 3b, the surfaces of the first base metal layer (255a) and the second base metal layer (256a) are surface-treated (OP) to form a first base metal layer (255a) having a first surface-treated region (ST1) on the upper surface, and a second metal layer (256) having a second surface-treated region (ST2) on the lower surface. Since the surface-treated region may be formed in the base metal layer in which a through hole will be formed later, forming the surface-treated region in the second base metal layer (256a) may be optional.

[0109] In an embodiment, the surface treatment (OP) may maximize the laser energy absorption rate by forming roughness on the surface of the first base metal layer (255a) or the second base metal layer (256a) through a pretreatment (e.g., an oxide process), and thus laser drilling may be possible without etching the metal layer at the laser processing location. In addition, the surface roughness formation according to the surface treatment (OP) may be possible through an etching process on the surface of the first base metal layer (255a) or the second base metal layer (256a). For example, the roughness formation may be performed through a surface treatment process using any one of an etchant selected from organic acid, inorganic acid, copper chloride, benzotriazole, and alkali metal formate, but is not limited thereto.

[0110]

[0111] Thereafter, as shown in Fig. 3c, an etching mask (P1) is formed to open an area where a first through hole (210H) is to be formed, and CO2 laser drilling (CL) is performed to form a surface-treated first metal layer (255) and a first through hole (210H). The etching mask (P1) may be a dry film, but is not limited thereto.

[0112] At this time, the surface-treated first metal layer (255) may include an extension (255P) having a rough surface as if the side of the first metal layer (255) at the entrance of the through hole (210H) is forcibly torn.

[0113] According to an embodiment, there is a feature that allows for the formation of through holes in an insulating layer by partially removing the copper foil without involving a photo process in a circuit layer formation process using a copper-clad laminate. Accordingly, since the photo process that was involved in the prior art to partially remove the copper foil in the formation of through electrodes in a copper-clad laminate is omitted, the process production delivery L / T (Lead Time) can be shortened and manufacturing costs can be reduced.

[0114]

[0115] Next, as shown in Fig. 3d, a plating process is performed on the first through hole (210H) to form a first via portion (251v) and a first wiring portion (251w). In addition, a third wiring portion (253w) may be formed on the lower side of the second metal layer (256).

[0116] According to an embodiment, the processability of a plating process performed after forming a through hole in a copper-clad laminate can be improved, thereby improving the physical reliability and electrical reliability of a through electrode and a circuit pattern layer (metal wiring).

[0117] For example, the physical reliability of the circuit layer including the first via portion (251v) can be improved by having the first metal layer (255) have an extension portion (255P) that vertically overlaps at least a portion of the first via portion (251v) and does not contact the inner wall of the first through hole (210H).

[0118] In addition, as shown in Fig. 2b, since the extension portion (255P) of the first metal layer has a side roughness (255R), the plating processability of the plating process can be improved, thereby improving the physical reliability and electrical reliability of the through electrode and wiring portion.

[0119]

[0120] Next, a semiconductor package including a circuit board according to an embodiment will be described.

[0121] FIG. 4 is a cross-sectional view showing a semiconductor package according to the first embodiment, and the semiconductor package may include the circuit board (200) of FIG. 1.

[0122] Referring to FIG. 4, the semiconductor package includes a first connection portion (291) and may also include a chip (310) or element (310) disposed on the first connection portion (291).

[0123] Specifically, the second wiring portion (252w) positioned on the uppermost side of the circuit board includes a pad. The pad of the second circuit layer (252) vertically overlaps with the opening of the first protective layer (281). The first connection portion (291) is positioned on the pad of the second circuit layer (252) that vertically overlaps with the opening of the first protective layer (281).

[0124] The first connecting portion (291) may have a spherical shape. For example, the cross-section of the first connecting portion (291) may have a circular shape or a semicircular shape. The first connecting portion (291) may be a solder ball, but is not limited thereto.

[0125] The semiconductor package may include a chip (310) or a device (310) disposed on the first connection portion (291). The chip (310) may be a processor chip. For example, the chip (310) may be an application processor (AP) chip of any one of a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0126] At this time, the bottom of the chip (310) may include a terminal (320), and the terminal (320) may be electrically connected to the second wiring portion (252w) of the circuit board through the first connection portion (291).

[0127] Meanwhile, the semiconductor package of the first embodiment may include a plurality of chips arranged and spaced apart from each other in the horizontal direction on a single circuit board. For example, the chip (310) may include a first chip and a second chip that are spaced apart from each other. The first chip and the second chip may be different types of application processor (AP) chips.

[0128] Meanwhile, the semiconductor package may include a second connection portion (292). The second connection portion (292) may be disposed on a lower surface of the third circuit layer (253). For example, the third circuit layer (253) includes at least one pad. And, the pad of the third circuit layer (253) may vertically overlap with an opening of the second protective layer (282). And, the second connection portion (292) may be disposed under the pad of the third circuit layer (253) that vertically overlaps with the opening of the second protective layer (282). The second connection portion (292) may be a solder ball, but is not limited thereto. The second connection portion (292) may be for connecting the semiconductor package and a main board (or motherboard) of an external device.

[0129]

[0130] Next, Fig. 5 is a drawing showing a semiconductor package according to the second embodiment.

[0131] Referring to FIG. 5, the semiconductor package of FIG. 4 according to the second embodiment further includes an external substrate (410) attached thereto. The external substrate (410) may be an interposer, but is not limited thereto.

[0132] The external substrate (410) includes a plurality of insulating layers (not shown). The external substrate (410) includes a circuit layer (450) disposed on the plurality of insulating layers. The external substrate (410) may be a substrate connecting a semiconductor package on which an AP chip is disposed and a semiconductor package on which a memory chip is disposed. To this end, the circuit layer of the external substrate (410) may be designed to correspond to the terminal specifications of the AP chip and the terminal specifications of the memory chip. Specifically, the width or pitch of the circuit layer of the circuit board on which the AP chip is disposed may be different from the width or pitch of the circuit layer of the circuit board on which the memory chip is disposed. Accordingly, the external substrate (410) may be disposed between a plurality of circuit boards having the same difference in width or pitch as that to electrically connect them therebetween.

[0133] For this purpose, the semiconductor package further includes a third connection portion (293).

[0134] The third connection portion (293) may be placed on the second wiring portion (252w). Specifically, the second wiring portion (252w) may include a first pad on which the chip (310) is placed and a second pad connected to the external substrate (410). In addition, the third connection portion (293) may be placed on the second pad. At this time, the uppermost portion of the third connection portion (293) may be positioned higher than the upper end of the chip (310). Through this, the embodiment can prevent the chip (310) from being damaged when coupled with the external substrate (410).

[0135] Additionally, the semiconductor package may include a first molding layer (270). The first molding layer (270) may mold the first connection portion (291), the chip (310), and the third connection portion (293). Meanwhile, although not illustrated in FIG. 5, a memory substrate (not illustrated) may be placed on the external substrate (410).

[0136]

[0137] An electronic device including a semiconductor package of the embodiment will be described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be electrically connected to the semiconductor package of the embodiment. Various components may be mounted on the semiconductor package.

[0138] For example, a semiconductor package may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), an antenna chip, a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC).

[0139] For example, a semiconductor package may contain at least one of various types of passive and active components.

[0140] At this time, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the present invention is not limited to this, and it is obvious that the electronic device may be any other electronic device that processes data.

[0141] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integrity or technical interoperability with each other.

[0142] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0143]

[0144] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as falling within the scope of the present invention.

[0145] Although the above description focuses on examples, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. An insulating layer including a through hole penetrating the upper and lower surfaces; a circuit layer disposed on the upper surface of the insulating layer; and A metal layer disposed between the circuit layer and the upper surface of the insulating layer; The above circuit layer is, A wiring portion arranged on the upper surface of the insulating layer; and a via portion extended from the wiring portion and arranged inside the through hole of the insulating layer and overlapping the insulating layer in a horizontal direction; The above metal layer, A circuit board including an extension portion extending inwardly of the through hole and vertically overlapping at least a portion of the via portion and not in contact with the inner wall of the through hole.

2. In paragraph 1, A circuit board wherein the side roughness of the extension of the metal layer is different from the roughness of the inner wall of the through hole formed in the insulating layer.

3. In paragraph 1, A circuit board, wherein the horizontal length of the extension of the metal layer extending into the inside of the through hole is smaller than half the horizontal width of the upper side of the through hole provided in the insulating layer.

4. In paragraph 1, A circuit board, wherein the upper surface of the metal layer in contact with the wiring portion includes a surface treatment region.

5. In paragraph 1, A circuit board, wherein the metal layer is arranged at a height higher than the through hole of the insulating layer.

6. In paragraph 1, A circuit board wherein the thickness of the above wiring portion is thicker than the thickness of the above metal layer.

7. In paragraph 1, The circuit layer further includes a second metal layer disposed on the lower surface of the insulating layer, A circuit board, wherein the second metal layer vertically overlaps the wiring portion and the via portion.

8. In paragraph 7, A circuit board, wherein the lower surface of the second metal layer includes a surface treatment area.

9. In paragraph 1, A circuit board, wherein the side slope of the extension of the metal layer corresponds to the slope of the inner wall of the through hole formed in the insulating layer.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9.

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