Circuit board and semiconductor package comprising same

Abstract

According to an embodiment, the circuit board comprises: a build-up structure; a protective layer disposed on the build-up structure, the protective layer comprising a first protection member having a through-hole and a second protection member disposed inside the through-hole of the first protection member; a first bonding part disposed between the inner surface of the through-hole of the first protection member and the outer surface of the second protection member; and a second bonding part penetrating the second protective member. The upper surface of the first bonding part and the upper surface of the second bonding part have different heights.

Description

Circuit boards and semiconductor packages including the same

[0001] The embodiment relates to a circuit board and a semiconductor package board including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] As the number of semiconductor devices and / or semiconductor chiplets mounted on a semiconductor package increases, the area of ​​the semiconductor package tends to increase. Furthermore, as the area of ​​the semiconductor package increases, the circuit board tends to warp more. If the circuit board warps significantly, the semiconductor devices may not be stably attached to the circuit board. For example, the circuit board includes pad portions that are connected to the terminals of the semiconductor devices. If the circuit board warps significantly in a specific direction, a deviation in the height of the multiple wiring portions may occur, preventing the semiconductor devices from being stably attached.

[0006] Accordingly, a circuit board capable of more stably mounting semiconductor devices is required.

[0007] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0008] In addition, the embodiment provides a circuit board having a structure that is relaxed from being bent in a specific direction and a semiconductor package including the same.

[0009] In addition, the embodiment provides a circuit board having a structure capable of more stably mounting a plurality of semiconductor elements and a semiconductor package including the same.

[0010] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0011] A circuit board according to an embodiment comprises: a build-up structure; a protective layer including a first protective member disposed on the build-up structure and having a through hole; and a second protective member disposed on an inner side of the through hole of the first protective member; a first bonding portion disposed between an inner side of the through hole of the first protective member and an outer side of the second protective member; and a second bonding portion penetrating the second protective member, wherein an upper surface of the first bonding portion and an upper surface of the second bonding portion have different heights.

[0012] Additionally, the upper surface of the first bonding portion is positioned higher than the upper surface of the second bonding portion based on the upper surface of the build-up structure.

[0013] In addition, the upper surface of the first protective member includes a first portion that is furthest from the upper surface of the build-up structure, and a second portion that is closer to the upper surface of the build-up structure than the first portion, and the upper surface of the first bonding portion is positioned higher than the upper surface of the first portion of the first protective member with respect to the upper surface of the build-up structure.

[0014] Additionally, the height of the upper surface of the second protective member is lower than or equal to the height of the upper surface of the first part of the first protective member based on the upper surface of the build-up structure.

[0015] Additionally, the first bonding portion is spaced apart from the inner surface of the through hole of the first protective member and the outer surface of the second protective member.

[0016] In addition, the first bonding portion is provided in plurality and spaced apart from each other along the circumferential direction of the outer surface of the second protective member.

[0017] Additionally, the vertical distance between the upper surface of the first bonding portion and the upper surface of the first portion of the first protective member is 5% to 45% of the vertical distance between the upper surface of the first bonding portion and the lower surface of the first bonding portion.

[0018] Additionally, the first part of the first protective member is provided along the circumferential direction of the second part of the first protective member and is located further from the through hole than the second part of the first protective member.

[0019] In addition, the height of the upper surface of the second bonding portion is lower than the height of the upper surface of the first portion of the first protective member and higher than the height of the upper surface of the second portion based on the upper surface of the build-up structure.

[0020] Additionally, the vertical distance between the upper surface of the first bonding portion and the upper surface of the first part of the first protective member is greater than the vertical distance between the upper surface of the first part of the first protective member and the upper surface of the second bonding portion.

[0021] Additionally, the first part of the first protective member has a width in a horizontal direction that is different from each other along the circumferential direction of the second part of the first protective member.

[0022] Additionally, the circuit board further includes a third bonding portion penetrating the first portion of the first protective member, and a vertical thickness of the third bonding portion is different from a vertical thickness of the first bonding portion.

[0023] Additionally, the vertical thickness of the third bonding portion is greater than the vertical thickness of the first bonding portion.

[0024] Additionally, the circuit board further includes a connecting member embedded within the build-up structure, the connecting member overlapping the second bonding portion along a vertical direction.

[0025] In addition, the circuit board further includes a first bonding portion arranged on the first bonding portion; a first semiconductor element arranged on the first bonding portion; a second bonding portion arranged on the second bonding portion; and a second semiconductor element arranged between the second bonding portion and the first semiconductor element, wherein a vertical thickness of the first bonding portion is greater than a vertical thickness of the second bonding portion.

[0026] In addition, the circuit board further includes a first bonding portion arranged on the first bonding portion; a second bonding portion arranged on the second bonding portion; and a semiconductor element arranged on the first bonding portion and the second bonding portion, wherein a vertical thickness of the first bonding portion is greater than a vertical thickness of the second bonding portion.

[0027] Additionally, the circuit board includes a bonding portion arranged on the second bonding portion; a first semiconductor element arranged on the bonding portion; a second semiconductor element arranged on the first semiconductor; and a connecting wire electrically connecting the first bonding portion and the second semiconductor element.

[0028] An embodiment includes a build-up structure and a protective layer disposed on the build-up structure. At this time, the protective layer includes a first protective member and a second protective member spaced apart from each other in a horizontal direction. Through this, the embodiment can prevent stress applied to the first protective member from being transferred to the second protective member. For example, the embodiment can cause the above-described stress to be absorbed or reduced in an open area (SA) or a spaced area (SA) between the first protective member and the second protective member. Accordingly, the embodiment can improve the physical reliability and / or electrical reliability of a circuit board and a semiconductor package. Furthermore, the embodiment can allow semiconductor devices to be more stably disposed, thereby allowing the semiconductor devices to operate more stably. Accordingly, the embodiment can improve product reliability. Furthermore, the embodiment can allow products such as servers to which the semiconductor package is applied to operate more stably.

[0029] In addition, the upper surface of the first protective member may have a step. The first protective member may include a first portion having a first thickness and a second portion having a second thickness smaller than the first thickness. In this case, the first portion of the first protective member may be disposed closer to the outer surface of the circuit board than the second portion of the first protective member, and may be provided to surround the second portion along the circumferential direction of the second portion. In this case, the first portion of the first protective member may have a function of preventing the circuit board from being bent in a specific direction. Therefore, the embodiment may further improve the physical reliability and / or electrical reliability of the circuit board.

[0030] In addition, the horizontal width of the first portion of the first protective member may be different along the circumferential direction of the second portion. For example, the horizontal width of the first portion of the first protective member on one side of the second portion of the first protective member may be different from the horizontal width of the first portion of the first protective member on the other side of the second portion of the first protective member. In particular, the embodiment may make the horizontal width of the first portion of the first protective member different along the circumferential direction of the second portion of the first protective member in consideration of the direction in which the circuit board is bent. Therefore, the embodiment can further prevent the circuit board from being bent.

[0031] At this time, a first bonding portion may be arranged in a gap area between the first protective member and the second protective member. At this time, a vertical thickness of the first bonding portion and / or a height of an upper surface of the first bonding portion may be different from a vertical thickness of the first part of the first protective member and / or a height of an upper surface of the first part of the first protective member. Specifically, a vertical thickness of the first bonding portion may be greater than a vertical thickness of the first part of the first protective member. Alternatively, a height of an upper surface of the first bonding portion may be positioned higher than an upper surface of the first part of the first protective member based on an upper surface of the build-up structure. For example, the first bonding portion may include an overlapping portion that overlaps the first protective member in a horizontal direction, and a non-overlapping portion that is positioned on the overlapping portion and does not overlap the first protective member in a horizontal direction.

[0032] In addition, the upper surface of the first bonding portion is positioned higher than the upper surface of the first part of the first protective member, thereby solving a reliability problem in which the semiconductor element is not stably positioned by the first part of the first protective member during the process of mounting the semiconductor element. For example, if the upper surface of the first bonding portion is positioned lower than the upper surface of the first part of the first protective member, the position of the semiconductor element may not be easily controlled by the first part of the first protective member during the process of mounting the semiconductor element.

[0033] In addition, the embodiment can prevent the stress described above from being transmitted to the contact portion between the first bonding portion and the terminal of the semiconductor element by positioning the upper surface of the first bonding portion higher than the first portion of the first protective member with respect to the upper surface of the build-up structure. For example, the stress described above can act in the horizontal direction along the first protective member. At this time, the embodiment can prevent the stress from being transmitted to the contact portion between the first bonding portion and the terminal of the semiconductor element or reduce the intensity of the stress by positioning the upper surface of the first bonding portion higher than the upper surface of the first portion of the first protective member. Accordingly, the embodiment can prevent cracks from occurring in the bonding member (e.g., solder) positioned between the first bonding portion and the terminal of the semiconductor element. Through this, the embodiment can improve the physical reliability and / or electrical reliability of the circuit board and the semiconductor package. Furthermore, the embodiment can allow the semiconductor element to be positioned more stably, thereby allowing the semiconductor element to operate more stably. Therefore, the embodiment can improve product reliability. Furthermore, the embodiment can enable products such as servers to which semiconductor packages are applied to operate more stably.

[0034] Additionally, the first bonding portion and the second bonding portion may have different thicknesses and / or heights. Here, the height may refer to the height of the upper surface of the first bonding portion and the height of the upper surface of the second bonding portion based on the upper surface of the build-up structure.

[0035] For example, the vertical thickness of the first bonding portion may be different from the vertical thickness of the second bonding portion. Alternatively, the height of the first bonding portion may be different from the height of the second bonding portion. The vertical thickness of the first bonding portion may be greater than the vertical thickness of the second bonding portion. Additionally, the upper surface of the first bonding portion may be positioned higher than the upper surface of the second bonding portion with respect to the upper surface of the build-up structure.

[0036] At this time, terminals of the same semiconductor element may be connected on the first bonding portion and the second bonding portion in one embodiment. In this case, the first bonding portion can easily control the height at which the above-described semiconductor element is arranged. For example, the arrangement position of the semiconductor element can be controlled based on the height of the upper surface of the first bonding portion, thereby allowing the semiconductor element to be arranged more stably on the circuit board. Therefore, the embodiment can easily control the arrangement position of the semiconductor element by using the first bonding portion having a relatively large thickness and / or height. Furthermore, the embodiment can easily electrically couple the semiconductor element on the second bonding portion while controlling the arrangement position of the semiconductor element by using the first bonding portion. Through this, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board and the semiconductor package.

[0037] In addition, in another embodiment, terminals of different semiconductor elements may be connected to the first bonding portion and the second bonding portion. For example, the first bonding portion may be an electrode to which the terminal of the first semiconductor element is connected, and the second bonding portion may be an electrode to which the terminal of a second semiconductor element different from the first semiconductor element is connected. In this case, the first semiconductor element may be positioned on the second semiconductor element and mounted on the first bonding portion. Therefore, the embodiment can easily mount a plurality of semiconductor elements that are stacked vertically on a circuit board.

[0038] Figure 1 is a cross-sectional view illustrating a circuit board according to the first embodiment.

[0039] Figures 2 and 3 are top views of the circuit board of Figure 1.

[0040] Figures 4a and 4b are enlarged cross-sectional views of a region (R1) of Figure 1.

[0041] Fig. 5 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0042] Fig. 6 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0043] Fig. 7 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0044] Fig. 8 is a cross-sectional view illustrating a circuit board according to the second embodiment.

[0045] Fig. 9 is a cross-sectional view illustrating a circuit board according to the third embodiment.

[0046] Fig. 10 is a cross-sectional view illustrating a circuit board according to the fourth embodiment.

[0047] Fig. 11 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0048] Fig. 12 is a cross-sectional view illustrating a circuit board according to the fifth embodiment.

[0049] Fig. 13 is a cross-sectional view illustrating a circuit board according to the sixth embodiment.

[0050] Fig. 14 is a cross-sectional view showing a semiconductor package according to the fifth embodiment.

[0051] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0052] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0053] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0054] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0055] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0056] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0057] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0058] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0059]

[0060] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0061]

[0062] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0063] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor element, a bonding member for electrically connecting the semiconductor element and the circuit board, a resin portion that fills the space between the semiconductor element and the circuit board, and a molding portion that entirely encloses the semiconductor element.

[0064] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0065] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0066]

[0067] FIG. 1 is a cross-sectional view showing a circuit board according to a first embodiment, FIG. 2 and FIG. 3 are top views of the circuit board of FIG. 1, FIG. 4a and FIG. 4b are enlarged cross-sectional views of a region (R1) of FIG. 1, FIG. 5 is a cross-sectional view showing a semiconductor package according to the first embodiment, FIG. 6 is a cross-sectional view showing a semiconductor package according to the second embodiment, FIG. 7 is a cross-sectional view showing a semiconductor package according to the third embodiment, FIG. 8 is a cross-sectional view showing a circuit board according to the second embodiment, FIG. 9 is a cross-sectional view showing a circuit board according to the third embodiment, FIG. 10 is a cross-sectional view showing a circuit board according to the fourth embodiment, FIG. 11 is a cross-sectional view showing a semiconductor package according to the fourth embodiment, FIG. 12 is a cross-sectional view showing a circuit board according to the fifth embodiment, FIG. 13 is a cross-sectional view showing a circuit board according to the sixth embodiment, and FIG. 14 is a cross-sectional view showing a circuit board according to the fifth embodiment. This is a cross-sectional view showing the semiconductor package.

[0068] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1 to 13.

[0069] Referring to FIGS. 1 and 2, the circuit board (100) includes a build-up structure (105), a protective layer (140, 150), and a bonding portion (160).

[0070] The build-up structure (105) includes a plurality of insulating layers, circuit layers, and via electrodes stacked along the vertical direction.

[0071] The build-up structure (105) includes a core layer (110), a first build-up layer (120), and a second build-up layer (130). The core layer (110) may be arranged on the inner side of the build-up structure (105) to serve as a core of the circuit board (100). The first build-up layer (120) may be arranged on one surface of the core layer (110). In addition, the second build-up layer (130) may be arranged on the other surface of the core layer (110).

[0072] Here, the meaning of being arranged on one side and the other side should not be understood as being limited to a configuration that is in direct contact with the one side and the other side, but should also be understood as having other configurations between the one side and the first build-up layer (120) and between the other side and the second build-up layer (130).

[0073] The core layer (110) may include a core insulating layer (111). The core insulating layer (111) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has the function of improving the rigidity of the circuit board (100).

[0074] As the number of terminals of semiconductor devices arranged on a recent circuit board (100) increases, wiring becomes more complex, and accordingly, the thickness of the first and second build-up layers (120, 130) is increasing. Accordingly, the core insulation layer (111) of the present embodiment may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board (100) and prevent excessive signal loss.

[0075] A via hole penetrating one surface and the other surface may be formed in the core insulating layer (111). The via hole in the core insulating layer (111) may be formed using a mechanical drilling process or a CO2 laser, etc. When the via hole in the core insulating layer (111) is formed using a mechanical drill, the slope of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core insulating layer (111), and when the via hole in the core insulating layer (111) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions that are alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the core insulating layer (111), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the core insulating layer (111). The concave and convex portions may be alternately provided along the vertical direction of the inner wall forming the via hole of the core insulating layer (111). Here, being alternately provided may mean that the convex portion is provided between a plurality of concave portions, and that the concave portion is provided between a plurality of convex portions.

[0076] At this time, in the case of a via hole formed using a mechanical drilling process, the path for transmitting an electrical signal may be shortened, which may be advantageous for electrical characteristics, but the process cost may increase. In addition, when a concave portion and a convex portion are formed on the inner wall of the via hole using a CO2 laser, the thickness of the core via electrode (114) provided on the inner wall of the via hole can be thickened in a subsequent process. Therefore, it can have the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the core layer (110) can be freely selectively used depending on the application field of the semiconductor package.

[0077] The core layer (110) may include a core via electrode (114) disposed within a via hole of the core insulating layer (111). The core via electrode (114) functions to electrically connect the first build-up layer (120) and the second build-up layer (130). Preferably, the core via electrode (114) may electrically connect a first core circuit layer (112) disposed on one surface of the core insulating layer (111) and a second core circuit layer (113) disposed on the other surface of the core insulating layer (111).

[0078] It is desirable that the core via electrode (114) densely fill the via hole for the function of resistance or heat dissipation. However, when the thickness of the core insulating layer (111) becomes thick as described above, it may become difficult for the core via electrode (114) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core insulating layer (111) as described above according to the plating process, a void may occur inside the core via electrode (114). The void expands due to heat generated during the operation of the semiconductor package, which becomes a factor that lowers the mechanical reliability of the circuit board. Therefore, a core via electrode (114) having a predetermined thickness is arranged on the inner wall of the via hole of the core insulating layer (111). The thickness of the core via electrode (114) refers to the thickness in the horizontal direction perpendicular to the vertical direction in which the first build-up layer (120), the core insulating layer (111), and the second build-up layer (130) are laminated.

[0079] The thickness of the core via electrode (114) may be arranged to have a thickness of 5 μm to 20 μm to prevent a voltage drop that occurs as the thickness of the core insulating layer (111) increases and to prevent the occurrence of voids. It is difficult to densely fill the inside of the core via electrode (114) with metal through a process such as plating, resulting in the creation of empty spaces. The empty spaces may cause a problem in that they make it difficult to evenly arrange the first build-up layer (120) when stacking the first build-up layer (120).

[0080] The core layer (110) may include an insulating member (143) disposed on the inner side of the core via electrode (114). The insulating member (143) is disposed on the inner side of the core layer (110) to ensure the flatness of the core layer (110). For example, the insulating member (143) may be disposed in a via hole of the core insulating layer (111), and the core via electrode (114) may surround a side of the insulating member (143) and be disposed between the inner wall of the via hole and the outer surface of the insulating member (143).

[0081] The upper surface of the insulating member (143) may be on the same plane as the upper surface of the core insulating layer (111), or may be arranged closer to the first build-up layer (120) in the vertical direction than the upper surface of the core insulating layer (111). The lower surface of the insulating member (143) may be on the same plane as the lower surface of the core insulating layer (111), or may be arranged closer to the second build-up layer (130) in the vertical direction than the lower surface of the core insulating layer (111). This can be freely designed to solve the flatness when laminating the first build-up layer (120) and the second build-up layer (130), or to secure the flatness of the first core circuit layer (112) and the second core circuit layer (113).

[0082] The core layer (110) may include a first core circuit layer (112) arranged on one surface of the core insulation layer (111) and a second core circuit layer (113) arranged on the other surface of the core insulation layer (111).

[0083] The first core circuit layer (112) and the second core circuit layer (113) can be formed simultaneously with the core via electrode (114) in the process of forming the core via electrode (114) in the core insulating layer (111) of the core layer (110). For example, after forming a via hole penetrating the core insulating layer (111), the first core circuit layer (112) and the second core circuit layer (113) can be arranged together with the core via electrode (114) filling a portion of the via hole.

[0084] The first core circuit layer (112) may be arranged on one surface of the core insulating layer (111). In this case, a part of the first core circuit layer (112) may be arranged to cover the above-described insulating member (115). That is, the lower surface of the first core circuit layer (112) may include a first portion in contact with the upper surface of the core via electrode (114), a second portion in contact with the upper surface of the insulating member (115), and a third portion in contact with the upper surface of the core layer (110). At this time, the lower surface of the first core circuit layer (112) may have a step difference depending on the arrangement structure of the insulating member (115).

[0085] The second core circuit layer (113) may be arranged on the other surface of the core insulating layer (111). In this case, a portion of the second core circuit layer (113) may be arranged to cover the above-described insulating member (115). That is, the upper surface of the second core circuit layer (113) may include a first portion in contact with the lower surface of the core via electrode (114), a second portion in contact with the lower surface of the insulating member (115), and a third portion in contact with the lower surface of the core layer (110).

[0086] A first build-up layer (120) is arranged on one surface of the core layer (110). The first build-up layer (120) includes a plurality of insulating layers (121-1, 121-2, 121-3), a plurality of circuit layers (122-1, 122-2, 122-3), and a plurality of via electrodes (123-1, 123-2, 123-3).

[0087] The plurality of circuit layers (122-1, 122-2, 122-3) of the first build-up layer (120) may include a first circuit layer (121-1) that is the farthest from the core layer (110) in the vertical direction, a second circuit layer (121-2) that is closer to the core layer (110) in the vertical direction than the first circuit layer (121-1), and a third circuit layer (121-3) that is closer to the core layer (110) in the vertical direction than the second circuit layer (121-2).

[0088] The first to third circuit layers (122-1, 122-2, 122-3) can function to electrically connect with semiconductor elements placed on a circuit board (100). Each of the first to third circuit layers (122-1, 122-2, 122-3) can be freely designed taking impedance into consideration.

[0089] The first circuit layer (121-1) may include a plurality of wiring portions connected to a bonding portion (160) to be described later. For example, the first circuit layer (121-1) may include a first wiring portion (122-1a) and a second wiring portion (122-1b).

[0090] The first wiring section (122-1a) may be placed in an open area (SA) of the first protective layer (140) to be described later. Here, the open area (SA) may refer to a separation area of ​​the first protective layer (140), which will be described in detail below.

[0091] The first wiring portion (122-1a) may not be in contact with the first protective layer (140). For example, the first wiring portion (122-1a) may not overlap the first protective layer (140) in the vertical direction. The first wiring portion (122-1a) may be arranged closer to the side of the build-up structure (105) in the horizontal direction than the second wiring portion (122-1b).

[0092] The second wiring portion (122-1b) may be spaced apart from the open area (SA) of the first protective layer (140). For example, at least a portion of the second wiring portion (122-1b) may be in contact with the first protective layer (140). For example, at least a portion of the upper surface of the second wiring portion (122-1b) may be covered with the first protective layer (140).

[0093] The second wiring section (122-1b) may be located further from the outer surface of the first protective layer (140) than the first wiring section (122-1a).

[0094] For example, a plurality of second wiring sections (122-1b) may be provided, and a plurality of first wiring sections (122-1a) may be provided along the perimeter of an area in which a plurality of second wiring sections (122-1b) are arranged.

[0095] The via electrodes (123-1, 123-2, 123-3) of the first build-up layer (120) may be provided to connect the first to third circuit layers (122-1, 122-2, 122-3), respectively.

[0096] For example, the first via electrode (123-1) is disposed between the first circuit layer (122-1) and the second circuit layer (122-2), the second via electrode (123-2) is disposed between the second circuit layer (122-2) and the third circuit layer (122-3), and the third via electrode (123-3) is disposed between the third circuit layer (123-3) and the first core circuit layer (112). As a result, the first to third circuit layers (122-1, 122-2, 122-3) and the first core circuit layer (112) are electrically connected.

[0097] The first to third via electrodes (123-1, 123-2, 123-3) can be formed simultaneously in the process of arranging the first to third circuit layers (122-1, 122-2, 122-3). For example, in the process of arranging the third circuit layer (123-3) on the first core circuit layer (112), a through hole can be formed in the third insulating layer (121-3) to expose a portion of the first core circuit layer (112). Through this, the third circuit layer (122-3) can be arranged together with the third via electrode (123-3) filling the through hole of the third insulating layer (121-3). Therefore, the third via electrode (123-3) can be distinguished as a protrusion of the third circuit layer (122-3). Likewise, each of the first and second via electrodes (123-1, 123-2) is separated by a protrusion of the first and second circuit layers (122-1, 122-2) and can be connected to another circuit layer disposed below each circuit layer.

[0098] The plurality of insulating layers (121-1, 121-2, 121-3) of the first build-up layer (120) may include a first insulating layer (121-1) that is furthest from the core layer (110) in a direction perpendicular to the core layer (110), a second insulating layer (121-2) that is closer to the core layer (110) in a direction perpendicular to the core layer (110) than the first insulating layer (121-1), and a third insulating layer (121-3) that is closer to the core layer (110) in a direction perpendicular to the core layer (110) than the second insulating layer (121-2).

[0099] The first to third insulating layers (121-1, 121-2, 121-3) are arranged to vertically insulate the first to third circuit layers (122-1, 122-2, 122-3) described above. For example, the first to third insulating layers (121-1, 121-2, 121-3) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0100] A second build-up layer (130) is arranged on the other side of the core layer (110). The second build-up layer (130) includes a plurality of insulating layers (131-1, 131-2, 131-3), a plurality of circuit layers (132-1, 132-2, 133-3), and a plurality of via electrodes (133-1, 133-2, 133-3).

[0101] The plurality of circuit layers (132-1, 132-2, 133-3) of the second build-up layer (130) may include a fourth circuit layer (132-1) that is most adjacent to the core layer (110) in the vertical direction, a fifth circuit layer (132-2) arranged under the fourth circuit layer (132-1), and a sixth circuit layer (132-3) arranged under the fifth circuit layer (132-2). The fourth to sixth circuit layers (132-1, 132-2, 133-3) may function to electrically connect a main board (not shown) of an electronic device and a semiconductor element arranged on a circuit board (100). Each of the fourth to sixth circuit layers (132-1, 132-2, 133-3) may be freely designed in consideration of impedance.

[0102] Additionally, via electrodes (133-1, 133-2, 133-3) may be arranged to connect each of the fourth to sixth circuit layers (132-1, 132-2, 133-3).

[0103] The fourth via electrode (133-1) is disposed between the second core circuit layer (113) and the fourth circuit layer (132-1), the fifth via electrode (133-2) is disposed between the fourth circuit layer (132-1) and the fifth circuit layer (132-2), and the sixth via electrode (133-3) is disposed between the fifth circuit layer (132-2) and the sixth circuit layer (132-3). As a result, the second core circuit layer (113) and the fourth to sixth circuit layers (132-1, 132-2, 133-3) are electrically connected.

[0104] As described above with respect to the first to third via electrodes (123-1, 123-2, 123-3) of the first build-up layer (120), the arrangement of the fourth to sixth via electrodes (133-1, 133-2, 133-3) can also be performed simultaneously with the process of arranging the fourth to sixth circuit layers (132-1, 132-2, 132-3). Therefore, as described above, the fourth via electrode (133-1) can be distinguished by the protrusion of the fourth circuit layer (132-1).

[0105] However, since the fourth to sixth circuit layers (132-1, 132-2, 133-3) are laminated in a different direction from the first build-up layer (120), the inclination direction of each via electrode (123-1, 123-2, 123-3) of the first build-up layer (120) may have a direction opposite to the inclination direction of each via electrode (133-1, 133-2, 133-3) of the second build-up layer (130). For example, each via electrode (123-1, 123-2, 123-3) of the first build-up layer (120) may have a slope that becomes narrower as it approaches the core layer (110), and each via electrode (133-1, 133-2, 133-3) of the second build-up layer (130) may also have a slope that becomes narrower as it approaches the core layer (110). For example, the slope of each via electrode (123-1, 123-2, 123-3) of the first build-up layer (120) may be symmetrical with respect to the slope of each via electrode (133-1, 133-2, 133-3) of the second build-up layer (130) with respect to the core layer (110).

[0106] The plurality of insulating layers (131-1, 131-2, 131-3) of the second build-up layer (130) may include a fourth insulating layer (131-1) that is most adjacent to the core layer (110) in the vertical direction, a fifth insulating layer (131-2) arranged under the fourth insulating layer (131-1), and a sixth insulating layer (131-3) arranged under the fifth insulating layer (131-2). The fourth to sixth insulating layers (131-1, 131-2, 131-3) are arranged to insulate the fourth to sixth circuit layers (132-1, 132-2, 133-3) in the vertical direction. In addition, as an example, the fourth to sixth insulating layers (131-1, 131-2, 131-3) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Imageable Dielectric, PID) for forming a fine pattern may be used.

[0107] A first protective layer (140) is disposed on the first build-up layer (120). The first protective layer (140) can protect the upper surface of the build-up structure (105) from external moisture or contaminants. Preferably, the first protective layer (140) can protect the first circuit layer (122-1). In addition, when a semiconductor element is bonded to a circuit board (100) using a material such as solder, the first protective layer (140) functions to prevent short circuits between solders due to low wettability with the solder. The first protective layer (140) can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0108] The first protective layer (140) may include a first protective member (141) and a second protective member (142).

[0109] The first protective member (141) may include a through hole (TH1). The through hole (TH1) may be provided to penetrate the upper and lower surfaces of the first protective member (141). The first protective member (141) may include an outer surface. The inner wall of the through hole (TH1) may penetrate the upper and lower surfaces of the first protective member (141) in a region spaced apart from the outer surface of the first protective member (141). The first protective member (141) may not overlap the first wiring portion (122-1a) of the first circuit layer (116) in a vertical direction.

[0110] The second protective member (142) may be disposed within the through hole (TH1) of the first protective member (141). Specifically, the second protective member (142) may be disposed on the inner side of the through hole (TH1) of the first protective member (141). At this time, the second protective member (142) may be spaced apart from the first protective member (141) in the horizontal direction. For example, the second protective member (142) may not be in contact with the first protective member (141).

[0111] For example, the first protective layer (140) may be provided with an open area (SA) or a separation area (SA) between the first protective member (141) and the second protective member (142). The open area (SA) or the separation area (SA) may refer to an area between the inner surface of the through hole (TH1) of the first protective member (141) and the outer surface of the second protective member (142). In addition, the first wiring portion (122-1a) of the first circuit layer (116) described above may be arranged in the open area (SA) or the separation area (SA) between the first protective member (141) and the second protective member (142).

[0112] For example, the open area (SA) or the separation area (SA) may be provided in a closed loop shape between the inner surface of the first protective member (141) and the outer surface of the second protective member (142). That is, the open area (SA) or the separation area (SA) may be provided along the circumferential direction of the outer surface of the second protective member (142).

[0113] The embodiment allows the first protective member (141) and the second protective member (142) to be spaced apart from each other in the horizontal direction. Through this, the embodiment can further improve the physical reliability and / or electrical reliability of the circuit board.

[0114] For example, during the operating environment of a circuit board and a semiconductor package including the same, stress due to thermal expansion or thermal contraction caused by a heat cycle may be applied. In addition, the above-described stress may be applied to the first protective layer (140). At this time, a first wiring portion (122-1a), a second wiring portion (122-1b), and a bonding portion (160) are arranged in an area overlapping the first protective layer (140) in a horizontal direction. The above-described first wiring portion (122-1a), the second wiring portion (122-1b), and the bonding portion (160) are electrodes connected to terminals of semiconductor elements. At this time, the above-described stress may be applied to portions in which each of the first wiring portion (122-1a), the second wiring portion (122-1b), and the bonding portion (160) is in contact with the terminals of the semiconductor elements along the first protective layer (140), and cracks may occur accordingly. In this case, the electrical reliability between the circuit board and the semiconductor element may deteriorate, and the semiconductor element may not operate stably. Furthermore, a physical reliability issue may occur in which the first protective layer (140) is peeled off from the build-up structure (105) due to the stress described above.

[0115] At this time, the embodiment is configured such that the first protective layer (140) includes a first protective member (141) and a second protective member (142) that are spaced apart from each other in the horizontal direction. Through this, the embodiment can prevent the stress applied to the first protective member (141) from being transmitted to the second protective member (142). For example, the embodiment can allow the above-described stress to be absorbed or reduced in the open area (SA) or the spaced area (SA) between the first protective member (141) and the second protective member (142). Therefore, the embodiment can improve the physical reliability and / or electrical reliability of the circuit board and the semiconductor package. Furthermore, the embodiment can allow the semiconductor device to be positioned more stably, thereby allowing the semiconductor device to operate more stably. Therefore, the embodiment can improve product reliability. Furthermore, the embodiment can allow a product, such as a server, to which the semiconductor package is applied to operate more stably.

[0116] The first protective member (141) may have a step. Specifically, the upper surface of the first protective member (141) may have a step. Here, having a step may mean that the upper surfaces of the first protective members (141) are connected to each other and have different heights.

[0117] For example, the first protective member (141) may be divided into a first portion (141-1) and a second portion (141-2) along the horizontal direction. In addition, the first portion (141-1) and the second portion (141-2) of the first protective member (141) may have different thicknesses and / or heights.

[0118] The first portion (141-1) of the first protective member (141) may be positioned further from the through hole (TH1) than the second portion (141-2). For example, the first portion (141-1) of the first protective member (141) may be closer to the outer surface of the first protective layer (140). For example, the first protective member (141) may have an outer surface. In addition, the upper surface of the first portion (141-1) of the first protective member (141) may be connected to the outer surface of the first protective member (141). In addition, the upper surface of the second portion (141-2) of the first protective member (141) may be connected to the inner surface of the through hole (TH1) while having a step difference from the upper surface of the first portion (141-1) of the first protective member (141).

[0119] Accordingly, the embodiment may provide a first portion (141-1) of a first protective member (141) having a relatively large thickness in an area adjacent to the outer surface of the first protective layer (140). Through this, the embodiment may improve the rigidity of the circuit board. For example, the first portion (141-1) of the first protective member (141) may function to prevent the circuit board from bending in a specific direction. Therefore, the embodiment may further improve the physical reliability and / or electrical reliability of the circuit board.

[0120] At this time, the first part (141-1) of the first protective member (141) may be provided along the circumferential direction of the second part (141-2) of the first protective member (141). Specifically, the second part (141-2) of the first protective member (141) may be provided along the circumferential direction of the inner surface of the through hole (TH1) while having a relatively small height and / or thickness, and the first part (141-1) of the first protective member (141) may be provided along the circumferential direction of the second part (141-2) while having a relatively large height and / or thickness. Through this, the embodiment can maximize the effect of the first protective member (141) exhibited by the first part (141-1).

[0121] In addition, according to the embodiment of FIG. 2, the horizontal width of the first part (141-1) of the first protective member (141) may be uniform along the circumferential direction of the second part (141-2). For example, the horizontal width of the first part (141-1) of the first protective member (141) on one side of the second part (141-2) of the first protective member (141) may be the same as the horizontal width of the first part (141-1) of the first protective member (141) on the other side of the second part (141-2) of the first protective member (141).

[0122] In contrast, the horizontal width of the first portion (141-1) of the first protective member (141) according to the embodiment of FIG. 3 may vary along the circumferential direction of the second portion (141-2). For example, the horizontal width of the first portion (141-1) of the first protective member (141) on one side of the second portion (141-2) of the first protective member (141) may vary from the horizontal width of the first portion (141-1) of the first protective member (141) on the other side of the second portion (141-2) of the first protective member (141). In particular, the embodiment may vary the horizontal width of the first portion (141-1) of the first protective member (141) along the circumferential direction of the second portion (141-2) of the first protective member (141) in consideration of the direction in which the circuit board is bent. Therefore, the embodiment can further prevent the circuit board from bending.

[0123] At this time, the upper surface of the second part (141-2) of the first protective member (141) may be positioned on the same plane as the upper surface of the second protective member (142). For example, the vertical thickness of the second part (141-2) of the first protective member (141) may be the same as the vertical thickness of the second protective member (142). Through this, the semiconductor element can be stably placed in the upper region of the second part (141-2) of the first protective member (141) and the upper region of the second part (141-2).

[0124] In addition, a second protective layer (150) is disposed under the second build-up layer (130). The second protective layer (150) can protect the sixth circuit layer (132-3) from external moisture or contaminants. In addition, when a semiconductor element and / or an external substrate are bonded under the circuit board (100) with a material such as solder, the second protective layer (150) functions to prevent short circuits between solders due to low wettability with the solder. A photocurable insulating material can be used as the second protective layer (150), and for example, a solder resist can be used.

[0125] In addition, each of the via electrodes (123-1, 123-2, 123-3, 133-1, 133-2, 133-3) of the first build-up layer (120) and the second build-up layer (130) may have a structure in which at least a portion thereof overlaps with each other along the vertical direction. Through this, problems of voltage drop and / or signal loss can be solved, and the degree of freedom for wiring design can be increased.

[0126] A bonding portion (160) is arranged on the first build-up layer (120). The bonding portion (160) may be arranged on the first circuit layer (116) exposed from the first protective layer (140).

[0127] At this time, as the terminal density of the semiconductor element increases, a solder short circuit problem may occur between adjacent wiring portions with the conventional solder bonding. Therefore, in order to reduce the amount of solder used as the terminal density of the semiconductor element increases, the semiconductor element and the circuit board may be bonded to each other through a thermal compression bonding method. When thermal compression bonding is used, the circuit board may include a bonding portion (160) protruding on the first protective layer (140). At this time, the bonding portion (160) may have a protrusion protruding on the first protective layer (140) and a penetration portion that penetrates the first protective layer (140) and makes contact with the wiring portion of the first circuit layer (116).

[0128] For example, the first circuit layer (116) may include a first wiring portion (122-1a) disposed in an open area (SA) or a separation area (SA) between the first protective member (141) and the second protective member (142). In addition, the first circuit layer (116) may include a second wiring portion (122-1b) overlapping the second protective member (142) along the vertical direction. The bonding portion (160) may be disposed on the first wiring portion (122-1a) and the second wiring portion (122-1b). The bonding portion (160) may include a first bonding portion (161) disposed on the first wiring portion (122-1a) and a second bonding portion (162) disposed on the second wiring portion (122-1b).

[0129] At this time, the first bonding portion (161) and the second bonding portion (162) according to the embodiment of Fig. 1 may have different thicknesses and / or heights. Here, the height may refer to the height of the upper surface of the first bonding portion (161) and the height of the upper surface of the second bonding portion (162) based on the upper surface of the build-up structure (105).

[0130] For example, the vertical thickness of the first bonding portion (161) may be different from the vertical thickness of the second bonding portion (162). Alternatively, the height of the first bonding portion (161) may be different from the height of the second bonding portion (162). The vertical thickness of the first bonding portion (161) may be greater than the vertical thickness of the second bonding portion (162). In addition, the upper surface of the first bonding portion (161) may be positioned higher than the upper surface of the second bonding portion (162) with respect to the upper surface of the build-up structure (105).

[0131] At this time, terminals of the same semiconductor element may be connected on the first bonding portion (161) and the second bonding portion (162) in one embodiment. In this case, the first bonding portion (161) can easily control the height at which the above-described semiconductor element is arranged. For example, the arrangement position of the semiconductor element can be controlled based on the height of the upper surface of the first bonding portion (161), thereby allowing the semiconductor element to be arranged more stably on the circuit board. Therefore, the embodiment can easily control the arrangement position of the semiconductor element by using the first bonding portion (161) having a relatively large thickness and / or height. Furthermore, the embodiment can easily electrically couple the semiconductor element on the second bonding portion (162) in a state where the arrangement position of the semiconductor element is controlled by using the first bonding portion (161). Through this, the embodiment can further improve the electrical reliability and / or physical reliability of the circuit board and the semiconductor package.

[0132] In addition, in another embodiment, terminals of different semiconductor elements may be connected to the first bonding portion (161) and the second bonding portion (162). For example, the first bonding portion (161) may be an electrode to which the terminal of the first semiconductor element is connected, and the second bonding portion (162) may be an electrode to which the terminal of the second semiconductor element different from the first semiconductor element is connected. In this case, the first semiconductor element may be positioned on the second semiconductor element and mounted on the first bonding portion (161). Therefore, the embodiment can easily mount a plurality of semiconductor elements that are stacked vertically on a circuit board.

[0133] Additionally, the vertical thickness of the first bonding portion (161) and / or the height of the upper surface of the first bonding portion (161) may be different from the vertical thickness of the first part (141-1) of the first protective member (141) and / or the height of the upper surface of the first part (141-1) of the first protective member (141).

[0134] For example, the vertical thickness of the first bonding portion (161) may be greater than the vertical thickness of the first portion (141-1) of the first protective member (141). Alternatively, the height of the upper surface of the first bonding portion (161) may be positioned higher than the upper surface of the first portion (141-1) of the first protective member (141) with respect to the upper surface of the build-up structure (105). For example, the first bonding portion (161) may include an overlapping portion that overlaps the first protective member (141) in the horizontal direction, and a non-overlapping portion that is positioned on the overlapping portion and does not overlap the first protective member (141) in the horizontal direction.

[0135] That is, the embodiment allows the upper surface of the first bonding portion (161) to be positioned higher than the upper surface of the first part (141-1) of the first protection member (141), thereby solving the reliability problem in which the semiconductor element is not stably placed by the first part (141-1) of the first protection member (141) during the process of mounting the semiconductor element. For example, when the upper surface of the first bonding portion (161) is positioned lower than the upper surface of the first part (141-1) of the first protection member (141), the placement position of the semiconductor element may not be easily controlled by the first part (141-1) of the first protection member (141) during the process of mounting the semiconductor element.

[0136] In addition, the embodiment may prevent the stress described above from being transmitted to the contact portion between the first bonding portion (161) and the terminal of the semiconductor element by positioning the upper surface of the first bonding portion (161) higher than the first portion (141-1) of the first protection member (141) with respect to the upper surface of the build-up structure (105). For example, the stress described above may act in a horizontal direction along the first protection member (141). At this time, the embodiment may prevent the stress from being transmitted to the contact portion between the first bonding portion (161) and the terminal of the semiconductor element by positioning the upper surface of the first bonding portion (161) higher than the upper surface of the first portion (141-1) of the first protection member (141). By doing so, the stress may be prevented from being transmitted to the contact portion between the first bonding portion (161) and the terminal of the semiconductor element, or the intensity of the stress may be reduced. Accordingly, the embodiment can prevent cracks from occurring in a bonding member (e.g., solder) disposed between the first bonding portion (161) and the terminal of the semiconductor element. Through this, the embodiment can improve the physical reliability and / or electrical reliability of the circuit board and the semiconductor package. Furthermore, the embodiment can enable the semiconductor element to be disposed more stably, thereby enabling the semiconductor element to operate more stably. Therefore, the embodiment can improve product reliability. Furthermore, the embodiment can enable products such as servers to which the semiconductor package is applied to operate more stably.

[0137] Below, the first protective layer (140) and the bonding portion (160) are described in more detail.

[0138] Referring to FIGS. 4a and 4b, a first protective layer (140) is disposed on the build-up structure (105). The first protective layer (140) includes a first protective member (141) and a second protective member (142).

[0139] The first protective member (141) includes a through hole (TH1). The second protective member (142) is disposed within the through hole (TH1) of the first protective member (141). The first protective member (141) and the second protective member (142) may represent a single protective layer. For example, a through hole corresponding to an open area (SA) or a spaced area (SA) may be formed in the first protective layer (140), thereby forming a structure including the first protective member (141) and the second protective member (142) that are spaced apart from each other.

[0140] The first protective member (141) includes a first portion (141-1) and a second portion (141-2). The first portion (141-1) is a portion located further from the through hole (TH1). The first protective member (141) is a portion located closer to the through hole (TH1) than the first portion (141-1).

[0141] The first part (141-1) and the second part (141-2) of the first protective member (141) have different thicknesses or heights. For example, the thickness or height of the first part (141-1) of the first protective member (141) may be greater than the thickness or height of the second part (141-2) of the first protective member (141).

[0142] At this time, as shown in Fig. 4a, the first protective member (141) may be provided in one layer. Accordingly, a process of thinning the thickness of the area corresponding to the second part (141-2) of the first protective member (141) may be performed so that the first part (141-1) and the second part (141-2) have different thicknesses.

[0143] In addition, as shown in FIG. 4b, the first part (141-1) may be provided in two layers. Accordingly, the second part (141-2) of the first protective member (141) may be provided in one layer. In addition, the first part (141-1) of the first protective member (141) may include a first layer (141-1a) corresponding to the second part (141-2), and a first layer (141-1b) disposed on the first layer (141-1a). For example, the first protective member (141) may additionally laminate a first layer (141-1b) on the first layer (141-1a) of the first part (141-1), so that the first part (141-1) and the second part (141-2) may have different thicknesses.

[0144] A first bonding portion (161) is arranged in the open area (SA) between the first protective member (141) and the second protective member (142). The first bonding portion (161) may not be in contact with the first protective member (141) and the second protective member (142).

[0145] The first bonding portion (161) may be provided to protrude above the first protective member (141) and the second protective member (142). For example, the upper surface of the first bonding portion (161) may be positioned higher than the first portion (141-1) of the first protective member (141) with respect to the upper surface of the build-up structure (105).

[0146] That is, the upper surface of the first part (141-1) of the first protective member (141) and the upper surface of the first bonding part (161) may have a first vertical distance (T1). The first vertical distance (T1) may be smaller than the vertical thickness of the first part (141-1) of the first protective member (141). In addition, the first vertical distance (T1) may be smaller than the vertical thickness of the first bonding part (161). For example, the first vertical distance (T1) may satisfy a range of 5% to 45%, or 7% to 42%, or 10% to 40% of the vertical thickness of the first bonding part (161). Alternatively, if the first vertical distance (T1) is less than 5% of the vertical thickness of the first bonding portion (161), the improvement effect of physical reliability and / or electrical reliability that appears as the upper surface of the first bonding portion (161) is positioned higher than the upper surface of the first portion (141-1) of the first protective member (141) may be insignificant. In addition, if the first vertical distance (T1) exceeds 45% of the vertical thickness of the first bonding portion (161), the size of the circuit board by the first bonding portion (161) and the circuit board including the circuit board in the vertical direction may increase.

[0147] The second bonding portion (162) may be provided to penetrate the first protective layer (140). For example, the second bonding portion (162) may be provided to penetrate the second protective member (142) of the first protective layer (140). In this case, the second bonding portion (162) may include a penetration portion provided to penetrate the second protective member (142), and a protrusion portion on the penetration portion protruding onto the second protective member (142).

[0148] At this time, the vertical thickness or the height of the upper surface of the second bonding portion (162) may be different from the vertical thickness or the height of the upper surface of the first bonding portion (161). For example, the vertical thickness or the height of the upper surface of the second bonding portion (162) may be smaller than the vertical thickness or the height of the upper surface of the first bonding portion (161). For example, the upper surface of the first bonding portion (161) and the upper surface of the second bonding portion (162) may have a height difference corresponding to the second vertical distance (T2). At this time, the second vertical distance (T2) may be greater than the first vertical distance (T1).

[0149] That is, the vertical thickness and / or the height of the upper surface of the first part (141-1) of the first protective member (141) may be greater than the vertical thickness and / or the height of the upper surface of the second bonding part (162). In addition, the vertical thickness and / or the height of the upper surface of the second part (141-2) of the first protective member (141) may be less than the vertical thickness and / or the height of the upper surface of the second bonding part (162). For example, the upper surface of the second bonding part (162) may be located between the upper surface of the first part (141-1) of the first protective member (141) and the upper surface of the second part (141-2).

[0150] The upper surface of the first part (141-1) of the first protective member (141) and the upper surface of the second bonding part (162) may have a height difference corresponding to the third vertical distance (T3).

[0151] At this time, the first vertical distance (T1) may be smaller than the second vertical distance (T2) and larger than the third vertical distance (T3). The second vertical distance (T2) may be larger than the first vertical distance (T1) and the third vertical distance (T3). The third vertical distance (T3) may be smaller than the first vertical distance (T1) and the second vertical distance (T2).

[0152] That is, the embodiment adjusts the vertical thickness and / or height of each of the first part (141-1) of the first protective member (141), the second part (141-2) of the first protective member (141), the first bonding portion (161), and the second bonding portion (162). Through this, the embodiment can efficiently distribute the stress acting on the circuit board and the semiconductor package, thereby improving the physical reliability and / or electrical reliability. Furthermore, the embodiment can prevent stress from being concentrated at the contact portion where the semiconductor element and the first bonding portion (161) and / or the second bonding portion (162) are connected, thereby preventing stress from being generated at the above-described contact portion.

[0153]

[0154] Below, a semiconductor package including the circuit boards of FIGS. 1 to 4 is described.

[0155] According to the embodiment of FIG. 4, a plurality of semiconductor elements may be arranged on a circuit board. For example, a semiconductor package according to the first embodiment may include a first semiconductor element (200) and a second semiconductor element (220). In this case, the first semiconductor element (200) and the second semiconductor element (220) may be arranged to overlap each other in a vertical direction.

[0156] For example, a first semiconductor element (200) may be arranged on a circuit board, and a second semiconductor element (220) may be additionally arranged between the circuit board and the first semiconductor element (200).

[0157] The first semiconductor element (200) may have a terminal (210). In addition, a first bonding portion (240) may be arranged between the terminal (210) of the first semiconductor element (200) and the first bonding portion (161). For example, the first bonding portion (161) may function as a mounting portion for mounting the first semiconductor element (200). At this time, the first bonding portion (240) may be solder, but is not limited thereto.

[0158] The second semiconductor element (220) may have a terminal (230). In addition, a second bonding portion (250) may be arranged between the terminal (210) of the second semiconductor element (220) and the second bonding portion (162). For example, the second bonding portion (162) may function as a mounting portion for mounting the second semiconductor element (220). The second bonding portion (250) may be solder, but is not limited thereto.

[0159] At this time, the area of ​​the first semiconductor element (200) in a planar view may be different from the area of ​​the second semiconductor element (220) in a planar view. For example, the area of ​​the first semiconductor element (200) in a planar view may be larger than the area of ​​the second semiconductor element (220) in a planar view. However, the embodiment is not limited thereto. For example, the terminal (210) of the first semiconductor element (200) and the terminal (230) of the second semiconductor element (220) may not overlap each other along the vertical direction, without reciprocating the areas of the first semiconductor element (200) and the second semiconductor element (220) in a planar view, respectively.

[0160] Accordingly, the embodiment can mount the first semiconductor element (200) on the first bonding portion (161) and mount the second semiconductor element (220) on the second bonding portion (162). Through this, the embodiment can mount the first semiconductor element (200) and the second semiconductor element (220) arranged along the vertical direction, respectively, using the first bonding portion (161) and the second bonding portion (162) having different heights. Through this, the embodiment can reduce the signal transmission length between the first semiconductor element (200) and the second semiconductor element (220). Therefore, the embodiment can improve the communication characteristics between the first semiconductor element (200) and the second semiconductor element (220), thereby enabling the first semiconductor element (200) and the second semiconductor element (220) to operate more stably.

[0161] At this time, the first semiconductor element (200) and the second semiconductor element (220) are illustrated as being arranged to be spaced apart from each other in the vertical direction, but this is not limited thereto. For example, the first semiconductor element (200) and the second semiconductor element (220) may be in contact with each other. For example, the lower surface of the first semiconductor element (200) and the upper surface of the second semiconductor element (220) may be in contact with each other.

[0162] The buried insulating layer (300) can be disposed to bury the first semiconductor element (200) and the second semiconductor element (220). For example, the buried insulating layer (300) can be a molding layer that molds the first semiconductor element (200) and the second semiconductor element (220).

[0163] At this time, the embedded insulating layer (300) can be in contact with the first portion (141-1) and the second portion (141-2) of the first protective member (141). For example, the embedded insulating layer (300) can be in contact with the upper surfaces of the first portion (141-1) and the second portion (141-2) of the first protective member (141), respectively. Through this, the lower surface of the embedded insulating layer (300) can have a step. Therefore, the embodiment can increase the contact area between the embedded insulating layer (300) and the first protective layer (140), thereby further improving the adhesion therebetween.

[0164]

[0165] Additionally, according to the embodiment of FIG. 6, one semiconductor element (200) may be placed on the circuit board. For example, the terminal (210) of the semiconductor element (200) may be connected to each of the first bonding portion (161) and the second bonding portion (162).

[0166] For example, a semiconductor device (200) may have a plurality of terminals (210), some of the plurality of terminals may be connected to the first bonding portion (161), and the remaining some may be connected to the second bonding portion (162).

[0167] That is, a first bonding portion (240) may be arranged between the terminal (210) of the semiconductor element (200) and the first bonding portion (161), and a second bonding portion (250) may be arranged between the terminal (210) of the semiconductor element (200) and the second bonding portion (162). At this time, the vertical thickness of the first bonding portion (240) and the vertical thickness of the second bonding portion (250) may be different from each other. For example, the vertical thickness of the first bonding portion (240) may be greater than the vertical thickness of the second bonding portion (250). That is, in the embodiment, the semiconductor element (200) can be mounted using the first bonding portion (161) in a state where the placement position of the semiconductor element (200) is determined using the first bonding portion (161) and the second bonding portion (250) on the second bonding portion (162).

[0168]

[0169] Additionally, according to the embodiment of FIG. 7, a first semiconductor element (200) and a second semiconductor element (220) may be arranged on a circuit board. At this time, the first semiconductor element (200) and the second semiconductor element (220) may be electrically coupled on the circuit board in different ways.

[0170] For example, a second bonding portion (250) may be placed on the second bonding portion (162). Then, a second semiconductor element (220) may be mounted on the second bonding portion (250).

[0171] In addition, a first semiconductor element (200) may be attached to a second semiconductor element (220). At this time, the first semiconductor element (200) has a terminal (210). At this time, the first semiconductor element (200) may be attached to the second semiconductor element (220) in a state where the terminal (210) is positioned on the upper surface.

[0172] In addition, the first bonding portion (161) and the terminal (210) of the first semiconductor element (200) can be electrically connected to each other through the first coupling portion (240). At this time, the first coupling portion (240) can be a wire. That is, the first semiconductor element (200) can be electrically coupled to the first bonding portion (161) through a wire bonding method. Alternatively, the second semiconductor element (220) can be electrically coupled to the second bonding portion (162) through a flip-chip bonding method.

[0173] In this case, the embodiment has a thickness or height greater than that of the second bonding portion (162), thereby reducing the length of the wire through the first joining portion (240). Accordingly, the embodiment can further improve the electrical bonding reliability between the first bonding portion (161) and the first semiconductor element (200).

[0174]

[0175] Below, various embodiments of the circuit board are described.

[0176] For the circuit boards below, structures that are substantially the same as those in FIGS. 1 to 7 are given the same reference numerals and detailed descriptions thereof are omitted.

[0177] According to the embodiment of Fig. 8, a first protective layer (140) is arranged on the build-up structure (105). The first protective layer (140) includes a first protective member (141) and a second protective member (142).

[0178] The first protective member (141) includes a through hole (TH1). The second protective member (142) is disposed within the through hole (TH1) of the first protective member (141). The first protective member (141) and the second protective member (142) may represent a single protective layer. For example, a through hole corresponding to an open area (SA) or a spaced area (SA) may be formed in the first protective layer (140), thereby forming a structure including the first protective member (141) and the second protective member (142) that are spaced apart from each other.

[0179] The first protective member (141) includes a first portion (141-1) and a second portion (141-2). The first portion (141-1) is a portion located further from the through hole (TH1). The first protective member (141) is a portion located closer to the through hole (TH1) than the first portion (141-1).

[0180] The first part (141-1) and the second part (141-2) of the first protective member (141) have different thicknesses or heights. For example, the thickness or height of the first part (141-1) of the first protective member (141) may be greater than the thickness or height of the second part (141-2) of the first protective member (141).

[0181] A first bonding portion (161) is arranged in the open area (SA) between the first protective member (141) and the second protective member (142). The first bonding portion (161) may not be in contact with the first protective member (141) and the second protective member (142).

[0182] The first bonding portion (161) may be provided to protrude above the first protective member (141) and the second protective member (142). For example, the upper surface of the first bonding portion (161) may be positioned higher than the first portion (141-1) of the first protective member (141) with respect to the upper surface of the build-up structure (105).

[0183] Additionally, the second bonding portion (162A) may be positioned to penetrate the second protective member (142). The second bonding portion (162A) may include a penetration portion penetrating the second protective member (142) and a protrusion portion protruding above the second protective member (142).

[0184] At this time, the vertical thickness and / or the height of the upper surface of the second bonding portion (162A) may correspond to the vertical thickness and / or the height of the upper surface of the first bonding portion (161). Preferably, the upper surface of the first bonding portion (161) and the upper surface of the second bonding portion (162A) may be positioned on the same plane. This allows the first bonding portion (161) and the second bonding portion (162A) to have the same height when the semiconductor element (200) is mounted as in the structure illustrated in FIG. 6.

[0185]

[0186] According to the embodiment of FIG. 9, a first protective layer (140) is arranged on the build-up structure (105). The first protective layer (140) includes a first protective member (141) and a second protective member (142).

[0187] The first protective member (141) includes a through hole (TH1). The second protective member (142) is disposed within the through hole (TH1) of the first protective member (141). The first protective member (141) and the second protective member (142) may represent a single protective layer. For example, a through hole corresponding to an open area (SA) or a spaced area (SA) may be formed in the first protective layer (140), thereby forming a structure including the first protective member (141) and the second protective member (142) that are spaced apart from each other.

[0188] The first protective member (141) includes a first portion (141-1) and a second portion (141-2). The first portion (141-1) is a portion located further from the through hole (TH1). The first protective member (141) is a portion located closer to the through hole (TH1) than the first portion (141-1).

[0189] The first part (141-1) and the second part (141-2) of the first protective member (141) have different thicknesses or heights. For example, the thickness or height of the first part (141-1) of the first protective member (141) may be greater than the thickness or height of the second part (141-2) of the first protective member (141).

[0190] The second protective member (142) may be positioned within the through hole (TH1) of the first protective member (141). At this time, the second protective member (142) may have an outer surface facing the inner surface of the through hole (TH1) of the first protective member (141). In addition, the second protective member (142) may have a plurality of through holes (TH2) spaced apart from the outer surface of the second protective member (142).

[0191] For example, the second protective member (142) may have a plurality of through holes (TH2) that overlap along the vertical direction with the second wiring portion (122-1b) provided in the build-up structure (105).

[0192] At this time, in the previous embodiment, the second bonding portion (162) is arranged in the through hole (TH2) of the second protective member (142). In contrast, according to the embodiment of FIG. 9, the second bonding portion (162) may not be provided in the through hole (TH2) of the second protective member (142). For example, in the circuit board of the embodiment of FIG. 9, the second bonding portion (162) may be omitted. In this case, the above-described second joining portion (250) may be arranged in the through hole (TH2) of the second protective member (142), thereby allowing the semiconductor element to be joined.

[0193]

[0194] Additionally, according to the embodiment of FIG. 10, a first protective layer (140) including a first protective member (141) and a second protective member (142) is placed on the build-up structure (105).

[0195] In addition, the first bonding portion (161) is disposed in a spaced area between the first protective member (141) and the second protective member (142). In addition, the second bonding portion (162) is disposed to penetrate the upper and lower surfaces of the second protective member (142).

[0196] At this time, a third bonding portion (163) may be further provided to penetrate the first protective member (141) of the circuit board in a vertical direction. The third bonding portion (163) may be arranged to penetrate the first protective member (141).

[0197] That is, the first protective member (141) includes a first portion (141-1) and a second portion (141-2). The first portion (141-1) is a portion located further from the through hole (TH1). The first protective member (141) is a portion located closer to the through hole (TH1) than the first portion (141-1).

[0198] The first part (141-1) and the second part (141-2) of the first protective member (141) have different thicknesses or heights. For example, the thickness or height of the first part (141-1) of the first protective member (141) may be greater than the thickness or height of the second part (141-2) of the first protective member (141).

[0199] At this time, the third bonding portion (163) may be arranged to penetrate the first portion (141-1) of the first protective member (141). The vertical thickness of the third bonding portion (163) and / or the height of the upper surface may be greater than the vertical thickness and / or the height of the upper surface of each of the first portion (141-1), the first bonding portion (161), and the second bonding portion (162) of the first protective member (141).

[0200] Here, at least a portion of the side of the third bonding portion (163) may be surrounded by the first portion (141-1) of the first protective member (141) having a relatively large thickness. Accordingly, the third bonding portion (163) having a relatively large thickness can be positioned more stably.

[0201] At this time, the third bonding portion (163) can function as a mounting portion where a separate semiconductor element and / or external substrate is placed.

[0202] Specifically, referring to FIG. 11, the third bonding portion (163) may be positioned so as to penetrate the buried insulating layer (300). The third bonding portion (163) may be positioned higher than the upper surface of the first semiconductor element (200).

[0203] A third bonding portion (280) may be placed on the third bonding portion (163), and a third semiconductor element or interposer (260) may be placed on the third bonding portion (280). The third semiconductor element or interposer (260) may be a memory element, or may be a memory substrate on which a memory element is placed.

[0204]

[0205] Meanwhile, according to the embodiment of FIG. 12, a connecting member (400) may be embedded within the build-up structure (105). For example, the connecting member (400) is embedded in the first build-up layer (120). The connecting member (400) is embedded in the first build-up layer (120) adjacent to the upper surface of the build-up structure (105) on which the semiconductor element is to be placed. Through this, the signal transmission distance between the connecting member (400) and the semiconductor element can be minimized, thereby improving the communication speed and minimizing signal loss.

[0206] The connecting member (400) functions to electrically connect a plurality of semiconductor elements mounted on the bonding portion (160) of the circuit board (100). At this time, FIG. 2 illustrates that two semiconductor elements are mounted on the circuit board (100) and thus one connecting member (400) is embedded in the first build-up layer (120), but the present invention is not limited thereto. For example, three or more semiconductor elements may be mounted on the circuit board (100), and thus a plurality of connecting members spaced apart horizontally may be embedded in the first build-up layer (120).

[0207] The connecting member (400) may include a plurality of connecting wiring portions (410). The plurality of connecting wiring portions (410) of the connecting member (400) may be electrically connected to the first build-up layer (120). For example, the connecting wiring portions (410) of the connecting member (400) may be connected to vias of the build-up structure (105). The connecting member (400) may be provided for horizontal connection between a plurality of semiconductor devices mounted on a circuit board (100).

[0208] The connecting member (400) may be composed of at least one material selected from the group consisting of silicon, organic materials, and glass. The connecting member (400) may include high-density rewiring patterns connected to the connecting wiring portion (410), thereby electrically connecting a plurality of semiconductor elements.

[0209] The connecting member (400) is advantageous in preventing signal loss when embedded in the first build-up layer (120) of the build-up structure (105). That is, the connecting member (400) electrically connects a plurality of semiconductor elements arranged on a circuit board, and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor elements can be advantageous in reducing signal transmission loss.

[0210] At this time, the first build-up layer (120) described above may include a second insulating layer (121-2) and a third insulating layer (121-3), and the second insulating layer (121-2) and the third insulating layer (121-3) may have a through hole (126), and the through hole (126) of the second insulating layer (121-2) and the third insulating layer (121-3) may form a cavity. In addition, the connecting member (400) may be placed within the cavity (126) described above and then covered with the first insulating layer (121-1) of the first build-up layer (120).

[0211] The connecting member (400) is arranged on the upper surface of the core layer (110) that overlaps the cavity (126) in a vertical direction, and the first insulating layer (121-1) of the first build-up layer (120) may be provided to fill the cavity (126) and surround the side of the connecting member (400) embedded in the cavity (126). In addition, as described above, a metal layer (not shown) may be provided on the upper surface of the core layer (110) to ensure the flatness of the connecting member (400) while ensuring that the connecting member (400) is stably arranged.

[0212] At this time, the cavity (126) of the embodiment may be provided to penetrate a plurality of insulating layers. At this time, if the cavity (126) penetrates only one insulating layer, the flatness of the upper surface of the first insulating layer (121-1) may be deteriorated. In addition, if the thickness of the connecting member (400) is thicker than the thickness of the third insulating layer (121-3) and / or the thickness of the second insulating layer (121-2), the flatness of the upper surface of the first insulating layer (121-1) may be further deteriorated. Therefore, it is necessary to improve the flatness of the first insulating layer (121-1) and further the flatness of the upper surface of the first build-up layer (120) by reducing the difference between the thickness of the connecting member (400) and the depth of the cavity.

[0213] At this time, in order to reduce the difference between the depth of the cavity (126) and the thickness of the connecting member (400), it is advantageous to form the cavity across the second insulating layer (121-2) and the third insulating layer (121-3). At this time, the through hole of the second insulating layer (121-2) can be formed to include a side wall (124) having a second inclination angle higher than the first inclination angle of the inner wall (125) forming the through hole of the third insulating layer (121-3). In this way, in order to increase the positional alignment of the connecting member (400) and prevent the occurrence of voids when filling the cavity (126) with the first insulating layer (121-1), the inclination angle of the inner wall (125) forming the through hole of the third insulating layer (121-3) and the inclination angle of the inner wall (124) forming the through hole of the second insulating layer (121-2) can be arranged to be different from each other.

[0214] In addition, the inclination angle of the inner wall (125) forming the through hole of the third insulating layer (121-3) is shown to have a gentler inclination angle than the inclination angle of the inner wall (125) forming the through hole of the second insulating layer (121-2), but is not limited thereto, and the inclination angle of the inner wall (125) forming the through hole of the second insulating layer (121-2) may have a gentler inclination angle than the inclination angle of the inner wall (124) forming the through hole of the third insulating layer (121-3).

[0215]

[0216] Referring to the embodiment of FIG. 13, the semiconductor package includes a circuit board manufactured by the Embedded Trace Substrate (ETS) method, and according to the above description, the circuit board (100A) according to the embodiment can be classified as a coreless substrate.

[0217] Specifically, the build-up structure of the circuit board (100A) may not include a core layer and may only include a build-up layer. For example, the build-up structure may be manufactured by performing a process of forming a build-up insulating layer, a circuit layer, and a via electrode through a sequential build-up process in one direction of the carrier member based on the carrier member.

[0218] That is, the first wiring portion (122-1a) and the second wiring portion (122-1b) can be embedded within the build-up structure (105). For example, the first wiring portion (122-1a) and the second wiring portion (122-1b) can be embedded in the upper surface of the first build-up layer (120) of the build-up structure (105).

[0219]

[0220] In addition, the circuit board described above can be used as an interposer provided between the semiconductor package substrate of the semiconductor package and the semiconductor element.

[0221] Referring to the embodiment of FIG. 14, the semiconductor package may include a circuit board (100), a first semiconductor element (200), a second semiconductor element (220), a first bonding portion (240), a second bonding portion (250), a buried insulating layer (300), and a semiconductor package substrate (500).

[0222] The circuit board (100) may refer to the circuit board described in the previous embodiment, which may function as an interposer. Accordingly, the circuit board (100) will be described as an interposer (100).

[0223] That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, the yield of the circuit board may decrease. Therefore, the circuit board may be divided into an interposer and a semiconductor package board (500) and used. The circuit board described above may be used as a semiconductor package board, or alternatively, may be used as an interposer.

[0224] Semiconductor elements (200, 220) are arranged on the interposer (100). The semiconductor elements (200, 220) may be provided in multiple numbers on the interposer (100) while being spaced apart from each other in the horizontal direction, but are not limited thereto. For example, the semiconductor elements (200, 220) may be arranged to be stacked not only in the horizontal direction but also in the vertical direction on the interposer (100). A connecting member for electrically connecting the semiconductor elements (200, 220) is arranged on the interposer (100).

[0225] A semiconductor package substrate (500) is placed on the lower surface of the interposer (100). The semiconductor package substrate (500) can electrically connect the main board of an electronic device and the interposer (100).

[0226] At this time, an external bonding member (510) may be placed between the interposer (100) and the semiconductor package substrate (500), through which the interposer (100) and the semiconductor package substrate (500) may be electrically bonded.

[0227]

[0228] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0229] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0230] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0231] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. Build-up structure; A protective layer comprising a first protective member disposed on the above build-up structure and having a through hole, and a second protective member disposed on the inside of the through hole of the first protective member; A first bonding portion arranged between the inner surface of the through hole of the first protective member and the outer surface of the second protective member; and Including a second bonding portion penetrating the second protective member, A circuit board, wherein the upper surface of the first bonding portion and the upper surface of the second bonding portion have different heights.

2. In paragraph 1, A circuit board, wherein the upper surface of the first bonding portion is positioned higher than the upper surface of the second bonding portion with respect to the upper surface of the build-up structure.

3. In paragraph 1, The upper surface of the first protective member includes a first portion that is furthest from the upper surface of the build-up structure, and a second portion that is closer to the upper surface of the build-up structure than the first portion, A circuit board, wherein the upper surface of the first bonding portion is positioned higher than the upper surface of the first portion of the first protective member based on the upper surface of the build-up structure.

4. In paragraph 3, A circuit board, wherein the height of the upper surface of the second protective member is lower than or equal to the height of the upper surface of the first part of the first protective member based on the upper surface of the build-up structure.

5. In paragraph 1, A circuit board, wherein the first bonding portion is spaced apart from the inner surface of the through hole of the first protective member and the outer surface of the second protective member.

6. In paragraph 1, A circuit board, wherein the first bonding portion is provided in plurality and spaced apart from each other along the circumferential direction of the outer surface of the second protective member.

7. In paragraph 3, A circuit board, wherein the vertical distance between the upper surface of the first bonding portion and the upper surface of the first portion of the first protective member is 5% to 45% of the vertical distance between the upper surface of the first bonding portion and the lower surface of the first bonding portion.

8. In paragraph 3, A circuit board, wherein the first portion of the first protective member is provided along the circumferential direction of the second portion of the first protective member and is located further from the through hole than the second portion of the first protective member.

9. In paragraph 3, A circuit board, wherein the height of the upper surface of the second bonding portion is lower than the height of the upper surface of the first portion of the first protective member and higher than the height of the upper surface of the second portion based on the upper surface of the build-up structure.

10. In paragraph 3, A circuit board, wherein the vertical distance between the upper surface of the first bonding portion and the upper surface of the first portion of the first protective member is greater than the vertical distance between the upper surface of the first portion of the first protective member and the upper surface of the second bonding portion.

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