Sidewall metal contact integration through the direct ETCH of a merged source-and-drain contact

Abstract

Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a plurality of unmerged source-and-drain (S / D) contacts. For example, the method can include forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate, forming a first merged S / D contact on the first channels, forming a first gate structure for each of the first channels, removing a portion of the first merged S / D contact such that a first remaining individual S / D contact is formed on each of the first channels at one end thereof after the first gate structure is formed, and forming a first interconnect that connects the first remaining individual S / D contacts.

Description

SIDEWALL METAL CONTACT INTEGRATION THROUGH THE DIRECT ETCH OF A MERGED SOURCE-AND-DRAIN CONTACTCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This present disclosure claims the benefit of U.S. Provisional Application No. 63 / 620,113, entitled “Sidewall Metal Contact Integration Through the Direct Etch of a Merged Source and Drain Contact” filed on January 11, 2024, which is incorporated herein by reference in its entirety.FIELD OF THE INVENTION

[0002] The present disclosure relates to semiconductor processing, and, in particular, to formation of unmerged sidewall metal contacts of semiconductor devices.BACKGROUND

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film -forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring / metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.SUMMARY

[0005] Aspects of the present disclosure provide a method of fabricating a semiconductor structure that includes a plurality of unmerged source-and-drain (S / D) contacts. For example, the method can include forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate, forming a first merged S / D contact on the first channels, forming a first gate structure for each of the first channels, removing a portion of the first merged S / D contact such that a first remaining individual S / D contact is formed on each of the first channels at one end thereof after the first gate structure is formed, and forming a first interconnect that connects the first remaining individual S / D contacts.

[0006] In an embodiment, the method can further include forming a first silicidation layer on at least one of the first S / D contacts. For example, the first silicidation layer can be formed after the first gate structure is formed. In another embodiment, the method can further include forming a first contact etch-stop layer (CESL) to cap each of the first S / D contacts before the first gate structure is formed, and removing the first CESL after the first gate structure is formed. In some embodiments, the method can further include forming a first cladding material on at least one of the first S / D contacts, and removing the first cladding material after the first gate structure is formed. For example, the first cladding material can be formed before the first gate structure is formed. As another example, the first cladding material can include silicon.

[0007] In an embodiment, the method can further include forming a first epitaxy layer over at least one of the first S / D contact. For example, the first epitaxy layer can be formed after the first gate structure is formed. In another embodiment, the semiconductor structure can include an N-type metal oxide semiconductor (NMOS), and the first epitaxy layer can include phosphorous- or arsenic-doped silicon or silicon germanium. In some embodiments, the semiconductor structure can include a P-type metal oxide semiconductor (PMOS), and the first epitaxy layer can include boron-doped silicon or silicon germanium.

[0008] In an embodiment, a first interconnect trench can be formed after the portion of the first merged S / D contact is removed, and the first interconnect can be formed within the first interconnect trench. In another embodiment, the first gate structure can wrap around each of the first channels. For example, forming the first gate structure can include forming a first replacement gate structure that wraps around each of the first channels, and performing a replacement metal gate (RMG) module to replace the first replacement gate structure with the first gate structure.

[0009] In an embodiment, the method can further include forming a first etch-selective cap over the first channels, forming over the first etch-selective cap a plurality of second channels that are stacked over each other and extend along the top surface of the substrate, forming on each of the second channels at one end thereof a second remaining individual S / D contact, forming a second gate structure for each of the second channels, and forming a second interconnect that connects the second remaining individual S / D contacts and connects the first interconnect through an inter-tier via formed within the first etch-selective cap.

[0010] In an embodiment, the method can further include forming a second merged S / D contact on the second channels before the second gate structure is formed, and removing a portion of the second merged S / D contact such that the second remaining individual S / D contact are formed after the second gate structure is formed. In another embodiment, a second interconnect trench can be formed after the portion of the second merged S / D contact is removed, and the second interconnect can be formed within the second interconnect trench, in some embodiments, the semiconductor structure can include a complementary fieldeffective transistor (CFET) structure. In various embodiments, the method can further include forming a second etch-selective cap under the first interconnect.

[0011] Aspects of the present disclosure also provide a method of fabricating a semiconductor structure that includes a plurality of merged source -and-drain (S / D) contacts. For example, the method can include forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate, forming a first merged S / D contact on the first channels, forming a first gate structure for each of the first channels, removing a portion of the first merged S / D contact after the first gate structure is formed such that a plurality of first remaining S / D contacts that are merged are formed, each of the first remaining S / D contacts formed on a corresponding one of the first channels at one end thereof, and forming a first interconnect that connects the merged first remaining S / D contacts.

[0012] Note that this summary section does not specify every embodiment and / or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various embodiments of this disclosure that are proposed as examples will be described in detail with reference to the following figures, wherein like numerals reference like elements, and wherein:

[0014] FIGs. 1A and IB show cross-sectional views of two CFET device structures that include merged S / D contacts and sidewall metal contacts, respectively;

[0015] FIGs. 2 and 3 show semiconductor structures each including unmerged sidewall metal contacts according to some embodiments of the present disclosure;

[0016] FIG. 4 shows a semiconductor structure including sidewall metal contacts that are merged according to some embodiments of the present disclosure;

[0017] FIGs. 5-20 show a semiconductor structure fabricated at various intermediate steps that includes unmerged sidewall metal contacts formed through incorporation of replacement metal contact integration according to some embodiments of the present disclosure;

[0018] FIG. 21 is a flow chart of an exemplary method of fabricating a semiconductor structure that includes unmerged sidewall metal contacts according to some embodiments of the present disclosure; and

[0019] FIG. 22 is a flow chart of an exemplary method of fabricating a semiconductor structure that includes merged sidewall metal contacts according to some embodiments of the present disclosure.DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed. Further, spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe oneelement or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0021] The order of discussion of the different steps as described herein has been presented for clarity sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc . herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.

[0022] Sidewall metal contact (SWMC) has been proposed as a design -technology -co- optimization (DTCO) solution to reduce parasitic contact resistance for both gate -all-around (GAA) and complimentary field -effective transistor (CFET) device structures. The sidewall metal contact replaces the conventional merged source -and-drain epitaxy contact with a small, un-merged source-and-drain (S / D) contact. This allows for parasitic resistance improvement through several mechanisms. For example, the merged doped silicon or silicon germanium epitaxy contact as the primary material filling the volume within an interconnect trench may be replaced with a highly conductive metal such as ruthenium (Ru), cobalt (Co), or tungsten (W) - thus providing a more highly conductive path from the signal wiring down through the collection of stacked nanosheets in a GAA or CFET device structure. An additional highly -doped, thin epitaxy may be grown overtop of the sidewall metal contact to further improve contact resistance as a substitution for implant doping of a merged source- and-drain contact, in which the implant would be limited to the top -most side of the source- and-drain contact. By having the more highly -doped epitaxy grown on top of the individual sidewall metal contact, this likewise ensures that all stacked nanosheets are more well- balanced and allows for the stacking of a greater number of nanosheets on top of one another in either GAA or CFET device structures which is important for future area scaling of the devices. An additional subtractive strain material maybe grown or deposited overtop of the sidewall metal contact in which the strain can be more equally placed into each of the individual stacked nanosheets in a GAA or CFET device structure. This is in contrast to conventional merged source-and-drain processing in which the merging of the epitaxy across vertical-facing stacking faults can significantly reduce the strain being imposed into the channel. Even with the addition of a subtractive straining layer to the merged source -and-drain contact, the straining layer will be relegated to the outer most edges of the merged source-and-drain contact, thus reducing the overall efficiency of the straining layer to impose equal strain into all of the stacked nanosheets.

[0023] The sidewall metal contact was proposed by Wen -Li Sung in a publication, entitled “Characteristics of Stacked Gate-All-Around Si Nanosheet MOSFETs With Metal Sidewall Source / Drain and Their Impacts on CMOS Circuit Properties,” Transactions on Electron Devices; volume 68 number 6; June 2021, which is incorporated herein for reference in its entirety. The publication shows the parasitic resistance improvement captured as an increase in performance of a three-stage ring oscillator in which performance continues to increase even with the increase in the number of stacked nanosheets. Typically for GAA and CFET device structures, stacking nanosheets on top of one another provide for increased drive current through the devices; however, this also simultaneously increases the effective gate and interconnect metal heights, which adds a large parasitic capacitance component to the overall power / performance of the device. Additionally, having a large merged S / D contact also leads to larger parasitic resistance in the contact as the connection to the merged S / D contact is usually made at the very top of the merged contact structure.

[0024] For the case of the sidewall metal contact, the parasitic resistance is reduced through the primary material filling within the interconnect trench being a high conductive metal as opposed to a merged S / D contact doped semiconductor material. The improvement in the parasitic resistance is adequate to compensate for the higher parasitic capacitance associated with the increased metal heights of the gate and interconnect associated with the larger number of stacked nanosheets in the device.

[0025] Cross-sectional views of two CFET device structures 100 A and 100B that include merged S / D contacts 110A and sidewall metal contacts HOB, respectively, are shown in FIGs. 1 A and IB, respectively, which illustrate the primary differences between the two different S / D contact approaches. FIGs. lA and IB show this for the case of a CFET device structure in which NMOSs 120 A and 120B are the lower-tier devices and PMOSs 130A and 130B are the upper-tier devices; as well as for the case of split power where VSSs 140 A and MOB are shown as the bottom copper back-side power rail and VDD is not shown in the cross-section, but will be a conventional top -side power rail within the M0 module. Any current supplied by the VDD for the case of the merged S / D contacts 110A will pass through the top-side of the wafer (i.e., the CFET device structure 100A) at the M0 power rail (not shown) and pass down to the top of the PMOS merged S / D contacts 110A where the silicide 150A is present; pass through the silicide 150 A into the bulk boron -doped Si Ge epitaxycontact (S / D contact 110 A), and through the deep merged boron -doped SiGe epitaxy contacts (S / D contact 110A) before encountering the stacked silicon PMOS channels 160A of the PMOS 130A. The path length of the current through the merged eSiGe:B contact (S / D contact 110A) is quite large before encountering the bottom-most PMOS channel 160A. Comparatively, FIG. IB shows the case of the sidewall metal contact 11 OB in which the current from the VDD power rail (not shown) will pass into a bulk PMOS interconnect 170B such as ruthenium (Ru) and be allowed to pass all the way down the depth of the PMOS interconnect 170B to then pass through a local silicide 150B grown at the end of the much smaller, un-merged boron-doped SiGe contacts (sidewall metal contacts HOB), and thus have much less path-length through this lower conductive medium before encountering the silicon PMOS channel 160B of the PMOS 13 OB.

[0026] The sidewall metal contact process is a more challenging integration compared to the merged S / D contact process, simply because the merged S / D contact 110A presents as a fixed structure in which the merged S / D contact 110A can be formed and covered up by a dielectric material such as a silicon oxide during the replacement metal gate module; and then subsequently re-opened either where only the top of the merged S / D contact 110A needs to be exposed to make connection to the interconnect metal, or for the case of wrap -around contact, where the oxide surrounding the merged S / D contact 110A can be opened on either side of the merged S / D contact 110A in order to make a wrap-around connection to the interconnect metal. For the case of the sidewall metal contact HOB, the protruding ends of the sidewall metal contacts 11 OB prevent anisotropic etching of the silicon oxide dielectric as the upper sidewall metal contacts 110B will “shadow” the dielectric etch to the sidewall metal contacts underneath. In order to integrate a sidewall metal contact process, a replacement metal contact integration is typically required. U.S. Patent No. 11,264, 274 -B2, entitled “Reverse contact and silicide process for three-dimensional logic devices,” describes such an integration method which can be adopted to enable a manufacturing process for the sidewall metal contact 110B, and is thus incorporated herein for reference in its entirety.

[0027] The replacement metal contact integration was initially designed to: enable to form a S / D contact on a lower-tier device for CFET device structures in which the silicide can be formed on the bottom contact well after the replacement metal gate processing in order to maintain thermal processing consistency; allow for the placement of wrap-around interconnect metal around a non-straight S / D contact; and enable the inclusion of a direct backside contact to directly connect the S / D to a back-side power rail to eliminate any fringecapacitance associated with having the connections to the wafer backside from having to extend well beyond the sides of the S / D contact

[0028] However, the replacement metal contact integration can be used to also enable the sidewall metal contact integration in which S / D contacts need to be formed and the interconnect trench memorized with an alternate etch -selective dielectric relative to the surrounding oxide, in which the interconnect trench can be re-opened following replacement metal gate processing to form the silicide and interconnect metallization without causing any degradation to the surrounding oxide field.

[0029] There is an economic push to simplify the sidewall metal contact integration flow in order to reduce the total number of processing steps as well as the overall process complexity. In this case, alternate integrations of the sidewall metal contact integration are proposed in which this can be realized. In an embodiment, the sidewall metal contact HOB can be formed by the use of the replacement metal contact (RMC) integration. The RMC integration can be employed to have a fully self -aligned backside contact to the backside power connections and / or power distribution network. In the RMC integration, the S / D contact can be memorized by the doped epitaxy which is captured within the protection of the inner spacer, and will have a lateral dimension equal to the lateral recess of the silicon nanosheet in the S / D formation module. The additional space the RMC integration provides will allow for additional contacted poly pitch (CPP) reduction as well as allowing additional space to have additional low-temperature / extremely high doping epitaxy grown overtop of the sidewall metal contact in order to further reduce contact resistance of the device.

[0030] The fundamental challenge with adopting an un -merged sidewall metal contact (e.g., the sidewall metal contact 110B) is with the intermediate steps between the formation of the contacts, which is typically done much earlier in the front-end-of-the-line (FEOL) processing, and the silicidation and metallization of the contacts, which is done following the replacement metal gate (RMG) module, after the reliability anneals have been done on the device. With a conventional merged source -and-drain (S / D) contact (e.g., the merged S / D contact 110 A), the contact can be created and the area surrounding the contact can be easily re-filled with a dielectric material such as silicon oxide; in the subsequent interconnect trench opening process, the silicon oxide can be opened where the merged S / D contact can provide some level of continuity where either a partial amount or the full amount of contact can be exposed to what will eventually become the interface to which the silicide can be formed over the contact and the interface between the silicide and the interconnect metal.

[0031] For a stacked nanosheet type of device, as what exists for gate -all-around (GAA) and complimentary field effective transistors (CFET) devices, the merged S / D contact allows for connection from the uppermost portion of the contact making connection to the interconnect metal down across all nanosheets in the stacked nanosheet device, where the electrical connectivity between the interconnect metal and the nanosheets is accomplished through the S / D contact itself.

[0032] The sidewall metal contact (SWMC) allows for each nanosheet to have a small volume of S / D contact at each terminal of the transistor which is directly connected to the interconnect metal which wraps around each of the S / D contacts and extends down to the bottom-most nanosheet, thus providing a much higher conductive medium in which signal to travel from the S / D contact to the metal signal wires, and vice-versa.

[0033] The sidewall metal contact, being un-merged, actually makes the standard integration process of forming the S / D contacts and re -filling with a dielectric such as silicon oxide before the RMG module more challenging. The challenge comes in the interconnect trench open process in which the silicon oxide needs to be etched to make connection to each individual S / D terminal of the group of sidewall metal contacts, as the protruding un-merged S / D contacts will block the silicon oxide transfer etch from reaching the un-merged S / D contacts directly underneath the uppermost S / D contact which is encountered by the etch process.

[0034] Applying some measure of anisotropicity and isotropicity to the trench etch process, where the initial trench is opened with the S / D contact being blocked or shadowed by the uppermost S / D contact, and then including an isotropic etch to ensure wrap-around of the trench etch to the underlying S / D contacts can be considered an option; however, the challenge with applying this approach as a solution is that the isotropic etch will extend the effective trench “heights” (with height meaning the north -south dimension of the interconnect trench in terms of the logic standard cell) which will likewise lead to higher parasitic capacitance and either slower overall device performance or greater device power consumption.

[0035] One potential solution to the formation of the sidewall metal contact may be an application of US Patent No. 11,264,274-B2 from Tokyo Electron in which a replacement metal contact integration flow is provided in which a replacement dielectric with etch selectivity to silicon oxides and other dielectric materials present in the device during the FEOL and middle-of-the-line (MOL) processing modules is used as a means to memorize the interconnect morphology such that in the sequence where the interconnect trench wouldnormally be opened, instead of etching into the silicon oxide dielectric, the trench is simply “re-formed” from its memorized morphology through the isotropic etching of the replacement dielectric gap-fill material which will have selectivity to the silicon oxide surrounding the memorized interconnect trench.

[0036] The replacement metal contact process outlined in the referenced Tokyo Electron patent was initially intended to allow for the thermal processing of the contact and interconnect modules in a CFET device where the bottom -most device would need to have the silicidation and metallization of the interconnect done after the RMG module proc essing. This was accomplished in the present disclosure through memorizing the interconnect shape with the replacement dielectric material; when the wafer would be flipped over to process the bottom-most device, the replacement dielectric could be removed in an isotropic manner with selectivity to the silicon oxide in order to perform the silicide and metallization of the bottom device through the backside of the wafer well after the RMG processing was finished. The application of the replacement metal contact was later adopted to allow for the inclusion of a self-aligned direct backside contact which would allow for a direct metal connection between the bottom-most device and any backside power lines or backside signal lines.

[0037] The concept herein is to adopt the replacement metal contact integration to allow for the formation of the sidewall metal contact, which otherwise could not be done through conventional interconnect integration processes.

[0038] An example of how such an integration would be done is shown below using a monolithic CFET device, which adds greater complexity over standard gate -all-around (GAA) device structures given that there needs to be consideration for the tier-to-tier connections which will be needed in some instances to merge the input and / or output of the NMOS and PMOS devices together without doing so utilizing a signal track in the BEOL metal stack.

[0039] For the monolithic CFET reference, a number of assumptions are used, including: (1) split power where VDD is supplied by a top-side power rail and VSS is connected through a backside power rail; (2) the connection of a NMOS device to VSS power is done through an integrated self-aligned backside direct contact (BSC) which also adds complexity to the integration at the benefit of significant reduction in fringe capacitance (and hence improvement in either cell -level performance and / or power consumption); (3) configuration of the monolithic CFET device in which a PMOS is the uppermost device, and a NMOS is the bottom -most device; where the PMOS being separated from the substrate would require additional processing in the integration to provide some measure of strain into the channel;(4) for this example a silicon-on-insulator (SOI) type of substrate wafer is used where a buried oxide layer exists under the silicon / silicon germanium active stack - it is realized that this integration can be adopted for standard silicon substrates without any buried oxide and other types of starting wafers such as sequentially processed wafers which could be used in a sequential CFET device structure; and (5) other assumptions include 4 stacked NMOS sheets (e.g., nanosheets) with four stacked PMOS sheets (e.g., nanosheets) overtop, with the nanosheet width being 21nm with a lOnm vertical spacing between silicon nanosheets; an physical gate length of 15nm, and a contacted poly pitch of 42nm.

[0040] It is stressed that the present disclosure would equally apply to any configuration of a CFET device where power can both be either top -side or back-side and even a combination of the two; and the device orientations can be swapped to where a NMOS is the uppermost device. It is also stressed that the present disclosure can equally pertain to gate -all-around (GAA) devices and is not limited to CFET device structures. Only the case of the monolithic CFET device is shown in this example as it provides the more challenging of the device structures to effectively demonstrate the present disclosure.

[0041] FIGs. 2-4 show a semiconductor structure 200 that includes sidewall metal contacts integrated through the direct etch of a merged source-and-drain contact according to some embodiments of the present disclosure. In an embodiment, the semiconductor structure 200 can include a monolithic CFET device (semiconductor structure 200) in which a NMOS 200N is a lower-tier device and a PMOS 200P is an upper-tier device.

[0042] In the fabrication of the semiconductor structure 200: (1) there is either some margin of gate extension created where the nanosheet structure is laterally recessed within an inner spacer dielectric, or where some additional dielectric spacer material is deposited overtop the initial dummy gate in which any nanosheet lateral recess will provide some vertical etch protection or “shadowing” of any source-and-drain (S / D) contact formation within the laterally recessed region; (2) a fully merged S / D contact is formed and can be in- situ doped to provide the necessary contact resistance and the contact material itself can be composed of multiple layers of semiconductor material and / or in -situ doping to provide maximum conductance and etch-selectivity to sub sequent processing; (3) any cladding of the contact using either a complimentary semiconductor material in terms of lattice structure, or strained dielectric material such as a strained contact etch stop layer (CESL) can be deposited overtop of the formed S / D contact; and (4) after replacement metal gate (RMG) module, an interconnect trench is opened to expose the merged S / D contact, with a subsequent etch designed to etch through the merged S / D contact, leaving only the S / D contact materialenclosed within the protection of either the inner spacer dielectric or any spacer deposited overtop the initial dummy gate which may even include a CESL deposition done over the initial merged S / D contact structure itself ; any semiconductor cladding material over the merged S / D contact can be etched during this same processing step and any dielectric CESL or strain layer can be removed from the top-most surface of the merged S / D contact in order to preserve any desired dielectric spacer on the gate sidewall to provide additional protection of the desired remaining S / D contact from being removed by the etch. The final morphology of this type of sidewall metal contact can exist across multiple different types including what is shown in the figures below.

[0043] FIG. 2 shows a case in which final PMOS sidewall metal contacts 21 OP of the PMOS 200P and final NMOS sidewall metal contacts 2 ION of the NMOS 200N of the semiconductor structure 200 are preserved within a gate extension region 220 in which the sidewall metal contacts 210P and 210N are protected by an inner spacer (e.g., including a dielectric material). The grown silicide 230P and 230N on the of the PMOS sidewall metal contacts 21 OP and the NMOS sidewall metal contacts 210N, respectively, may or may not extend beyond the borders of the inner spacer based on how much the silicide 23 OP and 230N are formed at the surface of the sidewall metal contacts 21 OP and 21 ON and based on how far the initial nanosheet is laterally etched into the gate extension region.

[0044] FIG. 3 shows a case in which the morphology of the case shown in FIG. 2 is further processed where thin, highly -doped additional source-and-drain (S / D) semiconductor materials 310P and 310N are further epitaxially grown at low temperature after an interconnect trench has been opened and the merged S / D contact 21 OP / 210N is etched through. This morphology is possible as low-temperature / highly-doped silicon and silicon germanium CVD epitaxy processes exist, but have the imitation of being extremely slow and low thru-put wafer processing. These processes canbe incorporated here because only a very small amount of very -highly doped contact material (i.e., the S / D semiconductor materials 310P and 310N) is required to make significant contact resistance reduction because of the proximity of the additional high -doped contact material to each individual channel 330P / 330N. The thermal processing of the additional highly in -situ doped epitaxy S / D semiconductor materials 310P and 310N should be below 500C where no degradation to the transistor will occur. A case can also be made that some type of solid state doping (SSD) processing can be done immediately after the processing to further reduce contact resistance.

[0045] FIG. 4 shows a case in which an additional dielectric liner 410 has been deposited overtop the initial dummy gate extension region 220 and is used to allow some vertical-facingmerging of the S / D contacts 21 OP (sidewall metal contacts) to be preserved. In this case, the dielectric liner 410 can be an additional low-k spacer material, a contact etch-stop (CESL) liner, or some other type of dielectric spacer used for the purpose of generating this specific final sidewall metal contact morphology.

[0046] As with the case described in the above condition, an additional high -doped contact material or SSD material (e.g., the S / D semiconductor materials 310P and 3 ION shown in FIG. 3) can be grown or deposited over the facing S / D contacts 210P and 210N (sidewall metal contacts) in order to further improve contact resistance.

[0047] An illustration of the processing of the example shown in FIG. 2 is shown in the next set of figures. The conditions shown in FIGs. 3 and 4 are not included in this example set; however, these additional integrations are covered under the present disclosure. The process sequence will follow that of the previous disclosure with the exceptions being: (1) the replacement metal contact integration is not used for the upper-tier device and is only used for the lower-tier device as a simple convenience to deal with the thermal processing constraints, (b) a merged S / D contact is formed rather than the un -merged S / D contact, and (c) the sidewall metal contact is formed through the direct etching of the merged S / D contact exposed within the opened interconnect trench.

[0048] FIGs. 5-20 show a semiconductor structure 500 fabricated at various intermediate steps that includes sidewall metal contacts integrated through the direct etch of a merged source-and-drain (S / D) contact according to some embodiments of the present disclosure. In an embodiment, the semiconductor structure 500 can include a monolithic CFET device (semiconductor structure 500). FIG. 5 shows a INVD4 standard logic cell in the monolithic CFET device (semiconductor structure 500) starting at an inner spacer formation step proceeding to a patterning step in which a self-aligned direct backside contact (BSC) is formed and then transferred through a NMOS buried oxide layer 530 formed on a substrate 540 (or a silicon-on-insulator (SOI) substrate) and then gap-filled and etch-recessed with a replacement dielectric material 510. The choice of the replacement dielectric material 510 will be co-optimized with the other surrounding dielectric materials is order to achieve the required etch selectivity - both in the selective etch recesses of the replacement dielectric material 510, but also for the eventual selective removal of the replacement dielectric material 510 selective to the surrounding dielectric materials. A number of potential materials can be used for the replacement dielectric material 510, ranging from silicon oxide - assuming that the surrounding dielectrics will either be heavily doped with carbon or lined with some type of carbon film to provide etch -selectivity; or the replacement dielectricmaterial 510 can be composed of materials such as boron nitride or similar dielectrics which can be removed with high degrees of selectivity with respect to silicon oxides and silicon nitrides. The replacement dielectric material 510 will possess good gap-filling capability and good etch selectivity to other dielectrics including, but not limited to, silicon oxides, silicon nitrides, and carbon-doped silicon oxides and silicon nitrides. The BSC contact here is fully self-aligned to a source / drain (S / D) contact region 520 which is critical for the eventual metal connection between a backside power (e.g., VSS) and / or backside signal wires to the contact without shortingto the adjacent metal gate which will be created adjacentto the BSC contact. In an embodiment, the semiconductor structure 500 can include a CFET device architecture in which a NMOS device nanosheets 500N is the lower-tier device nanosheets and a PMOS device nanosheets 5 OOP is the upper-tier device nanosheets.

[0049] FIG. 6 carries the integration on through the formation of a cover spacer 610 which will cover the upper-tier PMOS device nanosheets 500P (i.e., the PMOS in this example) from the exposed lower-tier device nanosheets 500N (i.e., the NMOS in this example). A lower-tier merged NMOS S / D contact 620 can be formed either inside a pre-patterned NMOS interconnect trench, or outside of any pre-defined structure, from the ends of the lower-tier device nanosheets 500N (i.e., the NMOS). For the NMOS device nanosheets 500N, the merged NMOS S / D contact 620 can be composed of epitaxy silicon which is in-situ doped with phosphorous (P) or arsenic (As) in order to improve the conductance of the merged NMOS S / D contact 620. Likewise, the morphology of the merged NMOS S / D contact 620 can be rectangular or hexagonal, depending on the number and widths of the nanosheets used in the NMOS device nanosheets 500N and the CVD epitaxy growth process. Additionally, the NMOS S / D contact 620 can be grown within a pre-defined structure such as an interconnect trench or within some other type of confined growth structure in order to ensure a perfectly rectangular shape is defined for the contact, which will make creating a wraparound contact (WAC) easier. In the example shown in FIG. 6, the NMOS S / D contact 620 is grown in a rectangular shape without any confinement; however, other approaches will be viable for the growth of the NMOS S / D contact 620. The lateral etching of the nanosheets can be anywhere to set a zero-extension for the metal gate to where the nanosheet is preserved to be flush with the inner spacer dielectric.

[0050] FIG. 7 shows the removal of the cover spacer 610 (shown in FIG. 6) from the upper-tier PMOS device nanosheets 500P which will no longer be needed for the case of the merged NMOS S / D contact 620 as a following CESL 710 deposited over the lower-tier NMOS S / D contact 620 as well as the upper-tier PMOS device nanosheets 500P will act tokeep the upper-tier PMOS device nanosheets 500P protected. Following the deposition of the CESL 710, the space between the gates is then re-filled with a filler material 720 (e.g., silicon oxide) and polished down.

[0051] FIG. 8 shows the case where a replacement metal contact integration (RMC) is used for the lower-tier device nanosheets 500N. Although this is not necessary from a contact perspective in this case where the NMOS S / D contact 620 is fully merged and will thus have no shadowing effect for the later interconnect trench process, the replacement metal contact (RMC) integration does allow for memorization of the lower-tier NMOS interconnect structure relative to the oxide around it which can be used as a means of memorizing the interconnect morphology such that the silicide and metallization can be done from the backside of the wafer (i.e., the semiconductor structure 500). Although other methods to do this backside processing without the absolute need of a replacement mental contact integration do exist, the adoption of the RMC integration does in fact provide for the full self- alignment of the eventual interconnect metal which is separated from the eventual gate metal by a fixed inner spacer and / or gate spacer at this point. This allows for the silicidation of the lower-tier NMOS S / D contact 620 to be done well after the replacement metal gate (RMG) module where high -temperature depositions and thermal anneals are done; where these thermal anneals exceed the thermal budget of the formed silicide. The RMC integration is used in this example because it does add some complexity and consideration to the overall process. As shown in FIG. 8, an interconnect trench 810 is etched into the filler material 720 (e.g., silicon oxide dielectric) to uncover the CESL 710 and is gap-filled with a NMOS replacement dielectric material (e.g., the replacement dielectric material 510) 820, which is then vertically recessed down to uncovered the CESL 710 from the upper-tier PMOS device nanosheets 500P.

[0052] FIG. 9 shows the removal of the CESL 710 from the upper-tier PMOS device nanosheets 5 OOP, and the deposition of an etch-selective cap 910 overtop of the recessed NMOS replacement dielectric material 820, at some point either before or after the removal of the CESL 710 from the upper-tier PMOS device nanosheets 500P, to memorize the lower- tier NMOS interconnect structure. The deposition of the etch-selective cap 910 can be done through selective deposition or through a gap-fill / chemical mechanical polish (CMP) / recess methodology. This is followed by a blanket deposition of silicon oxide (i.e., the filler material 720) to re-fill the interconnect trench 810 (shown in FIG. 8) not memorized by the NMOS replacement dielectric material 820. The filler material 720 is then subsequentlyrecessed etched down to the etch -selective cap 910 in order to fully open the upper-tier PMOS device nanosheets 5 OOP.

[0053] FIG. 10 shows the formation of an upper-tier merged PMOS S / D contact 1020. Unlike for the case of the un-merged sidewall metal contact, the upper-tier merged PMOS S / D contact 1020 can be formed either inside a pre-patterned interconnect trench, or outside of any pre-defined structure. Likewise, the morphology of the merged PMOS S / D contact 1020 can be rectangular or hexagonal, depending on the number and widths of the nanosheets used in the PMOS device nanosheets 500P and the CVD epitaxy growth process.Additionally, the PMOS S / D contact 1020 can be grown within a pre-defined structure such as an interconnect trench or within some other type of confined growth structure in order to ensure a perfectly rectangular shape is defined for the PMOS S / D contact 1020, which will make creating a wrap-around contact (WAC) easier. In this example, the PMOS S / D contact 1020 is grown in a rectangular shape without any confinement; however, other approaches can be also viable for the growth of the PMOS S / D contact 1020. For the PMOS device nanosheets 500P, the PMOS S / D contact 1020 can be composed of silicon germanium which is in-situ doped with baron (B) or similar species, and be composed of multiple layers of silicon germanium of different compositions of germanium in order to provide some level of additional strain to PMOS channels 920 (shown in FIG. 9) of the PMOS device nanosheets 500P, and to also provide some etch selectivity between the silicon germanium within the PMOS S / D contact 1020 and the silicon germanium comprised in a silicon / silicon germanium fin structure within a gate region.

[0054] The lateral etching of the nanosheets can be anywhere to set a zero -extension for the metal gate to where the nanosheet is preserved to be flush with the inner spacer dielectric.

[0055] For the case of having a PMOS be the upper-tier device, it may be necessary to add strain into the PMOS channel 920 through the inclusion of an optional stress layer 1010 to the PMOS S / D contact 1020 which can be composed either of a lattice-mismatched semiconductor material, or as a strained dielectric material. A CESL 1030 (e.g., the CESL 710) (or a cladding material, including, for example, silicon) can be then deposited overtop of the PMOS S / D contact 1020 and contact-plus-cladded material.

[0056] FIG. 11 continues the process flow where a filler material (e.g., silicon oxide) 1120 is gap-filled within a contact region 1040 (shown in FIG. 10) to cover the CESL 1030 and polished (e.g., using a CMP process) down to a gate cap. A secondary CMP process canthen be used to polish down to expose the amorphous silicon within a gate structure (e.g., a PMOS gate structure) 1110, followed by the replacement metal gate (RMG) module in which theamorphous silicon is selectively removed, followed by removal of the silicon germanium in an active fin stack, growth of an interface oxide layer (e.g., SiO2, HfO2, etc.) 1111 over the silicon nanosheets (e.g., including the upper-tier PMOS device nanosheets 500P and the lower-tier device nanosheets 500N), deposition of a high-k dielectric 1112, depositions of work function metals (and liners) 1113 to achieve required threshold voltage targets, and filling of a high conductive metal 1114 such a tungsten (W) into the gate as a gate electrode. During the RMG module, the single diffusion breaks are formed in a self -aligned manner and gap-filled with dielectric materials, any gate cuts are implemented and likewise filled with dielectric materials, and the final replacement metal gate is vertically recessed and then subsequently capped with a dielectric such as silicon nitride.

[0057] FIG. 12 shows the case where it is necessary to create shorting between the NMOS and PMOS interconnects for the monolithic CFET device (semiconductor structure 500), as would exist in the case of the output of an inverter. For GAA device architectures, the merging of the outputs between the NMOS device nanosheets 500N and the PMOS device nanosheets 500P would be done by the lateral merging of the NMOS and PMOS interconnects; however, for the case of monolithic CFET device architectures where NMOS and PMOS are stacked on top of one another, the merging of the NMOS and PMOS interconnects must be done vertically and bypassing the etch -selective dielectric which is placed to electrically isolated one from the other.

[0058] This can be done through a variety of methods; in this example an interconnect pattern in a transfer hardmask 1210 is memorized, and then an inter-tier via (inter-tier via) 1220 is patterned and self-alignedto the interconnect pattern in the transfer hardmask 1210. The inter-tier via 1220 can be etched through the filler material (e.g., silicon oxide) 1120 with the CESL 1030 over the PMOS S / D contact 1020 as protection to the PMOS S / D contact 1020 until the etch-selective cap 910 overtop the lower-tier replacement dielectric material 820 is reached

[0059] Another approach is to forego the patterning of the inter-tier via 1220 completely, and to pattern a “keep” mask which will isolate the interconnects which will be electrically merged from those which will not, and to develop an isotropic etch process which will only remove the etch-selective cap 910 over the lower-tier interconnect structure entirely, thus providing significant parasitic resistance improvement.

[0060] In this example, the etch-selective cap 910 can be then anisotropically opened followed by gap-fill and recess of a gap-filled carbon material 1230 which will protect the replacement dielectric material 820 in the lower-tier NMOS device nanosheets 500N when aPMOS interconnect trench 1240 is then fully transferred into the filler material (e.g., silicon oxide) 1120.

[0061] FIG. 13 shows that following the transferring of the PMOS interconnect trench 1240, the gap-filled carbon material 1230 (shown in FIG. 12) is removed through ashing to open the PMOS interconnect trench 1240, and the CESL 1030 (shown in FIG. 12) covering the PMOS S / D contact 1020 (shown in FIG. 12) is then removed.

[0062] At this point the silicon or silicon germanium PMOS S / D contact 1020 and any included semiconductor cladding material can be selectively etched in order to remove the bulk PMOS S / D contact 1020 from the PMOS interconnect trench 1240, leaving only the remaining individual PMOS S / D contacts 1020 (which cover their respective PMOS channels 920 (shown in FIG. 9)) within the gate extension area or area defined by the lateral recess of the nanosheets into the inner spacer dielectric. For alternate integrations in which an additional gate spacer is utilized, the remaining PMOS S / D contacts 1020 will be captured within this additional spacer thickness as well.

[0063] At this point in the integration, all activation, reliability, and roll-off anneals have been performed, so the junction of the PMOS S / D contacts 1020 to their respective PMOS channels 920 will be within this captured region and the doping levels of the remaining PMOS S / D contacts 1020 will be adequate to provide desired contact resistance.

[0064] At this point in alternate integrations, an additional low-temperature / highly in-situ boron-doped (or phosphorous-doped or arsenic-doped for a NMOS) growth of additional silicon or silicon germanium can be done to further extend the remaining PMOS S / D contacts 1020 to a shape more consistent with the previous disclosure section where some volume of S / D material emanates out from the inner spacer and gate extension areas. This follow-up CVD epitaxy process is extremely slow; however, in this case only a very thin additional amount of epitaxy growth (e.g., an epitaxy layer 1310) is required as the deposition will be done simultaneously among the remaining PMOS S / D contacts 1020 for each nanosheet and not to a larger, bulk merged S / D contact structure.

[0065] FIG. 14 starts with the orthogonal projection of the cross-section showing the remaining PMOS S / D contacts 1020 kept within the gate extension region within the inner spacer material. This is followed by the formation of PMOS silicidation layer 1410 and eventual metallization of the PMOS interconnect trench 1240. Here the parasitic resistance benefit should be obvious where nearly the full width of the PMOS interconnect trench 1240 is comprised of highly conductive metal (or the upper-tier PMOS interconnect) 1420 asopposed to the standard case where this would otherwise be filled with a merged S / D contact with much lower overall conductivity.

[0066] FIG. 15 continues the integration where the highly conductive metal (i.e., the PMOS interconnect) 1420 in the PMOS interconnect trench 1240 (shown in FIG. 13) is recessed down and then subsequently filled with an etch -selective cap 1510 which has etch selectivity to the silicon nitride gate cap, the silicon oxide field dielectric, and the carbon -doped silicon oxide film which typically comprises the low-k gate spacer. In an embodiment, the etch- selective cap 1510 can be composed of a dielectric material such as carbon-rich silicon nitride films, or even films composed of silicon carbide or SiCN.

[0067] The etch selectivity is important for the self-aligned gate contact (SAGC) or contact-over-active-gate (COAG) integrations in which etch -selectivity is used to be able to assign via-to-gate and via-to-contact connections through a self -aligned method to signal wires.

[0068] After the upper-tier PMOS interconnect metallization and capping (i.e., after the formation of the PMOS interconnect 1420 and the etch -selective cap 1510), the entire back- end-of-the-line (BEOL) module is completed where all of the signal layers are created along with any of power distribution network metal layers 1520, and any passivation and padding layers 1530.

[0069] Typically, this would be the end of the chip processing; however, for monolithic CFET as well as for device architectures which incorporate any backside metal routing or power layers, the wafer (i.e., the semiconductor structure 500) will need to be placed onto a carrier wafer and flipped over in order to continue the lower-tier NMOS interconnect metallization as well as any backside metal processing.

[0070] FIG. 16 continues the wafer processing after the wafer (i.e., the semiconductor structure 500) is bonded to a carrier wafer 1610 and flipped over in which the initial substrate 540 (shown in FIG. 15) is removed through a combination of a grinding process followed by optional CMP and etch removal processes to expose the NMOS buried oxide layer 530. Again, the assumption for this example is that a buried oxide layer is used; for other integrations where no SOI wafer is used, the stop would be done on the shallow trench isolation dielectric instead.

[0071] In this approach, the NMOS buried oxide layer 530 is revealed as well as the replacement dielectric materials 510 and 820 (shown in FIG. 15) from the lower-tier NMOS device nanosheets 500N. The replacement dielectric materials 510 and 820 can be isotropically removed with etch selectivity with respect to the buried oxide layer 510 / shallowtrench isolation dielectric as well as the field silicon oxide and the carbon-doped silicon oxide comprised in the inner spacer.

[0072] It is at this point where the inter-tier via 1220 (also shown in FIGs. 12 and 13) merging the PMOS interconnects 1420 and NMOS interconnects 1920 (shown in FIG. 19) is exposed along with the PMOS interconnects 1420. The CESL 1030 can be removed from the NMOS S / D contact 620 to open the NMOS S / D contact 620 and a NMOS interconnect trench 1620, and then the NMOS S / D contact 620 will be cleaned which will likewise clean the exposed PMOS interconnect 1420 from the upper-tier PMOS device nanosheets 500P.

[0073] Alternately, an additional step can be added to the integration which is not shown where some gap-filled carbon material can be gap-filled into the opened NMOS interconnect trench 1620 priorto the removal of the CESL 1030 and then recessed down to allow for full exposure of all of the NMOS S / D contact 620, but to maintain some level of protection over the exposed metal from the PMOS interconnect 1420, if desired.

[0074] FIG. 17 shows the case where a gap-filled carbon material 1710 is filled within the opened lower-tier NMOS S / D contact 620 and then recessed down to only fill a region in which the inter-tier via 1220 is present. This is done to protect the PMOS interconnect 1420 from being etched in the subsequent steps where the silicon or silicon germanium NMOS S / D contact 620 (shown in FIG. 16) is anisotropically etched in order to remove the bulk NMOS S / D contact 620 from the NMOS interconnect trench 1620 and preserve only the remaining individual NMOS S / D contacts 620 (which cover their respective NMOS channels 550 (shown in FIG. 5) of the NMOS device nanosheets 500N) to the gate extension region defined by the lateral recess of the nanosheets into the inner spacer or additional low-k spacer covering the gate structure.

[0075] Alternate integration would have the etch-selective cap 910 over the PMOS interconnect 1420 to be fully preserved which would allow for the removal of this challenging gap-filled carbon and recess step. In this manner, the bulk silicon or silicon germanium NMOS S / D contact 620 can be anisotropically etched away, leaving only the remaining individual NMOS S / D contacts 620, a gap-filled carbon material (e.g., the gap- filled carbon material 1710) could be deposited within the NMOS interconnect trench 1620 and the inter-tier via 1220 patterned and then transferred through the gap-filled carbon material, and then the etch-selective cap 910 could be opened. At this point the gap-filled carbon material could be ashed away.

[0076] FIG. 18 shows orthogonal cross-section perspective starting with the remaining NMOS S / D contacts 620 being confined to the gate extension region within the inner spacer.This is followed by the silicidation process where the optional gap-filled carbon material 1710 (shown in FIG. 17) is blocking the deposition of NMOS silicide 1810 on the upper-tier PMOS interconnect 1420, followedby ashing of the gap-filled carbon material 1710. Again, it is important to state that the gap-filled carbon material 1710 here is not necessary as any metal from the silicidation process will react with the silicon and / or silicon germanium NMOS S / D contacts 620 to form the NMOS silicide 1810 and not with a range of other metals which could be used as the interconnect metal, so a material such a titanium would be removed from the metal surface within the inter-tier via 1220 and only form the NMOS silicide 1810 on the surface of the NMOS S / D contacts 620.

[0077] Before the silicidation process in alternate integrations, an additional low- temp erature / highly in-situ doped growth of additional silicon or silicon germanium can be done to further extend the remaining NMOS S / D contacts 620 to a shape more consistent with the previous disclosure section where some volume of S / D material emanates out from the inner spacer and gate extension areas. This follow-up CVD epitaxy process is extremely slow; however, in this case only a very thin additional amount of epitaxy growth is required as the deposition will be done simultaneously among the remaining NMOS S / D contacts 620 for each nanosheet and not to a larger, bulk merged S / D contact structure.

[0078] FIG. 19 illustrates the process by which the NMOS interconnect 1920 and direct metal backside contacts (BSC) 1910 that are to connect to backside power or signal lines are formed. A masking layer 1930 is then patterned overtop of the NMOS buried oxide layer 530, with the NMOS interconnect 1920 and the backside contact 1910 “kept” through the masking layer 1930, and the metal unmasked by the masking layer 1930 is recessed to formed a recess 1940, which is then re-filled with a filler material (e.g., the buried oxide 530 or silicon oxide) and CMP to isolated the NMOS S / D contacts 620 not making any connection to the wafer backside.

[0079] In some embodiments, these steps can be removed from the integration flow if the initial self-aligned backside contact patterning illustrated in FIG. 5 is limited to just forming the BSC where there is to be a direct contact made. In this example, this additional processing step was maintaining in the flow in order to enable multiple types of backside connections.

[0080] FIG. 20 shows the patterning and etch transfer of a backside VSS rail 2010 which will make direct contract to the BSC 1910. The carrier wafer 1610 (shown in FIG. 16) can be polished and removed, and the semiconductor structure 500 can be re-flipped if it is desiredto have the top-side of the semiconductor structure 500 connect to a top-side power distribution network.

[0081] FIG. 21 is a flow chart of an exemplary method 2100 of fabricating a semiconductor structure (e.g., the semiconductor structure 500) that includes unmerged sidewall metal contacts according to some embodiments of the present disclosure. In various embodiments, some of the steps of the method 2100 shown can be performed concurrently or in a different orderthan shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. The method 2100 can start with step S2110, at which formed over a substrate can be a plurality of first channels that are stacked over each other and extend along a top surface of the substrate. For example, the PMOS channels 920 can be formed over the substrate 540, as shown in FIG. 9. The method 2100 can proceed to step S2120.

[0082] At step S2120, a first merged S / D contact (or a first merged sidewall metal contact) can be formed on the first channels. For example, the merged PMOS S / D contact 1020 can be formed on the PMOS channels 920, as shown in FIG. 10. In an embodiment, a first contact etch-stop layer (CESL) can be formed over the first merged S / D contacts. For example, the CESL 1030 can be formed overtop the merged PMOS S / D contact 1020, as shown in FIG. 10. In another embodiment, a first cladding material can be formed on the first merged S / D contact. For example, the CESL 710 (cladding material) can be formed on the merged PMOS S / D contact 1020, as shown in FIG. 10. The method 2100 can proceed to step S2130.

[0083] At step S2130, a first gate structure can be formed for each of the first channels. For example, the PMOS gate structure 1110 can be formed for each of the PMOS channels 920, as shown in FIG. 11. The method 2100 can proceed to step S2140.

[0084] At step S2140, a portion of the first merged S / D contact can be removed after the first gate structure is formed such that a first remaining individual S / D contact is formed on each of the first channels at one end thereof. For example, a portion of the merged PMOS S / D contact 1020 can be removed after the PMOS gate structure 1110 is formed such that the remaining individual PMOS S / D contact 1020 can be formed on each of the PMOS channels 920 at one end thereof, as shown in FIG. 13. In an embodiment, a first silicidation layer can be formed on at least one of the first remaining individual S / D contacts after the first gate structure is formed. For example, the PMOS silicidation layer 1410 can be formed on the remaining individual PMOS S / D contacts 1020 after the PMOS gate structure 1110 is formed, as shown in FIG. 14. The method 2100 can proceed to step S2150.

[0085] At step S2150, a first interconnect can be formed that connects the first remaining individual S / D contacts. For example, the PMOS interconnect 1420 can be formed that connects the remaining individual PMOS S / D contacts 1020, as shown in FIG. 14. As the first interconnect and the first silicidation layer are formed after the first gate structure is formed, the first interconnect and the first silicidation layer will not be impacted by the thermal process during which the first gate structure is formed.

[0086] FIG. 22 is a flow chart of an exemplary method 2200 of fabricating a semiconductor structure (e.g., the semiconductor structures 400 and 500) that includes sidewall metal contacts that are merged according to some embodiments of the present disclosure. In various embodiments, some of the steps of the method 2200 shown can be performed concurrently or in a different order than shown, can be substituted by other method steps, or can be omitted. Additional method steps can also be performed as desired. The method 2200 can also include steps S2110 to S2130. The method 2200 can proceed to step S2240.

[0087] At step S2240, a portion of the first merged S / D contact can be removed after the first gate structure is formed such that a plurality of first remaining S / D contacts that are merged are formed, each of the first remaining S / D contacts formed on a corresponding one of the first channels at one end thereof. For example, a portion of the merged S / D contact can be removed such that a plurality of remaining S / D contacts 21 OP (sidewall metal contacts) that are still merged are formed, as shown in FIG. 4. The method 2200 can proceed to step S2250.

[0088] At step S2250, a first interconnect can be formed that connects the first remaining S / D contacts that are merged.

[0089] In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.

[0090] Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed asto imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0091] “ Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the present disclosure. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a dielectric layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying dielectric layer or overlying dielectric layer, patterned or un-pattemed, but rather, is contemplated to include any such dielectric layer or base structure, and any combination of dielectric layers and / or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.

[0092] Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the present disclosure. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.

Claims

WHAT IS CLAIMED IS:

1. A method of fabricating a semiconductor structure that includes a plurality of unmerged source-and-drain (S / D) contacts, the method comprising: forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate; forming a first merged S / D contact on the first channels; forming a first gate structure for each of the first channels; removing a portion of the first merged S / D contact after the first gate structure is formed such that a first remaining individual S / D contact is formed on each of the first channels at one end thereof; and forming a first interconnect that connects the first remaining individual S / D contacts.

2. The method of claim 1, further comprising: forming a first silicidation layer on at least one of the first remaining individual S / D contacts.

3. The method of claim 2, wherein the first silicidation layer is formed after the first gate structure is formed.

4. The method of claim 1, further comprising: forming a first contact etch-stop layer (CESL) over the first merged S / D contact before the first gate structure is formed; and removing the first CESL after the first gate structure is formed.

5. The method of claim 1, further comprising: forming a first cladding material on the first merged S / D contact; and removing the first cladding material after the first gate structure is formed.

6. The method of claim 5, wherein the first cladding material is formed before the first gate structure is formed.

7. The method of claim 5, wherein the first cladding material includes silicon.

8. The method of claim 1, further comprising: forming a first epitaxy layer over at least one of the first remaining individual S / D contacts.

9. The method of claim 8, wherein the first epitaxy layer is formed after the first gate structure is formed.

10. The method of claim 8, wherein the semiconductor structure includes an N-type metal oxide semiconductor (NMOS), and the first epitaxy layer includes phosphorous - or arsenic-doped silicon or silicon germanium.11 . The method of claim 8, wherein the semiconductor structure includes a P-type metal oxide semiconductor (PMOS), and the first epitaxy layer includes boron -doped silicon or silicon germanium.

12. The method of claim 1, wherein a first interconnect trench is formed after the portion of the first merged S / D contact is removed, and the first interconnect is formed within the first interconnect trench.

13. The method of claim 1, wherein the first gate structure wraps around each of the first channels.

14. The method of claim 13, wherein forming the first gate structure includes: forming a first replacement gate structure that wraps around each of the first channels; and performing a replacement metal gate (RMG) module to replace the first replacement gate structure with the first gate structure.

15. The method of claim 1, further comprising: forming a first etch-selective cap over the first channels; forming over the first etch-selective cap a plurality of second channels that are stacked over each other and extend along the top surface of the substrate; forming on each of the second channels at one end thereof a second remaining individual S / D contact;forming a second gate structure for each of the second channels; and forming a second interconnect that connects the second remaining individual S / D contacts and connects the first interconnect through an inter-tier via formed within the first etch-selective cap.

16. The method of claim 15, further comprising: forming a second merged S / D contact on the second channels before the second gate structure is formed; and removing a portion of the second merged S / D contact such that the second remaining individual S / D contact are formed after the second gate structure is formed.

17. The method of claim 16, wherein a second interconnect trench is formed after the portion of the second merged S / D contact is removed, and the second interconnect is formed within the second interconnect trench.

18. The method of claim 15, wherein the semiconductor structure includes a complementary field-effective transistor (CFET) structure.

19. The method of claim 15, further comprising: forming a second etch-selective cap under the first interconnect.

20. A method of fabricating a semiconductor structure that includes a plurality of merged source-and-drain (S / D) contacts, the method comprising: forming over a substrate a plurality of first channels that are stacked over each other and extend along a top surface of the substrate; forming a first merged S / D contact on the first channels; forming a first gate structure for each of the first channels; removing a portion of the first merged S / D contact after the first gate structure is formed such that a plurality of first remaining S / D contacts that are merged are formed, each of the first remaining S / D contacts formed on a corresponding one of the first channels at one end thereof; and forming a first interconnect that connects the merged first remaining S / D contacts.

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