Level shifter and boot capacitor circuits, systems, and methods

Abstract

Circuits and methods are provided that more effectively and efficiently implement multi-level converter circuits. In some aspects, an integrated circuit is disclosed. In some embodiments, the integrated circuit includes a plurality of switching circuits comprising a first switching circuit, wherein the first switching circuit is configured to receive power supplied by a boot capacitor, and wherein the first switching circuit is configured to receive a first switch control signal. The integrated circuit may further include a monitor circuit configured to provide a status indictor of the boot capacitor; and a state selector configured to select a state of each of the plurality of switching circuits based on the status indicator and to provide the first switch control signal to the first switching circuit based on the selected state of the first switching circuit.

Description

LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODSGregory Szczeszynski and Gary WuCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of and priority to in their entirety the following United States Provisional Patent Applications filed on January 12, 2024, which are all incorporated by reference in their entirety:

[0002] Application No. 63 / 620,507 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0003] Application No. 63 / 620,623 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0004] Application No. 63 / 620,613 entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER;”

[0005] Application No. 63 / 620,465 entitled “STARTUP INTERLOCK FOR POWER CONVERTER CIRCUITS;”

[0006] Application No. 63 / 620,331 entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT;”

[0007] Application No. 63 / 620,450 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0008] Application No. 63 / 620,469 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0009] Application No. 63 / 620,678 entitled “RECONFIGURABLE MULTI-LEVEL POWER CONVERTER TO CHARGE PUMP MODE AND FRACTIONAL CHARGE PUMP MODE;”

[0010] Application No. 63 / 620,417 entitled “INPUT CURRENT SLEW FOR A MULTI¬LEVEL CONVERTER;”

[0011] Application No. 63 / 620,726 entitled “ADJUSTING OVERVOLTAGE PROTECTION BASED ON MODE OF OPERATION SYSTEMS AND METHODS;”

[0012] Application No. 63 / 620,737 entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL;”

[0013] Application No. 63 / 620,741 entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS;”

[0014] Application No. 63 / 620,527 entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS;”

[0015] Application No. 63 / 620,488 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0016] Application No. 63 / 620,553 entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS;”

[0017] Application No. 63 / 620,638 entitled “GENERAL STARTUP FOR MULTILEVEL POWER CONVERTER CIRCUITS;”

[0018] Application No. 63 / 620,733 entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER;”

[0019] Application No. 63 / 620,738 entitled “PREDICTIVE CONTROL LOOP PRECHARGING DURING A MULTI-LEVEL ZONE CHANGE;”

[0020] Application No. 63 / 620,764 entitled “DETECTOR CIRCUIT FOR DETECTING ONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROLLOOP CIRCUIT;”

[0021] Application No. 63 / 620,607 entitled “STARTUP VOLTAGE SELECTION FOR MULTI-LEVEL POWER CONVERTER CIRCUITS;”

[0022] Application No. 63 / 620,575 entitled “MULTI-LEVEL CAPACITOR FAULT DETECTION SYSTEMS AND METHODS;”

[0023] Application No. 63 / 620,582 entitled “PARALLEL OPERATION OF MULTILEVEL POWER CONVERTERS;” and

[0024] Application No. 63 / 620,763 entitled “AVERAGE AND PEAK CURRENT SENSE SYSTEMS AND METHODS.”BACKGROUND

[0025] This disclosure relates to electronic circuits, and more particularly for example to multi-level power converters.

[0026] Many electronic products, including mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD, LED displays, and the like) use multiple voltage levels for operation. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or more), whereas logic circuitry may operate at a relatively low voltage level (e.g., 1-3V) and other circuitry may operate at an intermediate voltage level (e.g., 5-10V).

[0027] Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUT is greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output.

[0028] One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled switches to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors”. When a fly capacitor is used (z.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it.

[0029] There is a continued need for improved circuits and methods for more effectively and efficiently operating and implementing various type of electrical circuits and devices, including for example multi-level converter circuits.SUMMARY

[0030] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing various electronics circuits, including multi-level converter circuits.

[0031] In some aspects, an integrated circuit is disclosed. In some embodiments, the integrated circuit includes a plurality of switching circuits comprising a first switching circuit, wherein the first switching circuit is configured to receive power supplied by a boot capacitor, and wherein the first switching circuit is configured to receive a first switch control signal. The integrated circuit may further include a monitor circuit configured to provide a status indictor of the boot capacitor; and a state selector configured to select a state of each of the plurality of switching circuits based on the status indicator and to provide the first switch control signal to the first switching circuit based on the selected state of the first switching circuit.

[0032] In some aspects, a system is disclosed. In some embodiments, the system includes a multi-level power converter that includes a plurality of field effect transistor (FET) switches connected in series, wherein the multi-level power converter is configured to receive a plurality of state selection signals, and wherein there is a one-to-one correspondence between the plurality of FET switches and the plurality of state selection signals. The multi-level power converter may further include a state selector configured to generate the plurality of state selection signals corresponding to states of the FET switches. The multi-level power converter may further include a plurality of counters, wherein there is a one-to-one correspondence between the plurality of counters and the plurality of state selection signals, and wherein the plurality of counters is configured to measure durations of off states of the plurality of FET switches and provide the durations of off states to the state selector, wherein state selector generates the plurality of state selection signals based on the durations of off states.

[0033] In some aspects, a method of operating an apparatus is disclosed. In some embodiments, the apparatus includes a plurality field effect transistor (FET) switches and a plurality of counters, wherein the plurality of counters is configured to measure durations of off states of the plurality of FET switches. The method of operating the apparatus may include monitoring the durations of off states of the plurality of FET switches; and generating a plurality of state selection signals for the plurality of FET switches based on the durations of off states.

[0034] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.DESCRIPTION OF THE DRAWINGS

[0035] FIG. 1 A is an example power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0036] FIG. IB is an example power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0037] FIG. 2A is an example dual integrated circuit (IC) power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0038] FIG. 2B is an example dual IC power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0039] FIG. 3A is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0040] FIG. 3B is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0041] FIG. 4 is a diagram illustrating an example charging function in step down regulation mode of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0042] FIG. 5 is a diagram illustrating an example charging function in step down divide by 3 charge pump mode, in accordance with one or more embodiments of the present disclosure.

[0043] FIG. 6 is a functional block diagram illustrating aspects of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0044] FIG. 7 is a block diagram illustrating an example system implementing a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0045] FIG. 8A is a circuit diagram illustrating an example 3-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0046] FIG. 8B is a circuit diagram illustrating an example 4-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0047] FIG. 8C is a circuit diagram illustrating an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0048] FIG. 9 is an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0049] FIG. 10 is a block diagram of an example embodiment of control circuitry for an -level converter cell, in accordance with one or more embodiments of the present disclosure.

[0050] FIG. 11 illustrates an embodiment of a multi-level power converter system, in accordance with one or more embodiments of the present disclosure.

[0051] FIG. 12 illustrates a detailed block diagram of an example level shifter / gate driver circuit connected to a switch, in accordance with one or more embodiments of the present disclosure.

[0052] FIG. 13 A illustrates a detailed diagram of example level-shifter circuitry, in accordance with one or more embodiments of the present disclosure.

[0053] FIG. 13B illustrates a further example of level-shifter circuitry, in accordance with one or more embodiments of the present disclosure.

[0054] FIG. 14 illustrates example operating condition ranges and thresholds as a function of a differential supply rail, in accordance with one or more embodiments of the present disclosure.

[0055] FIG. 15 illustrates another example of level-shifter circuitry, in accordance with one or more embodiments of the present disclosure.

[0056] FIG. 16 illustrates an example of a method of using level-shifter circuitry, in accordance with one or more embodiments of the present disclosure.

[0057] FIG. 17 illustrates a detailed block diagram of another example level shifter / gate driver circuit connected to a switch, in accordance with one or more embodiments of the present disclosure.

[0058] FIG. 18 illustrates another example of level-shifter circuitry, in accordance with one or more embodiments of the present disclosure.

[0059] FIG. 19 illustrates an example method of blanking in multi-level power converters, in accordance with one or more embodiments of the present disclosure.

[0060] FIG. 20 illustrates an example of a boot capacitor control system, in accordance with one or more embodiments of the present disclosure.

[0061] FIG. 21 illustrates another example of a boot capacitor control system, in accordance with one or more embodiments of the present disclosure.

[0062] FIG. 22 illustrates a method of controlling boot capacitor voltage, in accordance with one or more embodiments of the present disclosure.

[0063] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.DETAILED DESCRIPTION

[0064] The present disclosure encompasses novel circuits, architectures, systems, and methods that more effectively and efficiently address the configuration and operation of multilevel converter circuits. It will be appreciated that various improvements disclosed herein encompass innovative circuits, hardware components, architectures, and related logic that are applicable to applications beyond multi-level converter circuits.

[0065] FIGs. 1-6 illustrate various embodiments of a high efficiency 4-level step-down and step-up power converter for battery charging applications, such as single cell Li-ion and Li- polymer battery applications. In the illustrated embodiments, the power converter is configured to deliver up to 5 amperes (A) of charging current in regulation mode and in a divide-by-3 charge pump mode, though other configurations are within the scope of the present disclosure. The power converter can be configured, for example, into dual ICs operation for 9A charging current in regulation mode and in divide-by-3 charge pump mode. Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, where M >= 3.

[0066] In some implementations, for example, the power converter may supply an input range of approximately 4.5 V to 18 V input to support both universal serial bus (USB) and wireless inputs, and in a reverse step-up mode, the output may be programmable from 4.8 V to 16 V in 100 mV step with a programmable output current limit up to 1.7 A. This input voltage range may be used, for example, to support fast charging of single Li-Ion cells from USB and wireless input. It will be appreciated that other voltage and current ranges and limits may be implemented depending on the application. It will also be appreciated that while compatibility with USB is described herein, other wired interfaces and protocols may be implemented with the power converter of the present disclosure.

[0067] In various embodiments, the power converter may be implemented as a single integrated circuit (IC) (see, e.g., Figs. 1 A-B), dual-integrated circuits (see, e.g., Figs. 2A-B), or in other configurations depending on the implementation. In various embodiments, the power converter may operate as a parallel charger along with a main charger, as shown in Fig. 3B, to provide the desired functionality noted herein and, for example, as illustrated in Figs. 4 and 5 for the desired charging functionality for various applications, as would be understood by one skilled in the art. Fig. 3B may represent a system level point of view of a mobile architecturehaving a parallel charger and a main charger that accepts power from a wired port (e.g., a wired USB) or from a wireless interface. The parallel charger for one or more embodiments may represent an IC as illustrated in Figs. 1-3 A, for example, and may function to charge a battery for some portion of the charging profile (e.g., as shown in Figs. 4 and 5), while the main charger charges the battery for other portions of the charging profile. In various embodiments, the parallel charger may also be configured to function as the main charger as well, depending upon the desired application. The novel architecture disclosed herein may be implemented to enable (i) improved efficiency (e.g., at 9A charging current) in a low-profile solution; (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via interintegrated circuit (EC) technology; and / or (iv) full protection including input and output under voltage lockout (UVLO), input and output over voltage protection (OVP), input and output over current protection (OCP), and IC over-temperature with fault and warning status. In some implementations, the power converter supports divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and / or paralleled operation.

[0068] In the illustrated embodiments, the power converter is implemented as a multi-level charge pump incorporating power switches and control circuitry. The power converter’s internal bias may be provided by the system battery through a VOUT connection (e.g., pin). The charging input can be USB (or other wired input) or wireless input by an external FET register control. In some implementations, the power converter may be programmed to different operating modes, which may include a step-down regulation mode, a step-down divide-by-3 charge pump mode, and a reverse step-up mode.

[0069] In a step-down regulation mode, the power converter operates as a multi-level stepdown regulator to support USB power delivery (USB-PD) (or other wired protocol) or fixed input charging. During a constant-current (CC) phase, the maximum charging current may be limited for example, by configuring registers. When the input current does not reach a predetermined maximum input setting, the charge current is set to a predetermined maximum output setting. If the input current reaches the input maximum setting, then the charge current throttles and maintains input current at the input maximum setting. This allows maximum charging current while ensuring that the charge current does not go above a battery maximum current rating and the input current does not trip adapter over-current protection.

[0070] During a constant-voltage (CV) phase, the CV regulation may be limited, for example, by configuring registers. In operation, a single-wire sense pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value stored in a register, VOUT REG. The voltage differential between the battery’s positive terminal and negative terminal is sensed and compared to a predetermined value stored in a register, VBATT REG. In some implementations, a single-wire sense pin or other sensor senses VBATTP (battery voltage at positive terminal) and a single-wire sense pin or other sensor senses VBATTN (battery volage at negative terminal). The CV regulates to the lower of the two settings. If the VOUT sensed voltage reaches VOUT REG first, then CV is regulated to VOUT REG. If the VBATTP sensed voltage reaches VBATT REG first, then CV is regulated to VB ATT REG. This provides a fast battery top off while preventing voltage above safety limit.

[0071] In a step-down divide-by-3 charge pump mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a divide- by-3 step-down charge divider to support USB-Programmable Power Supply (USB-PPS) or other charging protocol or programmable input charging. In some embodiments, the power converter allows the USB-PPS adapter to control voltage and current and ignores conflicting settings (e.g., settings stored in registers for I0UT MAX, VOUT REG and VBATT REG). In this mode, the power converter monitors an IIN MAX setting, shuts down the power train (which includes switches to configure, enable and disable various modes of operation) and disconnects external FET when UN current exceeds IIN MAX setting. In the illustrated embodiment, the output current is up to 10A in dual IC operation and 5 A in single IC operation.

[0072] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register) the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to the VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit may be set, for example, by an IIN_MAX register.

[0073] In some embodiments, to enable the IC, both an EN pin and an IC EN bit are set to logic high (1). When either the EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC is enabled, the POR status bit sets to 1 to indicate the IC has a fresh power up.

[0074] In some embodiments, the power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs may be controlled by registers (e.g., 1 -bit registers V EXTG, EXTG EN and EXTGX). The V EXTG bit sets the gate drive voltage and can be set to 9V or 5 V, in the illustrated embodiment. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). In various embodiments, the external FET can be turned on or off independently from other IC operations except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled. When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respected FET would not turn on from the off mode.

[0075] In various embodiments, the power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path may be configured between the external FET on time and the power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train may be configured to turn on first before the master IC. The COMP, SYNC and SYNCH pins from two ICs gate the power train and synchronize the operation. The SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down the power train operation when fault is detected.

[0076] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates VIN pin to a VOUT REG programmable setting of 4.8V to 16V. The VIN output current limit is set by IIN_MAX register.

[0077] To enable the IC, both the EN pin and IC EN bit are set to logic high (1). When either EN pin or IC EN bit is set to logic low (0), the IC is disabled. After the IC enables, the POR status bit sets to 1 to indicate the IC has a fresh power up. The power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs are controlled by register bits, such as V EXTG, EXTG EN and EXTGX. The V EXTG bit sets the gate drive voltage and can be set to 9V or5V, for example. The EXTGX bits select which FET(s) to turn on. The EXTG EN bit enables the gate driver to turn on the selected FET(s). The external FET can be turned on or off independently from other IC operation except when the IC is disabled. The EXT EN IND status bit set to 1 when external FET is enabled.

[0078] When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respective FET would not turn on from off mode. The power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path should be given between external FET on time to power train on time to minimize in-rush current. Next, both PT EN pin and PT EN bit are set to logic high (1) to turn on the power train. When either PT EN pin or PT EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train is turned on before the master IC. The COMP, SYNC and SYNCH pins from the two ICs gate the power train and synchronize the operation. SYNC SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down power train operation when a fault is detected.

[0079] In accordance with various embodiments, an example power converter initialization, an example power up sequence, and an example fault handling will now be described for the three different operating modes. In an example step-down regulation mode, the initialization and power up sequence uses EXT1 as an example. The same sequence may apply to EXT2 with the only change in EXTGX bit and related EXT2 register settings. First, pull EN to logic high and then set IC EN bit= 1 at lOOus(TBD) after EN is logic high to enable IC. IC startup from POR stage, POR bit reports 1 indicating fresh IC startup. Next, the POR bit is read to confirm the IC is enabled. The FREQUENCY register is then set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage on the VOUT sense pin in CV operation. The VBATT REG register is set to the target regulation voltage on the VBATTP sense pin in CV operation. The IOUT MAX register is set to the target maximum charger current in CC operation, and the IIN MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers was set to a desired setting. Each Fault and Warning enables at a different time based on IC status and operating mode. The WATCHDOG register is then set to a desired setting.

[0080] The MODE register and other related registers are set for step -down regulation mode, including power train setup and enablement of an external FET, while checking for faults. In a dual IC operation, the external FETs are controlled by the master IC. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the external FET after the shutdown fault is initiated. Next, the power train is enabled. In a dual IC operation, the slave IC power train is turned on before the master IC. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation.

[0081] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0082] An example step-down divide-by-3 power converter mode initialization and power up sequence will now be described. The initialization and power up sequence uses EXT1 as an example, but it will be appreciated that the same sequence applies to EXT2 with a change in EXTGX bit and related EXT2 register settings. The EN is pulled to logic high and then IC EN bit=l at 100us(TBD) after EN is logic high to enable IC. The IC starts up from POR stage, POR bit reports 1 indicating fresh IC startup. The POR bit is read to confirm the IC is enabled. The FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The IIN MAX register is set to a value below the adapter current limit. VOUT REG, VBATT REG and I0UT MAX registers are not used in step-down divide-by-3 charge pump mode. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at different time based on IC status and operating mode.

[0083] The MODE register and other registers are set for step-down divide-by-three mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, abit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter.

[0084] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0085] An example reverse step-up mode initialization and power up sequence will now be described. This initialization and power up sequence uses EXT2 as an example, but the same sequence applies to EXT1 with the change in EXTGX bit and related EXT1 register setting. The value EN is pulled to logic high and then IC EN bit is set to 1 at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from the POR stage, and the POR bit reports 1 indicating a fresh IC startup. The POR bit is read to confirm the IC is enabled. Next, the FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT REG register is set to the target regulation voltage at VIN. Next, the IIN MAX register is set to the target current limit. VBATT REG and I0UT MAX registers are not used in reverse step-up mode. FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at a different time based on IC status and operating mode.

[0086] The MODE register and other registers are set for reverse step-up mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. In dual IC operation, the slave IC power train is turned on before the master IC and is controlled by the master IC.

[0087] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault. The EXT2 or VIN pins are not configured to detect OVP as it is set as the output in reverse step-up mode. But if EXT2 or VIN pin detects an OVP event, then IC STATUS1 and IC STATUS2 would report the fault event.

[0088] In an example system 700 illustrated in FIG. 7, a power converter 720 is implemented in a host 710 (e.g., a device or system) that includes a battery 730 and various system components 740. The host 710 may be any system or device that implements a power converter as described herein, including but not limited to a smart phone, tablet, portable electronics, a mobile device, low power electronics, and other electronic systems. The battery 730 may include one or more batteries that store electricity for use by the host 710, such as single cell Li-ion and Li-polymer batteries.

[0089] The power converter 720 may be configured to convert electricity stored in the battery 730 to a desired system voltage, VSYS, for powering various system components 740, which may include one or more logic devices 742, memories 744, communications components 746, input / output (I / O) components 748, circuitry 750, and other components 752. The power converter 720 may also supply power to one or more external devices 760, such as a component connected to the host 710 through a wired or wireless connection, such as a USB compatible device. The power converter 720 may also be configured to receive power from an external power source 712 and convert the received power to the battery 730 for storage, or to the system components 740 and / or external device 760, as applicable.

[0090] In various embodiments, the one or more logic devices 742 and memories 744 may be configured to perform operations of the host 710. A logic device 742 may be implemented as a general -purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), or other programmable logic device(s). The logic device 742 and other components may be configured through hardwiring, software execution, or a combination of both. In various embodiments, the host 710 includes one or more memory devices designed to retain data, such as software instructions for execution by the logic device. The memory may include volatile and non-volatile memories, such as random-access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile randomaccess memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory, hard disk drives, or other memory types. The logic device may be configured to execute software instructions residing in the memory, thereby accomplishing method steps and operations.

[0091] Referring to FIGs. 8A-8C, the converter circuit may be configured to switch between two or more switch states. One or more PWM duty cycle controllers may be provided to set the time in each switch state based on the voltage at VOUT. For example, FIG. 8A is a schematic diagram of a 3 -level DC-to-DC buck converter circuit 800 that may be used as the converter circuit 920 of FIG. 9. A set of four switches, S1-S4, is series-coupled between VIN and circuit ground. A fly capacitor Cl is coupled in series with switches S3 and S4, and in parallel with switches SI and S2. An inductor LI is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and the voltage across the output capacitor COUT is VOUT.

[0092] In the illustrated example, the presence of the single fly capacitor Cl in the converter circuit 800 enables four switch states that each generate one of three voltage levels at node Lx. In a first switch state, S2 and S4 are closed and SI and S3 are open, effectively bypassing Cl and connecting Lx to circuit ground (voltage level at Lx = GND). In a second switch state, S2 and S4 are open and SI and S3 are closed, effectively bypassing Cl and connecting Lx to VIN (voltage level at Lx = VIN). In a third switch state SI and S4 are open and S2 and S3 are closed, connecting Cl from VIN to LX, and thus charging Cl with inductor LI current flowing into a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2. In a fourth switch state, SI and S4 are closed and S2 and S3 are open, connecting Cl from Lx to GND and thus discharging Cl with inductor LI current flowing to a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2 (e.g., this may assume that Cl was previously charged in state three). Accordingly, the illustrated converter circuit 800 has two switch states that generate a voltage level of VIN / 2 at the Lx node.

[0093] If the converter circuit 800 is toggled between switch states three and four (avoiding switch state two that bypasses the fly capacitor Cl), the inductor LI sees small jumps in the voltage level at Lx, going from GND to only VIN / 2 and back to GND, which results in reducedvoltage ripple across the inductor LI and less filtering to smooth VOUT than a converter circuit with only SI and S2 switches.

[0094] Adding additional series switches Sx and fly capacitors Cx to the 2-level converter circuit 800 increases the number of switch states and resulting voltage levels between VEST and circuit ground that can be applied to the Lx node, thus generating an even smaller voltage ripple across the inductor L. This reduces the filtering requirements to get a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, e.g., FIG. 8B) includes 6 series- coupled switches S1-S6 and two fly capacitors Cx (X = 2). Consequently, a 4-level converter circuit can define 4 voltage levels (VIN, GND, ’AVIN, and %VIN) at node LX from 8 switch states (3 switch states result in the ’AVIN level at Lx, and 3 other switch states result in the %VIN level at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next higher voltage level available. For higher output voltages, the switching pattern may never use GND. For example, in a 4-level converter circuit, an output VOUT set to 0.5*VIN can be achieved by alternating the Lx node between % VIN and ’A V.

[0095] A different interpretation of a multi-level converter circuit is that the fly capacitors Cx create a charge-pump for the buck converter circuit. Unlike a standard charge-pump where the output is restricted to one output, a multi-level converter circuit allows the fly capacitors Cx to be coupled to create multiple intermediate voltages. For the 4-level example, the two fly capacitors each act as a ’A charge-pump with the additional benefit that any input voltage that is a sum of ’A ratios can be created, including VIN and GND.

[0096] A multi-level converter circuit couples the fly capacitors Cx in different combinations in order to bring the voltage level at the Lx node down or up. As noted above, when a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it, which creates a control problem in maintaining an average voltage.

[0097] Resolving the charge-balance problem so as to maintain an average voltage across the single capacitor in a 3 -level converter circuit will now be described. For example, in a 3- level converter circuit, one way to generate the Level-1 (GND) and Level-3 (VIN) voltage levels at the Lx node is to not use the fly capacitors Cl for these Lx voltage levels. However, for the Level 2 (VIN / 2) voltage level at Lx, two separate switch states can be used: one switchstate charges the capacitor (S3 and S2 closed, SI and S4 open) and the other switch state discharges the capacitor (S3 and S2 open, SI and S4 closed). The control of a 3-level converter circuit may operate such that each time the converter circuit switches states to Level-2, a controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide on a charging state or a discharging state. For instance, if the capacitor voltage is below VEN / 2, then a controller would select charge (the third switch state), and if the capacitor voltage is above VIN / 2, then the controller would select discharge (the fourth switch state).

[0098] Referring to FIGs. 8B, a 4-level converter circuit 830 (X = 2) illustrates the chargebalance difficulty when more capacitors are present. A Level-1 voltage level (GND) and a Level-4 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’A VIN) and Level-3 voltage level (% VIN) at Lx each can be achieved by any of three different switch states. At higher orders of a multi-level converter circuit (X > 2), more switch states are possible for generating the intermediate levels between VIN and GND. The problem gets more complicated with a 5-level converter circuit (X= 3). A Level-1 voltage level (GND) and a Level-5 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level (’AVIN) and Level-4 voltage level (3A VIN) at Lx each can be achieved by any of four different switch states, the Level-3 voltage level (2 / 4 VIN) at Lx can be achieved by any of six different switch states.

[0099] As should be clear from these examples, determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. As previously noted, most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of switch states generally assume that all system variables - such as input voltage and output current - are constant during the sequence. This is unrealistic for a real- world environment, where all system variables tend to be dynamic.

[0100] In a 2-Level example, the converter circuit switches between two switch states: SI closed and S2 open (voltage level at Lx = VIN), or SI open and S2 closed (voltage level at Lx = GND). A PWM duty cycle controller sets the time in each switch state based on the voltage at VOUT, which determines the amplitude of the average voltage at Lx (noting that, the average Lx voltage in theory is equal to the VOUT average voltage, but that, due to parasitics, the Lx average voltage is higher and / or lower (for negative currents) than the VOUT average). As canbe appreciated, the inductor L sees large jumps in the voltage level at Lx, from GND to VIN and back to GND. The resulting voltage ripple across the inductor L necessitates a significant amount of filtering to smooth VOUT.

[0101] An alternative way of reducing the voltage ripple across the inductor L is to add more series switches as well as charge transfer capacitors as energy storage elements to transfer charge from VIN to VOUT. AS noted above, such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of a converter circuit. The presence of X fly capacitors Cx defines a multi-level capacitive converter circuit capable of generating M=X+ 2 voltage levels at node Lx from 2(y+1)switch states.

[0102] FIG. 8C is schematic diagram of a generalized A7-level multi-level converter cell 870 that may be used as the converter circuit 920 of FIG. 9. A set of switches, Sl-S[2*( f- 1)], is series-coupled between VIN and circuit ground. The set of switches are organized in switch pairs: SI & S2, S3 & S4, ... S[2*( f- 2)+l] & S[2*( f- 1)]. A set ofM- 2 fly capacitor Cx is coupled in series with certain respective switches, and in parallel with switches in between those switches. In terms of switch pairs, there are M~ 1 pairs of switches, or one more than the number of fly capacitors. An optional inductor L is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and again the voltage across the output capacitor COUT is VOUT. The inductor L doubles as a virtual current source that facilitates movement of charge between the fly capacitors Cx. This creates a very efficient form of charge transfer, but introduces the problem of charge-balancing the fly capacitors Cx.

[0103] In various embodiments, each fly capacitor Cx has a first terminal coupled between an outer high-side switch S[2*x + 1] and an inner high-side switch S[2*x-1], where “high- side” refers to the VIN side of the converter circuit. Each fly capacitor Cx has a second terminal coupled between an outer low-side switch S[2*x + 2] and an inner low-side switch S[2*x], where “low-side” refers to the circuit ground (GND) side of the converter circuit. Thus, for an M= 3 multi-level converter cell, a first terminal of the single (X= 1) fly capacitor Cl would be coupled between outer high-side switch S3 and inner high-side switch SI, and a second terminal of the capacitor Cl would be coupled between inner low-side switch S2 and outer low-side switch S4. Accordingly, each fly capacitor Cx within the multi-level converter cell 870 has four switches that can affect current flow through that fly capacitor Cx.

[0104] In some embodiments, a voltage detector, which may be a simple comparator-type circuit, is provided to sense the voltage across a corresponding fly capacitor Cx with respect to a reference voltage, VREF, which represents a desired target voltage for the fly capacitor Cx. Every fly capacitor Cx may have a target average voltage in order to maintain proper output level. For an A-f-level converter and capacitor Cx, where x = 1, 2, ... [M~ 2], its target voltage is:Vtarget

[0105] The voltage detector may be configured to output a HIGH / LOW status signal, CT.v _H / L, indicating with the voltage across the corresponding fly capacitor Cx is greater than VREF or less than VREF. The CFX_H / L status signal is coupled to control circuitry for the switches associated with the fly capacitor Cx.

[0106] The control circuitry for the four switches that can affect current flow through a fly capacitor Cx set states for those switches in part as a function of the voltage across the fly capacitor Cx as measured by the associated voltage detector and conveyed by the CT.VH / LX status signal. Accordingly, for ease of understanding, it can be said that each fly capacitor Cx “controls” its own pairs of high-side and low-side switches. If it is assumed that current flow in the inductor is charging the output VOUT, there are four possible states that can be defined for the pairs of high-side and low-side switches for each fly capacitor Cx.

[0107] In a switch state in which the outer high-side and inner low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a charging configuration (whether or not charging actually occurs may depend on the switch states for other fly capacitors Cx). In a switch state in which the inner high-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a discharging configuration (whether or not discharging actually occurs may depend on the switch states for other fly capacitors Cx). In a switching state in which the inner low-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be bypassed. In a switching state in which the outer high-side and inner high-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would again be bypassed.

[0108] While each fly capacitor Cx can control both of its own pairs of high-side and low- side switches, in general, methods of control disclosed herein may utilize either the outer switches or the inner switches controllable by each corresponding capacitor. For example, referring to FIG. 8B, in “outer-switch” methods, fly capacitor Cl will control its outer switches S3 and S4, fly capacitor C2 will control its outer switches S5 and S6, etc. Conversely, for example, in “inner-switch” methods, fly capacitor Cl will control its inner switches SI and S2, fly capacitor C2 will control its inner switches S3 and S4, etc. The switch states of either pair (inner or outer) of switches controlled by a fly capacitor Cx may be complementary - that is, no fly capacitor Cx closes or opens both of its high-side and low-side controlled switches at the same time. If each fly capacitor Cx controls its outer-switches, then no fly capacitor controls the left-over innermost switches SI and S2. If instead each fly capacitor Cx controls its inner- switches, then no fly capacitor controls the left-over outermost switches S[2*(A / -1)] and S[2*(A / -2)+l], Switch states for the left-over switches are also complementary.

[0109] FIG. 9 is a high-level block diagram of an example circuit that includes a power converter 900, in accordance with one or more embodiments of the present disclosure. In the illustrated example, the power converter 900 includes a converter circuit 920 and a controller 910. The converter circuit 920 and controller 910 may be configured to implement, for example, any of the multi-level power converter circuits as previously described with reference to FIGs. 1 A-8C, and as described further herein. In the illustrated embodiment, the converter circuit 920 is configured to receive an input voltage VIN from a voltage source and transform the input voltage VIN into an output voltage VOUT. In some embodiments of the power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator(s), a clock generator, a voltage control circuit, etc., may also be present and coupled to the converter circuit 920 and the controller 910.

[0110] The controller 910 receives a set of input signals and produces a set of output signals. Some of these input signals arrive along a signal path connected to the converter circuit 920. These input signals carry information that is indicative of the operational state of the converter circuit 920. The controller 910 may also receive a clock signal CLK (for synchronous converter circuits 920) and one or more external input / output signals VO that may be analog, digital (encoded or direct signal lines), or a combination of both. Based upon the received input signals, the controller 910 produces a set of control signals back to the converter circuit 920 that control the internal components of the converter circuit 920 (e.g., internal switches, suchas low voltage FETs / MOSFETs) to cause the converter circuit 920 to boost or buck VEST to VOUT. In some embodiments, an auxiliary circuit (not shown) may provide various signals to the controller 910 (and optionally directly to the converter circuit 920), such as the clock signal CLK, the input / output signals VO, as well as various voltages, such as a general supply voltage VDD and a transistor bias voltage VBIAS.[OHl] FIG. 10 is a block diagram of one embodiment of advanced control circuitry 1000 for an -level converter cell 1000 such as the generalized version depicted in FIG. 8B. The M- level converter cell 1020 is shown coupled to an output block 1001 comprising an inductor L and an output capacitor COUT (conceptually, the inductor L also may be considered as being included within the A / -level converter cell 1020). The advanced control circuitry 1000 functions as a control loop coupled to the output of the A / -level converter cell 1020 and to switch control inputs of the A / -level converter cell 1020. In general, the advanced control circuitry 1000 is configured to monitor the output (e.g., voltage and / or current) of the AT-level converter cell 1020 and dynamically generate a set of switch control inputs to the V-level converter cell 1020 that attempt to stabilize the output voltage and / or current at specified values, taking into account variations of VIN and output load. In alternative embodiments, the advanced control circuitry 1000 may be configured to monitor the input of the AAlevel converter cell 1020 (e.g., voltage and / or current) and / or an internal node of the A- / - level converter cell 1020 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the advanced control circuitry 1000 may be configured to monitor the voltage and / or current of a node (e.g., input terminal, internal node, or output terminal) of the A- / - level converter cell 1020. The advanced control circuitry 1000 may be incorporated into, or separate from, the overall controller for a power converter 100 embodying the A / -level converter cell 1020.

[0112] A first block comprises a feedback controller 1002, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-ON- time controller, a hysteretic controller, or any other variant. The feedback controller 1002 is shown as being coupled to VOUT from the A / -level converter cell 1020. In alternative embodiments, the feedback controller 1002 may be configured to monitor the input of the M- level converter cell 1020 and / or an internal node of the A / -level converter cell 1020. The feedback controller 1002 produces a signal directly or indirectly indicative of the voltage at VOUT that determines in general terms what needs to be done in the multi-level converter cell1020 to maintain desired values for VOUT: charge, discharge, or tri-state (z.e., open, with no current flow).

[0113] In the illustrated example, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and a PWM generator 1008. The feedback circuit 1004 may include, for example, a feedback-loop voltage detector which compares VOUT (or an attenuated version of VOUT) to a reference voltage which represents a desired VOUT target voltage (which may be dynamic) and outputs a control signal to indicate whether VOUT is above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

[0114] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 may be implemented in known manner, and may include LC and / or RC circuits.

[0115] The PWM generator 1008 generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the multi-level converter cell 1020. In addition, in some embodiments, the PWM generator 1008 may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOUT and the reference voltage (thus indicating that some levels of the A-f-level converter cell 1020 should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., whether VOUT is greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit 1006, or from the output of the feedback circuit 1004, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUT is from a target output voltage, thus allowing faster charging of the inductor L if the VOUT is severely under regulated.

[0116] A second block comprises a multi-level controller 1010, the primary function of which is to select the switch states that generate a desired VOUT while maintaining a chargebalance state on the fly capacitors within the A-f-level converter cell 1020 every time an output voltage level is selected, regardless of what switch state or states were used in the past.

[0117] The multi-level controller 1010 includes a Voltage Level Selector 1012 which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector 1012 may be coupled to VOUT and / or VIN, and, in some embodiments, to the HIGH / LOW status signals, C .- _H / L, from the voltage detectors coupled to corresponding fly capacitors Cx within the AT-level converter cell 1020. A function of the Voltage Level Selector 1012 is to translate the received signals to an output voltage Target Level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector 1012 typically will consider at least VOUT and VIN to determine which Target Level should charge or discharge the output of the AT-level converter cell 1020 with a desired rate. For example, in a 6-level converter circuit, the available Target Levels are Level-1 (GND), Level-2 (1 / 5VIN), Level-3 (2 / 5VIN), Level-4 (3 / 5VIN), Level-5 (4 / 5VIN), and Level-6 (VIN), which may be represented as a count value from 1-6 (or 0-5).

[0118] As an example, in a 4-Level converter circuit, if VIN = 12V and VOUT nominally should be 3 V, then the Voltage Level Selector 1012 may indicate that a Target Level of “2” can be selected, which results in a 1 / 3 VIN voltage level at Lx (i.e. , 4V). The PWM control signal sets a duty cycle between that Target Level and another Target Level (e.g., GND) so that the average voltage level at Lx will be about 3 V.

[0119] In general, for steady-state operations, the Target Level voltage closest to VOUT that either charges or discharges the inductor L may be selected for simplicity of the selection algorithm. In general, for transient response, a Target Level that is higher (for charging) or lower (for discharging) than the closest Target Level may be selected to quickly charge or discharge the inductor L. The Voltage Level Selector 1012 may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. In some embodiments, the Voltage Level Selector 1012 can implement advanced methods (described below) that try to speed up charging or discharging based on additional factors, such as inductor voltage drop, load transients, the magnitude of output deviations, and / or external input signals from external sources. The output of the Voltage Level Selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) as well as switch state.

[0120] The output of the Voltage Level Selector 1012 is coupled to a Multi-Level Switch State Selector 1014, which generally would be coupled to the status signals, CT.v _H / L, from the voltage detectors for the fly capacitors Cx. Taking into account the Target Level generated bythe Voltage Level Selector 1012, the Multi-Level Switch State Selector 1014 determines a pattern of switch states for the desired output level that generally achieves charge-balancing the fly capacitors Cx. The Multi-Level Switch State Selector 1014 may be implemented, for example, as comparison circuitry and combinatorial logic, as a look-up table (LUT), or as more generalized processor circuitry. The output of the Multi-Level Switch State Selector 1014 is coupled to the switches of the multi-level converter cell 1020 (through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes a pattern of switch state settings determined by the Multi-Level Switch State Selector 1014. The pattern of switch state settings selects the configuration of the switches within the multi-level converter cell 1020.

[0121] In general (but not always), for PWM-based control systems, the Voltage Level Selector 1012 and the / W-level Switch State Selector 1014 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector 1012 selects which level results in charging of the inductor L and the A-f-level Switch State Selector 1014 sets which version to use of that level. Then when the PWM signal goes low, the Voltage Level Selector 1012 selects which level can discharge the inductor L and the A-f-level Switch State Selector 1014 sets which version of that level to use. Thus, the Voltage Level Selector 1012 and the AT-level Switch State Selector 1014 generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signal to change the state of the Voltage Level Selector 1012. Further, there may be situations or events where it is desirable for the CFX H / L status signal(s) to cause the A-f-level Switch State Selector 1014 to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the Al- level Switch State Selector 1014 to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

[0122] One notable benefit of the control circuitry shown in FIG. 10 is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

[0123] In alternative unregulated charge-pumps embodiments, the feedback controller 1002 and the Voltage Level Selector 1012 may be omitted, and instead a clock signal CLKmay be applied to the A7-level Switch State Selector 1014. The A7-level Switch State Selector 1014 would generate a pattern of switch state settings that periodically charge balances the fly capacitors Cx regardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VIN changes or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors Cx.

[0124] In some embodiments, the A / -level Switch State Selector 1014 may take into account the current II flowing through the inductor L by way of an optional currentmeasurement input 1016, which may be implemented in conventional fashion.

[0125] In an A / -level multi-level converter circuit, the configuration of switches that achieves Level-1 (e.g., GND) or Level -A / (e.g., VIN) effectively bypasses the fly capacitors Cx. Conversely, for all intermediate voltage levels, at least one fly capacitor Cx is coupled to VOUT and there are always at least two configurations of switches that can achieve any intermediate voltage level. For any particular intermediate voltage level, at least one configuration of switches results in charging the associated fly capacitor and at least one other configuration of switches results in discharging the associated fly capacitor. One aspect of the present disclosure is the realization that any achievable output voltage VOUT requiring intermediate voltage levels can be attained by dynamically selecting patterns of switch configurations - that is, by selecting switch configurations without regard to or memory of the switch configurations of any previous switching cycle - to select appropriate Levels, and doing so in a way that purposefully selects either charging or discharging switch configurations that also balance charge across the fly capacitors Cx.

[0126] Embodiments of the disclosure use the following approach for positive inductor L current (charging VOUT):(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer high-side switch in outer-switch control methods, or the inner low-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer low-side switch for outer-switch control methods, or the inner high-side switch for inner-switch control methods).

[0127] For negative inductor L current (discharging VOUT), the selection of switches inverts. Accordingly:(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer low-side switch in outer-switch control methods, or the inner high-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer high-side switch for outer-switch control methods, or the inner low-side switch for inner-switch control methods).

[0128] Note again that whether or not charging actually occurs for a particular fly capacitor Cx generally depends on the switch states for all other fly capacitors. For a fly capacitor C(x) to actually charge or discharge, the next inward (if one exists) fly capacitor C(x 7) (for outerswitch control methods) or the previous outward (if one exists) fly capacitor C(x+7) (for inner- switch control methods) must be set to the opposite state (z.e., discharge or charge) so that a bypass situation does not occur.

[0129] For any multi-level converter circuit of order M that can create M voltage levels - z.e., Level-1 (e.g., GND) through Level -M (e.g., VIN) - then the following switch count rules apply for any Level -m:(1) - zzz low-side switches must be set to be closed (ON);(2) m - 1 high-side switches must be set to be closed (ON); and(3) switches that are not required to be ON must be set to be OFF (open).

[0130] With these switch count rules in mind, the following generalized capacitor control method applies for each state change of the Multi-Level Switch State Selector 1014:Step 1) Select a fly capacitor that has not previously been selected;Step 2) If the voltage of the selected fly capacitor is above its Vtarget and there are remaining (z.e., not been set by this method in this cycle) low-side or high-side switches that can be set to be closed to enable a discharge path for the selected fly capacitor, then set those switches that enable a discharge path for the selected fly capacitor to be closed, decrement one or more appropriate counters (e.g., for the number of low-side switches set to be closed and the number of high-side switches set to be closed), and flag the current fly capacitor as “done” (z.e., as having been selected); otherwise (since the voltage of the selected fly capacitor is below its Vtarget) set the switches that enable a charging path for the selected fly capacitor to be closed and flag the current fly capacitor as “done”;Step 3) Loop to Step 1 until all fly capacitors have been selected;Step 4) For the remaining pair of left-over switches, set the high-side switch or the low-side switch to be closed based on the switch count rules and the counter values.

[0131] With the above generalized capacitor control method, more specific multi-level charge-balancing control methods can be created. Examples can be found, for example, in U.S. Patent Publication No. 20230148059, which is incorporated by reference herein in its entirety.

[0132] Power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, Universal Serial Bus (USB) or USB-C power sources, or a rectified AC power source that is converted to DC. Some power converters, such as multi-level power converters, employ one or more switched capacitor networks. Some multilevel power converters use capacitors as the primary energy storage elements to transfer power from the input to the output of the circuit. A series of switches, such as transistors used as switches, may be used to place a power converter in different states to charge or discharge capacitors as needed. These charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of the switches and associated control circuitry.

[0133] Low- Voltage Level Shifters

[0134] As multi-level converter circuits employ an increasing number of fly capacitors and associated power levels, voltages applied to internal circuitry can vary greatly. Thus, it can be important for internal circuitry to be designed to accommodate a range of voltages.

[0135] In a multi-level converter, and as explained more fully below, it can be beneficial for a level shifter to be able to operate with an upper supply rail voltage range from 5.5V to as low as 2.4V using 5V MOSFETs. It may also be beneficial for a high level-shifting voltage difference between a lower supply rail and an upper supply rail. It may further be beneficial for an upper supply level to drop below the lower supply VSS1 level by a body diode voltage drop. Embodiments of level-shifter circuitry are presented herein to achieve these benefits.

[0136] A simplified diagram of an embodiment of a multi-level power converter system 1100 is illustrated in FIG. 11, in accordance with one or more embodiments of the present disclosure. As shown, the system 1100 includes circuitry 1150 that may be implemented on an integrated circuit. The system 1100 further includes a series of boot capacitors (labeled asCBOOT), fly capacitors Ci and C2, inductors LI and L2, a load 1160, a sense resistor (labeled as “R Buck Sense”), and an output capacitor (Cout) connected as shown. Circuitry 1150 may represent an embodiment of an IC described previously with respect to FIGS. 1- 3 A, and various signal lines internal to circuitry 1150 may be connected to pins or other types of connections on integrated circuit, such as pins / connections denoted as CA, CB, PA, and PB. Note that boot capacitors may also be referred to as bootstrap capacitors in the art.

[0137] Circuitry 1150 includes field-effect transistors (FETs) QI to Q6 connected in series as shown. The FETs QI to Q6 may be implemented as switches, where the on / off (closed / open) state of each FET is controlled by a corresponding gate voltage generated by a level shifter / gate driver circuit. Circuitry 1150 includes level shifter / gate driver circuits 1102- 1112, and these level shifter / gate driver circuits 1102-1112 are controlled by a state select circuit 1140. The state select circuit 1140 provides inputs (labeled generically as 1130) to each level shifter / gate driver circuit 1102-1112, and the level shifter / gate driver circuits 1102-1112 in turn control the on / off states of FETs QI to Q6. Thus, the state select circuit 1140 repeatedly selects the states of FETs QI to Q6 during operation of the system. The states of FETs QI to Q6 at a given point in time may collectively be referred to as a power state. The system 1100 may implement a four-level multi-level power converter because the voltage supplied to node LX1 may be one of four levels, depending on the states of the switches QI to Q6. The circuitry 1150 includes capacitors Ci and C2 that are charged to a target voltage range during steady-state operation. For example, in some embodiments, the voltage across C2 is maintained at around Vin / 3, and the voltage across Ci is maintained at around 2Vin / 3. State select circuit 1140 may also control FET Q7, which can connect inductor L2 in parallel with LI as needed.

[0138] The circuitry 1150 further includes boot capacitor charging circuits 1164 to 1172 configured to facilitate charging of boot capacitors CBOOT. AS shown, various signals may be fed back to circuitry 1150. State select circuit 1140 may use various inputs, such as signals external to the circuitry 1150 fed back to the circuit as shown and / or signals internal to the circuit 1150 fed back to the state select circuitry 1150. Signals fed into state select circuit are illustrated generically as 1120. For example, state select circuit 1140 may use indications of voltages of capacitors Ci and C2, and / or indications of voltages or currents involving boot capacitors CBOOT, as described herein.

[0139] FIG. 12 illustrates a detailed block diagram of an example level shifter / gate driver circuit 1200 connected to a switch implemented as a FET 1210, according to some aspects of the present disclosure. The level shifter / gate driver circuit 1200 includes a level shifter 1202 and gate driver 1204 connected as shown. An input switch control signal is applied to the input of a level shifter 1202 that is coupled to a general system supply voltage VDD and to the voltage VcAPn across an associated boot capacitor C / / , as well as to a local reference potential (the source of an associated NFET power switch Q / / ). The voltage VCAP„ may be, for example, about 5V above the local reference potential or may be as low as 2.4V above the local reference potential. A level shifter translates an input signal from one voltage domain (e.g., digital logic voltages) to another voltage domain (e.g., transistor control voltages). The output of the level shifter 1202 thus follows the input switch control signal but in a different voltage range.

[0140] The output of the level shifter 1202 is applied to the input of a driver 1204 that is coupled to the voltage VCAP„ across an associated boot capacitor C / / , as well as to a local reference potential (the source of an associated NFET power switch Qw). The level shifter 1202 may have either a non-inverting or an inverting output (as indicated by the dotted circle 1206) that is coupled to the gate of an associated NFET power switch Q / / (e.g., high-side NFET power switches and the low-side NFET power switches receive complementary control clock signals, hence the potential need for different output polarities). In some embodiments, the gate driver 1204 may comprise one or more inverters or buffers, and the number of constituent inverters and / or buffers within the driver 1204 may be adjusted to accommodate signal delay requirements of a particular application. In general, it may be useful to design the driver 1204 so that it may be placed into a high impedance (high-Z) output state.

[0141] An optional resistor Rw may be coupled between the output of the driver 1204 (and hence also to the gate of the associated NFET power switch Q / z) and the local reference potential (and hence also to the source of the associated NFET power switch Qw). The resistor R / z preferably has a reasonably high resistance (e.g, 100 k or more) that does not interfere with normal control of the associated power switch Q / z by the circuit 1200, but allows draining of charge from the gate of the associated NFET power switch Q / z to maintain that power switch in an OFF state. This capability is useful by creating a known system state (z.c., a default OFF state for the NFET power switches M / z) if the driver 304 is not fully powered and operational or if the corresponding circuit 1200 is placed in a high-Z state.

[0142] As noted above, power to each level shifter / driver circuit 1200 is provided by charge stored on a corresponding bootstrap capacitor Cn (in this example, n = 1 . . .6) coupled to a VcAPn voltage input of the level shifter / gate driver circuit 1200. Each boot capacitor Cn is preferably sized to provide at least sufficient charge, with minimal voltage drop, to allow the associated level shifter / gate driver circuit 1200 to switch the state of the associated NFET power switch Qn. Generally, each boot capacitor Cn may lose charge in switching the gate of the associated FET switch Qn. Further, the bootstrap capacitors Cn may lose charge even when not switching an associated power switch, such as through DC current drain from other connected circuitry (e.g., bias currents for analog circuits). Accordingly, the boot capacitors Cn may need to be periodically recharged during normal operation to replenish lost charge. Exemplary techniques are presented later herein for replenishing lost charge.

[0143] FIG. 13 A illustrates a detailed diagram of example level-shifter circuitry 1300, in accordance with one or more embodiments of the present disclosure. For example, in some embodiments, the level shifter 1202 of FIG. 12 may be implemented using the level-shifter circuitry 1300. As shown, the level-shifter circuitry 1300 includes an input circuit 1340, output buffers 1310 and 1330, and memory cell 1320. NMOS FETs are labeled as “MNn” and PMOS FETs are labeled as “MPn,” where “n” denotes an associated numbering. The memory cell 1320 is implemented as a cross-coupled inverter latch. The buffers 1310 and 1330 are optional components. One function of the level-shifter circuitry 1300 is to transmit logic level change from the input pin (IN) at the lower supply rail (VDD1 / VSS1) to the outputs (OUTA / OUTB) at the upper supply rail (VDD2 / VSS2).

[0144] FIG. 13B illustrates a further example of level-shifter circuitry 1390, in accordance with one or more embodiments of the present disclosure. OUTA and OUTB may represent the outputs from level-shifter circuitry 1300 in FIG. 13A, and level-shifter circuitry 1390 may add internal blanking signal functionality to level-shifter circuitry 1300. In some embodiments, the level-shifter circuitry 1300 and 1390 are combined and used to implement a level shifter, such as the level shifter 1202 in level shifter / gate driver circuit 1200.

[0145] The level-shifter circuitry 1390 includes a blanking circuit 1370 that introduces a delay that holds the gate-drive signal for a blanking interval. This blanking interval prevents the gate-drive signal from changing during this time. The blanking interval begins with the selection of the fast bit and lasts at least long enough so that, by the time the blanking intervalhas finished, the slow bit will already have been presented to the multiplexer 1350. The latch 1360 is an SR latch that may serve two functions.

[0146] Prior to the memory transition, the latch 1360 stores the value of the most recently read fast bit. This provides the a priori knowledge that the multiplexer 1350 needs to know which of the OUTA and OUTB signals holds the new fast bit. Then, after the multiplexer 1350 has read the new fast bit from the appropriate one of the OUTA and OUTB signals, the latch 1360 locks the value of the new fast bit.

[0147] The operation of level-shifter circuitry 1300 is described with reference to FIG. 14, which illustrates example operating condition ranges and thresholds as a function of the differential upper supply rail voltage (VDD2-VSS2). Since the level-shifter circuitry 1300 may be used to receive switch control signal as shown in FIG. 12, the input logic IN is illustrated as receiving a switch control signal in this example.

[0148] As an example of operation, as in input logic (IN) changes from low-to-high, node N1 is pulled down from a VDD2 voltage level through devices MN7, MN5 and MP5. As node N1 voltage drops below the MP2 / MN2 inverter trip-point threshold, the cross-coupled latch 1220 flips state. To pull node N1 below the MP2 / MN2 inverter trip-point threshold, there are at least two factors that are working against it: 1) the threshold voltage (Vth) of MP5 and its strength (gm) limits how low N1 voltage can drop; and 2) a high inverter trippoint above the lowest voltage node N1 can be pulled is needed, but high inverter trip-point also means that inverters MP1 / MN1 and MP2 / MN2 have much larger PMOS devices compared to NMOS devices, which worsens the ability for MP5 to pull N1 low due to MP5 fighting against a large MP1 that is pulling high. MP5 may need to be much larger than MP1 to meet these criteria. However, a large MP5 device may have an additional undesirable effect of slowing down the speed due to a large capacitance of MP5.

[0149] Also, as VDD2 / VSS2 voltage rail is reduced, it becomes increasingly difficult for MP5 to fight against MP1 pull-up and pull down past the inverter trip-point due to the fixed MP1, MN1 and MP5 voltage thresholds (Vths) as shown in FIG. 14. The voltage thresholds (Vths) are relatively fixed, so as the difference VDD2-VSS2 voltage drops, the functional range may collapse and disappear below certain VDD2 / VSS2 voltage rail levels.

[0150] As explained earlier, in a multi-level converter, it can be beneficial for a level shifter to be able to operate with an upper supply rail voltage range (VDD2-VSS2) from 5.5Vto as low as 2.4V using 5V MOSFETs. It may also be beneficial for a high level-shifting voltage difference between a lower supply rail and an upper supply rail. It may further be beneficial for the upper supply VSS2 level to drop below the lower supply VSS1 level by a body diode voltage drop. Embodiments of level-shifter circuitry are presented herein to achieve these benefits.

[0151] FIG. 15 illustrates a detailed diagram of example level-shifter circuitry 1500 that achieves the above-described benefits, in accordance with one or more embodiments of the present disclosure. The level-shifter circuitry 1500 includes a memory cell 1510 connected to an input circuit 1520 as shown. As compared to level-shifter circuitry 1300, the memory cell 1510 replaces the pair of cross-coupled inverters in memory cell 1320 (MP1 / MN1 and MP2 / MN2) with two sets of three inverters cross-coupled in a feedback loop as shown (one set is MP2 / MN2, MP4 / MN4, and MP10 / MN10 and another set is MP1 / MN1, MP3 / MN3, and MP9 / MN9). The memory cell 1510 decouples competing criteria that existed in memory 1320 by recognizing that one inverter (e.g., MP2 / MN2) can be replaced by three inverters (e.g., MP2 / MN2, MP4 / MN4, and MP10 / MN10) and different inverters in the set of three inverters being designed to satisfy various design criteria. In some embodiments, the final states MP9 / MN9 and MP10 / MN10 may have the same strength of output buffers 1310 and 1320 in the design of FIG. 13 A.

[0152] Referring to node N1 for convenience, the design of circuitry 1500 allows the high trip-point inverter to be MP4 / MN4, while MP2 would be the PMOS pull-up fighting against MP5 pulldown. Since the high trip-point stage and MP2 are separate, the MP2 / MN2 inverter can have a low trip-point which would provide a smaller MP2 size that is easier for MP5 to overdrive. Therefore, MP5 does not need to be very large. As a result, the minimum functional voltage of VDD2 / VSS2 rail is reduced. To further improve the low voltage operation, a low voltage threshold (Vth) PMOS process can be used for MP3 and MP4 to further increase the inverter trip-point of MP3 / MN3 and MP4 / MN4.

[0153] The level-shifter circuitry 1500 is but one embodiment of level-shifter circuitry that decouples design parameters in a beneficial way. More generally, this disclosure recognizes the benefits of a level shifter that includes a first circuit portion (e.g., an inverter such as MP4 / MN4 in FIG. 15) and a second circuit portion (e.g., an inverter such as MP2 / MN2 in FIG. 15), wherein the first circuit portion has a first trip-point threshold and the second portion has a second trip-point threshold that is less than the first trip-point threshold. The firstcircuit portion and the second circuit portion may be connected in, or as part of, a feedback loop such that when an input to the first circuit portion is pulled below a first trip-point threshold to change a logical value output, the input to the second circuit portion is pulled in an opposite direction above the second trip-point threshold to reinforce the change in the logical value output. In some aspects, the first circuit portion and the second circuit portion may be viewed as mutually reinforcing.

[0154] One downside of this new design is that the positive feedback loop to pull node N1 to VS S2 by MN2 now consists of six stages (MP4 / MN4MP1 / MN1MP2 / MN2), whereas in a previous cross-couple inverter design, there are only two stages (MP2 / MN2 MP1 / MN1). However, the fast side of the level-shifter may be selected as the primary output, alleviating these concerns. An additional design consideration is that a level-shifter blanking can be extended to prevent the memory cell 1510 from switching again before the positive feedback loop has been settled.

[0155] FIG. 16 illustrates an example of a method 1600 of operating a level shifter, such as level shifter circuitry 1500, in accordance with one or more embodiments of the present disclosure. The level shifter comprises a first plurality of inverters comprising a first inverter and a second inverter connected in series, and a second plurality of inverters connected in series, wherein the first and second plurality of inverters are configured in a cross-coupled configuration. In step 1610, an input signal is provided to the second inverter, such as MP4 / MN4 in FIG. 15, to generate an output of the first plurality of inverters, such as MP2 / MN2, MP4 / MN4, and MP10 / MN10 and output OUTB in FIG. 15. The input signal may be signal Ai in FIG. 15, for example, in step 1620, the output of the first plurality of inverters is provided to an input of the second plurality of inverters, such as MP1 / MN1, MP3 / MN3, and MP9 / MN9 in FIG. 15, to generate an output of the second plurality of inverters, such as OUTA in FIG. 15. In step 1630, an inverted version of the input signal is provided to the second plurality of inverters. The inverted version of the input signal may be signal A2 in FIG.15, for example. In step 1640, an output of the second plurality of inverters, such as OUTA in FIG. 15, is provided to the first inverter, such as MP2 / MN2 in FIG. 15.

[0156] Blanking in Level-Shifters for Multi-Level Converter Applications

[0157] It is not unusual for a level shifter to include circuitry internal to the level shifter to generate an internal blanking signal that prevents the output from changing during someperiod of time, such as a blanking interval, to allow the level-shifter to settle after certain noisy events, such as after a level-shifter sends an output to a gate driver. However, internal blanking is insufficient to mitigate the variety of noise events and transients that can occur in multi-level power converters, particularly as the number of levels increases.

[0158] This disclosure recognizes that the use of level shifters in multi-level converters, such as the multi-level conversion system 1100 in FIG. 11, create new problems. When a multi-level converter changes state, yielding a new circuit configuration of fly capacitors, some of the switches may change state and other switches may not change state, depending on the states chosen during operation. However, this disclosure recognizes that for switches that are not intended to change state (sometimes referred to herein as “non-switched switches”), there may be noise / transients that are desirable to ignore when other switches switch. Therefore, level shifters are configured to receive blanking signals, which are issued to the level shifters connected to non-switched switches to prevent the corresponding level shifter outputs from changing, thereby preventing a change in state in non-switched switches.

[0159] FIG. 17 illustrates a detailed block diagram of another example level shifter / gate driver circuit 1700 connected to a switch 1210, in accordance with one or more embodiments of the present disclosure. Elements that are common with earlier figures use the same numbering. In this example embodiment, the level shifter / gate driver circuit 1700 includes a level shifter 1702 and gate driver 1204 connected as shown. In this embodiment the level shifter 1702 is configured to receive both a switch control signal and a blanking control signal as shown. The level shifter 1702 is configured to prevent its output (provided to gate driver 1204) from changing during a blanking interval based on reception of the blanking signal. The blanking signal itself may include a blanking interval or the blanking signal may instead simply be a trigger that triggers blanking with the level shifter 1702 during a programmable blanking period.

[0160] FIG. 18 illustrates another example of level-shifter circuitry 1800, in accordance with one or more embodiments of the present disclosure. As shown, the level-shifter circuitry 1800 includes an input circuit 1830, a memory cell 1810, and an output latch 1820 as shown. The digital logic gates are powered by the upper supply rail, labeled as VDDout / VSSout. Level-shifter circuitry 1800 may be used in a level shifter, such as level shifter 1702 illustrated in FIG. 17, in which case the upper supply rail VDDout / VSSout is typically connected to a boot capacitor, such as a boot capacitor CBOOT as described in FIG. 11.

[0161] The level-shifter circuitry 1800 implements both (1) an input transition triggered blanking, when the switch control transitions, to allow certain outputs to settle, and (2) blanking triggered by the blanking input (BLNK). In this embodiment 1800, the blanking input is a one-shot pulse, and the blanking duration is set by a reset delay. The output of circuitry 1800 is prevented from changing during the duration of the reset delay.

[0162] The level-shifter circuitry 1800 further includes delay blocks 1840 and 1850. Delay blocks 1840 and 1850 are configured as cascaded delay blocks. In this embodiment, delay block 1840 has 10 blocks in series, delay block 1850 has 14 blocks in series. For each of delay blocks 1840 and 1850, the corresponding input is at the left of each of delay block 1840 and 1850 and the corresponding output is shown on the right of these blocks. Delay block 1850 has 13 intermediate nodes, “del<l : I3>”. The right most input is “delin”. The left most output is del<14>. But selecting which signal to tap off, the correct delay can be chosen. Delay block 1840 operates similarly.

[0163] Level-shifter circuitry 1800 can be used to implement the level shifters in the various level shifter / gate driver circuits in a multi-level power converter, such as the level shifter / gate driver circuits 1102 to 1112 in FIG. 11. When the level-shifter circuitry 1800 implements level shifters in a multi-level power converter, the state select circuit 1140 not only generates the switch control signals input to each level shifter / gate driver circuit 1102 to 1112, the state select circuit 1140 also generates blanking signal inputs to each level shifter / gate driver circuit in the set 1102 to 1112. In operation, the state select circuit 1140 generates blanking signals for level shifter / gate driver circuits connected to switches that are not changing state. The circuitry 1800 is configured to receive a blanking signal input to prevent the output from changing state. For example, for non-switching switches in the group of switches QI to Q6 at a given time, there may be noise or transients in the overall system that are beneficial to ignore because such noise or transients may be strong enough to change the state of the non-switching switches. As one example, in a non-switching level shifter (i.e., a level shifter connected to a switch that is not changing state at a particular time), the associated boot capacitor supply may have a fast voltage change in a relatively small amount of time, which can cause glitches that can momentarily change the state of the corresponding switch connected to the non-switching level shifter. As a result, proper blanking of a nonswitching level shifters is beneficial in multi-level power converters.

[0164] FIG. 19 illustrates an example method 1900 of blanking in multi-level power converters, in accordance with one or more embodiments of the present disclosure. In step 1910, a switching cycle of a multi-level power converter begins. For example, in multi-level power converter system 1100, the start of a switching cycle initiates the decision regarding selection of the next power state of switches QI to Q6. Next in step 1920, after the decision regarding selection of the next power state occurs, certain switches from among QI to Q6 are designated to change states and the remaining switches from among QI to Q6 are not changing states during the switching cycle. Switching commands are transmitted to those level shifter / gate driver circuits corresponding to the switches from among QI to Q6 that are changing states. The switching decisions and / or commands are evaluated in step 1930 to determine which of the switches are not designated to change states. After this evaluation, next in step 1940 blanking signals are transmitted to the switches from among QI to Q6 that are not changing states to prevent that outputs of those switches from changing. For example, the switching commands sent to the circuitry for switches that are changing states may otherwise cause transients or noise in the system to temporarily cause non-switching switches to change state by affecting outputs of level shifters for the non-switching switches. However, nonswitching level shifters have been designed to prevent the outputs from changing based on reception of blanking signals thereby preventing states of associated switches from changing state.

[0165] Charging of Boot Capacitors in Multi-Level Power Converters

[0166] Boot capacitors may provide a bootstrap power supply for level shifter / gate driver circuits in multi-level power converters. For example, boot capacitors CBOOT provide power supplies for corresponding level-shifter / gate driver circuits 1102-1110 in the multi-level power converter system 1100 of FIG. 11. Boot capacitors may be charged at using a technique called ripple charging in which a power switch in a tier below the boot capacitor is turned on to charge the boot capacitor. For example, U.S. Patent No. 11,646,665, which is entitled “Efficient Bootstrap Supply Generators for Multi-Level Power Converters” and is incorporated herein by reference in its entirety, provides additional background on charging of boot capacitors.

[0167] During operation of multi-level power converters, because a boot capacitor is used to supply power to a corresponding level shifter / gate driver circuit, it may be beneficial to recharge the boot capacitor every so often, beyond the charging that may naturally occur whenassociated switches change states. For example, due to ripple charging, if a power switch, such as switches Q1-Q6 in FIG. 11, is not turned on for a long time, there may be no mechanism for the boot capacitor located in the tier immediately above the switch to charge. This disclosure recognizes that monitoring of boot capacitor status is desirable so that the boot capacitor remains adequately charged. Techniques for maintaining a target level of charge on a boot capacitor are presented here.

[0168] FIG. 20 illustrates an example boot capacitor control system 2000, in accordance with one or more embodiments of the present disclosure. A partial view of a multi-level power converter, such as the multi-level power converter system of FIG. 11, is shown to illustrate operation of the control system 2000. Capacitors 2030 and 2050 are boot capacitors representing boot capacitors in adjacent tiers or levels of a number of boot capacitors in a multi-level power converter. Boot capacitor 2030 is connected to a level shifter / gate driver circuit 2008 as shown, and boot capacitor 2050 is also connected to a corresponding level shifter / gate driver circuit, represented by 2070. As would be understood by a person of ordinary skill, the level-shifter / gate driver circuit represented by 2070 includes the same components as level-shifter / gate driver circuit 2008. For example, boot capacitors 2030 and 2050 may represent two of the boot capacitors of FIG. 11. Due to the nature of charging of boot capacitors using ripple charging, when switch Qn is closed boot charge capacitor 2030 helps to charge the boot capacitor in the tier above it, in this case boot capacitor 2050. The level shifter 2002 may be configured using any of the level shifter circuitry described earlier, including level shifter 1702 implemented using level shifter circuitry 1800, in which case a blanking signal input is also provided to the level shifter 2002 but not shown in FIG. 20. FIG. 20 illustrates a subset of the switches of a power converter, in this case switches Qn and Qn- 1.

[0169] A monitor circuit 2040 may be coupled either directly or indirectly to each boot capacitor to provide a status indictor regarding each boot capacitor. The monitor circuit 2040 may take various forms, such as a circuit to estimate the voltage across a boot capacitor or a circuit to estimate current being discharged by the boot capacitor. The monitor circuit 2040 provides the status indicator to a state selector 2010. The state selector 2010 takes the status indicator into account when selecting states for the switches, such as switches QI to Q6 inFIG. 11. For example, if the status indicator indicates that boot capacitor 2050 voltage is getting too low, state selector 2010 will prioritize states that result in switch Qn being closed to charge boot capacitor 2050 using capacitor 2030.

[0170] FIG. 21 illustrates another example of a boot capacitor control system 2100, in accordance with one or more embodiments of the present disclosure. The boot capacitor control system 2100 includes a counter 2120 as another example of a monitoring circuit. The counter 2120 measures the amount of time a switch, such as switch Qn, has been turned off (i.e., in an open state), using the input signal to the level shifter 1202 to indicate when the switch Qn is turned off and on. The counter 2120 measures time in clock cycles. In other embodiments, the counter 2120 may instead be any other type of timer that provides a measure of time in which switch Qn is turned off and whose time value is reset when switch Qn is turned on. The counter 2120 provides the clock cycle count that switch Qn has been turned off to state selector 2110. Each of the switches in a power converter may have its own associated counter 2120 connected as shown. In this case, the signal controlling the level shifter / gate driver circuit 2008 indicates the intended state of the switch Qn.

[0171] The state selector 2110 takes this clock cycle count into account when selecting states for the switches, such as switches QI to Q6 in FIG. 11. If switch Qn has been turned off too long, indicating that boot capacitor 2050 (not shown) is not being charged enough, then state selector 2110 prioritizes states that result in Qn being closed. Once Qn is closed, the counter is reset until Qn is again in an open state.

[0172] FIG. 22 illustrates a method 2200 of controlling boot capacitor voltage, in accordance with one or more embodiments of the present disclosure. In step 2210, a switch associated with charging a boot capacitor in a power converter is monitored until the switch turns off. As long as the switch is in the on state, which implies that the boot capacitor is being charged, no action is taken. Once the switch is in the off state, the method progresses to step 2220.

[0173] In step 2220, an indication of boot capacitor voltage is determined. For example, the length of time the switch has been turned off, as determined by a counter, such as the counter 2120 in FIG. 21, is an indicator of how much time the boot capacitor in the next tier has been discharging. The length of time is measured in clock cycles in this example. In another embodiment, a monitor circuit may be configured to measure voltage across the bootcapacitor directly as the indicator of boot capacitor voltage. In yet another embodiment, a current discharged from the capacitor may be measured and used as the indicator of boot capacitor voltage.

[0174] In step 2230, a condition is evaluated, such as comparing a measure of boot capacitor voltage against a threshold or comparing the number of clock cycles since the switch has been turned off against a threshold. In step 2240, a determination is made whether the condition indicates insufficient boot capacitor voltage. If the boot capacitor voltage is deemed sufficient, according to the condition, then the method returns to decision block 2210 to determine if the switch state remains off. If the boot capacitor voltage is deemed insufficient, the method proceeds to step 2250 in which states are prioritized that turn on the switch, until the switch is turned on. After the switch is turned on, the method returns to decision block 2210, in which the switch is monitored until it turns off.

[0175] Note that there may be multiple switches in a set of switches that satisfy the condition in step 2240 at a given time. There are various ways to further prioritize states. For example, a state selector may compare the different durations that various switches have been in an off state and determine which switches to prioritize closing according to the durations of the off states. As a simple example, suppose that a first switch has been in an off state for a duration tl and a second switch has been in an off state for a duration t2, and both durations tl and t2 exceed a threshold indicating that it is time for the switches to be closed. States may be prioritized in which both switches are off simultaneously. Alternatively, states may be prioritized in which the switch having the greatest off time is closed. Then states may be prioritized in which the switch having the next greater off time is closed, and so on, such that switches are closed in a first in, first out manner so to speak in order in which switches satisfy the condition in decision block 2240.

[0176] In some embodiments, counters are not counted when there are no switching events. This may occur when the capacitor is not charging or discharging as there is no load that causes the capacitor to charge or discharge. Because counters are tied to a frequency at which a system clock (e.g., a clock generating signals CLK) operates, conventionally counters would increment when a clock signal CLK is received even though no switching events were occurring. Because counters are tied to a state of a power converter, this, in turn, would cause a state of the power converter to time out. To prevent the counters from causing time outs when there are no switching events, the power converter may include circuitry thatwould cause the power converter to skip or ignore clock pulses (e.g., clock signals CLK) and prevent the counters from being incremented. In this way, the system clock is running at the same frequency regardless of whether the capacitor is or is not charging or discharging or is idle because there is no load and hence no switching events. When there are no switching events, however, the counters are not incremented during each clock pulse and do not cause the state in a power converter to time out at all or as quickly.

[0177] Further aspects of the present disclosure include the following:

[0178] Aspect 1 includes an integrated circuit comprising: a plurality of switching circuits comprising a first switching circuit, wherein the first switching circuit is configured to receive power supplied by a boot capacitor, and wherein the first switching circuit is configured to receive a first switch control signal; a monitor circuit configured to provide a status indictor of the boot capacitor; and a state selector configured to select a state of each of the plurality of switching circuits based on the status indicator and to provide the first switch control signal to the first switching circuit based on the selected state of the first switching circuit.

[0179] Aspect 2 includes the integrated circuit of aspect 1, wherein the first switching circuit comprises: a first transistor, wherein the first transistor comprises a gate; a level shifter configured to receive the first switch control signal; and a gate driver comprising a gate driver input and a gate driver output, wherein the level shifter is connected to the driver input, wherein the gate driver output is connected to the gate of the first transistor, and wherein the state of the first switching circuit is set by the driver output.

[0180] Aspect 3 includes the integrated circuit of any of aspects 1-2, wherein the monitor circuit comprises a counter, wherein the counter is configured to determine a number of clock cycles that the first switch control signal has indicated an off state for the first transistor as the status indicator, wherein the state selector monitors the status indicator and determines that the number of clock cycles exceeds a threshold, and wherein the state selector prioritizes states of each of the plurality of switching circuits that result in the first transistor being switched on.

[0181] Aspect 4 includes he integrated circuit of any of aspects 1-3, wherein the first switching circuit comprises a first transistor, wherein the first transistor comprises a gate,wherein the monitor circuit comprises a counter, wherein the counter is configured to determine a number of clock cycles that the first switch control signal has indicated an off state for the first transistor, wherein the state selector monitors the number of clock cycles and determines that the number of clock cycles exceeds a threshold, and wherein the state selector prioritizes states of each of the plurality of switching circuits that result in the first transistor being switched on.

[0182] Aspect 5 includes the integrated circuit of any of aspects 1-4, wherein the counter is reset when the first transistor switches on.

[0183] Aspect 6 includes the integrated circuit of any of aspects 1-5, wherein each of the plurality of switching circuits other than the first switching circuit comprises a transistor, wherein the first transistor and the transistors of each of the plurality of switching circuits other than the first switching circuit form a plurality of transistors, and wherein the plurality of transistors is connected in series and configured to be positioned between a first voltage and a second voltage.

[0184] Aspect 7 includes the integrated circuit of any of aspect 1-6, wherein the level shifter is configured to cause the first transistor to switch between an open state and a closed state based on the first switch control signal.

[0185] Aspect 8 includes a portable electronic device comprising: the integrated circuit of claim 1; the boot capacitor; at least one fly capacitor; and a battery, wherein the plurality of switching circuits is connected to the at least one fly capacitor in a multi-level power converter configuration to charge the battery.

[0186] Aspect 9 includes the integrated circuit of any of aspects 1-7, wherein the monitor circuit comprises a voltage sense circuit configured to measure a voltage across the boot capacitor as the status indicator, wherein the state selector priorities states of each of the plurality of switching circuits that result in the first transistor being switched on when the status indicator is less than a threshold.

[0187] Aspect 10 includes the integrated circuit of any of aspects 1-7, wherein the monitor circuit comprises a current sense circuit configured to measure a current discharged from the boot capacitor as the status indicator, wherein the state selector priorities states of each ofthe plurality of switching circuits that result in the first transistor being switched on when the status indicator exceeds a threshold.

[0188] Aspect 11 includes a system comprising: a multi-level power converter comprising: a plurality of field effect transistor (FET) switches connected in series, wherein the multi-level power converter is configured to receive a plurality of state selection signals, and wherein there is a one-to-one correspondence between the plurality of FET switches and the plurality of state selection signals; a state selector configured to generate the plurality of state selection signals corresponding to states of the FET switches; and a plurality of counters, wherein there is a one-to-one correspondence between the plurality of counters and the plurality of state selection signals, and wherein the plurality of counters is configured to measure durations of off states of the plurality of FET switches and provide the durations of off states to the state selector, wherein state selector generates the plurality of state selection signals based on the durations of off states.

[0189] Aspect 12 includes the system of aspect 11, wherein the durations of off states are measured in clock cycles.

[0190] Aspect 13 includes the system of any of aspects 11-12, wherein the multi-level power converter further comprises: a first fly capacitor connected across a first subset of the plurality of FET switches; and a second fly capacitor connected across a second subset of the plurality of FET switches; and an output, wherein the state selection signals select a connection of the first and second fly capacitors to supply a voltage to the output.

[0191] Aspect 14 includes the system of any of aspects 11-13, wherein the multi-level power converter further comprises: a plurality of gate drivers equal in number to the number of the plurality of FET switches; and a plurality of level shifters equal in number to the number of the plurality of gate drivers, wherein each level shifter of the plurality of level shifters is connected to a corresponding FET switch of the plurality of FET switches via a corresponding driver of the plurality of gate drivers, and wherein the plurality of level shifters is configured to receive the plurality of state selection signals.

[0192] Aspect 15 includes the system of any of aspects 11-14, wherein the state selector prioritizes states of the plurality of FET switches that result in a FET switch of the plurality of FET switches being turned on when a counter of the plurality of counters corresponding to the FET switch indicates that an off duration of the FET switch exceeds a threshold.

[0193] Aspect 16 includes the system of any of aspects 11-15, further comprising a plurality of boot capacitors equal in number to the number of the plurality of FET switches, wherein the plurality of boot capacitors is configured in a ripple charging configuration.

[0194] Aspect 17 includes the system of any of aspects 11-16, wherein the state selector prioritizes states that result in a boot capacitor of the plurality of boot capacitors being charged by a switch below it in the series being closed.

[0195] Aspect 18 includes the system of any of aspects 11-17, wherein boot capacitors are selected for charging in an order according to lengths of durations of off states.

[0196] Aspect 19 includes a method of operating an apparatus comprising a plurality field effect transistor (FET) switches and a plurality of counters, wherein the plurality of counters is configured to measure durations of off states of the plurality of FET switches, and wherein the method comprises: monitoring the durations of off states of the plurality of FET switches; and generating a plurality of state selection signals for the plurality of FET switches based on the durations of off states.

[0197] Aspect 20 includes the method of aspect 19, wherein the apparatus further comprises a first fly capacitor connected across a first subset of the plurality of FET switches and a second fly capacitor connected across a second subset of the plurality of FET switches, and wherein the plurality of state selection signals is further based on measures of voltages across the first fly capacitor and the second fly capacitor.

[0198] Aspect 21 includes the method of any of aspects 19-20, wherein the apparatus further comprises an output, wherein the state selection signals connect the plurality of FET switches in a circuit to supply a voltage to the output.

[0199] Further aspects of the present disclosure include the following:

[0200] Aspect 1 includes method of operating a power converter comprising a plurality of transistor switches, the method comprising: during each of a plurality of repeating switching cycles: selecting a state for each of the plurality of transistor switches, resulting in a subset of the plurality of transistor switches that are changing state and a remaining subset of the plurality of transistor switches whose states are prevented from changing; issuing a switching command to each of the subset of the plurality of transistor switches; and issuing a blankingsignal to each of the remaining subset of the plurality of transistor switches to prevent the remaining subset of the plurality of transistor switches from changing states.

[0201] Aspect 2 includes the method of aspect 1, wherein the power converter further comprises a plurality of level shifters and a plurality of gate drivers, wherein each of the plurality of level shifters is coupled to a corresponding one of the plurality of gate drivers and a corresponding one of the plurality of switches in one-to-one correspondence, wherein switching commands and blanking signals are issued to respective transistor switches via corresponding level shifters of the plurality of level shifters.

[0202] Aspect 3 includes the method of any of aspects 1-2, wherein the state for each of the plurality of transistor switches is an on state or an off state.

[0203] Aspect 4 includes the method of any of aspects 1-3, wherein the plurality of transistor switches is connected in series to form a series connection of switches.

[0204] Aspect 5 includes the method of any of aspects 1-4, wherein the plurality of transistor switches is connected to a first fly capacitor and a second fly capacitor to maintain a first voltage across the first fly capacitor and a second voltage across the second fly capacitor, wherein the power converter further comprises an output connection among the series connection of switches, and wherein on / off states of the transistor switches are selected to maintain a power level at the output connection.

[0205] Aspect 6 includes the method of any of aspects 1-5, wherein each of the plurality of level shifters comprises a respective first plurality of inverters and a respective second plurality of inverters configured in a cross-coupled configuration and configured to receive any of the switching commands intended for the level shifter.

[0206] Aspect 7 includes a level shifter configured to receive a blanking signal and a switch control signal, wherein an output is prevented from changing state during a blanking interval when the blanking signal indicates for blanking to occur.

[0207] Aspect 8 includes the level shifter of aspect 7, further comprising: a first plurality of inverters comprising a first inverter and a second inverter connected in series and configured to generate a first output; a second plurality of inverters configured to generate a secondoutput; and an input circuit comprising the switch control signal input, wherein the input circuit is configured to couple a switching control signal to the second inverter, and wherein the second output is coupled to an input of the first inverter.

[0208] Aspect 9 includes the level shifter of any of aspects 7-8, wherein the second plurality of inverters comprises a third inverter and a fourth inverter connected in series, wherein input circuit is further configured to couple the switching control signal to the fourth invertor, and wherein an output of the first plurality of inverters is coupled to an input to the third invertor.

[0209] Aspect 10 includes a power converter comprising: the level shifter of aspect 8; a FET switch, wherein the FET switch comprises a gate; and a gate driver connected to receive a selected one of the first output or the second output and configured to provide a drive signal to the gate, wherein the selected one of the first output and second output is prevented from changing during the blanking interval.

[0210] Aspect 11 includes the power converter of aspect 10, further comprising: a state selection controller configured to provide the switching control signal and the blanking signal to level shifter.

[0211] Aspect 12 includes the power converter of any of aspects 10-11, further comprising: a plurality of level shifters comprising the level shifter; a plurality of field effect transistor (FET) switches each comprising a gate, wherein the FET switches are connected in series to form a series connection of switches, and wherein a state of each FET switch is controlled via its gate; and a plurality of gate drivers, wherein each of the plurality of gate drivers is coupled to the gate of a corresponding one of the plurality of FET switches in one-to-one correspondence, and wherein each of the plurality of level shifters is coupled to a corresponding one of the plurality of gate drivers in on-to-one correspondence.

[0212] Aspect 13 includes the level shifter of aspect 7, wherein the level shifter is configured with a programmable blanking period, wherein the blanking signal is a pulse that triggers the level shifter to prevent the output from changing during the programmable blanking period.

[0213] Aspect 14 includes the level shifter of aspect 7, wherein the blanking signal has a pulse width equal to a blanking duration thereby preventing the level shifter output from changing during the blanking duration.

[0214] Aspect 15 includes the power converter of aspect 10, further comprising: a boot supply configured to supply a voltage to the level shifter, wherein the output is prevented from changing state despite a fluctuation in the voltage.

[0215] Aspect 16 includes a system comprising: a first level shifter comprising a first output and a second level shifter comprising a second output; a first gate driver and a second gate driver; and a first transistor and a second transistor connected in series, wherein the first transistor comprises a first gate, and wherein the second transistor comprises a second gate, wherein the first output is connected to the first gate driver to deliver a switch state signal to the first gate, wherein the second output is connected to the second gate driver to deliver a switch state signal to the second gate, wherein each of the first and second level shifters is configured to receive a respective switching control signal or a respective blanking signal to generate a respective output signal at the first output and the second output, respectively, and wherein the first level shifter is configured to not change the first output during clock cycles when the second level shifter receives a switching control signal and the first level shifter receives a blanking signal.

[0216] Aspect 17 includes the system of aspect 16, further comprising: a state selection controller configured to provide the respective switching control signals and the respective blanking signals to the first and second level shifters.

[0217] Aspect 18 includes the system of any of aspects 16-17, further comprising: a first fly capacitor; a second fly capacitor; and an output connection, wherein the first level shifter and the second level shifter are configured to selectively configure the first fly capacitor and the second fly capacitor to provide a power level at the output connection based on the respective switching control signals or respective blanking signals.

[0218] Aspect 19 includes the system of any of aspects 16-18, wherein the first transistor and the second transistor are field effect transistors that are configured to be in either an on state or an off state.

[0219] Aspect 20 includes the system of any of aspects 16-19, further comprising a battery configured to be charged by the power level at the output connection.

[0220] Further aspects of the present disclosure include the following:

[0221] Aspect 1 includes a level shifter comprising: a first circuit portion configured to change a logical value based on a first internal signal being pulled below a first trip-point threshold by a change in an input signal; and a second circuit portion coupled to the first circuit portion in a feedback loop configured to change a second internal signal in a direction opposite of changes in the first internal signal, wherein the second circuit portion is configured to reinforce the change of the logical value based on the second internal signal being pulled above a second trip-point threshold, and wherein the first trip-point threshold is greater than the second trip-point threshold.

[0222] Aspect 2 includes the level shifter of aspect 1, wherein the first circuit portion comprises a first inverter, and wherein the second circuit portion comprises a second inverter.

[0223] Aspect 3 includes the level shifter of any of aspects 1-2, further comprising: a first plurality of inverters comprising the first inverter and the second inverter connected in series and configured to generate a first output; a second plurality of inverters configured to generate a second output; and an input circuit, wherein the input circuit is configured to couple the input signal to the first inverter, and wherein the second output is coupled to an input of the second inverter.

[0224] Aspect 4 includes the level shifter of any of aspects 1-3, wherein the second plurality of inverters comprises a third inverter and a fourth inverter connected in series, wherein the input circuit is further configured to couple the input signal to the fourth invertor, and wherein an output of the first plurality of inverters is coupled to an input of the third inverter.

[0225] Aspect 5 includes the level shifter of any of aspects 1-4, wherein the first plurality of inverters further comprises a fifth inverter connected in series with the second inverter, and wherein the fifth inverter is configured to generate the output of the first plurality of inverters.

[0226] Aspect 6 includes the level shifter any of aspects 1-5, wherein the second plurality of inverters further comprises a sixth inverter connected in series with the fourth inverter, andwherein the sixth inverter is configured to generate the output of the second plurality of inverters.

[0227] Aspect 7 includes the level shifter of any of aspects 1-6, further comprising: a multiplexer connected to the first output and the second output, wherein the multiplexer is configured to selected between the first output and the second output.

[0228] Aspect 8 includes an integrated circuit comprising: the level shifter of aspect 4; a switch, wherein the switch comprises a field effect transistor (FET) comprising a gate; and a driver connected to receive one of the first output or the second output as the signal and configured to provide a drive signal to the gate.

[0229] Aspect 9 includes the integrated circuit of aspect 8, wherein the level shifter is configured to work in conjunction with the driver to cause the FET to toggle between an open state and a closed state based on the input signal.

[0230] Aspect 10 includes the integrated circuit of any of aspects 8-9, wherein the first plurality of inverters and the second plurality of inverters are configured be powered by a voltage rail having a differential voltage of less than 3 volts (V).

[0231] Aspect 11 includes the integrated circuit of any of aspects 8-10, wherein the voltage rail is configured to be supplied by a boot capacitor.

[0232] Aspect 12 includes the integrated circuit of aspect 9, further comprising a plurality of FETs connected in series with the FET to form a series connection of switches, wherein the series connection of switches is connected between a first voltage connection and a second voltage connection, and wherein the integrated circuit is configured as a multi-level power converter.

[0233] Aspect 13 includes the level shifter of aspect 4, wherein the input circuit comprises an input inverter, and wherein the input signal is coupled to the fourth inverter via the input inverter.

[0234] Aspect 14 includes the integrated circuit of aspect 10, wherein the input circuit is configured to be powered by a second voltage rail.

[0235] Aspect 15 includes the level shifter of aspect 3, wherein the second inverter comprises: a p-channel field effect transistor (FET) having a first drain and a first gate; and an n- channel FET having a second drain and a second gate, wherein the first drain is directly connected to the second drain, and wherein the input circuit couples the input to the first gate and the second gate.

[0236] Aspect 16 includes an integrated circuit comprising: a plurality of switches connected in series to form a series connection of switches, wherein the series connection of switches is connected between a first voltage connection and a second voltage connection; a plurality of level shifters comprising a first level shifter; and a plurality of drivers, wherein each of the plurality of level shifters is coupled to a corresponding one of the plurality of drivers and a corresponding one of the plurality of switches in one-to-one correspondence, wherein the first level shifter comprises: a first plurality of inverters comprising a first inverter and a second inverter connected in series and configured to generate a first output; a second plurality of inverters configured to generate a second output; and an input circuit, wherein the input circuit is configured to couple an input signal to the first inverter, and wherein the second output is coupled to an input of the second inverter.

[0237] Aspect 17 includes the integrated circuit of aspect 16, wherein the first inverter is configured with a first trip-point threshold and the second inverter is configured with a second trip-point threshold, and wherein the first trip-point threshold is greater than the second trip-point threshold.

[0238] Aspect 18 includes the integrated circuit of any of aspects 16-17, wherein the second plurality of inverters comprises a third inverter and a fourth inverter connected in series, wherein the input circuit is further configured to couple the input signal to the fourth invertor, and wherein an output of the first plurality of inverters is coupled to an input of the third inverter.

[0239] Aspect 19 includes the integrated circuit of any of aspects 16-18, wherein the first plurality of inverters further comprises a fifth inverter connected in series with the second inverter, and wherein the fifth inverter is configured to generate the output of the first plurality of inverters.

[0240] Aspect 20 includes the integrated circuit of any of aspects 16-19, wherein the plurality of switches comprises a first field effect transistor (FET), wherein the first FET comprises a gate, and wherein the plurality of drivers comprises a first driver connected to receive one of the first output or the second output and configured to provide a drive signal to the gate.

[0241] Aspect 21 includes the integrated circuit of any of aspects 16-20, wherein the first plurality of inverters and the second plurality of inverters are configured be powered by a voltage rail having a differential voltage of less than 3 volts (V).

[0242] Aspect 22 includes the integrated circuit of any of aspects 16-21, wherein the second inverter comprises: a p-channel field effect transistor (FET) having a first drain and a first gate; and an n-channel FET having a second drain and a second gate, wherein the first drain is directly connected to the second drain, and wherein the input circuit couples the input to the first gate and the second gate.

[0243] Aspect 23 includes method of operating an integrated circuit comprising a level shifter, wherein the level shifter comprises a first plurality of inverters comprising a first inverter and a second inverter connected in series, and a second plurality of inverters connected in series, wherein the first and second plurality of inverters are configured in a cross-coupled configuration, and wherein the method comprises: providing an input signal to the second inverter to generate an output of the first plurality of inverters; providing the output of the first plurality of inverters to an input of the second plurality of inverters to generate an output of the second plurality of inverters; providing an inverted version of the input signal to the second plurality of inverters; and providing an output of the second plurality of inverters to the first inverter.

[0244] General Benefits and Advantages of Multi-Level Power Converters

[0245] Embodiments of the current invention improve the power density and / or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing embodiments of the current invention in critical ways, including lower power and / or longer battery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

[0246] More particularly, multi-level power converters provide or enable numerous benefits and advantages, including:

[0247] - adaptability to applications in which input and / or output voltages may have a wide dynamic-range (e.g., varying battery input voltage levels, varying output voltages);

[0248] - efficiency improvements on the run-time of devices operating on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);

[0249] - efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g., displays, nearby ICs) from excessive heat;

[0250] - enabling design optimizations for power efficiency, power density, and formfactor of the power converter - for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and / or to lower an overall bill of materials;

[0251] - the ability to take advantage of the performance of smaller, low voltage transistors;

[0252] - adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g, USB, USB-C, power-over Ethernet, etc.);

[0253] - adaptability to applications in which loads may vary widely, such as ICs in general (including microprocessors and memory ICs), electrical motors and actuators, transducers, sensors, and displays (e.g, LCDs and LEDs of all types);

[0254] - the ability to be implemented in a number of IC technologies (e.g., MOSFETs,GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0255] The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters includeportable and mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z- Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery -backup systems and / or power conversion for processing systems and / or electronic / op- tical networking systems), internet-of-things (IOT) devices (e.g., smart switches and lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC / DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and / or infotainment systems), and other devices and systems that utilize portable electricity generating sources and / or require power conversion.

[0256] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.1 la, b, g, ac, ax), as well as other radio communication standards and protocols.

[0257] Programmable Embodiments

[0258] Some or all aspects of the invention, particularly the Multi-Level Switch State Selector 1014 of FIG. 10, may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the algorithms included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform particular functions. Thus, embodiments of the invention may be implemented in one or more computer programs (i.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client / server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code maybe applied to input data to perform the functions described in this disclosure and generate output information. The output information may be applied to one or more output devices in known fashion.

[0259] Each such computer program may be implemented in any desired computer language (including machine, assembly, or high-level procedural, logical, or object-oriented programming languages) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different computers or processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the invention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in a computer readable medium or other organized data conforming to a data model stored in a data repository.

[0260] Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non-transitory storage media or device (e.g., solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently or permanently), the storage media or device being readable by a general or special purpose programmable computer or processor for configuring and operating the computer or processor when the storage media or device is read by the computer or processor to perform the procedures described above. The inventive system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer or processor to operate in a specific or predefined manner to perform the functions described in this disclosure.

[0261] Fabrication Technologies & Options

[0262] In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small volume. Low ESR is especially important for multi-levelpower converters that incorporate additional switches and fly capacitors to increase the number of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC -based capacitors. Capacitor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiCh), hafnium dioxide (HFO2), or aluminum oxide AI2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic parasitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of designed capacitors to reduce circuit size and / or increase circuit performance. Selection of capacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

[0263] Similarly, in various embodiments of multi-level power converters, it may be beneficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

[0264] The controlled s) used to control startup and operation of a multi-level power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and / or combinatorial logic.

[0265] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0266] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0267] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0268] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0269] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greatercurrents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0270] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0271] A number of embodiments of the disclosure have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0272] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the disclosure includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A method of operating a power converter comprising a plurality of transistor switches, the method comprising: during each of a plurality of repeating switching cycles: selecting a state for each of the plurality of transistor switches, resulting in a subset of the plurality of transistor switches that are changing state and a remaining subset of the plurality of transistor switches whose states are prevented from changing; issuing a switching command to each of the subset of the plurality of transistor switches; and issuing a blanking signal to each of the remaining subset of the plurality of transistor switches to prevent the remaining subset of the plurality of transistor switches from changing states.

2. The method of claim 1, wherein the power converter further comprises a plurality of level shifters and a plurality of gate drivers, wherein each of the plurality of level shifters is coupled to a corresponding one of the plurality of gate drivers and a corresponding one of the plurality of switches in one-to-one correspondence, wherein switching commands and blanking signals are issued to respective transistor switches via corresponding level shifters of the plurality of level shifters.

3. The method of claim 1, wherein the state for each of the plurality of transistor switches is an on state or an off state.

4. The method of claim 1, wherein the plurality of transistor switches is connected in series to form a series connection of switches.

5. The method of claim 4, wherein the plurality of transistor switches is connected to a first fly capacitor and a second fly capacitor to maintain a first voltage across the first fly capacitor and a second voltage across the second fly capacitor, wherein the power converter further comprises an output connection among the series connection of switches, and wherein on / off states of the transistor switches are selected to maintain a power level at the output connection.

6. The method of claim 2, wherein each of the plurality of level shifters comprises a respective first plurality of inverters and a respective second plurality of inverters configured in a cross-coupled configuration and configured to receive any of the switching commands intended for the level shifter.

7. A level shifter configured to receive a blanking signal and a switch control signal, wherein an output is prevented from changing state during a blanking interval when the blanking signal indicates for blanking to occur.

8. The level shifter of claim 7, further comprising: a first plurality of inverters comprising a first inverter and a second inverter connected in series and configured to generate a first output; a second plurality of inverters configured to generate a second output; and an input circuit comprising the switch control signal input, wherein the input circuit is configured to couple a switching control signal to the second inverter, and wherein the second output is coupled to an input of the first inverter.

9. The level shifter of claim 8, wherein the second plurality of inverters comprises a third inverter and a fourth inverter connected in series, wherein input circuit is further configured to couple the switching control signal to the fourth inverter, and wherein an output of the first plurality of inverters is coupled to an input to the third inverter.

10. A power converter compri sing : the level shifter of claim 8; a FET switch, wherein the FET switch comprises a gate; and a gate driver connected to receive a selected one of the first output or the second output and configured to provide a drive signal to the gate, wherein the selected one of the first output and second output is prevented from changing during the blanking interval.

11. The power converter of claim 10, further comprising: a state selection controller configured to provide the switching control signal and the blanking signal to level shifter.

12. The power converter of claim 11, further comprising: a plurality of level shifters comprising the level shifter; a plurality of field effect transistor (FET) switches each comprising a gate, wherein the FET switches are connected in series to form a series connection of switches, and wherein a state of each FET switch is controlled via its gate; and a plurality of gate drivers, wherein each of the plurality of gate drivers is coupled to the gate of a corresponding one of the plurality of FET switches in one-to-one correspondence, and wherein each of the plurality of level shifters is coupled to a corresponding one of the plurality of gate drivers in one-to-one correspondence.

13. The level shifter of claim 7, wherein the level shifter is configured with a programmable blanking period, wherein the blanking signal is a pulse that triggers the level shifter to prevent the output from changing during the programmable blanking period.

14. The level shifter of claim 7, wherein the blanking signal has a pulse width equal to a blanking duration thereby preventing the level shifter output from changing during the blanking duration.

15. The power converter of claim 10, further comprising: a boot supply configured to supply a voltage to the level shifter, wherein the output is prevented from changing state despite a fluctuation in the voltage.

16. A system comprising: a first level shifter comprising a first output and a second level shifter comprising a second output; a first gate driver and a second gate driver; and a first transistor and a second transistor connected in series, wherein the first transistor comprises a first gate, and wherein the second transistor comprises a second gate, wherein the first output is connected to the first gate driver to deliver a switch state signal to the first gate, wherein the second output is connected to the second gate driver to deliver a switch state signal to the second gate,wherein each of the first and second level shifters is configured to receive a respective switching control signal or a respective blanking signal to generate a respective output signal at the first output and the second output, respectively, and wherein the first level shifter is configured to not change the first output during clock cycles when the second level shifter receives a switching control signal and the first level shifter receives a blanking signal.

17. The system of claim 16, further comprising: a state selection controller configured to provide the respective switching control signals and the respective blanking signals to the first and second level shifters.

18. The system of claim 17, further comprising: a first fly capacitor; a second fly capacitor; and an output connection, wherein the first level shifter and the second level shifter are configured to selectively configure the first fly capacitor and the second fly capacitor to provide a power level at the output connection based on the respective switching control signals or respective blanking signals.

19. The system of claim 16, wherein the first transistor and the second transistor are field effect transistors that are configured to be in either an on state or an off state.

20. The system of claim 18, further comprising a battery configured to be charged by the power level at the output connection.

21. A level shifter comprising: a first circuit portion configured to change a logical value based on a first internal signal being pulled below a first trip-point threshold by a change in an input signal; and a second circuit portion coupled to the first circuit portion in a feedback loop configured to change a second internal signal in a direction opposite of changes in the first internal signal,wherein the second circuit portion is configured to reinforce the change of the logical value based on the second internal signal being pulled above a second trip-point threshold, and wherein the first trip-point threshold is greater than the second trip-point threshold.

22. The level shifter of claim 21, wherein the first circuit portion comprises a first inverter, and wherein the second circuit portion comprises a second inverter.

23. The level shifter of claim 22, further comprising: a first plurality of inverters comprising the first inverter and the second inverter connected in series and configured to generate a first output; a second plurality of inverters configured to generate a second output; and an input circuit, wherein the input circuit is configured to couple the input signal to the first inverter, and wherein the second output is coupled to an input of the second inverter.

24. The level shifter of claim 23, wherein the second plurality of inverters comprises a third inverter and a fourth inverter connected in series, wherein the input circuit is further configured to couple the input signal to the fourth invertor, and wherein an output of the first plurality of inverters is coupled to an input of the third inverter.

25. The level shifter of claim 24, wherein the first plurality of inverters further comprises a fifth inverter connected in series with the second inverter, and wherein the fifth inverter is configured to generate the output of the first plurality of inverters.

26. The level shifter of claim 24, wherein the second plurality of inverters further comprises a sixth inverter connected in series with the fourth inverter, and wherein the sixth inverter is configured to generate the output of the second plurality of inverters.

27. The level shifter of claim 24, further comprising: a multiplexer connected to the first output and the second output, wherein the multiplexer is configured to selected between the first output and the second output.

28. An integrated circuit comprising: the level shifter of claim 24;a switch, wherein the switch comprises a field effect transistor (FET) comprising a gate; and a driver connected to receive one of the first output or the second output as the signal and configured to provide a drive signal to the gate.

29. The integrated circuit of claim 28, wherein the level shifter is configured to work in conjunction with the driver to cause the FET to toggle between an open state and a closed state based on the input signal.

30. The integrated circuit of claim 29, wherein the first plurality of inverters and the second plurality of inverters are configured be powered by a voltage rail having a differential voltage of less than 3 volts (V).

31. The integrated circuit of claim 30, wherein the voltage rail is configured to be supplied by a boot capacitor.

32. The integrated circuit of claim 29, further comprising a plurality of FETs connected in series with the FET to form a series connection of switches, wherein the series connection of switches is connected between a first voltage connection and a second voltage connection, and wherein the integrated circuit is configured as a multi-level power converter.

33. The level shifter of claim 24, wherein the input circuit comprises an input inverter, and wherein the input signal is coupled to the fourth inverter via the input inverter.

34. The integrated circuit of claim 30, wherein the input circuit is configured to be powered by a second voltage rail.

35. The level shifter of claim 23, wherein the second inverter comprises: a p-channel field effect transistor (FET) having a first drain and a first gate; and an n-channel FET having a second drain and a second gate, wherein the first drain is directly connected to the second drain, and wherein the input circuit couples the input to the first gate and the second gate.

36. An integrated circuit comprising:a plurality of switches connected in series to form a series connection of switches, wherein the series connection of switches is connected between a first voltage connection and a second voltage connection; a plurality of level shifters comprising a first level shifter; and a plurality of drivers, wherein each of the plurality of level shifters is coupled to a corresponding one of the plurality of drivers and a corresponding one of the plurality of switches in one-to-one correspondence, wherein the first level shifter comprises: a first plurality of inverters comprising a first inverter and a second inverter connected in series and configured to generate a first output; a second plurality of inverters configured to generate a second output; and an input circuit, wherein the input circuit is configured to couple an input signal to the first inverter, and wherein the second output is coupled to an input of the second inverter.

37. The integrated circuit of claim 36, wherein the first inverter is configured with a first trip-point threshold and the second inverter is configured with a second trip-point threshold, and wherein the first trip-point threshold is greater than the second trip-point threshold.

38. The integrated circuit of claim 37, wherein the second plurality of inverters comprises a third inverter and a fourth inverter connected in series, wherein the input circuit is further configured to couple the input signal to the fourth invertor, and wherein an output of the first plurality of inverters is coupled to an input of the third inverter.

39. The integrated circuit of claim 38, wherein the first plurality of inverters further comprises a fifth inverter connected in series with the second inverter, and wherein the fifth inverter is configured to generate the output of the first plurality of inverters.

40. The integrated circuit of claim 39, wherein the plurality of switches comprises a first field effect transistor (FET), wherein the first FET comprises a gate, and wherein the plurality of drivers comprises a first driver connected to receive one of the first output or the second output and configured to provide a drive signal to the gate.

41. The integrated circuit of claim 36, wherein the first plurality of inverters and the second plurality of inverters are configured be powered by a voltage rail having a differential voltage of less than 3 volts (V).

42. The integrated circuit of claim 36, wherein the second inverter comprises: a p-channel field effect transistor (FET) having a first drain and a first gate; and an n-channel FET having a second drain and a second gate, wherein the first drain is directly connected to the second drain, and wherein the input circuit couples the input to the first gate and the second gate.

43. A method of operating an integrated circuit comprising a level shifter, wherein the level shifter comprises a first plurality of inverters comprising a first inverter and a second inverter connected in series, and a second plurality of inverters connected in series, wherein the first and second plurality of inverters are configured in a cross-coupled configuration, and wherein the method comprises: providing an input signal to the second inverter to generate an output of the first plurality of inverters; providing the output of the first plurality of inverters to an input of the second plurality of inverters to generate an output of the second plurality of inverters; providing an inverted version of the input signal to the second plurality of inverters; and providing an output of the second plurality of inverters to the first inverter.

44. An integrated circuit comprising: a plurality of switching circuits comprising a first switching circuit, wherein the first switching circuit is configured to receive power supplied by a boot capacitor, and wherein the first switching circuit is configured to receive a first switch control signal; a monitor circuit configured to provide a status indictor of the boot capacitor; and a state selector configured to select a state of each of the plurality of switching circuits based on the status indicator and to provide the first switch control signal to the first switching circuit based on the selected state of the first switching circuit.

45. The integrated circuit of claim 44, wherein the first switching circuit comprises: a first transistor, wherein the first transistor comprises a gate;a level shifter configured to receive the first switch control signal; and a gate driver comprising a gate driver input and a gate driver output, wherein the level shifter is connected to the driver input, wherein the gate driver output is connected to the gate of the first transistor, and wherein the state of the first switching circuit is set by the gate driver output.

46. The integrated circuit of claim 45, wherein the monitor circuit comprises a counter, wherein the counter is configured to determine a number of clock cycles that the first switch control signal has indicated an off state for the first transistor as the status indicator, wherein the state selector monitors the status indicator and determines that the number of clock cycles exceeds a threshold, and wherein the state selector prioritizes states of each of the plurality of switching circuits that result in the first transistor being switched on.

47. The integrated circuit of claim 44, wherein the first switching circuit comprises a first transistor, wherein the first transistor comprises a gate, wherein the monitor circuit comprises a counter, wherein the counter is configured to determine a number of clock cycles that the first switch control signal has indicated an off state for the first transistor, wherein the state selector monitors the number of clock cycles and determines that the number of clock cycles exceeds a threshold, and wherein the state selector prioritizes states of each of the plurality of switching circuits that result in the first transistor being switched on.

48. The integrated circuit of claim 47, wherein the counter is reset when the first transistor switches on.

49. The integrated circuit of claim 47, wherein each of the plurality of switching circuits other than the first switching circuit comprises a transistor, wherein the first transistor and the transistors of each of the plurality of switching circuits other than the first switching circuit form a plurality of transistors, and wherein the plurality of transistors is connected in series and configured to be positioned between a first voltage and a second voltage.

50. The integrated circuit of claim 46, wherein the level shifter is configured to cause the first transistor to switch between an open state and a closed state based on the first switch control signal.

51. A portable electronic device comprising: the integrated circuit of claim 44; the boot capacitor; at least one fly capacitor; and a battery, wherein the plurality of switching circuits is connected to the at least one fly capacitor in a multi-level power converter configuration to charge the battery.

52. The integrated circuit of claim 45, wherein the monitor circuit comprises a voltage sense circuit configured to measure a voltage across the boot capacitor as the status indicator, wherein the state selector priorities states of each of the plurality of switching circuits that result in the first transistor being switched on when the status indicator is less than a threshold.

53. The integrated circuit of claim 45, wherein the monitor circuit comprises a current sense circuit configured to measure a current discharged from the boot capacitor as the status indicator, wherein the state selector priorities states of each of the plurality of switching circuits that result in the first transistor being switched on when the status indicator exceeds a threshold.

54. A system comprising: a multi-level power converter comprising:a plurality of field effect transistor (FET) switches connected in series, wherein the multi-level power converter is configured to receive a plurality of state selection signals, and wherein there is a one-to-one correspondence between the plurality of FET switches and the plurality of state selection signals; a state selector configured to generate the plurality of state selection signals corresponding to states of the FET switches; and a plurality of counters, wherein there is a one-to-one correspondence between the plurality of counters and the plurality of state selection signals, and wherein the plurality of counters is configured to measure durations of off states of the plurality of FET switches and provide the durations of off states to the state selector, wherein state selector generates the plurality of state selection signals based on the durations of off states.

55. The system of claim 54, wherein the durations of off states are measured in clock cycles.

56. The system of claim 54, wherein the multi-level power converter further comprises: a first fly capacitor connected across a first subset of the plurality of FET switches; and a second fly capacitor connected across a second subset of the plurality of FET switches; and an output, wherein the state selection signals select a connection of the first and second fly capacitors to supply a voltage to the output.

57. The system of claim 54, wherein the multi-level power converter further comprises: a plurality of gate drivers equal in number to the number of the plurality of FET switches; and a plurality of level shifters equal in number to the number of the plurality of gate drivers, wherein each level shifter of the plurality of level shifters is connected to a corresponding FET switch of the plurality of FET switches via a corresponding gate driver of the plurality of gate drivers, and wherein the plurality of level shifters is configured to receive the plurality of state selection signals.

58. The system of claim 56, wherein the state selector prioritizes states of the plurality of FET switches that result in a FET switch of the plurality of FET switches being turned on when a counter of the plurality of counters corresponding to the FET switch indicates that an off duration of the FET switch exceeds a threshold.

59. The system of claim 56, further comprising a plurality of boot capacitors equal in number to the number of the plurality of FET switches, wherein the plurality of boot capacitors is configured in a ripple charging configuration.

60. The system of claim 59, wherein the state selector prioritizes states that result in a boot capacitor of the plurality of boot capacitors being charged by a switch below it in the series being closed.

61. The system of claim 59, wherein boot capacitors are selected for charging in an order according to lengths of durations of off states.

62. A method of operating an apparatus comprising a plurality field effect transistor (FET) switches and a plurality of counters, wherein the plurality of counters is configured to measure durations of off states of the plurality of FET switches, and wherein the method comprises: monitoring the durations of off states of the plurality of FET switches; and generating a plurality of state selection signals for the plurality of FET switches based on the durations of off states.

63. The method of claim 62, wherein the apparatus further comprises a first fly capacitor connected across a first subset of the plurality of FET switches and a second fly capacitor connected across a second subset of the plurality of FET switches, and wherein the plurality of state selection signals is further based on measures of voltages across the first fly capacitor and the second fly capacitor.

64. The method of claim 63, wherein the apparatus further comprises an output, wherein the state selection signals connect the plurality of FET switches in a circuit to supply a voltage to the output.

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