Information processing device, program, and neural network architecture manufacturing method

Abstract

An information processing device includes processing circuitry configured to obtain predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase, calculate an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors, and select a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures.

Description

INFORMATION PROCESSING DEVICE, PROGRAM, AND NEURAL NETWORK ARCHITECTURE MANUFACTURING METHODCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2024-003909 filed January 15, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present technology relates to a technical field of an information processing device for selecting a neural network architecture, a program, and a neural network architecture manufacturing method.

[0003] A learned AI model may be subjected to a performance evaluation for determining whether or not the learned AI model exerts a predetermined capability.　However, in a case where the learned AI model is difficult to achieve a predetermined performance, the performance evaluation needs to be performed again after another learned AI model is obtained by learning. 　　　　However, the learned AI model takes time to learn, and therefore an efficient evaluation is difficult to be performed. 　　　　For such a problem, PTL 1 below discloses a method of evaluating the performance of a neural network architecture before learning.　A neural network, that is, an AI model that executes a task of performance prediction is used for the evaluation of the performance of the neural network architecture.　That is, by using an AI model for performance prediction which model is obtained by learning, a performance evaluation is realized without the learning of the neural network architecture.

[0004] JP2021-504844 TSummary

[0005] However, in the method in PTL 1, learning for obtaining the AI model that executes the task of performance prediction is difficult to be reduced, and thus there is room for improvement.

[0006] The present technology has been made in view of such problems.　It is desirable to evaluate the performance of a neural network architecture without performing learning.

[0007] An information processing device according to an embodiment of the present technology includes processing circuitry configured to obtain predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase, calculate an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors, and select a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures. 　　　　That is, the predicted performance index value is a value obtained without undergoing the learning phase.　Moreover, the integrated index value obtained on the basis of the predicted performance index value does not necessitate the learning phase either.

[0008] FIG. 1 is a block diagram illustrating a general configuration of a signal processing system according to a present embodiment.FIG. 2 is a block diagram illustrating an example of a configuration of a computer device.FIG. 3 is a block diagram illustrating an example of a configuration of a camera device as an example of an AI processing device.FIG. 4 is a functional block diagram of an information processing device.FIG. 5 is a diagram illustrating an example of an input form.FIG. 6 is a diagram illustrating another example of the input form.FIG. 7 is a diagram illustrating yet another example of the input form.FIG. 8 is a diagram of assistance in explaining a processing content of alteration processing.FIG. 9 is a diagram illustrating an example of a presentation screen.FIG. 10 is a flowchart illustrating an example of processing performed by the information processing device in a first processing example.FIG. 11 is a diagram of assistance in explaining the generation of altered architectures.FIG. 12 is a flowchart illustrating an example of integrated index value calculation processing performed by the information processing device.FIG. 13 is a flowchart illustrating an example of processing performed by the information processing device in a second processing example.FIG. 14 is a flowchart illustrating an example of processing performed by the information processing device in a third processing example.

[0009] An embodiment of an information processing device according to an embodiment of the present technology will hereinafter be described in the following order with reference to the accompanying drawings. <1. Configuration of Information Processing System> <2. Functional Configuration of Information Processing Device> <3. Processing Examples> <3-1. First Processing Example> <3-2. Second Processing Example> <3-3. Third Processing Example> <4. Summary> <5. Present Technology>

[0010] <1. Configuration of Information Processing System> 　　　　An example of a configuration of an information processing system 1 in the present embodiment is illustrated in FIG. 1. 　　　　The information processing system 1 includes an information processing device 2, a user terminal 3, and an AI (Artificial Intelligence) processing device 4.　The information processing device 2, the user terminal 3, and the AI processing device 4 are capable of mutual communication via a communication network 5.

[0011] The information processing device 2 is, for example, a server device that performs various processing according to requests of a user using the user terminal 3.

[0012] The information processing device 2 performs processing related to the generation of an AI model in order to implement a task desired by the user.　Specifically, the information processing device 2 searches for a neural network architecture suitable for the task, and presents the neural network architecture to the user.

[0013] The user can obtain a high-performance AI model that is specialized in the target task of the user by subjecting the neural network architecture presented by the information processing device 2 to learning.

[0014] The user terminal 3 is a terminal device used by the user.　The user terminal 3 is, for example, a smart phone, a tablet terminal, a PC (Personal Computer) terminal, or the like.　The user can provide a type of the task desired to be performed by the AI model, specifications, and the like to the information processing device 2 via the user terminal 3.　The information processing device 2 makes a search for a neural network architecture matching the task type of the AI model and the specifications input via the AI processing device 4.

[0015] The AI processing device 4 is a device in which a neural network model obtained by subjecting the neural network architecture to learning is deployed, and the AI processing device 4 is a device that performs predetermined inference processing by inputting input data to the deployed neural network model.

[0016] In the following description, the neural network model may be simply described as an “AI model.”　Moreover, the neural network model obtained by the learning will be described as a “learned AI model.”　In addition, the inference processing using the AI model will be described as “AI processing.”　That is, the AI processing device 4 refers to a device that performs the AI processing.

[0017] The AI processing device 4 may, for example, be a camera device, may be an image sensor device disposed within the camera device, or may be another arithmetic device. 　　　　In the case of the AI processing device 4 as a camera device, for example, the inference processing is performed by inputting, to the AI model, RAW image data output from a light receiving unit of an image sensor, and thereby the AI processing such as semantic segmentation that classifies a subject is realized.

[0018] An example of a configuration of the information processing device 2 is illustrated in FIG. 2. 　　　　The information processing device 2 includes a CPU (Central Processing Unit) 71.　The CPU 71 functions as an arithmetic processing unit that performs the various kinds of processing described above.　The CPU 71 performs the various kinds of processing according to a program stored in a nonvolatile memory unit 74 such as a ROM (Read Only Memory) 72 or an EEP-ROM (Electrically Erasable Programmable Read-Only Memory), for example, or a program loaded from a storage unit 79 into a RAM (Random Access Memory) 73.　The RAM 73 also stores, as appropriate, data necessary for the CPU 71 to perform the various kinds of processing and the like.

[0019] The CPU 71, the ROM 72, the RAM 73, and the nonvolatile memory unit 74 are interconnected via a bus 83.　The bus 83 is also connected with an input-output interface (I / F) 75.

[0020] The input-output interface 75 is connected with an input unit 76 including operating elements and operating devices. 　　　　For example, assumed as the input unit 76 are various kinds of operating elements and operating devices such as a keyboard, a mouse, keys, a dial, a touch panel, a touch pad, and a remote controller. 　　　　The input unit 76 detects an operation of the user.　A signal corresponding to the input operation is interpreted by the CPU 71.

[0021] In addition, a display unit 77 including an LCD, an organic EL panel, or the like and an audio output unit 78 including a speaker or the like are connected integrally or as a separate body to the input-output interface 75. 　　　　The display unit 77 is a display unit that makes various kinds of display.　The display unit 77 is constituted by, for example, a display device provided to a casing of a computer device, a display device as a separate body connected to the computer device, or the like.

[0022] The display unit 77 displays an image for various kinds of image processing, a moving image of a processing target, or the like on a display screen on the basis of an instruction of the CPU 71.　In addition, the display unit 77 displays various kinds of operation menus, icons, messages, and the like, that is, displays a GUI (Graphical User Interface) on the basis of an instruction of the CPU 71.

[0023] The input-output interface 75 may be connected with the storage unit 79 including a hard disk, a solid-state memory, or the like and a communicating unit 80 including a modem or the like.

[0024] The communicating unit 80 performs communication processing via a transmission line such as the Internet and performs communication by wire / wireless communication, bus communication, or the like with various kinds of apparatuses.

[0025] The input-output interface 75 is also connected as necessary with a drive 81, which is loaded with a removable storage medium 82 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory as appropriate.

[0026] The drive 81 can read, from the removable storage medium 82, a data file or the like such as a program used for various processing.　The read data file is stored in the storage unit 79, or an image or sound included in the data file is output by the display unit 77 or the audio output unit 78.　In addition, the computer program read from the removable storage medium 82 or the like is installed in the storage unit 79 as necessary.

[0027] In this computer device, software for processing according to the present embodiment, for example, can be installed through network communication by the communicating unit 80 or via the removable storage medium 82.　Alternatively, the software may be stored in the ROM 72, the storage unit 79, or the like in advance. 　　　　In addition, an imaged image imaged in the camera or a processing result obtained by subjecting the imaged image to the AI processing may be received, and stored in the storage unit 79 or stored on the removable storage medium 82 via the drive 81.

[0028] The information processing device 2 including the arithmetic processing unit described above can be implemented with the CPU 71 performing processing operation on the basis of various kinds of programs. 　　　　It is to be noted that the information processing device 2 is not limited to being constituted by a single computer device as in FIG. 2, but may be constituted by forming multiple computer devices into a system.　The multiple computer devices may be formed into a system by a LAN (Local Area Network) or the like, or may be arranged at remote places on a VPN (Virtual Private Network) or the like using the Internet or the like.　The multiple computer devices may include computer devices as a server group (cloud) usable by cloud computing service.

[0029] The user terminal 3 has a configuration similar to that of the information processing device 2 illustrated in FIG. 2.

[0030] FIG. 3 illustrates an example of a configuration in a case where the AI processing device 4 is provided as a camera device.

[0031] The AI processing device 4 includes an imaging optical system 31, an optical system driving unit 32, an image sensor IS, a control unit 33, a memory unit 34, and a communicating unit 35.　The image sensor IS, the control unit 33, the memory unit 34, and the communicating unit 35 are connected to each other via a bus 36, and can thereby perform data communication with each other.

[0032] The imaging optical system 31 includes lenses such as a cover lens, a zoom lens, and a focus lens and a diaphragm (iris) mechanism.　This imaging optical system 31 guides light (incident light) from a subject, and condenses the light on a light receiving surface of the image sensor IS.

[0033] The optical system driving unit 32 comprehensively represents driving units of the zoom lens, the focus lens, and the diaphragm mechanism possessed by the imaging optical system 31.　Specifically, the optical system driving unit 32 includes actuators for driving the zoom lens, the focus lens, and the diaphragm mechanism, respectively, and driving circuits of the actuators.

[0034] The control unit 33 includes a microcomputer having, for example, a CPU, a ROM, and a RAM.　The CPU performs various kinds of processing according to a program stored in the ROM or a program loaded into the RAM, and thereby controls the whole of the AI processing device 4 as a camera device.

[0035] In addition, the control unit 33 gives the optical system driving unit 32 driving instructions for the zoom lens, the focus lens, the diaphragm mechanism, and the like.　The optical system driving unit 32 performs the movement of the focus lens and the zoom lens, the opening and closing of diaphragm blades of the diaphragm mechanism, and the like according to these driving instructions.

[0036] In addition, the control unit 33 controls the writing and reading of various kinds of data to and from the memory unit 34. 　　　　The memory unit 34 is a nonvolatile storage device such as, for example, an HDD (Hard Disk Drive) or a flash memory device.　The memory unit 34 is used as a storage destination (recording destination) of image data output from the image sensor IS.

[0037] Further, the control unit 33 performs various kinds of data communication with an external device via the communicating unit 35.　The communicating unit 35 in the present example is configured to be capable of performing data communication with at least the information processing device 2 illustrated in FIG. 1.

[0038] The image sensor IS is configured as, for example, a CCD (Charge Coupled Device) type image sensor, a CMOS (Complementary Metal Oxide Semiconductor) type image sensor, or the like.

[0039] The image sensor IS includes an imaging unit 41, an image signal processing unit 42, an intra-sensor control unit 43, an AI image processing unit 44, a memory unit 45, and a communication I / F 46, which are each capable of mutual data communication via a bus 47.

[0040] The imaging unit 41 includes a pixel array unit in which pixels having a photoelectric conversion element such as a photodiode are arranged two-dimensionally, and a reading circuit that reads an electric signal obtained by photoelectric conversion from each of the pixels included in the pixel array unit.　The imaging unit 41 can output the electric signal as an imaged image signal.

[0041] The reading circuit subjects the electric signal obtained by the photoelectric conversion to, for example, CDS (Correlated Double Sampling) processing, AGC (Automatic Gain Control) processing, and the like, and further subjects the electric signal to A / D (Analog / Digital) conversion processing.

[0042] The image signal processing unit 42 subjects the imaged image signal as digital data after the A / D conversion processing to preprocessing, synchronization processing, YC generation processing, resolution conversion processing, codec processing, and the like.　The preprocessing performs clamping processing of clamping black levels of R, G, and B to predetermined levels for the imaged image signal, correction processing between color channels of R, G, and B, and the like.　The synchronization processing performs color separation processing such that the image data of each pixel has color components of all of R, G, and B.　In a case of an imaging element using color filters in a Bayer array, for example, demosaicing processing is performed as the color separation processing.　The YC generation processing generates (separates) a luminance (Y) signal and a color (C) signal from the image data of R, G, and B.　The resolution conversion processing subjects the image data resulting from the various kinds of signal processing to the resolution conversion processing. 　　　　The codec processing performs, for example, coding processing for recording or for communication and file generation for the image data resulting from the various kinds of processing described above.　The codec processing can perform file generation using a format such as, for example, MPEG-2 (MPEG: Moving Picture Experts Group) or H.264 as a file format of a moving image.　In addition, file generation using a format such as JPEG (Joint Photographic Experts Group), TIFF (Tagged Image File Format), and GIF (Graphics Interchange Format) may be performed for a still image file.　Incidentally, in a case where the image sensor IS is a distance measuring sensor, the image signal processing unit 42 calculates distance information of a subject on the basis of two signals output from the image sensor IS as an iToF (indirect Time of Flight) sensor, for example, and outputs a distance image.

[0043] The intra-sensor control unit 43 controls the execution of an imaging operation by giving an instruction to the imaging unit 41.　The image signal processing unit 42 is also similarly controlled in performing processing.

[0044] The AI image processing unit 44 performs image recognition processing as AI image processing on an imaged image.　Incidentally, the AI image processing refers to AI processing on the image data.

[0045] An image recognition function using AI can be implemented by using a programmable arithmetic processing device such as, for example, a CPU, an FPGA (Field Programmable Gate Array), or a DSP (Digital Signal Processor).

[0046] The function of image recognition that can be implemented in the AI image processing unit 44 differs according to the type of the AI model deployed in the image sensor IS.　The following, for example, can be cited as types of the image recognition function. 　　　　- class identification 　　　　- semantic segmentation 　　　　- person detection 　　　　- vehicle detection 　　　　- target tracking 　　　　- OCR (Optical Character Recognition)

[0047] These functional types of image recognition correspond to the task type described above. 　　　　Of the functional types described above, the class identification is a function of identifying the class of a target.　The “class” referred to here is information indicating the category of an object, and distinguishes, for example, a “person,” an “automobile,” an “airplane,” a “ship,” a “truck,” a “bird,” a “cat,” a “dog,” a “deer,” a “frog,” a “horse,” or the like. 　　　　The target tracking is a function of tracking a subject set as a target, and can be reworded as a function of obtaining history information of the position of the subject.

[0048] The memory unit 45 is used as a storage destination of various kinds of data such as the imaged image data obtained by the image signal processing unit 42.　In addition, the memory unit 45 in the present example can be used also to temporarily store data used by the AI image processing unit 44 in a process of the AI image processing.

[0049] In addition, the memory unit 45 stores the information of an AI application or an AI model used in the AI image processing unit 44. 　　　　Incidentally, the information of the AI application or the AI model may be deployed in the memory unit 45 as a container or the like by using a container technology, for example, or may be deployed by using a microservice technology. 　　　　In addition, in a case where the memory unit 45 has a small capacity, the information of the AI application or the AI model may be deployed as a container or the like in a memory outside the image sensor IS, such as the memory unit 34, by using the container technology, and thereafter only the AI model may be stored in the memory unit 45 within the image sensor IS via the communication I / F 46 to be described in the following.

[0050] The communication I / F 46 is an interface that performs communication with the control unit 33, the memory unit 34, and the like located outside the image sensor IS.　The communication I / F 46 performs communication for externally obtaining a program to be executed by the image signal processing unit 42, the AI application or the AI model to be used by the AI image processing unit 44, and the like, and stores the program, the AI application or the AI model, and the like in the memory unit 45 included in the image sensor IS. 　　　　Thus, the AI model is stored in a part of the memory unit 45 included in the image sensor IS, and becomes usable by the AI image processing unit 44.

[0051] The AI image processing unit 44 performs subject recognition according to an objective by performing predetermined image recognition processing using the AI application or the AI model thus obtained.

[0052] Recognition result information of the AI image processing is output to the outside of the image sensor IS via the communication I / F 46.

[0053] That is, not only the image data output from the image signal processing unit 42 but also the recognition result information of the AI image processing are output from the communication I / F 46 of the image sensor IS. 　　　　Incidentally, it is possible to output only one of the image data and the recognition result information from the communication I / F 46 of the image sensor IS.

[0054] <2. Functional Configuration of Information Processing Device>

[0055] The CPU 71 of the information processing device 2 implements a series of functions illustrated in FIG. 4 by executing a predetermined program, for example.

[0056] The CPU 71 of the information processing device 2 functions as a condition obtaining section F1, an alteration processing section F2, an index calculating section F3, an integration processing section F4, a selection processing section F5, and a presentation processing section F6.

[0057] The condition obtaining section F1 performs processing of obtaining the task type of the AI model and specifications input via the user terminal 3.　Specifically, the condition obtaining section F1 performs processing of displaying a predetermined input form 10 on the user terminal 3, and obtains conditions obtained via the input form 10.

[0058] Here, FIG. 5 illustrates an example of the input form 10 for inputting the task type of the AI model and specifications, the input form 10 being presented to the user on the user terminal 3.

[0059] The input form 10 includes a title 11, multiple input fields 12, a canceling button 13, a search start button 14, and a closing button 15.

[0060] As the title 11, text for notifying an outline of the input form 10 is displayed.　In the example illustrated in FIG. 5, text “condition input form” is displayed as the title 11.

[0061] The input fields 12 are fields in which information for determining the specifications of a neural network architecture to be presented by the information processing device 2 is input.　Various forms are conceivable for the input fields 12.

[0062] The title 11 illustrated in FIG. 5 is provided with an input field 12A for inputting an upper limit number of parameters of the neural network architecture and an input field 12B for inputting an upper limit number of product-sum operations to be performed at a time of performing inference processing using the neural network architecture.

[0063] When predetermined information is input to the input field 12A and the input field 12B, an AI model generated from the neural network architecture selected and presented by the information processing device 2 can be set to be of an appropriate size.

[0064] Incidentally, other forms of the input fields 12 are also conceivable.　For example, provided in the example illustrated in FIG. 6 are an input field 12C for inputting the memory capacity of a device in which to deploy a learned AI model and an input field 12D for inputting information about the computing power of the device.

[0065] The information about the computing power may be information about FLOPS (FLoating point number Operations Per Second), or may be information about the operating frequency, the number of cores, or the like of the arithmetic processing unit.

[0066] The canceling button 13 is an operating element operated in a case of canceling the condition input and not making a search for the neural network architecture.

[0067] The search start button 14 is an operating element operated in a case of completing the condition input and performing a search for the neural network architecture.　When the search start button 14 is operated, the information processing device 2 makes a search for the neural network architecture, and presents a search result on the screen of the user terminal 3 or the like.

[0068] The closing button 15 is an operating element operated in a case of closing the input form 10.　In a case where the closing button 15 is operated, processing similar to that in the case of operating the canceling button 13 is performed.

[0069] Incidentally, in a case of obtaining type information of a task to be solved by using an ultimately obtained learned AI model, the input form 10 may be provided with an input field 12E to which the task type is input (selected), as illustrated in FIG. 7.

[0070] The alteration processing section F2 obtains a new neural network architecture by selecting one neural network architecture, and causing an alteration (Mutation) in a part of the neural network architecture. 　　　　The alteration of the neural network architecture by the alteration processing section F2 is achieved by causing a mutation in a small part of the structure by using an evolutionary algorithm, for example.

[0071] The neural network architecture includes a feature extractor that extracts features of input data and a subsequent classifier.　The alteration processing section F2 alters a part of the feature extractor in alteration processing (see FIG. 8).

[0072] For example, the alteration processing section F2 selects one convolutional layer constituting the neural network architecture to be altered, and changes the size of a kernel used in the layer.

[0073] Alternatively, the alteration processing section F2 selects one convolutional layer constituting the neural network architecture to be altered, and changes the kind of the kernel used in the layer.

[0074] In addition, the alteration processing section F2 may select one convolutional layer constituting the neural network architecture to be altered, and change the number of channels (width) or the number of times of repetition (depth).

[0075] In addition, the alteration processing section F2 may select one layer constituting the neural network architecture to be altered and change an activation function used in the layer, or may select one or multiple layers and provide a new branch by, for example, adding a residual connection, a Self-attention Branch, various skip connection, or the like.

[0076] Further, the alteration processing section F2 may selecting one convolutional layer constituting the neural network architecture to be altered, and change the kind of the layer.

[0077] By repeatedly performing such alteration processing, the alteration processing section F2 obtains neural network architectures resulting from subjecting a first selected neural network architecture serving as a basis (which first selected neural network architecture will hereinafter be described as a “base architecture Ab”) to multiple alterations.

[0078] The alteration processing section F2 obtains multiple kinds of neural network architectures by subjecting the base architecture Ab to multiple kinds of alterations.　The neural network architectures resulting from the alterations will be described as “altered architectures Ac.”

[0079] The alteration processing section F2 selects one of the altered architectures Ac, and further alters a part thereof.　Thus repeating a selection and an alteration obtains not only altered architectures Ac resulting from slight alterations of the base architecture Ab but also altered architectures Ac resulting from many alterations of the base architecture Ab.

[0080] Incidentally, the alteration processing section F2 considers the conditions obtained by the condition obtaining section F1 when the alteration processing section F2 selects the base architecture Ab.　Specifically, the alteration processing section F2 selects the number of layers, the number of nodes, and the like of the base architecture Ab such that the number of parameters and the number of product-sum operations of the altered architectures Ac satisfy the conditions or in consideration of the memory capacity of the device in which to deploy the learned AI model and the computing power of the arithmetic processing unit.

[0081] For example, the alteration processing section F2 selects the number of parameters and the number of product-sum operations of the base architecture Ab to be less than 80 percent or less than 70 percent of respective values allowable for the neural network architectures.　It is thereby possible to make the number of parameters and the number of product-sum operations of the altered architectures Ac after the alteration processing is performed satisfy the conditions.

[0082] In addition, the alteration processing section F2 may select the base architecture Ab on the basis of information about the task type of the user obtained by the condition obtaining section F1. 　　　　For example, the alteration processing section F2 may select different base architectures Ab, which include a base architecture Ab to be selected in a case where the task type is object recognition, object detection, or semantic segmentation as an objective, a base architecture Ab to be selected in a case where voice recognition is an objective, and a base architecture Ab to be selected in a case where a selection of an optimum procedure in a game is an objective.

[0083] The base architecture Ab and the altered architectures Ac generated by the alteration processing section F2 are set as candidates for the AI model for executing the task as an objective of the user.　In the following, the base architecture Ab and the altered architectures Ac will be described as “candidate architectures Ap.”

[0084] The alteration processing section F2 may perform processing of excluding a part of the candidate architectures Ap from a candidate architecture group in a case where the number of the candidate architectures Ap belonging to the candidate architecture group exceeds a predetermined number.　The processing of excluding the candidate architecture Ap is performed on the basis of an integrated index value Vf to be described later, for example.

[0085] The index calculating section F3 calculates predicted performance index values Vi as index values predicting the performance of a candidate architecture Ap.　Performance predictors Pr are used for the calculation of the predicted performance index values Vi.

[0086] Specifically, the index calculating section F3 uses multiple kinds of performance predictors Pr in order to calculate the predicted performance index values Vi of the candidate architecture Ap.　Used as the performance predictors Pr is zero shot NAS (Neural Architecture Search) such as MAE-NAS, NASWOT, or Zen-NAS.

[0087] The zero shot NAS is a performance predictor Pr that can estimate the performance of the learned AI model obtained from the neural network architecture without performing learning.　When the performance of the neural network architecture is estimated by using the zero shot NAS, it becomes possible to estimate the performance of multiple neural network architectures in a short time, and thereby greatly improve the efficiency of determining the neural network architecture.

[0088] The integration processing section F4 calculates one integrated index value Vf by performing integration using the respective predicted performance index values Vi calculated by respective zero shot NASes.

[0089] Specifically, the integration processing section F4 calculates post-standardization index values Vs of the respective zero shot NASes by standardizing the predicted performance index values Vi of the respective zero shot NASes used to calculate the integrated index value Vf.　Further, the integration processing section F4 calculates the integrated index value Vf by using the post-standardization index values Vs of the respective zero shot NASes.

[0090] The integration processing section F4 may perform weighting according to the characteristics of the respective zero shot NASes at a time of calculating the integrated index value Vf.　For example, in a case where the task type is object recognition, the integration processing section F4 may calculate the integrated index value Vf after increasing the weight of the predicted performance index value Vi of a zero shot NAS that can accurately predict the performance of the learned AI model obtained from the candidate architecture Ap in a field of object recognition.

[0091] The selection processing section F5 selects one candidate architecture Ap on the basis of the integrated index values Vf of the respective candidate architectures Ap calculated by the integration processing section F4.　A learned AI model obtained by subjecting the selected candidate architecture Ap to predetermined learning is highly likely to exert a high performance in the target task of the user.

[0092] The presentation processing section F6 performs processing of displaying predetermined information on the display unit 77 of the user terminal 3 in order to present the candidate architecture Ap selected by the selection processing section F5 to the user.

[0093] As a result of the presentation processing of the presentation processing section F6, a presentation screen 20 as illustrated in FIG. 9, for example, is displayed on the display unit 77 of the user terminal 3.

[0094] The presentation screen 20 is provided with a title 21, an image display section 22, a parameter section 23, a score section 24, and a histogram section 25.

[0095] The title 21 displays text for notifying an outline of the information displayed on the presentation screen 20.　In the example illustrated in FIG. 9, text is displayed which indicates that a search for the neural network architecture is completed and that the neural network architecture is presented.

[0096] The image display section 22 displays an image illustrating a structure of the candidate architecture Ap selected by the selection processing section F5.　The number of layers and the number of nodes may be indicated by numerical values instead of being illustrated in an image as in FIG. 9.

[0097] The parameter section 23 displays the number of parameters and the number of product-sum operations of the candidate architecture Ap selected by the selection processing section F5.　By checking the numerical values presented in the parameter section 23, the user can grasp the size and the amount of operations of the candidate architecture Ap.

[0098] The score section 24 displays the predicted performance index values Vi or the post-standardization index values Vs of the respective performance predictors Pr for the candidate architecture Ap selected by the selection processing section F5.

[0099] The histogram section 25 displays a histogram indicating the positioning of the candidate architecture Ap selected by the selection processing section F5 among the performance predictors Pr for which the integrated index values Vf are calculated. 　　　　By checking the histogram section 25, the user can grasp an expected value of the performance of the learned AI model obtained on the basis of the presented candidate architecture Ap. 　　　　In addition, by presenting information serving as evidence such as the score section 24 and the histogram section 25 to the user, it is possible to increase an appeal of being able to obtain a high-performance learned AI model on the basis of the selected and presented candidate architecture Ap.

[0100] Incidentally, FIG. 9 illustrates an example in which one candidate architecture Ap selected by the information processing device 2 is presented.　Without limitation to this, the presentation screen 20 as illustrated in FIG. 9 may be generated and presented to the user for each of multiple candidate architectures Ap selected by the information processing device 2.　That is, the number of candidate architectures Ap presented to the user is not necessarily one.　For example, three or five candidate architectures Ap may be presented to the user in order in which the obtainment of high-performance learned AI models is expected.

[0101] <3. Processing Example> 　　　　Description will be made of processing performed by the CPU 71 of the information processing device 2 in order to implement each of the functions described above.

[0102] <3-1. First Processing Example> 　　　　A first processing example is illustrated in FIG. 10. 　　　　The CPU 71 of the information processing device 2 in first step S101 determines performance predictors Pr to be used.　The performance predictors Pr have respective features, and are different from each other in terms of architectures whose performance the performance predictors Pr can predict.　For example, a certain performance predictor Pr - predict the performance of a neural network architecture including a branch straddling layers.

[0103] Depending on the performance predictors Pr selected in step S101, a processing content of the alteration processing by the alteration processing section F2 is limited.

[0104] The CPU 71 in step S102 generates or selects a base architecture Ab.　In this processing, the CPU 71 selects the base architecture Ab so as to satisfy the conditions obtained by the condition obtaining section F1.　Incidentally, as described earlier, this processing may select the base architecture Ab according to the target task of the user.

[0105] The CPU 71 in step S103 updates the candidate architecture group.　When the processing of step S103 is performed first, processing of adding the base architecture Ab to candidate architectures Ap belonging to the candidate architecture group is performed.

[0106] Next, the CPU 71 proceeds to step S104, where the CPU 71 determines whether or not the processing of adding a candidate architecture Ap to the candidate architecture group has been performed a predetermined number of times.　That is, the processing of step S104 is processing of determining whether or not a sufficient number of altered architectures Ac are generated for the base architecture Ab.

[0107] When a sufficient number of altered architectures Ac are generated, it is possible to present a neural network architecture for generating an AI model with higher accuracy to the user.

[0108] In a case where the CPU 71 determines that the predetermined number of times of repetition is not performed (step S104: No determination), the CPU 71 proceeds to step S105, where the CPU 71 selects one candidate architecture Ap to be altered from the candidate architectures Ap belonging to the candidate architecture group.

[0109] The CPU 71 in step S106 obtains an altered architecture Ac by performing alteration processing on the selected candidate architecture Ap.　In the alteration processing of step S106, the CPU 71 subjects the candidate architecture Ap to an alteration such that performance prediction by the performance predictors Pr may not become impossible.

[0110] In a case where performance evaluation is performed by using MAE-NAS, NASWOT, and Zen-NAS as the performance predictors Pr, for example, the alteration processing is performed such that the neural network architecture has a serial structure and such that each layer of an intermediate layer is constituted by a convolution layer and a ReLU (Rectified Linear Unit) as an activation function.

[0111] Incidentally, the CPU 71 may generate multiple altered architectures Ac by subjecting one candidate architecture Ap belonging to the candidate architecture group to different alterations in step S106.

[0112] For example, as illustrated in FIG. 11, in a case of performing the processing of step S105 and step S106 for a first time, the CPU 71 selects a base architecture Ab as only one candidate architecture Ap belonging to the candidate architecture group, and generates altered architectures Ac1, Ac2, and Ac3 by performing respective different alterations.

[0113] In a case of performing the processing of step S105 and step S106 for a second time, the CPU 71 selects the altered architecture Ac2 as one candidate architecture Ap from the candidate architectures Ap belonging to the candidate architecture group, and generates altered architectures Ac21, Ac22, and Ac23 by performing respective different alterations.

[0114] In a case of performing the processing of step S105 and step S106 for a third time, the CPU 71 selects the altered architecture Ac21 as one candidate architecture Ap from the candidate architectures Ap belonging to the candidate architecture group, and generates altered architectures Ac211, Ac212, and Ac213 by performing respective different alterations.

[0115] Thus repeating a selection of an altered architecture Ac and an alteration can generate altered architectures Ac that greatly differ in structure from the base architecture.

[0116] Incidentally, the selection processing of step S105 may select an altered architecture Ac having a high performance predicted on the basis of the integrated index value Vf. 　　　　In addition, in the example of FIG. 11, one altered architecture Ac is selected from the altered architectures Ac generated last.　Without limitation to this, the CPU 71 in the selection processing of step S105 may select one of the candidate architectures Ap belonging to the candidate architecture group without considering timing of the generation.　That is, when the processing of step S105 is performed again after the altered architecture Ac2 is selected, the altered architecture Ac1 or the altered architecture Ac3 may be selected.

[0117] The CPU 71 performs processing of calculating an integrated index value Vf of the newly generated altered architecture Ac in step S107.　Incidentally, in a case where multiple altered architectures Ac are generated in step S106, the CPU 71 performs the integrated index value calculation processing of step S107 for each of the generated altered architectures Ac.

[0118] An example of the integrated index value calculation processing is illustrated in FIG. 12.

[0119] The CPU 71 in step S201 first selects one unselected performance predictor Pr from the performance predictors Pr to be used.

[0120] The CPU 71 in step S202 calculates the predicted performance index value Vi of the candidate architecture Ap selected in a preceding step S105 by using the performance predictor Pr selected in step S201.

[0121] The CPU 71 in step S203 determines whether or not predicted performance index values Vi of the target candidate architecture Ap are calculated by using all of the performance predictors Pr to be used.

[0122] In a case where the CPU 71 determines that there is a performance predictor Pr by which the predicted performance index value Vi is not yet calculated (step S203: No determination), the CPU 71 returns to step S201, where the CPU 71 selects one unselected performance predictor Pr, and performs the calculation processing of step S202.

[0123] In a case where the CPU 71 determines that the calculation of the predicted performance index values Vi is performed by using all of the performance predictors Pr (step S203: Yes determination), on the other hand, the CPU 71 proceeds to step S204, where the CPU 71 performs standardization processing.　This processing is processing of calculating post-standardization index values Vs in order to unify possible ranges, variances, or the like of the predicted performance index values Vi that differ for the respective performance predictors Pr.　The post-standardization index values Vs of the respective performance predictors Pr can be thereby treated equally.

[0124] The CPU 71 in step S205 performs weighting processing.　The weighting processing is processing of assigning a weight to the post-standardization index value Vs of a performance predictor Pr having a high accuracy of performance prediction according to the target task type of the user.　Incidentally, the weighting processing of step S205 is not important.

[0125] The CPU 71 in step S206 calculates the integrated index value Vf by using the post-standardization index values Vs after the weighting processing.　The candidate architecture Ap selected in a preceding step S105 is thereby given one index value, that is, the integrated index value Vf. 　　　　The integrated index value Vf is used when the candidate architecture Ap to be presented to the user is selected from the candidate architecture group.

[0126] After the processing of step S206 is ended, the CPU 71 proceeds to step S108 in FIG. 10. 　　　　The CPU 71 in step S108 adds the new altered architecture Ac generated in step S106 as a candidate architecture Ap to the candidate architecture group.　One or multiple candidate architectures Ap are thereby added to the candidate architecture group.

[0127] Incidentally, the candidate architectures Ap added to the candidate architecture group are preferably limited to candidate architectures Ap that match the conditions obtained by the condition obtaining section F1. 　　　　For example, an altered architecture Ac in which the number of product-sum operations performed at a time of inference is larger than a predetermined number after the structure of the neural network architecture becomes complicated as a result of repeatedly performing the alteration processing of step S106 is preferably discarded without being added as a candidate architecture Ap to the candidate architecture group.　The same is true for a case where the number of parameters exceeds a predetermined number due to the alterations.

[0128] The CPU 71 in step S109 determines whether or not the number of candidate architectures Ap belonging to the candidate architecture group is equal to or less than a predetermined number.　This processing is processing of achieving a saving of memory capacity used, by excluding a candidate architecture Ap that has a low likelihood of being presented to the user.

[0129] In a case where the CPU 71 determines that the number of candidate architectures Ap belonging to the candidate architecture group is equal to or less than the predetermined number (step S109: Yes determination), the CPU 71 returns to step S104, where the CPU 71 determines whether or not the processing of adding a candidate architecture Ap to the candidate architecture group (or the alteration processing) has been repeated the predetermined number of times.

[0130] In a case where the CPU 71 determines that the number of candidate architectures Ap belonging to the candidate architecture group is larger than the predetermined number (step S109: No determination), on the other hand, the CPU 71 returns to step S103, where the CPU 71 updates the candidate architecture group.　Step S103 performs processing of excluding a candidate architecture Ap corresponding to an amount by which the predetermined number is exceeded from the candidate architecture group.

[0131] In a case where the CPU 71 determines in step S104 that the processing of adding a candidate architecture Ap to the candidate architecture group has been performed the predetermined number of times (step S104: Yes determination), the CPU 71 proceeds to step S110, where the CPU 71 selects one or a few candidate architectures Aps to be presented.

[0132] The processing of step S110 is performed by comparing the integrated index values Vf of the respective candidate architectures Ap with each other.　For example, one or a few candidate architectures Ap are selected in decreasing order of the integrated index values Vf.

[0133] The CPU 71 in step S111 performs processing of presenting the candidate architecture(s) Ap selected in step S110 to the user.　This processing is realized by the CPU 71 of the information processing device 2 by making the user terminal 3 perform display processing.

[0134] <3-2. Second Processing Example> 　　　　The first processing example has been described as an example in which alterations are not performed that the performance prediction in the performance predictor Pr may not be possible.　A second processing example is an example in which no limitation is imposed on alterations of neural network architectures, and the integrated index value Vf is calculated using only performance predictors Pr that can predict the performance of an altered architecture Ac after an alteration.

[0135] A concrete processing example is illustrated in FIG. 13.　Incidentally, pieces of processing similar to respective pieces of processing illustrated in FIG. 10 are identified by the same step numbers, and description thereof will be omitted as appropriate.

[0136] The CPU 71 of the information processing device 2 in step S121 determines a kind of alteration to be used in the alteration processing on neural network architectures.　This processing determines whether or not to allow alteration processing that provides a new branch straddling layers.

[0137] Next, the CPU 71 in step S101 determines performance predictors Pr capable of predicting the performance of an altered architecture Ac obtained after the alteration.　The performance predictors Pr determined here correspond to the kind of alteration determined in step S121.

[0138] After generating or selecting a base architecture Ab in step S102, the CPU 71 repeatedly performs each piece of processing from step S103 to step S109.　Then, after performing the alteration processing the predetermined number of times (step S104: Yes determination), the CPU 71 proceeds to step S110, where the CPU 71 selects a candidate architecture Ap to be presented.

[0139] The CPU 71 in step S111 performs processing of presenting the candidate architecture Ap selected in step S110 to the user.

[0140] Thus, in the second processing example, no limitation is imposed on the kind of alteration, and therefore a neural network architecture that adopts a more complex structure can be included as a candidate architecture Ap.　Hence, it is possible to increase a possibility of a high-performance neural network architecture being presented to the user.

[0141] In addition, a neural network architecture can be considered to be divided into a backbone and a head.　Moreover, in a neural network architecture of a complex structure, a neck may be provided between the backbone and the head.

[0142] The backbone in the neural network architecture refers to layers from an initial state to a middle stage of the network, and includes layers for extracting features in the input data and the like. 　　　　In addition, the head in the neural network architecture refers to layers in a final stage of the network, and may include, for example, a fully connected layer, a softmax function, and the like. 　　　　Further, the neck in the neural network architecture is a layer having a function of more condensing, extracting, and refining feature quantities and the like.　An FPN (Feature Pyramid Networks) or the like, for example, corresponds to the neck.

[0143] It is possible to evaluate the whole of the neural network architecture by selecting performance predictors Pr that can estimate the performance of the whole of the neural network architecture including not only the backbone of the neural network architecture but also the layers corresponding to the head and the layers corresponding to the neck in the processing of step S101 in FIG. 13.

[0144] It is thereby possible to present a neural network architecture having a higher performance to the user.

[0145] <3-3. Third Processing Example> 　　　　A third processing example is an example in which the kind of alteration is not limited, nor are performance predictors Pr to be used for performance evaluation determined in advance.　An example thereof is illustrated in FIG. 14.　Incidentally, pieces of processing similar to respective pieces of processing illustrated in FIG. 10 are identified by the same step numbers, and description thereof will be omitted as appropriate.

[0146] The CPU 71 of the information processing device 2 in step S102 generates or selects a base architecture Ab.

[0147] The CPU 71 in step S103 adds the base architecture Ab to the candidate architecture group.　The CPU 71 thereafter repeats each piece of processing from step S104 to step S109.

[0148] At this time, in calculating the integrated index value Vf in step S107, the CPU 71 uses all of performance predictors Pr capable of evaluating the altered architecture Ac to be evaluated to calculate respective predicted performance index values Vi.　That is, the performance predictors Pr used for each altered architecture Ac differ.

[0149] The integrated index value Vf calculated in step S107 is a tentative value because the performance predictors Pr used for each altered architecture Ac to be evaluated are not unified.

[0150] The CPU 71 adds candidate architectures Ap to the candidate architecture group by repeating the processing from step S104 to step S109.　Then, the CPU 71 performs the processing of step S103 as appropriate in a case where the number of candidate architectures Ap belonging to the candidate architecture group is larger than the predetermined number.　The CPU 71 thereby organizes the candidate architectures Ap on the basis of the tentatively calculated integrated index values Vf.

[0151] In a case where the CPU 71 determines that the predetermined number of times of repetition is performed (step S104: Yes determination), the CPU 71 proceeds to step S122, where the CPU 71 identifies performance predictors Pr that can evaluate all of the candidate architectures Ap belonging to the candidate architecture group.

[0152] Next, the CPU 71 in step S123 calculates the integrated index values Vf of the respective candidate architectures Ap again by using these performance predictors Pr.　The integrated index values Vf calculated here are calculated by using the same performance predictors Pr for each of the candidate architectures Ap.　It is therefore possible to perform comparison accurately.

[0153] The CPU 71 in step S110 selects one candidate architecture Ap on the basis of the integrated index values Vf newly calculated in step S123.　The CPU 71 in step S111 presents the candidate architecture Ap to the user.

[0154] <4. Summary> 　　　　As described in each of the foregoing examples, the information processing device 2 includes the index calculating section F3 that obtains a predicted performance index value Vi indicating a result of prediction of performance of a learned AI model, the learned AI model resulting from subjecting a neural network architecture before learning to the learning, by using a performance predictor Pr that predicts the performance of the learned AI model without undergoing a learning phase, the integration processing section F4 that calculates an integrated index value Vf of the neural network architecture before the learning by integrating the predicted performance index value Vi of each performance predictor Pr obtained by using multiple performance predictors Pr, and the selection processing section F5 that selects one neural network architecture before the learning on the basis of the integrated index value Vf calculated for each of multiple neural network architectures before the learning. 　　　　That is, the predicted performance index value Vi is a value obtained without undergoing the learning phase.　Moreover, the integrated index value Vf obtained on the basis of the predicted performance index value Vi does not necessitate the learning phase either. 　　　　Hence, a time necessary to select a neural network architecture as a candidate for generating a high-performance learned AI model can be shortened greatly as compared with a case where the learning is performed in each neural network architecture. 　　　　Hence, it becomes possible to readily perform work of selecting a neural network architecture for generating a learned AI model according to an objective of the user, and it becomes easy to generate an appropriate learned AI model according to a situation. 　　　　In addition, multiple predicted performance index values Vi are calculated by predicting the performance of the learned AI model by using the multiple performance predictors Pr, and the integrated index value Vf is calculated by integrating these predicted performance index values Vi.　It is therefore possible to increase the accuracy of the integrated index value Vf, and select a neural network architecture from which a learned AI model having a higher performance is generated. 　　　　Further, inference processing using an AI model is rendered unnecessary when one neural network architecture is selected from the multiple neural network architectures.　It is therefore possible to reduce an amount of operations until the neural network architecture is selected.

[0155] As described with reference to FIG. 10 and FIG. 11 and the like, the information processing device 2 may include the alteration processing section F2 that generates a neural network architecture before the learning as an altered architecture Ac by performing alteration processing of setting the neural network architecture before the learning as a base architecture Ab and altering a part of the base architecture Ab.　Moreover, the altered architecture Ac may be at least a part of the multiple the neural network architectures before the learning. 　　　　It is thereby possible to easily prepare a neural network architecture as a candidate for selection by the selection processing section F5.

[0156] As described with reference to FIG. 4 and the like, in the information processing device 2, the alteration processing may be processing of applying an evolutionary algorithm to the base architecture Ab. 　　　　The altered architecture Ac can be generated suitably by using the evolutionary algorithm.　Incidentally, the alteration of the base architecture Ab by the evolutionary algorithm refers to, for example, the changing of a kind of layer constituting the neural network, the changing of the number of channels (width), the changing of a kind of kernel used in convolution operation, a kernel size, or a stride, the number of times of repetition of each layer (depth), and the like. 　　　　In addition, the alteration of the base architecture Ab may include a change that provides a new branch such as a Residual path, the changing of an activation function being used, and the like.

[0157] As described with reference to FIG. 4 and the like, in the information processing device 2, the alteration processing may be processing of causing mutation in a part of the base architecture Ab. 　　　　Thus, by merely first determining the base architecture Ab, integrated index values Vf are calculated for many neural network architectures derived from the base architecture Ab.　It is thereby possible to select a neural network architecture having high performance from the many neural network architectures without taking much cost of manual work.

[0158] As described with reference to FIG. 10 and FIG. 11 and the like, by performing the alteration processing on the altered architecture Ac, the alteration processing section F2 in the information processing device 2 may generate an altered architecture Ac that results from subjecting the base architecture Ab to a further alteration. 　　　　Consequently, the altered architectures Ac can include a neural network architecture obtained by subjecting the base architecture Ab to a significant alteration. 　　　　Hence, a possibility of selecting and presenting a neural network architecture having a high performance can be improved.

[0159] As described with reference to FIG. 10 and FIG. 11 and the like, the alteration processing section F2 in the information processing device 2 may generate multiple altered architectures Ac by repeating the alteration processing a predetermined number of times. 　　　　Thus, neural network architectures resulting from subjecting the base architecture Ab to alteration a predetermined number of times can be generated as altered architectures Ac. 　　　　Hence, a possibility of generating and selecting a neural network architecture having a high performance can be improved.

[0160] As described with reference to FIG. 10 and the like, in a case where the number of neural network architectures belonging to a candidate architecture group including the base architecture Ab and the altered architecture Ac is larger than a predetermined number, the selection processing section F5 in the information processing device 2 may select the predetermined number of neural network architectures from the candidate architecture group by using the integrated index value Vf. 　　　　It is thereby possible to reduce the candidate architecture group, and achieve a reduction in an amount of usage of memory in the information processing device 2 and the like. 　　　　In addition, in a case of presenting neural network architectures ultimately remaining in the candidate architecture group to the user, it is possible to reduce the number of neural network architectures to be presented to the user, and therefore reduce an inconvenience associated with a selecting operation of the user.

[0161] As described with reference to FIG. 10 and the like, in the information processing device 2, performance of the altered architecture Ac may be able to be predicted by the performance predictor Pr used to predict performance of the base architecture Ab. 　　　　That is, the alteration performed on the base architecture Ab is restricted to alterations in a range in which performance prediction by the performance predictor Pr used to predict the performance of the base architecture Ab is possible. 　　　　It is thereby possible to perform an evaluation of the base architecture Ab and the altered architecture Ac generated so as to be derived from the base architecture Ab by using the same performance predictor Pr, and thus perform a proper evaluation of each neural network architecture.

[0162] As described with reference to FIG. 11 and the like, the integration processing section F4 in the information processing device 2 may calculate a post-standardization index value Vs by standardizing the predicted performance index value Vi according to the performance predictor Pr, and calculate the integrated index value Vf by using multiple post-standardization index values Vs. 　　　　Consequently, the predicted performance index values Vi in different ranges which values are calculated by the respective performance predictors Pr can be treated equally, and thus an appropriate integrated index value Vf can be calculated.　Hence, it is possible to increase a possibility of proposing a neural network architecture having a high performance to the user.

[0163] As described with reference to FIG. 11 and the like, the integration processing section F4 in the information processing device 2 may perform standardization such that average values and variance values of the post-standardization index values Vs are identical in the respective performance predictors Pr. 　　　　It is thereby possible to obtain the post-standardization index values Vs resulting from appropriate standardization.

[0164] As described with reference to FIG. 11 and the like, the integration processing section F4 in the information processing device 2 may perform weighting of the post-standardization index value Vs according to the performance predictor Pr, and calculate the integrated index value Vf. 　　　　For example, the performance predictors Pr may respectively have different degrees of importance.　In such a case, by weighting the post-standardization index values Vs of the respective predicted performance index values Vi calculated by the respective performance predictors Pr, it is possible to calculate the integrated index value Vf such that an effect of the prediction result of an important performance predictor Pr is increased. 　　　　Hence, a possibility of proposing a neural network architecture suitable for the user can be increased.

[0165] As described with reference to FIG. 11 and the like, the integration processing section F4 in the information processing device 2 may perform the weighting using a level of prediction performance of the performance predictor Pr. 　　　　For example, some performance predictors Pr can accurately predict the performance of the AI model generated by using the neural network architecture, and some performance predictors Pr are difficult to accurately predict the performance of the AI model.　Moreover, the prediction accuracy of the performance predictors Pr also differs according to the type of a task of the AI model. 　　　　According to this configuration, it is possible to, for example, according to the type of the task of the AI model, increase the weight of the post-standardization index value Vs of a performance predictor Pr having a high prediction accuracy, and decrease the weight of the post-standardization index value Vs of a performance predictor Pr having a low prediction accuracy. 　　　　It is consequently possible to increase correlation between the integrated index value Vf and the predicted performance, and increase a possibility of proposing a neural network architecture having a high performance to the user.

[0166] As described with reference to FIG. 13 and the like, the index calculating section F3 in the information processing device 2 may obtain the predicted performance index value Vi by using the performance predictor Pr capable of predicting performance of both of the base architecture Ab and the altered architecture Ac obtained by altering the base architecture Ab. 　　　　This obviates a need to impose a limitation on an alteration mode at a time of generating the altered architecture Ac from the base architecture Ab. 　　　　For example, even when the whole of a neural network architecture including not only a backbone but also a neck and a head is adopted as the base architecture Ab and the altered architecture Ac, an appropriate evaluation of the neural network architecture can be performed by adopting performance predictors Pr capable of predicting the performance of the neural network architecture including all of the backbone, the neck, and the head. 　　　　Hence, it is possible to calculate the integrated index value Vf based on an evaluation of the whole of the AI model, and consequently increase a possibility of presenting a more appropriate neural network architecture as a neural network architecture that achieves a task desired by the user.

[0167] As described with reference to FIG. 4 and FIG. 5 and the like, the information processing device 2 may include the condition obtaining section F1 that obtains conditions of the number of parameters and the number of product-sum operations allowed for the learned AI model, and the selection processing section F5 may select the neural network architecture before the learning on the basis of the conditions obtained by the condition obtaining section F1. 　　　　Thus, in a case where the learned AI model is deployed and used in a certain device (AI processing device 4), the neural network architecture selected by the selection processing section F5 and ultimately presented to the user is set such that the AI model obtained after the learning satisfies the conditions. 　　　　Hence, it is possible to avoid a situation in which the generated learned AI model does not satisfy specifications, and thereby obviate a need for searching for a neural network architecture again or the like. 　　　　Incidentally, the condition obtaining section F1 may make the generated learned AI model satisfy specifications by obtaining the memory size and arithmetic processing power (for example, FLOPS) of a device planned for the deployment in place of the number of parameters and the number of product-sum operations.

[0168] As described with reference to FIG. 4 and the like, the information processing device 2 may include the alteration processing section F2 that generates a neural network architecture before the learning as an altered architecture Ac by performing alteration processing of altering a part of a base architecture Ab as the neural network architecture before the learning serving as a base, the altered architecture Ac may be at least a part of the multiple the neural network architectures before the learning, and the number of parameters and the number of product-sum operations in the base architecture Ab may be smaller, by a certain ratio or more, than the conditions obtained by the condition obtaining section F1. 　　　　The base architecture Ab is a neural network architecture serving as a base for the altered architecture Ac.　The number of parameters and the number of product-sum operations of a new neural network architecture obtained by altering the neural network architecture may become larger than those before the alteration. 　　　　Hence, by adopting a neural network architecture provided with a margin for demanded specifications thereof as the base architecture Ab, it is possible to increase a possibility that the neural network architecture after the alteration satisfies the specifications. 　　　　Moreover, it is possible to reduce a possibility that a high-performance neural network architecture obtained after the alteration does not satisfy the specifications, and increase a possibility that a high-performance neural network architecture is presented to the user.

[0169] As described with reference to FIG. 9 and the like, the information processing device 2 may include the presentation processing section F6 that presents the predicted performance index value Vi of each performance predictor Pr and the integrated index value Vf for the neural network architecture before the learning selected by the selection processing section F5. 　　　　The user can, for example, select the neural network architecture while grasping the index values related to the performance predicted for the neural network architecture selected by the selection processing section F5. 　　　　Moreover, when the index values or the like of not only the neural network architecture ultimately selected by the selection processing section F5 but also other neural network architectures belonging to the candidate architecture group are presented to the user, the user can select a desired neural network architecture from the multiple neural network architectures while considering the neural network architecture selected by the selection processing section F5, and make the desired neural network architecture learn.

[0170] As described with reference to FIG. 9 and the like, the presentation processing section F6 in the information processing device 2 may present a histogram of the integrated index values Vf related to the multiple neural network architectures before the learning. 　　　　The presentation of the histogram enables an evaluation of the neural network architecture selected by the selection processing section F5 to be grasped relatively and used as an aid for the user to select the neural network architecture.

[0171] A neural network architecture manufacturing method according to an embodiment of the present technology includes a step of obtaining a predicted performance index value Vi indicating a result of prediction of performance of a learned AI model, the learned AI model resulting from subjecting a neural network architecture before learning to the learning, by using a performance predictor Pr that predicts the performance of the learned AI model without undergoing a learning phase, a step of calculating an integrated index value Vf of the neural network architecture before the learning by integrating the predicted performance index value Vi of each performance predictor Pr obtained by using multiple performance predictors Pr, and a step of selecting one neural network architecture before the learning on the basis of the integrated index value Vf calculated for each of multiple neural network architectures before the learning.

[0172] A program according to an embodiment of the present technology is a program to be executed by an arithmetic processing device, the program including a function of obtaining a predicted performance index value Vi indicating a result of prediction of performance of a learned AI model, the learned AI model resulting from subjecting a neural network architecture before learning to the learning, by using a performance predictor Pr that predicts the performance of the learned AI model without undergoing a learning phase, a function of calculating an integrated index value Vf of the neural network architecture before the learning by integrating the predicted performance index value Vi of each performance predictor Pr obtained by using multiple performance predictors Pr, and a function of selecting one neural network architecture before the learning on the basis of the integrated index value Vf calculated for each of multiple neural network architectures before the learning.

[0173] The various actions and effects described above can be obtained also by such a signal processing method and such a program.

[0174] Incidentally, such a program can be recorded in advance in an HDD (Hard Disk Drive) as a recording medium included in an apparatus such as a computer device, a ROM within a microcomputer including a CPU, or the like.　Alternatively, the program can be temporarily or permanently stored (recorded) in advance on a removable recording medium such as a flexible disk, a CD-ROM (Compact Disk Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a Blu-ray Disk (registered trademark), a magnetic disk, a semiconductor memory, or a memory card.　Such a removable recording medium can be provided as generally-called packaged software. 　　　　In addition, such a program can also be installed into a personal computer or the like from the removable recording medium, and downloaded from a download site via a network such as a LAN and the Internet.

[0175] It is to be noted that effects described in the present specification are merely illustrative and are not limited, and that there may be other effects.

[0176] In addition, the examples described above may be combined with each other in any manner, and various actions and effects described above can be obtained even in cases where the various kinds of combinations are used.

[0177] The present technology may also be implemented in the following configurations. (1) An information processing device, comprising: processing circuitry configured to: obtain predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase, calculate an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors, and select a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures. (2) The information processing device according to (1), wherein the processing circuitry is further configured to: generate the neural network architectures by performing alteration processing to alter a part of a base architecture. (3) The information processing device according to (2), wherein the alteration processing applies an evolutionary algorithm to the base architecture. (4) The information processing device according to (2), wherein the processing circuitry is further configured to: generate multiple altered architectures by repeating the alteration processing a predetermined number of times. (5) The information processing device according to (2), wherein the processing circuitry is further configured to: generate an altered architecture by performing the alteration processing on a previously altered architecture. (6) The information processing device according to (1), wherein the processing circuitry is further configured to: calculate post-standardization index values by standardizing the predicted performance index values according to each performance predictor, and calculate the integrated index value using the post-standardization index values. (7) The information processing device according to (6), wherein the processing circuitry is further configured to: perform standardization such that average values and variance values of the post-standardization index values are identical for the respective performance predictors. (8) The information processing device according to (6), wherein the processing circuitry is further configured to: perform weighting of the post-standardization index values according to each performance predictor when calculating the integrated index value. (9) The information processing device according to (8), wherein the weighting is based on a level of prediction performance of each performance predictor. (10) The information processing device according to (1), wherein the processing circuitry is further configured to: obtain conditions for the learned AI model, and select the neural network architecture based on the conditions. (11) A method of processing information, the method comprising: obtaining predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase; calculating an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors; and selecting a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures. (12) The method according to (11), further comprising: generating the neural network architectures by performing alteration processing to alter a part of a base architecture. (13) The method according to (12), wherein the alteration processing applies an evolutionary algorithm to the base architecture. (14) The method according to (12), further comprising: generating multiple altered architectures by repeating the alteration processing a predetermined number of times. (15) The method according to (11), wherein calculating the integrated index value comprises: calculating post-standardization index values by standardizing the predicted performance index values according to each performance predictor; and calculating the integrated index value using the post-standardization index values. (16) A non-transitory computer-readable storage medium having a program thereon, which when executed by a computer, causes the computer to execute a method, the method comprising: obtaining predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase; calculating an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors; and selecting a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures. (17) The non-transitory computer-readable storage medium according to (16), wherein the method further comprises: generating the neural network architectures by performing alteration processing to alter a part of a base architecture. (18) The non-transitory computer-readable storage medium according to (17), wherein the alteration processing applies an evolutionary algorithm to the base architecture. (19) The non-transitory computer-readable storage medium according to (16), wherein calculating the integrated index value comprises: calculating post-standardization index values by standardizing the predicted performance index values according to each performance predictor; and calculating the integrated index value using the post-standardization index values. (20) The non-transitory computer-readable storage medium according to (19), wherein the method further comprises: performing weighting of the post-standardization index values according to each performance predictor when calculating the integrated index value, wherein the weighting is based on a level of prediction performance of each performance predictor.

[0178] 2: Information processing device 　　　　Ab: Base architecture 　　　　Ac: Altered architecture 　　　　F1: Condition obtaining section 　　　　F2: Alteration processing section 　　　　F3: Index calculating section 　　　　F4: Integration processing section 　　　　F5: Selection processing section 　　　　F6: Presentation processing section 　　　　Pr: Performance predictor 　　　　Vf: Integrated index value 　　　　Vi: Predicted performance index value 　　　　Vs: Post-standardization index value

Claims

1. An information processing device, comprising: processing circuitry configured to: obtain predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase, calculate an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors, and select a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures.

2. The information processing device according to claim 1, wherein the processing circuitry is further configured to: generate the neural network architectures by performing alteration processing to alter a part of a base architecture.

3. The information processing device according to claim 2, wherein the alteration processing applies an evolutionary algorithm to the base architecture.

4. The information processing device according to claim 2, wherein the processing circuitry is further configured to: generate multiple altered architectures by repeating the alteration processing a predetermined number of times.

5. The information processing device according to claim 2, wherein the processing circuitry is further configured to: generate an altered architecture by performing the alteration processing on a previously altered architecture.

6. The information processing device according to claim 1, wherein the processing circuitry is further configured to: calculate post-standardization index values by standardizing the predicted performance index values according to each performance predictor, and calculate the integrated index value using the post-standardization index values.

7. The information processing device according to claim 6, wherein the processing circuitry is further configured to: perform standardization such that average values and variance values of the post-standardization index values are identical for the respective performance predictors.

8. The information processing device according to claim 6, wherein the processing circuitry is further configured to: perform weighting of the post-standardization index values according to each performance predictor when calculating the integrated index value.

9. The information processing device according to claim 8, wherein the weighting is based on a level of prediction performance of each performance predictor.

10. The information processing device according to claim 1, wherein the processing circuitry is further configured to: obtain conditions for the learned AI model, and select the neural network architecture based on the conditions.

11. A method of processing information, the method comprising: obtaining predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase; calculating an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors; and selecting a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures.

12. The method according to claim 11, further comprising: generating the neural network architectures by performing alteration processing to alter a part of a base architecture.

13. The method according to claim 12, wherein the alteration processing applies an evolutionary algorithm to the base architecture.

14. The method according to claim 12, further comprising: generating multiple altered architectures by repeating the alteration processing a predetermined number of times.

15. The method according to claim 11, wherein calculating the integrated index value comprises: calculating post-standardization index values by standardizing the predicted performance index values according to each performance predictor; and calculating the integrated index value using the post-standardization index values.

16. A non-transitory computer-readable storage medium having a program thereon, which when executed by a computer, causes the computer to execute a method, the method comprising: obtaining predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase; calculating an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors; and selecting a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures.

17. The non-transitory computer-readable storage medium according to claim 16, wherein the method further comprises: generating the neural network architectures by performing alteration processing to alter a part of a base architecture.

18. The non-transitory computer-readable storage medium according to claim 17, wherein the alteration processing applies an evolutionary algorithm to the base architecture.

19. The non-transitory computer-readable storage medium according to claim 16, wherein calculating the integrated index value comprises: calculating post-standardization index values by standardizing the predicted performance index values according to each performance predictor; and calculating the integrated index value using the post-standardization index values.

20. The non-transitory computer-readable storage medium according to claim 19, wherein the method further comprises: performing weighting of the post-standardization index values according to each performance predictor when calculating the integrated index value, wherein the weighting is based on a level of prediction performance of each performance predictor.

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