Semiconductor device

Abstract

Provided is a semiconductor device having, in a diode region of an RC-IGBT, a small cell size, a low voltage in a conduction state when a low voltage is applied, a short recovery time after a large current is conducted, and a high pressure resistance. A semiconductor device 1 includes an IGBT region 2 and a diode region 3 in the same chip. The diode 30 includes: a second-conductivity-type first semiconductor layer 31, and a second-conductivity-type second semiconductor layer 32 having an impurity concentration lower than that of the first semiconductor layer 31, sandwiched by third trenches 13; a first-conductivity-type third semiconductor layer 33; a fourth trench 14 that penetrates through the first semiconductor layer 31 and the second semiconductor layer 32 and reaches the third semiconductor layer 33; and a first electrode 51 provided inside the fourth trench 14. The side surface of the fourth trench 14 is in contact with the first semiconductor layer 31 and the second semiconductor layer 32. The first electrode 51 forms a Schottky junction with the third semiconductor layer 33 on at least the bottom surface of the fourth trench 14.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] RC-IGBTs (RC: Reverse-Conducting IGBTs), which incorporate an IGBT (Insulated Gate Bipolar Transistor) and a diode within the same chip, have the advantage of being able to share the termination area between the IGBT and the diode, thereby reducing the chip size. Furthermore, because the IGBT and the diode operate at different times, heat generated by losses in either the IGBT or the diode area is distributed to the other, allowing heat to be dissipated throughout the chip, reducing thermal resistance.

[0003] On the other hand, the RC-IGBT has the problem that it is difficult to simultaneously optimize the IGBT and diode because the IGBT and diode are fabricated on the same chip.

[0004] A technique for shortening the recovery time of a diode or a diode built into an RC-IGBT is disclosed, for example, in Patent Document 1. In Figures 1 to 3 and paragraphs 0009 to 0038 of Patent Document 1, it is described that a pin diode is formed by a p+ type semiconductor region (31), an n- type semiconductor region (21), and an n+ type semiconductor region (22), and that a connection region (16) connected to a second electrode (11) which is an anode electrode passes through the p+ type semiconductor region (31) and reaches the n- type semiconductor region (21), and an SBD (Schottky barrier diode) is formed by the connection region (16) and the n- type semiconductor region (21), and a low current conduction state is achieved. The document describes a technology in which the SBD operates preferentially over the pin diode in a high current conducting state, thereby increasing the current when a low voltage is applied compared to the pin diode and reducing the voltage in the conducting state, and the pin diode operates preferentially over the SBD in a high current conducting state, and reducing the width of the p+ type semiconductor region (31) in the Y-axis direction or the contact area between the p+ type semiconductor region (31) and the second electrode (11) to suppress the amount of hole injection from the anode side and shorten the recovery time. Furthermore, Figure 12 of Patent Document 1 describes the application of the above technology to a diode region (7D) built into an RC-IGBT.

[0005] Another technique for forming an SBD in a diode built into an RC-IGBT is, for example, Patent Document 2. Figure 1 of Patent Document 2 describes a technique in which a Schottky barrier diode (10) is formed between an n-drift layer (n-layer) (3) and a sidewall of an Si etched region (7) (second trench) provided in the diode section of an RC-IGBT, and a p+ layer (16) and a p-layer (17) are formed below the Si etched region (7), forming a pn diode between the n-drift layer (n-layer) (3).

[0006] Another technique for forming an SBD in a diode built into an RC-IGBT is disclosed in, for example, Patent Document 3. In Figure 35, paragraph 132 of Patent Document 3, a technique is described in which, in the diode region (108) of an RC-IGBT, a metal pillar electrode (142a) is electrically connected to the emitter / anode electrode (148), penetrates the p-anode region (124), and forms a Schottky junction with the n-barrier region (122) via a Schottky interface (152a).

[0007] JP 2017-55079 A JP 2023-144460 A JP 2013-48230 A

[0008] However, in the technology described in FIG. 12 of Patent Document 1, since there is no p-type semiconductor region around the connection region (16) that has a lower concentration than the p+-type semiconductor region (31), when the breakdown voltage is maintained (when a reverse bias is applied and the diode is off), an electric field concentrates at the corners of the connection region (16), which raises concerns about a decrease in breakdown voltage and an increase in leakage current.

[0009] 11 of Patent Document 1 describes a technology in which a p-type semiconductor region (30) having a lower impurity concentration than the p+ type semiconductor region (31) and the p-type base region (32) of the IGBT in the IGBT region (7RI) is provided in the diode region (7D) built into the RC-IGBT, and covers the bottom and side surfaces of the connection region (16). Here, Figure 8 and paragraph 0064 of Patent Document 1 describe that by providing a low-concentration p-type semiconductor region (30) between the n- type semiconductor region (21) and the p+ type semiconductor region (31), a depletion layer extends from the junction between the p-type semiconductor region (30) and the n- type semiconductor region (21) in the off-state in the semiconductor device (4), thereby further increasing the breakdown voltage in the off-state, and that since the p-type semiconductor region (30) is a low-concentration region, it does not affect the rise of current in a low-current conduction state, thereby reducing the on-state voltage in the semiconductor device (4).

[0010] 8 and 11 of Patent Document 1, an SBD is not formed, and although Patent Document 1 states that the p-type semiconductor region (30) is a low-concentration region and therefore does not affect the rise of current in a low-current conduction state, in reality it forms a pn junction, which causes a built-in voltage to occur at the rise time to some extent compared to a Schottky junction, thereby affecting the rise of current in a low-current conduction state to some extent. Note that the lower the concentration of the p-type semiconductor region (30), the less noticeable the built-in voltage becomes, but if the concentration of the p-type semiconductor region (30) is made too low so that the built-in voltage is not noticeable, there is a trade-off problem in that the breakdown voltage cannot be obtained.

[0011] Furthermore, in the technology of FIG. 1 of Patent Document 2, a Schottky barrier diode (10) is formed between the n-drift layer (n-layer) (3) on the sidewall of the Si-etched region (7) (second trench). Therefore, the periphery of the Si-etched region (7) (second trench) cannot be sufficiently covered with the p-layer (17). This may result in a failure to ensure a sufficient breakdown voltage when maintaining the breakdown voltage (when a reverse bias is applied and the diode is off).

[0012] 35 of Patent Document 3, the p+ contact region 144 and the pillar electrode 142a are spaced apart, and the p anode region 124 is present therebetween, which results in a problem of a large cell size. Furthermore, since the cell size is large, the distance between the gate electrode 140 of the diode region 108 and the pillar electrode 142a is also large, which results in insufficient electric field relaxation at the bottom of the pillar electrode 142a, making it difficult to ensure a sufficient breakdown voltage.

[0013] The problem to be solved by the present invention is to provide a semiconductor device having a small cell size in the diode region of an RC-IGBT, a low voltage in the conductive state when a low voltage is applied, a short recovery time after a large current is conducted, and a high breakdown voltage.

[0014] In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device having an IGBT region and a diode region within the same chip, wherein the IGBT in the IGBT region has a plurality of first trenches each having a gate electrode therein, an emitter layer of a first conductivity type sandwiched between the first trenches, a body layer of a second conductivity type sandwiched between the first trenches and provided below the emitter layer, a second trench extending through the emitter layer to a middle of the body layer, and an emitter electrode electrically connected to the emitter layer and the body layer via the second trench; and the diode in the diode region has a plurality of third trenches each having an intra-trench electrode therein to which an emitter potential is applied, and a diode sandwiched between the third trenches. the fourth trench is formed on the first semiconductor layer and the second semiconductor layer, and the fourth trench is formed on the second semiconductor layer and the first electrode is electrically connected to the emitter electrode and is provided in a layer above the first semiconductor layer and inside the fourth trench; the fourth trench has a side surface in contact with the first semiconductor layer and the second semiconductor layer, and the first electrode forms a Schottky junction with the third semiconductor layer at least at a bottom surface of the fourth trench.

[0015] According to the present invention, a semiconductor device can be realized in which the cell size is small in the diode region of the RC-IGBT, the voltage in the conductive state when a low voltage is applied is low, the recovery time after a large current is conducted is short, and a high breakdown voltage is achieved.

[0016] 1A and 1B are cross-sectional views of a semiconductor device according to a first embodiment and a second embodiment, respectively.

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0018] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

[0019] The semiconductor device 1 of this embodiment is an RC-IGBT having an IGBT region 2 and a diode region 3 on the same chip. Silicon, for example, can be used as the semiconductor.

[0020] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but this is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type. Note that when the first conductivity type is p-type and the second conductivity type is n-type, carrier holes and electrons are interchanged, and the anode and cathode are interchanged. Furthermore, although the impurity concentration is shown as an example in this embodiment, this is not limited thereto, and it may be changed as appropriate within a range that can realize the operation intended in the embodiment.

[0021] The IGBT 20 in the IGBT region 2 has a plurality of first trenches 11 with gate electrodes 43 provided therein, an emitter layer 21 of a first conductivity type sandwiched between the first trenches 11, a body layer 22 of a second conductivity type sandwiched between the first trenches 11 and provided below the emitter layer 21, a second trench 12 that penetrates the emitter layer 21 and extends partway through the body layer 22, and an emitter electrode 41 electrically connected to the emitter layer 21 and the body layer 22 via the second trench 12.

[0022] The impurity concentration of each semiconductor layer is, for example, a high concentration n+ for the emitter layer 21 and a medium concentration p for the body layer 22. The gate electrode 43 is made of, for example, polysilicon. The emitter electrode 41 is made of, for example, a metal.

[0023] The IGBT 20 also has a contact layer 25 of a second conductivity type provided between the second trench 12 and the body layer 22. The impurity concentration of the contact layer 25 is, for example, a high concentration of p+. The contact layer 25 is provided to reduce the contact resistance between the emitter electrode 41 and the body layer 22.

[0024] The IGBT 20 also has a gate insulating film 61 and an interlayer insulating film 63. The gate insulating film 61 is provided inside the first trench 11 and between the gate electrode 43 and other semiconductor layers. The interlayer insulating film 63 is provided, for example, between the emitter electrode 41 and the gate electrode 43 and between the emitter electrode 41 and the emitter layer 21.

[0025] The IGBT 20 also has a first conductivity type drift layer 23 provided below the body layer 22, a second conductivity type collector layer 24 provided below the drift layer 23, and a collector electrode 42 electrically connected to the collector layer 24. The impurity concentration of each semiconductor layer is, for example, low concentration n- for the drift layer 23 and medium concentration p for the collector layer 24. The collector electrode 42 is formed of, for example, a metal.

[0026] The IGBT 20 preferably also has a buffer layer 26 provided between the drift layer 23 and the collector layer 24 and having a higher impurity concentration than the drift layer 23. The impurity concentration of the buffer layer 26 is, for example, a medium concentration of n.

[0027] The diode 30 in the diode region 3 includes a plurality of third trenches 13 each having an intra-trench electrode 53 therein to which an emitter potential is applied, a first semiconductor layer 31 of a second conductivity type sandwiched between the third trenches 13, a second semiconductor layer 32 of the second conductivity type sandwiched between the third trenches 13 and provided below the first semiconductor layer 31, and having a lower impurity concentration than the first semiconductor layer 31, a third semiconductor layer 33 of the first conductivity type provided below the second semiconductor layer 32, a fourth trench 14 penetrating the first semiconductor layer 31 and the second semiconductor layer 32 to reach the third semiconductor layer 33, and a first electrode 51 electrically connected to the emitter electrode 41 and provided above the first semiconductor layer 31 and inside the fourth trench 14.

[0028] The impurity concentrations of the first semiconductor layer 31 are, for example, a high concentration p+, the second semiconductor layer 32 are, for example, a medium concentration p, and the third semiconductor layer 33 are, for example, a low concentration n-. The second semiconductor layer 32 is preferably formed simultaneously with the body layer 22 to share a manufacturing process, and the impurity concentration of the second semiconductor layer 32 is preferably substantially the same as the impurity concentration of the body layer 22. The third semiconductor layer 33 can be formed simultaneously with the drift layer 23, and the impurity concentration of the third semiconductor layer 33 is substantially the same as the impurity concentration of the drift layer 23. The trench electrode 53 can be formed simultaneously with the gate electrode 43 using the same material, for example, polysilicon. The first electrode 51 is formed integrally with the emitter electrode 41 and is formed, for example, of a metal.

[0029] The diode 30 also has an intra-trench insulating film 62 and an interlayer insulating film 63. The intra-trench insulating film 62 is provided inside the third trench 13, and is provided between the intra-trench electrode 53 and another semiconductor layer. The interlayer insulating film 63 is provided, for example, between the first electrode 51 and the intra-trench electrode 53 and between the first electrode 51 and the first semiconductor layer 31.

[0030] The diode 30 also includes a fourth semiconductor layer 34 of the first conductivity type that is provided below the third semiconductor layer 33 and has a higher impurity concentration than the third semiconductor layer 33, and a second electrode 52 that is electrically connected to the fourth semiconductor layer 34 and the collector electrode 42. The fourth semiconductor layer 34 has a high impurity concentration of n+, for example. The second electrode 52 is formed integrally with the collector electrode 42 and is made of, for example, a metal.

[0031] The diode 30 also preferably has a buffer layer 26 provided between the third semiconductor layer 33 and the fourth semiconductor layer 34 and having a higher impurity concentration than the third semiconductor layer 33 .

[0032] In the diode 30 of this embodiment, the side surface of the fourth trench 14 contacts the first semiconductor layer 31 and the second semiconductor layer 32. Since there is no separation between the first semiconductor layer 31 and the fourth trench 14, the cell size can be reduced.

[0033] Moreover, the first electrode 51 forms a Schottky junction with the third semiconductor layer 33 at least on the bottom surface of the fourth trench 14. As a result, a Schottky barrier diode is formed between the bottom surface of the first electrode 51 and the third semiconductor layer 33. Furthermore, it is desirable that the first electrode 51 also forms a Schottky junction with the third semiconductor layer 33 on part of the side surface of the fourth trench 14 (the side surface near the bottom). As a result, the area in which the Schottky barrier diode is formed can be increased.

[0034] Furthermore, a pn diode is formed between the second semiconductor layer 32 and the third semiconductor layer 33. The first electrode 51 functions as an anode electrode, the second electrode 52 functions as a cathode electrode, the first semiconductor layer 31 and the second semiconductor layer 32, which are semiconductor layers of the second conductivity type, function as anode layers, and the third semiconductor layer 33, the buffer layer 26, and the fourth semiconductor layer 34, which are semiconductor layers of the first conductivity type, function as cathode layers.

[0035] Next, the operation of the diode 30 of this embodiment will be described.

[0036] In a low current conduction state, the Schottky barrier diode operates preferentially over the pn diode, so the current can be increased when a low voltage is applied compared to a pn diode, and since the built-in voltage that rises in a pn diode does not occur in a Schottky barrier diode, the voltage in a low current conduction state when a low voltage is applied can be reduced.

[0037] In a state where a large current is conducted, the pn diode operates preferentially over the Schottky barrier diode. At this time, the width of the first semiconductor layer 31, which is a highly doped p+, is narrowed by the fourth trench 14, thereby suppressing the amount of holes injected from the anode side. As a result, the recovery time during the subsequent reverse recovery can be shortened.

[0038] Furthermore, since the second semiconductor layer 32 having a lower impurity concentration than the first semiconductor layer 31 is present around the fourth trench 14, it is possible to alleviate the concentration of the electric field at the corners of the fourth trench 14 when the withstand voltage is maintained (when a reverse bias is applied and the diode 30 is off), thereby achieving a high withstand voltage.

[0039] Since the first semiconductor layer 31 is a highly doped p+, a depletion layer does not easily spread in the first semiconductor layer 31. Since electric field = voltage / depletion layer width, if the depletion layer does not spread, the electric field becomes strong and the breakdown voltage is not obtained. Therefore, in order to ensure the breakdown voltage, it is important to have the second semiconductor layer 32, which has a lower impurity concentration than the first semiconductor layer 31. However, if the impurity concentration is too low, the breakdown voltage will not be obtained. Therefore, it is desirable to make the impurity concentration of the second semiconductor layer 32 substantially the same as the impurity concentration of the body layer 22.

[0040] Furthermore, it is desirable that the depth of the fourth trench 14 is deeper than the depth of the second trench 12 and shallower than the depth of the third trench 13. Since the depth of the fourth trench 14 is shallower than the depth of the third trench 13, a depletion layer extending from the third trench 13 can alleviate the electric field at the corners of the fourth trench 14. Furthermore, since the first semiconductor layer 31 and the fourth trench 14 are not spaced apart, the cell size is small, and the distance between the third trench 13 and the fourth trench 14 is short, the depletion layer extending from the third trench 13 can easily alleviate the electric field at the corners of the fourth trench 14. Furthermore, since the depth of the fourth trench 14 is deeper than the depth of the second trench 12, a Schottky barrier diode can be formed between the bottom surface of the first electrode 51 and the third semiconductor layer 33. The second trench 12 and the fourth trench 14 are formed in separate steps. The first trench 11 and the third trench 13 can be formed simultaneously. Therefore, it is desirable that the first trench 11 and the third trench 13 have the same depth.

[0041] According to this embodiment, in the diode region 3 of the RC-IGBT, a semiconductor device 1 can be realized in which the cell size is small, the voltage in the conductive state when a low voltage is applied is low, the recovery time after a large current is conducted is short, and the withstand voltage is high.

[0042] FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment.

[0043] The second embodiment is a modification of the first embodiment, in which a barrier layer 27 is added and the configurations of the third semiconductor layer 33, the fourth semiconductor layer 34, and the fifth semiconductor layer 35 are different from those of the first embodiment.

[0044] The IGBT 20 of this embodiment further includes a barrier layer 27 of the first conductivity type that is provided between the drift layer 23 and the body layer 22 and has a higher impurity concentration than the drift layer 23. The impurity concentration of the barrier layer 27 is, for example, a medium concentration of n.

[0045] When the IGBT 20 is on, holes flow from the collector layer 24 of the second conductivity type on the back surface side, but the barrier layer 27 of the first conductivity type acts as a barrier, so holes accumulate around the barrier layer 27. Then, electrons flow in from the front surface side in amounts equivalent to the accumulated holes. Compared to when the barrier layer 27 is not present, there are more carriers around the barrier layer 27, and the higher the carrier concentration, the lower the resistance, so the on-voltage of the IGBT 20 can be reduced.

[0046] The diode 30 of this embodiment includes a fourth semiconductor layer 34 of the first conductivity type that is provided below the third semiconductor layer 33 and has a lower impurity concentration than the third semiconductor layer 33, a fifth semiconductor layer 35 of the first conductivity type that is provided below the fourth semiconductor layer 34 and has a higher impurity concentration than the fourth semiconductor layer 34, and a second electrode 52 electrically connected to the fifth semiconductor layer and a collector electrode 42. The impurity concentration of the third semiconductor layer 33 is substantially the same as the impurity concentration of the barrier layer 27, and the impurity concentration of the fourth semiconductor layer 34 is substantially the same as the impurity concentration of the drift layer 23.

[0047] That is, the third semiconductor layer 33 forming a Schottky junction with the first electrode 51 corresponds to the drift layer 23 of the IGBT 20 in the first embodiment, but corresponds to the barrier layer 27 of the IGBT 20 in the second embodiment. Furthermore, the fourth semiconductor layer 34 of the second embodiment corresponds to the third semiconductor layer 33 of the first embodiment, and the fifth semiconductor layer 35 of the second embodiment corresponds to the fourth semiconductor layer 34 of the first embodiment.

[0048] The impurity concentration of each semiconductor layer is, for example, a medium concentration of n for the third semiconductor layer 33, a low concentration of n- for the fourth semiconductor layer 34, and a high concentration of n+ for the fifth semiconductor layer 35. The third semiconductor layer 33 can be formed simultaneously with the barrier layer 27.

[0049] When the diode 30 is in a high current conduction state, holes are injected from the first semiconductor layer 31 and second semiconductor layer 32 of the second conductivity type on the front surface side, but are blocked by the third semiconductor layer 33 of the first conductivity type. Electrons enter from the back surface side, causing conductivity modulation, but because the holes are blocked by the third semiconductor layer 33, conductivity fluctuations are unlikely to occur. As a result, carrier injection becomes low, making it difficult for current to flow. Furthermore, as a result of the low carrier injection, the recovery time during subsequent reverse recovery can be shortened.

[0050] The rest is the same as in the first embodiment, so the explanation will be omitted.

[0051] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0052] 1: Semiconductor device 2: IGBT region 3: Diode region 11: First trench 12: Second trench 13: Third trench 14: Fourth trench 20: IGBT 21: Emitter layer 22: Body layer 23: Drift layer 24: Collector layer 25: Contact layer 26: Buffer layer 27: Barrier layer 30: Diode 31: First semiconductor layer 32: Second semiconductor layer 33: Third semiconductor layer 34: Fourth semiconductor layer 35: Fifth semiconductor layer 41: Emitter electrode 42: Collector electrode 43: Gate electrode 51: First electrode (anode electrode) 52: Second electrode (cathode electrode) 53: Trench electrode 61: Gate insulating film 62: Trench insulating film 63: Interlayer insulating film

Claims

1. A semiconductor device having an IGBT region and a diode region within the same chip, wherein the IGBT in the IGBT region includes a plurality of first trenches each having a gate electrode provided therein, an emitter layer of a first conductivity type sandwiched between the first trenches, a body layer of a second conductivity type sandwiched between the first trenches and provided in a layer lower than the emitter layer, a second trench penetrating the emitter layer and provided up to the middle of the body layer, and an emitter electrode electrically connected to the emitter layer and the body layer via the second trench; the diode in the diode region includes a plurality of third trenches each having an in-trench electrode to which an emitter potential is applied, a first semiconductor layer of a second conductivity type sandwiched between the third trenches, a second semiconductor layer of a second conductivity type sandwiched between the third trenches, provided in a layer lower than the first semiconductor layer and having an impurity concentration lower than that of the first semiconductor layer, a third semiconductor layer of a first conductivity type provided in a layer lower than the second semiconductor layer, a fourth trench penetrating the first semiconductor layer and the second semiconductor layer and reaching the third semiconductor layer, and a first electrode electrically connected to the emitter electrode and provided in a layer upper than the first semiconductor layer and inside the fourth trench; a side surface of the fourth trench is in contact with the first semiconductor layer and the second semiconductor layer; and at least at a bottom surface of the fourth trench, the first electrode is in Schottky contact with the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein at a part of a side surface of the fourth trench, the first electrode is in Schottky contact with the third semiconductor layer.

3. The semiconductor device according to claim 1, wherein an impurity concentration of the second semiconductor layer of the diode is substantially the same as an impurity concentration of the body layer of the IGBT.

4. The semiconductor device according to claim 1, wherein a depth of the fourth trench is deeper than a depth of the second trench and shallower than a depth of the third trench.

5. In claim 1, the IGBT has a drift layer of a first conductivity type provided below the body layer, a collector layer of a second conductivity type provided below the drift layer, and a collector electrode electrically connected to the collector layer. The diode has a fourth semiconductor layer of a first conductivity type provided below the third semiconductor layer and having a higher impurity concentration than the third semiconductor layer, and a second electrode electrically connected to the fourth semiconductor layer and the collector electrode. The impurity concentration of the third semiconductor layer of the diode is substantially the same as the impurity concentration of the drift layer of the IGBT. A semiconductor device characterized by this.

6. In claim 1, the IGBT has a drift layer of a first conductivity type provided below the body layer, a collector layer of a second conductivity type provided below the drift layer, a collector electrode electrically connected to the collector layer, and a barrier layer of a first conductivity type provided between the drift layer and the body layer and having a higher impurity concentration than the drift layer. The diode has a fourth semiconductor layer of a first conductivity type provided below the third semiconductor layer and having a lower impurity concentration than the third semiconductor layer, a fifth semiconductor layer of a first conductivity type provided below the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer, and a second electrode electrically connected to the fifth semiconductor layer and the collector electrode. The impurity concentration of the third semiconductor layer of the diode is substantially the same as the impurity concentration of the barrier layer of the IGBT, and the impurity concentration of the fourth semiconductor layer of the diode is substantially the same as the impurity concentration of the drift layer of the IGBT. A semiconductor device characterized by this.

7. In claim 1, the first conductivity type is n-type, the second conductivity type is p-type, and the first electrode is an anode electrode. A semiconductor device characterized by this.

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