Control method, control apparatus, computer system, computer device, and medium

Abstract

Disclosed in the present application are a control method and control apparatus for a computer system, and a computer system, a computer device and a computer-readable storage medium. The control method comprises: acquiring a current instruction address of a currently executed instruction; determining whether there is a preset correspondence between the current instruction address and a preset address; if there is a preset correspondence between the current instruction address and the preset address, resetting a timing value of a watchdog; and under the condition that the timing value of the watchdog reaches a preset value, controlling a computer system to generate a corresponding action, such that the computer system can be recovered to a controllable state. In this way, by means of setting a preset address and synchronously comparing the preset address with a current instruction address, the timing value of a watchdog can be reset only when there is a preset correspondence between the current instruction address and the preset address. Therefore, a watchdog operation can be rationally executed, and a computer system can be recovered to a controllable state when the computer system is interfered with and thus operates abnormally, thereby improving the stability and reliability of the computer system.

Description

Control method, control device, computer system, computer equipment and medium Technical Field

[0001] The present application relates to the technical field of computer systems, and in particular to a control method, a control device, a computer system, and a computer-readable storage medium. Background Art

[0002] In related technologies, a computer system can return to the starting point of system initialization when a watchdog timer overflows, resolving issues such as system uncontrollability or system freezes in unstable environments. The computer system can automatically resume normal operation without human intervention. Proper execution of clearing the watchdog timer is an important method for ensuring that the computer system can resume normal operation in the event of an abnormal or malfunctioning state and is crucial for computer system stability. However, in many cases, clearing the watchdog timer is not sufficient to restore a chaotic computer system to normal operation. Therefore, effectively clearing the watchdog timer is a significant technical issue that urgently needs to be addressed in this field. Summary of the Invention

[0003] Embodiments of the present application provide a computer system control method, a control device, a computer system, a computer device, and a computer-readable storage medium.

[0004] The control method of the embodiments of the present application can be used in a computer system. The computer system includes a watchdog, and the control method includes: obtaining a current instruction address of a currently executed instruction; determining whether a preset correspondence exists between the current instruction address and a preset address; resetting a timer value of the watchdog when the current instruction address and the preset address do exist; and controlling the computer system to generate a corresponding action when the watchdog timer value reaches a preset value, so that the computer system can be restored to a controllable state.

[0005] The control device of the embodiment of the present application can be used in a computer system, and the computer system includes a watchdog. The control device includes an acquisition module, a judgment module, a reset module and a processing module. The acquisition module is used to obtain the current instruction address of the currently executed instruction; the judgment module is used to determine whether there is a preset correspondence between the current instruction address and the preset address; the reset module is used to reset the timing value of the watchdog when the current instruction address and the preset address have the preset correspondence; the processing module is used to control the computer system to generate a corresponding action when the timing value of the watchdog reaches a preset value, so that the computer system can be restored to a controllable state.

[0006] The computer system according to the embodiment of the present application includes a watchdog and the above-mentioned control device.

[0007] The computer device of the embodiment of the present application includes a memory and a processor, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes any one of the above-described control methods for a computer device.

[0008] The computer-readable storage medium of the embodiment of the present application stores a computer program thereon, and when the program is executed by a processor, the processor executes any one of the above-described computer system control methods.

[0009] The computer system control method, control device, computer system, computer equipment, and computer-readable storage medium of the embodiments of the present application set a preset address and synchronously compare the preset address with the current instruction address. Only when a preset correspondence exists between the current instruction address and the preset address can the watchdog timer value be reset. This allows for proper execution of watchdog operations, enabling the computer system to recover to a controllable state when disturbed and operating abnormally, thereby improving the stability and reliability of the computer system.

[0010] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0012] FIG1 is a schematic flow chart of a control method according to certain embodiments of the present application;

[0013] FIG2 is a schematic diagram of a control device according to certain embodiments of the present application;

[0014] FIG3 is a flow chart of a control method according to certain embodiments of the present application;

[0015] FIG4 is another flow chart of a control method according to certain embodiments of the present application;

[0016] FIG5 is another flow chart of a control method according to certain embodiments of the present application;

[0017] FIG6 is another flow chart of a control method according to certain embodiments of the present application;

[0018] FIG7 is another schematic flow chart of a control method according to certain embodiments of the present application;

[0019] FIG8 is a schematic diagram of a computer device according to certain embodiments of the present application; and

[0020] FIG9 is a schematic diagram showing a connection between a computer device and a computer-readable storage medium according to an embodiment of the present application. Modes for Carrying Out the Invention

[0021] The following describes in detail embodiments of the present application, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0022] Referring to FIG1 , the control method according to the embodiment of the present application may be used in a computer system including a watchdog. The control method includes:

[0023] 01: Get the current instruction address of the currently executed instruction;

[0024] 02: Determine whether there is a preset corresponding relationship between the current instruction address and the preset address;

[0025] 03: When the current instruction address and the preset address have a preset corresponding relationship, reset the watchdog timing value;

[0026] 04: When the watchdog timer reaches a preset value, the computer system is controlled to take corresponding actions so that the computer system can be restored to a controllable state.

[0027] Referring to FIG. 2 , the control device 10 according to an embodiment of the present application can be used in a computer system including a watchdog. The control device 10 includes an acquisition module 12, a judgment module 14, a reset module 16, and a processing module 18. The control method according to an embodiment of the present application can be implemented by the control device 10 according to an embodiment of the present application, wherein step 01 can be implemented by the acquisition module 12, step 02 can be implemented by the judgment module 14, step 03 can be implemented by the reset module 16, and step 04 can be implemented by the processing module 18. Specifically, the acquisition module 12 is used to obtain the current instruction address of the currently executed instruction. The judgment module 14 is used to determine whether a preset correspondence exists between the current instruction address and a preset address. The reset module 16 is used to reset the watchdog timer value when a preset correspondence exists between the current instruction address and the preset address. The processing module 18 is used to control the computer system to generate a corresponding action when the watchdog timer value reaches a preset value, thereby restoring the computer system to a controllable state.

[0028] The control method and control device 10 of the present embodiment set a preset address and synchronously compare the preset address with the current instruction address. Only when a preset correspondence exists between the current instruction address and the preset address can the watchdog timer value be reset. In this way, the control method and control device 10 of the present embodiment can properly perform watchdog operations and restore the computer system to a controllable state when it is disturbed and operating abnormally, thereby improving the stability and reliability of the computer system.

[0029] Specifically, a computer system includes a watchdog timer (WDT). A watchdog is a means of monitoring system operation and includes both hardware and software watchdogs. In certain embodiments, a combination of hardware and software can be used to monitor the operation of the computer system. The watchdog includes a watchdog timer that counts during operation. In one embodiment, if the computer system is operating stably, the watchdog timer is reset based on a control signal to ensure normal system operation. If no control signal to reset the watchdog timer or clear the watchdog timer is received by the preset time, the system is considered to have failed, and an interrupt handler is executed or the system is forced to reset. This allows the computer system to automatically resume normal operation without human intervention. However, to avoid system resets, some technicians place clear watchdog timer instructions in multiple locations within the system. This indiscriminate feeding of the watchdog timer results in irrational execution of clear watchdog timer instructions, affecting the effectiveness of the watchdog timer and resulting in reduced stability and reliability of the computer system. The control method of the embodiment of the present application sets a preset address and synchronously compares the preset address with the current instruction address. Only when there is a preset corresponding relationship between the current instruction address and the preset address can the watchdog timing value be reset, thereby solving the above problem.

[0030] Specifically, in one embodiment, the control method of the present application can be implemented by a control device 10, which includes a microcontroller unit (MCU) including a program counter (PC). The program counter sequentially stores multiple instructions currently being executed and recently executed by the MCU. This instruction sequence is referred to as the PC value. The multiple instructions in the PC value are stored in the order in which they are executed by the MCU. When the MCU is operating, the instructions in the PC value are continuously retrieved by the MCU, and new instructions are sequentially added to the PC value, allowing the MCU to continuously retrieve new instructions. When the MCU executes a program after power-on, it can obtain the current instruction address of the program's currently executed instruction, where the currently executed instruction is the instruction currently being executed on the system. The current instruction address of the currently executed instruction can be determined based on the PC value. For example, the current instruction address of the currently executed instruction can be determined to be 0100H based on the PC value; or it can be determined to be 0200H based on the PC value, without limitation. A preset address is pre-set within the computer system, and the current instruction address is compared with the preset address in real time to determine whether a preset correspondence exists between the current instruction address and the preset address. If a preset correspondence exists between the current instruction address and the preset address, the watchdog timer value is reset; if the watchdog timer value reaches the preset value, the computer system is controlled to take corresponding actions to restore the computer system to a controllable state. In this way, by setting a preset address and the current instruction address to implement address-based watchdog feeding, the watchdog operation can be properly executed, and the computer system can be restored to a controllable state when it is disturbed and operating abnormally, thereby improving the stability and reliability of the computer system.

[0031] It's worth noting that when using a computer system, ambient interference can cause internal programs to escape into unpredictable locations. This includes, but is not limited to, electrical noise, power failures, and electrostatic discharges. For example, ambient interference can include signals radiated from walkie-talkies, microwave ovens, or arcing from industrial relays.

[0032] In one embodiment, the preset address can be pre-set to 0080H, and the preset value of the watchdog can be set to 400 (which can be understood as setting the preset time of the watchdog to 400ms). The current PC value is executed to 0050H. Due to the presence of an industrial relay in the surrounding area, the industrial relay generates an arc, causing the PC value to jump to 0200H, resulting in program execution disorder, the internal program running away, and the program execution not passing the preset address 0080H. When the watchdog timing value can be increased from 0ms to 400ms, the control computer system will generate corresponding actions to enable the computer system to be restored to a controllable state. After the system is reset, the watchdog timing value is cleared (i.e., 400ms is cleared), so that the watchdog is restarted from 0ms. In this way, the control method and control device 10 of the embodiment of the present application can reasonably perform the operation of the watchdog, and can be restored to a controllable state when the computer system is disturbed and working abnormally, thereby improving the stability and reliability of the computer system.

[0033] It's worth noting that, in certain embodiments, the program portion of a computer system includes a Code area and a Data area. The Code area is used to store instructions, and the Data area is used to store data. During normal computer system operation, instructions in the Code area are read. However, in the presence of ambient interference, internal programs may escape into the Data area. In related art, the Data area may store binary data values ​​corresponding to clear watchdog timer instructions. If an internal program escapes into the Data area and executes the binary data corresponding to the clear watchdog timer instruction, it will be equivalent to executing the clear watchdog timer instruction, clearing the timer value, making it difficult to reset the computer system. This infinite loop in the Data area can lead to poor reliability of the computer system. The computer system control method of the present embodiment only resets the watchdog timer value when a preset correspondence exists between the current instruction address and a preset address. This ensures that even if the program escapes into the Data area, the data in the Data area will not affect the clearing of the watchdog timer value. Therefore, when the watchdog timer value reaches a preset value, the computer system can initiate a corresponding action, restoring the computer system to a controllable state and improving the reliability of the computer system.

[0034] In some embodiments, the preset corresponding relationship includes any one of the following: the current instruction address is the same as the preset address; the difference between the current instruction address and the preset address is a preset difference; the current instruction address and the preset address satisfy a preset relationship.

[0035] In one embodiment, when determining whether a preset correspondence exists between the current instruction address and the preset address, the preset correspondence may be that the current instruction address and the preset address are identical. Thus, the watchdog timer value is reset only when the current instruction address and the preset address are determined to be identical. For example, the preset address may be 0080H. If the current instruction address of the currently executed instruction is 0080H, it is determined that the current instruction address and the preset address are identical, and a preset correspondence exists between the current instruction address and the preset address, and the watchdog timer value is reset.

[0036] In another embodiment, when determining whether a preset correspondence exists between the current instruction address and the preset address, the preset correspondence may be that the difference between the current instruction address and the preset address is a preset difference. Thus, the watchdog timer value is reset only when the difference between the current instruction address and the preset address is determined to be the preset difference. For example, the preset difference may be 2, the preset address may be 0080H, and when the current instruction address of the currently executed instruction is obtained as 0078H, it is determined that the difference between the current instruction address and the preset address is 2, and a preset correspondence exists between the current instruction address and the preset address, and the watchdog timer value is reset.

[0037] In another embodiment, when determining whether a preset correspondence exists between the current instruction address and the preset address, it may be determined whether the current instruction address and the preset address satisfy a preset relationship. Thus, the watchdog timer value can be reset only when it is determined that the current instruction address and the preset address satisfy the preset relationship. The preset relationship may be user-defined or pre-set, and is not limited here.

[0038] It should be noted that the above examples and specific numerical values ​​are for the convenience of explaining the implementation of this application and should not be understood as limiting the scope of protection of this application.

[0039] It is worth mentioning that, in certain embodiments, the conditions for the watchdog timer value to reach a preset value include, but are not limited to: the watchdog timer value being the preset value, the difference between the watchdog timer value and the preset value being a preset fixed value, etc. Specifically, in one embodiment, the preset value may be 400ms. When the watchdog timer value can be incremented from 0ms to 400ms, the watchdog timer value can be considered to be the preset value, and the watchdog timer value has met the preset value condition. In another embodiment, the preset value may be 400ms, and the preset fixed value may be -2ms. When the watchdog timer value can be incremented from 0ms to 398ms, the difference between the watchdog timer value and the preset value being a preset fixed value, and the watchdog timer value has met the preset value condition. In another embodiment, the preset value can be 400ms, and the preset fixed value is +5ms. When the watchdog timing value can increase from 0ms to 405ms, it can be considered that the difference between the watchdog timing value and the preset value is the preset fixed value. At this time, the watchdog timing value meets the preset value condition.

[0040] It should be noted that the above examples and specific numerical values ​​are for the convenience of explaining the implementation of this application and should not be understood as limiting the scope of protection of this application.

[0041] In some embodiments, controlling the computer system to generate corresponding actions includes at least one of the following: resetting, hardware coordinated interruption, jumping to a preset address, calling a special processing program, shutting down or suspending the computer system, and transferring the processing to other units.

[0042] In one embodiment, when the timing value of the watchdog reaches a preset value, the computer system is controlled to reset so that the computer system can be restored to a controllable state.

[0043] In another embodiment, when the watchdog timer reaches a preset value, the computer system is controlled to cooperate with the hardware to interrupt, so that the computer system can be restored to a controllable state.

[0044] In yet another embodiment, when the watchdog timer reaches a preset value, the computer system is controlled to jump to a preset address, thereby restoring the computer system to a controllable state. It is worth noting that the preset address can be pre-set. If the computer system's internal program fails due to peripheral interference, the computer system can be controlled to jump to the preset address, thereby restoring the computer system to a controllable state.

[0045] In yet another embodiment, when the watchdog timer reaches a preset value, the control computer system invokes a special processing program to restore the computer system to a controllable state. It is worth noting that the special processing program can be a pre-set program that can handle situations where the computer system's internal program may be lost due to peripheral interference, thereby restoring the computer system to a controllable state.

[0046] In another embodiment, when the watchdog timer reaches a preset value, the computer system is controlled to shut down or pause and be processed by other units, so that the computer system can be restored to a controllable state.

[0047] In certain embodiments, the corresponding actions generated by the aforementioned control computer system may be used individually or in combination, which is not limited herein.

[0048] In some embodiments, the computer system includes a program stack register, and the control method further includes:

[0049] When a preset corresponding relationship exists between the current instruction address and the preset address, the program stack register is reset.

[0050] In some embodiments, the above steps may be implemented by the control device 10 , that is, the control device 10 is configured to reset the program stack register when a preset correspondence exists between the current instruction address and the preset address.

[0051] Specifically, a computer system includes a program stack register, which includes a stack pointer register (SP), also known as an SP register. The SP register can be used to store the stack pointer and manage stack space. During program execution, operations such as function calls and termination processing require pushing and popping data from the stack. Therefore, the SP register can be used to store the stack address pointer, ensuring the normal operation of the program. However, to avoid system resets, some technicians set up a subroutine to clear the watchdog timer. This subroutine uses the SP register to store and call the subroutine, thereby placing the clear watchdog timer instruction in multiple locations within the subroutine. This results in irrational execution of the clear watchdog timer instruction, affecting the effectiveness of the watchdog timer and reducing the stability and reliability of the computer system. The control method and control device 10 of the present embodiment not only implements address-based clearing of the watchdog timer by setting a preset address, but also allows for resetting the program stack register to avoid technicians generating and calling the clear watchdog timer subroutine multiple times. This improves system stability and reliability. Resetting the program stack register is not only necessary to facilitate address-based clearing of the watchdog timer; it is also a method for making the system more reliable, further improving system reliability.

[0052] In some embodiments, the computer system includes a system register, and the control method further includes:

[0053] When there is a preset corresponding relationship between the current instruction address and the preset address, the system register is reset.

[0054] In some embodiments, the above steps may be implemented by the control device 10 , that is, the control device 10 is configured to reset the system register when a preset correspondence exists between the current instruction address and the preset address.

[0055] Specifically, system registers store and reflect program status information. If a computer system's internal program fails due to peripheral interference, the program status information stored and reflected in the system registers may be incorrect, affecting the normal operation of the computer system. Therefore, resetting the system registers when the current instruction address corresponds to a preset address can ensure the stability and reliability of the computer system.

[0056] In some embodiments, the system registers include an interrupt flag register, an emulation mode register, a burn-in mode register, and a digital signal processing register.

[0057] Specifically, the interrupt flag register can store an interrupt flag, which is used to indicate whether a certain interrupt request has occurred. In one embodiment, when an interrupt request occurs, the corresponding interrupt flag will be set to "1", indicating that the interrupt request has been triggered. After the interrupt service routine handles the interrupt request, the corresponding interrupt flag needs to be cleared, that is, set to "0", so that the next interrupt request can be triggered normally. However, in the case where the internal program of the computer system runs away due to peripheral interference, the interrupt flag register may be confused, that is, the interrupt flag may be incorrect, which in turn causes errors when other functions are subsequently executed. For example: when the internal program of the computer system runs away due to peripheral interference, the interrupt flag is still set to "1", and the corresponding hardware is marked as "interrupted", which affects the next interrupt request from being triggered. The control method of the computer system according to the embodiment of the present application resets the interrupt flag register when there is a preset correspondence between the current instruction address and the preset address to ensure that the interrupt flag is restored to the correct state. It can be understood that when there is a preset correspondence between the current instruction address and the preset address, it can be determined that the system is not in interrupt mode (i.e., not in "interrupt"), and the interrupt flag should not be set to "1". If the interrupt flag is set to "1", then the interrupt flag is wrong and the interrupt flag register should be reset.

[0058] In one embodiment, the system register further includes an In-Circuit Emulator (ICE) mode register. When a preset correspondence exists between a current instruction address and a preset address, the ICE mode register is reset.

[0059] In one embodiment, the system register further includes a burning mode register, and when a preset corresponding relationship exists between the current instruction address and the preset address, the burning mode register is reset.

[0060] In one embodiment, the system register further includes a digital signal processing register, and when a preset corresponding relationship exists between the current instruction address and the preset address, the digital signal processing register is reset.

[0061] It is worth mentioning that the system registers include but are not limited to interrupt flag registers, registers in simulation mode, burn mode registers and registers in digital signal processing. The above examples are for the convenience of explaining the implementation of this application and should not be understood as limiting the scope of protection of this application.

[0062] In some embodiments, the computer system includes a frequency oscillator, and the control method further includes:

[0063] When a preset corresponding relationship exists between the current instruction address and the preset address, the frequency setting value of the frequency oscillator is reset.

[0064] Specifically, the frequency oscillator is set to a frequency setting value before leaving the factory. However, during actual use, the frequency oscillator may deviate from the actual frequency setting value due to peripheral interference and other conditions. For example, the frequency setting value of the frequency oscillator is set to 10MHz before leaving the factory. However, during actual use, the actual frequency setting value of the frequency oscillator is 11.3MHz due to peripheral interference and other conditions. Thus, when there is a preset correspondence between the current instruction address and the preset address, the frequency setting value of the frequency oscillator is reset so that the frequency setting value of the frequency oscillator is restored to 10MHz.

[0065] Referring to FIG. 3 , in some embodiments, the computer system includes a main loop program, and the preset address is set in the main loop program.

[0066] Specifically, the main loop program can be understood as the portion of the computer system program that enters an infinite loop of a combination of key subroutines, with a preset address set within the main loop program. In one embodiment, the control device 10 includes a single-chip microcomputer, which is a programmable device that can be programmed to meet specific requirements during use. After configuration initialization is completed, the main loop program is entered. The main loop program can be understood as an infinite loop program composed of a combination of key subroutines. In one embodiment, the main loop program can include a main loop entry and three sub-loop programs (as shown in Figure 3), namely sub-loop program 1, sub-loop program 2, and sub-loop program 3. The preset address can be set within the main loop program and located at the main loop entry. In another embodiment, the main loop program can include a main loop entry and three sub-loop programs (sub-loop program 1, sub-loop program 2, and sub-loop program 3). The preset address can be set within sub-loop program 1 (as shown in Figure 4). In some embodiments, the preset address is any address set within the main loop program, which is not limited here. It should be noted that the above examples and specific numerical values ​​are for the convenience of explaining the implementation of this application and should not be understood as limiting the scope of protection of this application.

[0067] It is worth noting that the instruction at the preset address location can be a setting output port instruction, a setting input port instruction, a light-on instruction, an operation instruction, and the like, without limitation herein. In one embodiment, the instruction at the preset address location can be a light-on instruction. In determining whether a preset correspondence exists between the current instruction address and the preset address, the preset correspondence can be that the current instruction address and the preset address are the same. Thus, when the current instruction address is determined to be the preset address, the processor 20 can reset the watchdog timer value.

[0068] In certain embodiments, a timer interrupt may occur while the microcontroller is executing the main loop. If an interrupt occurs, the interrupt content is processed first (as shown in Figure 5). After the interrupt is acknowledged, the interrupt service routine begins execution. After the interrupt service routine completes, the system returns from the breakpoint at which the main loop is executed. Thus, setting the preset address within the main loop makes the preset address placement more reasonable, more compatible with the overall computer system design framework, and further enhances stability and reliability.

[0069] Referring again to Figure 3, in one embodiment, the main loop program includes a main loop entry and three sub-loop programs, namely sub-loop program 1, sub-loop program 2, and sub-loop program 3. The preset address can be the address at the main loop entry. The instruction at the preset address can be a set output port instruction, a set input port instruction, a light-on instruction, an arithmetic instruction, and the like, without limitation. Upon determining that the current instruction address is the preset address, the processor 20 can reset the watchdog timer value.

[0070] Referring to FIG. 6 , in certain embodiments, the computer system includes an initialization program, and the control method includes:

[0071] 05: Execute the initialization program;

[0072] 06: Execute the main loop program after executing the initialization program.

[0073] In some embodiments, the control device 10 includes a first execution module and a second execution module. Step 05 can be implemented by the first execution module, and step 05 can be implemented by the second execution module. In other words, the first execution module is used to execute the initialization program. The second execution module is used to execute the main loop program after executing the initialization program.

[0074] Specifically, the computer system includes an initialization program (main_initial). The initialization program is the first step in the computer system's operation to prepare it for operation. After the system is running, the initialization program is executed first, followed by the main loop program. Furthermore, a preset address is set within the main loop program.

[0075] Referring to FIG. 7 , in certain embodiments, the computer system includes an initialization program, and the control method includes:

[0076] 07: Declare the preset address in the initialization procedure.

[0077] In some embodiments, the control device 10 includes a declaration module, and step 07 can be implemented by the declaration module. In other words, the declaration module is used to declare the preset address in the initialization program.

[0078] Specifically, the computer system includes an initialization program (main_initial), in which a preset address can be declared. In some embodiments, the initialization program can also configure IO ports, set timers, and so on. Thus, the preset address can be pre-declared in the initialization program to facilitate synchronous comparison of the preset address with the current instruction address to determine whether there is a preset correspondence between the current instruction address and the preset address.

[0079] In certain embodiments, the control method comprises:

[0080] When the computer system is reset, the preset address remains unchanged.

[0081] In some embodiments, the above steps can be implemented by the control device 10, that is, the control device 10 is used to keep the preset address unchanged when the computer system is reset.

[0082] In this way, the preset address remains unchanged after the computer system is reset. It is understandable that if the preset address is declared as 0100H in the initialization program, the address of the computer system initialization program will not include 0100H.

[0083] In one embodiment, the preset address is declared as 0100H in the initialization program, and the computer system is reset when the watchdog timer value reaches the preset value. After the computer system is reset, the preset address is still 0100H.

[0084] In some embodiments, the preset address can be determined based on input information.

[0085] Specifically, in some embodiments, the preset address can be determined based on input information. That is, in some embodiments, the preset address can be modified according to the technician's wishes, and the technician can customize the preset address by inputting information. In one embodiment, the technician can use input information to declare the preset address as 0100H in the initialization program. In another embodiment, the technician can use input information to declare the preset address as 0200H in the initialization program. In yet another embodiment, the technician can use input information to declare the preset address as 0300H in the initialization program. In this way, the technician can customize the preset address by inputting information, so that the preset address setting meets the technician's usage needs and is more suitable for the overall design framework of the computer system.

[0086] In one example, the preset address may be 0100H. After the computer system is reset, the preset address may be changed to 0200H according to the technician's wishes.

[0087] It's worth noting that in some implementations, the preset address can be pre-set before the program runs, based on the overall design framework of the computer system. Furthermore, the preset address cannot be arbitrarily changed by a technician while the computer system is in use; it is a fixed address. For example, the preset address is fixed at 0100H, and a technician cannot change it to 0200H, 0300H, or similar. Even after the computer system performs a corresponding action (such as a reset), the technician cannot change the preset address; the preset address remains unchanged at 0100H. This effectively avoids the risk of errors caused by technicians customizing the preset address, ensures the effectiveness of the watchdog function, and further enhances the stability and reliability of the computer system.

[0088] The present application discloses a computer system, which includes a watchdog and the control device 10 described above.

[0089] The computer system of the present application sets a preset address and synchronously compares the preset address with the current instruction address. Only when a preset correspondence exists between the current instruction address and the preset address can the watchdog timer be reset. In this way, the computer system of the present application can properly perform watchdog operations and restore the computer system to a controllable state when it is disturbed and operating abnormally, thereby improving stability and reliability.

[0090] Please refer to Figures 1 and 8 together. The present application discloses a computer device 100, which includes a processor 20. The processor 20 is used to obtain a current instruction address of a currently executed instruction; determine whether there is a preset correspondence between the current instruction address and a preset address; when there is a preset correspondence between the current instruction address and the preset address, reset the watchdog timing value; when the watchdog timing value reaches a preset value, control the computer system to generate a corresponding action so that the computer system can be restored to a controllable state.

[0091] The computer device 100 of the present embodiment can set a preset address and synchronously compare the preset address with the current instruction address. Only when a preset correspondence exists between the current instruction address and the preset address can the watchdog timer value be reset. This allows for proper watchdog operation, enabling the computer system to recover from interference and abnormal operation, thereby improving the stability and reliability of the computer system.

[0092] The processor 20 may refer to a driver board. The driver board may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0093] The computer device 100 of the embodiments of the present application may be a terminal device equipped with a processor 20. For example, the computer device 100 may include a smartphone, a smartwatch, a tablet computer, or other terminal device, without limitation herein. In one embodiment, the computer device 100 may be a computer, which includes a housing and a processor 20, with the processor 20 being mounted within the housing.

[0094] It is worth mentioning that the control method of the above embodiment can be implemented by the control device 10, and can also be implemented by the computer device 100 of the embodiment of the present application, which is not limited here.

[0095] Please refer to Figures 1 and 9 together. The computer-readable storage medium 300 of the embodiment of the present application stores a computer program thereon. When the computer program is executed by the processor 20, the steps of the control method of any of the above embodiments are implemented.

[0096] The computer-readable storage medium 300 of the aforementioned embodiment sets a preset address and synchronously compares the preset address with the current instruction address. Only when a preset correspondence exists between the current instruction address and the preset address does the watchdog timer reset its value. This ensures proper watchdog operation, enabling the computer system to recover from interruptions and abnormal operation, thereby improving the stability and reliability of the computer system.

[0097] In some embodiments, the computer system control method can be implemented by the computer device 100 of the present application. It should be noted that the computer-readable storage medium 300 can be a storage medium built into the computer device 100 or a storage medium that can be plugged into the computer device 100.

[0098] It is understood that a computer program includes computer program code. The computer program code may be in source code form, object code form, an executable file, or some intermediate form. The computer-readable storage medium 300 may include any entity or device capable of carrying computer program code, a recording medium, a USB flash drive, a mobile hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), and software distribution media.

[0099] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0100] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0101] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and a portable compact disc read-only memory (CDROM).

[0102] Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0103] It should be understood that various parts of the embodiments of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0104] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0105] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0106] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0107] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are illustrative and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above implementation methods within the scope of the present application.

Claims

1. A control method for a computer system, characterized in that, The computer system includes a watchdog, and the control method includes: Obtain the current instruction address of the currently executing instruction; Determine whether there is a preset corresponding relationship between the current instruction address and a preset address; When there is the preset corresponding relationship between the current instruction address and the preset address, reset the timing value of the watchdog; When the timing value of the watchdog reaches a preset value, control the computer system to generate corresponding actions so that the computer system can be restored to a controllable state.

2. The control method of the computer system according to claim 1, characterized in that The preset corresponding relationship includes any one of the following: The current instruction address is the same as the preset address; The difference between the current instruction address and the preset address is a preset difference; The current instruction address and the preset address satisfy a preset relational expression.

3. The control method of the computer system according to claim 1, characterized in that Controlling the computer system to generate corresponding actions includes at least one of the following: Reset; Hardware-assisted interrupt; Jump to a preset address; Call a special handler; Shut down or pause the computer system and transfer it to other units for processing.

4. The control method of the computer system according to claim 1, characterized in that, The computer system includes a program stack register, and the control method further includes: When there is the preset corresponding relationship between the current instruction address and the preset address, reset the program stack register.

5. The control method of the computer system according to claim 1, characterized in that, The computer system includes a system register, and the system register is used to store system values. The control method for the system register further includes: When there is the preset corresponding relationship between the current instruction address and the preset address, reset the system register.

6. The control method of the computer system according to claim 5, characterized in that, The system register includes an interrupt flag register, an in-emulation mode register, a programming mode register, and a digital signal processing in-register.

7. The control method of the computer system according to claim 1, wherein The computer system includes a frequency oscillator, and the control method further includes: When there is the preset corresponding relationship between the current instruction address and the preset address, reset the frequency setting value of the frequency oscillator.

8. The control method of the computer system according to claim 1, characterized in that, The computer system includes a main loop program, and the preset address is set within the main loop program.

9. The control method of the computer system according to claim 8, wherein, The computer system includes an initialization program, and the control method includes: Execute the initialization program; After executing the initialization program, execute the main loop program.

10. The control method of the computer system according to claim 9, wherein The computer system includes an initialization program, and the control method includes: Declare the preset address in the initialization program.

11. The control method of the computer system according to claim 1, characterized in that, The control method includes: When the computer system generates corresponding actions, keep the preset address unchanged.

12. The control method of the computer system according to claim 1, wherein The preset address can be determined according to input information.

13. A control device for a computer system, characterized in that The computer system includes a watchdog, and the control device includes: An acquisition module, which is used to acquire the current instruction address of the currently executing instruction; A judgment module, which is used to judge whether there is a preset corresponding relationship between the current instruction address and a preset address; A reset module, which is used to reset the timing value of the watchdog when there is the preset corresponding relationship between the current instruction address and the preset address; A processing module, which is used to control the computer system to generate corresponding actions when the timing value of the watchdog reaches a preset value so that the computer system can be restored to a controllable state.

14. A computer system, characterized in that, The computer system includes a watchdog and the control device described in claim 13.

15. A computer device, characterized in that, It includes a memory and a processor. Computer-readable instructions are stored in the memory. When the computer-readable instructions are executed by the processor, the processor is caused to execute the control method of the computer system described in any one of claims 1 to 12.

16. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, the processor is caused to execute the control method of the computer system described in any one of claims 1 to 12.

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