Pixel driving circuit and driving method therefor, and display panel

Abstract

A pixel driving circuit (PDC) and a driving method therefor, and a display panel (PNL). In the pixel driving circuit (PDC), a second end of a data writing module (M1), a second end of a reference voltage module (M3), a first end (Cst11) of a first capacitor (Cst1), and a gate of a driving transistor (DT) are electrically connected to a fifth node (NG). A second end of a first light-emitting control module (M2) and a first electrode of the driving transistor (DT) are electrically connected to a first node (N1). A second electrode of the driving transistor (DT), a first end of a second light-emitting control module (M4), a second end (Cst12) of the first capacitor (Cst1), and a second end (Cst22) of a second capacitor (Cst2) are electrically connected to a fourth node (NS). A second end of a voltage stabilizing module (M6), a first end (Cst21) of the second capacitor (Cst2), and a first end (Cst31) of a third capacitor (Cst3) are electrically connected to a third node (N3).

Description

Pixel driving circuit and driving method thereof, and display panel Technical Field

[0001] The present disclosure relates to the technical field of display panels, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] In the display industry, oxide processes are often used due to their high uniformity. Internal compensation circuits are also commonly used due to their low IC requirements, low cost, and simple algorithms. However, in existing pixel driver circuits, fluctuations in the drive voltage can lead to fluctuations in the gate voltage of the driver transistor, which in turn reduces display quality.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a pixel driving circuit and a driving method thereof, as well as a display panel, so as to reduce the impact of fluctuations in the gate voltage of the driving transistor on the sub-pixel light-emitting phase.

[0006] According to one aspect of the present disclosure, a pixel driving circuit is provided, including a driving transistor, a data writing module, a first light-emitting control module, a reference voltage module, a second light-emitting control module, a voltage stabilizing module, a first capacitor, a second capacitor, and a third capacitor; wherein a second end of the data writing module, a second end of the reference voltage module, a first end of the first capacitor, and a gate electrode of the driving transistor are electrically connected to a fifth node; a second end of the first light-emitting control module and a first electrode of the driving transistor are electrically connected to the first node; a second electrode of the driving transistor, a first end of the second light-emitting control module, a second end of the first capacitor, and a second end of the second capacitor are electrically connected to a fourth node; and a second end of the voltage stabilizing module, a first end of the second capacitor, and a first end of the third capacitor are electrically connected to a third node.

[0007] The second end of the third capacitor is used to load the driving power supply voltage; the data writing module is used to load the data voltage to the fifth node in response to the selection level of the first scanning signal; the reference voltage module is used to load the reference voltage to the fifth node in response to the selection level of the second scanning signal; the first light-emitting control module is used to load the driving power supply voltage to the first node in response to the selection level of the first light-emitting signal; the voltage stabilizing module is used to load the regulated voltage to the third node in response to the selection level of the second reset signal; and the second light-emitting control module is used to be turned on in response to the selection level of the second light-emitting signal.

[0008] According to an embodiment of the present disclosure, the pixel driving circuit further includes a reset module;

[0009] The second end of the reset module, the second end of the second light emitting control module, and the light emitting element are electrically connected to the second node; the reset module is used to load the initialization voltage to the second node in response to the selection level of the first reset signal.

[0010] According to an embodiment of the present disclosure, the capacitance value of the third capacitor is smaller than the capacitance value of the second capacitor.

[0011] According to an embodiment of the present disclosure, the pixel driving circuit further includes a noise reduction module; a first end of the noise reduction module is electrically connected to the first end of the third capacitor, and a second end of the noise reduction module is electrically connected to the third node;

[0012] The noise reduction module is configured to be turned on in response to a strobe level of the second reset signal.

[0013] According to an embodiment of the present disclosure, the pixel driving circuit further includes a noise reduction module; a first end of the noise reduction module is electrically connected to the first end of the third capacitor, and a second end of the noise reduction module is electrically connected to the third node;

[0014] The noise reduction module is configured to be turned on in response to a strobe level of a third reset signal.

[0015] According to an embodiment of the present disclosure, the transistors in the pixel driving circuit are metal oxide transistors.

[0016] According to an embodiment of the present disclosure, the regulated voltage is one of the reference voltage, the initialization voltage and the driving power supply voltage.

[0017] According to one embodiment of the present disclosure, the data writing module includes a first transistor, a first electrode of the first transistor is electrically connected to a data voltage lead, a second electrode of the first transistor is electrically connected to a fifth node, and a gate of the first transistor is electrically connected to a first scan signal lead;

[0018] The reference voltage module includes a third transistor, a first electrode of the third transistor is electrically connected to the reference voltage lead, a second electrode of the third transistor is electrically connected to the fifth node, and a gate of the third transistor is electrically connected to the second scan signal lead;

[0019] The first light emitting control module includes a second transistor, a first electrode of the second transistor is electrically connected to the driving power supply voltage lead, a second electrode of the second transistor is electrically connected to the first node, and a gate of the second transistor is electrically connected to the first light emitting signal lead;

[0020] The second light emitting control module includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the fourth node, a second electrode of the fourth transistor is electrically connected to the second node, and a gate of the fourth transistor is electrically connected to the second light emitting signal lead;

[0021] The voltage stabilization module includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the stabilization voltage lead, a second electrode of the sixth transistor is electrically connected to the third node, and a gate of the sixth transistor is electrically connected to the second reset signal lead.

[0022] According to one embodiment of the present disclosure, the reset module includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the initialization voltage lead, a second electrode of the fifth transistor is electrically connected to the second node, and a gate of the fifth transistor is electrically connected to the first reset signal lead.

[0023] According to one embodiment of the present disclosure, the noise reduction module includes a seventh transistor, the first electrode of the seventh transistor is electrically connected to the first end of the third capacitor, the second electrode of the seventh transistor is electrically connected to the third node; the gate of the seventh transistor is electrically connected to the second reset signal lead.

[0024] According to one embodiment of the present disclosure, the noise reduction module includes a seventh transistor, the first electrode of the seventh transistor is electrically connected to the first end of the third capacitor, the second electrode of the seventh transistor is electrically connected to the third node; the gate of the seventh transistor is electrically connected to the third reset signal lead.

[0025] According to a second aspect of the present disclosure, a driving method of a pixel driving circuit is further provided, which is applied to the above-mentioned pixel driving circuit; wherein the driving method of the pixel driving circuit includes:

[0026] In a reset phase, the strobe level of the second scan signal is applied to the pixel driving circuit so that the reference voltage is applied to the fifth node, and the strobe level of the second reset signal is applied to the pixel driving circuit;

[0027] In the compensation phase, the first light emitting signal, the second scanning signal and the gating level of the second reset signal are applied to the pixel driving circuit;

[0028] In the data writing phase, applying a gate level of a first scanning signal to the pixel driving circuit so that the data voltage is applied to the fifth node;

[0029] In the light emitting stage, the strobe levels of the first light emitting signal and the second light emitting signal are applied to the pixel driving circuit.

[0030] According to one embodiment of the present disclosure, the pixel driving circuit further includes a reset module; a second terminal of the reset module, a second terminal of the second light emitting control module, and the light emitting element are electrically connected to the second node; the reset module is configured to load an initialization voltage to the second node in response to a strobe level of a first reset signal;

[0031] The driving method of the pixel driving circuit further includes:

[0032] In the reset phase, the second light emitting signal and the gate level of the first reset signal are applied to the pixel driving circuit, so that the initialization voltage is applied to the fourth node.

[0033] According to an embodiment of the present disclosure, the driving method of the pixel driving circuit further includes:

[0034] During the compensation phase and the data writing phase, the gate level of the first reset signal is applied to the pixel driving circuit.

[0035] According to one embodiment of the present disclosure, the pixel driving circuit further includes a noise reduction module; a first end of the noise reduction module is electrically connected to the first end of the third capacitor, and a second end of the noise reduction module is electrically connected to the third node; the noise reduction module is configured to be turned on in response to a strobe level of a third reset signal;

[0036] The driving method of the pixel driving circuit further includes:

[0037] In the light emitting phase, the gate level of the third reset signal is applied to the pixel driving circuit.

[0038] According to one embodiment of the present disclosure, the pixel driving circuit further includes a noise reduction module; a first end of the noise reduction module is electrically connected to the first end of the third capacitor, and a second end of the noise reduction module is electrically connected to the third node; the noise reduction module is configured to be turned on in response to a strobe level of a third reset signal;

[0039] The driving method of the pixel driving circuit further includes:

[0040] In the light emitting phase, the gate level of the third reset signal is not applied to the pixel driving circuit.

[0041] According to a third aspect of the present disclosure, a display panel is further provided, comprising the above-mentioned pixel driving circuit.

[0042] The present disclosure provides a third capacitor in the pixel drive circuit, so that during the light-emitting phase, the capacitance connected to the fourth node is the equivalent capacitance of the second and third capacitors connected in series. According to the calculation formula for the equivalent capacitance of series capacitors, the equivalent capacitance is smaller than that obtained by simply providing the second capacitor, reducing the noise introduced into the fourth node. This makes the control voltage of the gate of the drive transistor more stable, thereby improving the stability of the drive transistor current.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0045] FIG1 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0046] FIG2 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0047] FIG3 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0048] FIG. 4 is an operation timing diagram of the pixel driving circuit in FIG. 3 in one embodiment of the present disclosure.

[0049] FIG5 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0050] FIG6 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0051] FIG. 7 is an operation timing diagram of the pixel driving circuit in FIG. 6 in one embodiment of the present disclosure.

[0052] 8-1 to 8-4 are equivalent circuit state diagrams of the pixel driving circuit in FIG6 at different stages according to the working timing diagram of FIG7 in one embodiment of the present disclosure.

[0053] FIG. 9 is another operation timing diagram of the pixel driving circuit in FIG. 6 in one embodiment of the present disclosure.

[0054] FIG10-1 is an equivalent circuit state diagram of the first sub-light-emitting stage of the pixel driving circuit in FIG6 in one embodiment of the present disclosure.

[0055] FIG10-2 is an equivalent circuit state diagram of the second sub-light-emitting phase of the pixel driving circuit in FIG6 in one embodiment of the present disclosure.

[0056] FIG11 is an equivalent circuit state diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0057] 12-1 to 12-4 are equivalent circuit state diagrams of the pixel driving circuit in FIG11 at different stages according to the working timing diagram of FIG7 in one embodiment of the present disclosure.

[0058] FIG13 is an equivalent circuit diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0059] FIG. 14 is an operation timing diagram of the pixel driving circuit in FIG. 13 in one embodiment of the present disclosure.

[0060] Explanation of the accompanying symbols: AA, display area; BB, peripheral area; BP, base substrate; Buff, buffer layer; CFL, color filter layer; COML, common electrode layer; Cst1, first capacitor; Cst11, first end of the first capacitor; Cst12, second end of the first capacitor; Cst2, second capacitor; Cst21, first end of the second capacitor; Cst22, second end of the second capacitor; Cst3, third capacitor; Cst31, first end of the third capacitor; Cst32, second end of the third capacitor; CVD1, first inorganic encapsulation layer; CVD2, second inorganic encapsulation layer; DBP, driving backplane; DH, row direction; DL, data line ;DRL, driving layer;DT, driving transistor;DV, column direction;EFL, light-emitting functional layer;EM1, first light-emitting signal;EM2, second light-emitting signal;EMA, first sub-light-emitting phase;EMB, second sub-light-emitting phase;G1, first scan signal;G2, second scan signal;GI, gate insulating layer;GL, scan line;GT, gate layer;IC, chip;IJP, organic encapsulation layer;ILD, interlayer dielectric layer;M1, data writing module;M2, first light-emitting control module;M3, reference voltage module; M4, second light-emitting control module; M5, reset module; M6, voltage stabilization module; M7, noise reduction module; N1, first node; N2, second node; N3, third node; NG, fifth node; NS, fourth node; PDC, pixel driving circuit; PDL, pixel definition layer; PE, pixel electrode; PEL, pixel electrode layer; PIX, sub-pixel; PIXL, pixel layer; PLN, planarization layer; PNL, display panel; RST1, first reset signal; RST2, second reset signal; RST3, third reset signal Signal; SCL, semiconductor layer; SD, source and drain metal layer; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; C7, coupling capacitor; TFE, thin film encapsulation layer; TFT, thin film transistor; TSL, touch function layer; Vdata, data voltage; VDD, driving power supply voltage; Vinit, initialization voltage; Vref, reference voltage; Vth, threshold voltage; Vx, regulated voltage. DETAILED DESCRIPTION

[0061] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0062] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0063] In the embodiments of the present disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region refers to the region through which current primarily flows.

[0064] In the embodiments of the present disclosure, when using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged. In the embodiments of the present disclosure, for any transistor, one of the "source electrode" and the "drain electrode" is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor, and the gate is referred to as the control terminal of the transistor. The first electrode can be the drain electrode, the second electrode can be the source electrode, or the first electrode can be the source electrode, and the second electrode can be the drain electrode. In the embodiments of the present disclosure, at least some signals have a high level and a low level; one of the high level and the low level can be used as the gating level of the signal, and the gating level of the signal can turn on the controlled transistor; the other of the high level and the low level can be used as the cutoff level of the signal, and the cutoff level of the signal can turn off the controlled transistor. For example, for a signal that controls a P-type transistor (the signal can be loaded to the control terminal of the P-type transistor), its gating level is a low level and its cutoff level is a high level. For another example, for a signal controlling an N-type transistor (the signal can be applied to the control terminal of the N-type transistor), its selection level is a high level, and its cutoff level is a low level.

[0065] An embodiment of the present disclosure provides a display panel PNL, as shown in FIG1 , wherein the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. The display area AA of the display panel PNL includes display units distributed in an array. The display units include sub-pixels PIX and pixel driving circuits PDC that drive the sub-pixels PIX. The display panel PNL has a plurality of scan lines GL arranged along a row direction DH in the display area AA, and each scan line GL is arranged in a one-to-one correspondence with each display unit row; the scan line GL is connected to each pixel driving circuit PDC of the corresponding display unit row. The display panel PNL has a plurality of data lines DL arranged along a column direction DV in the display area AA, and each data line DL is arranged in a one-to-one correspondence with each display unit column; the data line DL is connected to each pixel driving circuit PDC of the corresponding display unit column. In this way, the pixel driving circuit PDC of each display unit is connected to one scan line GL and one data line DL. When the strobe signal is loaded on the scan line GL, the data voltage loaded on the data line DL can be loaded to the pixel driving circuit PDC, so that the pixel driving circuit PDC can control the brightness of the sub-pixel PIX according to the written driving voltage.

[0066] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, it can be any one of the light-emitting elements such as OLED, PLED, QLED, Micro LED, Mini LED, etc. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, a red sub-pixel for emitting red light, a green sub-pixel for emitting green light, and a blue sub-pixel for emitting blue light. It is understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also have sub-pixels PIX of other colors (for example, a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0067] In one embodiment of the present disclosure, referring to FIG. 2 , a display panel PNL may include a base substrate BP, a drive layer DRL, and a pixel layer PIXL, which are stacked in sequence. The pixel layer PIXL includes subpixels PIX, and the drive layer DRL includes a pixel drive circuit PDC for driving the subpixels PIX. Each subpixel PIX can emit light to display an image under the drive of the pixel drive circuit PDC. Furthermore, the display panel PNL includes a thin film encapsulation layer TFE located on a side of the pixel layer PIXL away from the base substrate BP. The thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0068] Optionally, the substrate BP can be a substrate of an inorganic material, or a substrate of an organic material; of course, it can also be a composite substrate formed by stacking a substrate of an inorganic material and a substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate BP can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate BP can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate BP can also be a flexible substrate, for example, the material of the substrate BP can include polyimide.

[0069] Optionally, in the drive layer DRL, any pixel drive circuit PDC may include a thin film transistor TFT and a storage capacitor. Furthermore, the thin film transistor TFT may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0070] It is understandable that, among the transistors in the pixel driving circuit PDC, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit PDC, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit PDC, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0071] Optionally, the drive layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate BP and the pixel layer PIXL. The various thin film transistors and storage capacitors may be located in film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source / drain metal layer SD. The positional relationship of the various film layers may be determined based on the film layer structure of the thin film transistor. Furthermore, the semiconductor layer SCL may be used to form the channel region of the transistor, and may also be used to form partial wiring or conductive structures by conductorization when necessary. The gate layer GT may be used to form one or more of the gate layer GT wirings such as the write control wiring, the reset control wiring, and the light emission control wiring, may also be used to form the gate of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer SD may be used to form source / drain metal layer wirings such as the data wiring and the drive power supply voltage wiring, and may also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer located between the semiconductor layer SCL and the substrate BP. As needed, any of the above-mentioned film layers such as the semiconductor layer SCL, the gate layer GT, the source / drain metal layer SD, etc. may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0072] Optionally, the driving layer DRL may further include a passivation layer. The passivation layer may be provided on a surface of the source / drain metal layer SD away from the substrate BP so as to protect the source / drain metal layer SD.

[0073] As an example, referring to FIG2 , the driving layer DRL may include a buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor.

[0074] In one embodiment of the present disclosure, the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional unit sandwiched between the two electrodes. For example, referring to FIG2 , the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML, which are stacked in sequence. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of ​​the display panel; the portion of the light-emitting functional layer EFL connected to the pixel electrode PE serves as the light-emitting functional unit of the sub-pixel PIX, and the common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional units of each sub-pixel PIX.

[0075] Furthermore, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode PE (the area directly connected to the light-emitting functional unit), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PIX. The light-emitting functional layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The portion of the light-emitting functional layer EFL located between the pixel electrode layer PEL and the common electrode layer COML can serve as a light-emitting functional unit. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form a sub-pixel PIX, wherein one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.

[0076] In one example, the pixel electrode PE serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0077] It is understood that the materials and film layers of the light-emitting functional unit vary depending on the type of light-emitting element. For example, when the light-emitting element is an OLED, the light-emitting functional unit may include an organic electroluminescent material layer and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0078] Referring to Figure 2 , the thin-film encapsulation layer (TFE) can be provided on the surface of the pixel layer PIXL facing away from the base substrate BP. It may include alternating inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing material degradation within the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin-film encapsulation layer (TFE) includes a first inorganic encapsulation layer (CVD1), an organic encapsulation layer (IJP), and a second inorganic encapsulation layer (CVD2) stacked sequentially on the side of the pixel layer PIXL facing away from the base substrate BP. The first inorganic encapsulation layer (CVD1) covers the display area and extends to the outside of the barrier wall; the organic encapsulation layer (CVD2) covers the organic encapsulation layer (IJP) and extends to the outside of the barrier wall. Outside the retaining wall, the second inorganic encapsulation layer CVD2 contacts the first inorganic encapsulation layer CVD1. This seals the organic encapsulation layer IJP between the first and second inorganic encapsulation layers CVD1 and CVD2, balancing the stresses within them. The first and second inorganic encapsulation layers CVD1 and CVD2 seal the organic encapsulation layer IJP, isolating it from water and oxygen.

[0079] In some embodiments of the present disclosure, referring to FIG. 2 , the display panel PNL may further include a touch function layer TSL. The touch function layer TSL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the display panel PNL has a touch function.

[0080] In some embodiments of the present disclosure, referring to FIG. 4 , the display panel PNL may further include a color filter layer CFL. The color filter layer CFL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP to reduce reflection of ambient light and improve display quality.

[0081] Optionally, the pixel drive circuit PDC includes at least a data write transistor, a drive transistor and a storage capacitor, and the gate of the drive transistor can be electrically connected to an electrode plate of the storage capacitor. The source of the data write transistor can be electrically connected to the data line DL, and the gate of the data write transistor can be electrically connected to the scan line GL. The pixel drive circuit PDC is configured so that when a scan signal is loaded on the scan line GL, the data write transistor is turned on, thereby causing the drive voltage on the data line DL to be written to the gate of the drive transistor and the storage capacitor. When the data write transistor is turned off, the drive voltage can be maintained by the storage capacitor. The drive transistor can output a drive current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It is understandable that the pixel drive circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors to enable the pixel drive circuit PDC to have better driving performance. For example, the pixel drive circuit PDC can be a pixel drive circuit of 7T1C (7 thin film transistors and one storage capacitor), 8T1C (8 thin film transistors and one storage capacitor) or other architectures.

[0082] For example, see Figures 3 and 4 showing a pixel driving circuit PDC and its corresponding timing diagram. As shown in Figure 3, the pixel driving circuit PDC includes a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor Cst1, and a second capacitor Cst2; the first transistor T1 is a data writing transistor. The second electrode of the first transistor T1, the second electrode of the third transistor T3, the first end Cst11 of the first capacitor, and the gate of the driving transistor DT are electrically connected to a fifth node NG. The second electrode of the second transistor T2 and the first electrode of the driving transistor DT are electrically connected to a first node N1. The second electrode of the driving transistor DT, the first electrode of the fourth transistor T4, the second end Cst12 of the first capacitor, and the second end Cst22 of the second capacitor are electrically connected to a fourth node NS. The second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4, and the light-emitting element are electrically connected to a second node N2.

[0083] The first terminal Cst21 of the second capacitor is configured to apply a driving power supply voltage VDD. A first electrode of the first transistor T1 is electrically connected to a data voltage line (for applying a data voltage Vdata), and a gate of the first transistor T1 is electrically connected to a first scan signal line (for applying a first scan signal G1). The first electrode of the second transistor T2 is electrically connected to the driving power supply voltage line (for applying a driving power supply voltage VDD), and a gate of the second transistor T2 is electrically connected to a first emission signal line (for applying a first emission signal EM1). The gate of the second transistor T2 is configured to turn on the second transistor T2 in response to the strobe level of the first emission signal EM1. A first electrode of the third transistor T3 is electrically connected to the reference voltage line (for applying a reference voltage Vref), and a gate of the third transistor T3 is electrically connected to the second scan signal line (for applying a second scan signal G2). The gate of the third transistor T3 is configured to apply the reference voltage Vref to the fifth node NG in response to the strobe level of the second scan signal G2. The gate of the fourth transistor T4 is electrically connected to the second light emitting signal lead (for applying the second light emitting signal EM2), and is configured to turn on the fourth transistor T4 in response to the strobe level of the second light emitting signal EM2. The first electrode of the fifth transistor T5 is electrically connected to the initialization voltage lead (for applying the initialization voltage Vinit), and the gate of the fifth transistor T5 is electrically connected to the first reset signal lead (for applying the first reset signal RST1), and is configured to apply the initialization voltage Vinit to the second node N2 in response to the strobe level of the first reset signal RST1.

[0084] 4 , the process of driving the pixel driving circuit PDC shown in FIG3 includes (all transistors in the pixel driving circuit PDC shown in FIG3 are N-type transistors):

[0085] During the reset phase, the pixel driving circuit PDC is supplied with the gate level of the second scanning signal G2 to turn on the third transistor T3 and apply the reference voltage Vref to the fifth node NG. The pixel driving circuit PDC is supplied with the gate level of the first reset signal RST1 and the gate level of the second emission signal EM2 to turn on the fifth transistor T5 and the fourth transistor T4, apply the initialization voltage Vinit to the second node N2 and the fourth node NS, respectively, and reset the pixel electrode of the sub-pixel. During the reset phase, the pixel driving circuit PDC is supplied with the off level of the first scanning signal G1 and the off level of the first emission signal EM1 to turn off the first transistor T1 and the second transistor T2.

[0086] In the compensation (Comp) phase, the pixel driving circuit PDC is loaded with the cut-off level of the first scanning signal G1 and the cut-off level of the second light-emitting signal EM2, so that the first transistor T1 and the fourth transistor T4 are turned off. The pixel driving circuit PDC continues to load the selection level of the second scanning signal G2 to turn on the third transistor T3, and the first end Cst11 of the first capacitor maintains the voltage at the reference voltage Vref, that is, the voltage at the fifth node NG is the reference voltage Vref. At the same time, the selection level of the first light-emitting signal EM1 is loaded to the pixel driving circuit PDC to turn on the second transistor T2, thereby causing the first node N1 to charge the fourth node NS through the driving transistor DT until the driving transistor DT is turned off, and finally V NS =V N1 =Vref-Vth. Where, V NS is the voltage of the fourth node NS; V N1 is the voltage of the first node N1.

[0087] In the data writing (Write) phase, the first scanning signal G1 is applied to the pixel driving circuit PDC to turn on the first transistor T1, and the data voltage Vdata is applied to the fifth node NG. Based on the coupling effect of the first capacitor Cst1 and the second capacitor Cst2, the voltage V NS =Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), where C1 is the capacitance of the first capacitor Cst1 and C2 is the capacitance of the second capacitor Cst2. During the data writing phase, the pixel driving circuit PDC is supplied with the off-level of the first light-emitting signal EM1, the off-level of the second scanning signal G2, and the off-level of the second light-emitting signal EM2, so that the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off.

[0088] In the light-emitting phase, the gating level of the first light-emitting signal EM1 and the gating level of the second light-emitting signal EM2 are applied to the pixel driving circuit PDC, so that the second transistor T2 and the fourth transistor T4 are turned on. Under the control of the fifth node NG, the driving transistor DT outputs a driving current to the light-emitting element corresponding to the pixel driving circuit PDC, thereby controlling the brightness of the light-emitting element. In the light-emitting phase, the cut-off level of the first scanning signal G1, the second scanning signal G2 and the cut-off level of the first reset signal RST1 are applied to the pixel driving circuit PDC, so that the first transistor T1, the third transistor T3, and the fifth transistor T5 are all turned off.

[0089] In the light-emitting phase, the gate-source voltage difference Vgs of the driving transistor DT is: Vgs = Vdata – (Vref – Vth + (Vdata – Vref) * C1 / (C1 + C2)) = (Vdata – Vref) * (C2 / (C1 + C2)) + Vth; then the current of the driving transistor DT is I = K * (Vgs – Vth) 2 , that is, I=K*((Vdata–Vref)*(C2 / (C1+C2))) 2 . In this way, the influence of the threshold voltage Vth of the driving transistor DT on the current is eliminated. However, it can be seen from the above formula that in order to achieve the stability of the potential of the fifth node NG when the capacitance value of the first capacitor Cst1 is large, two aspects can be considered: (1) The data voltage Vdata can be increased, but generally the size W / L (W is the width of the channel region, L is the length of the channel region) of the driving transistor DT is fixed, and this method requires the data voltage Vdata to be adjusted to a large value. (2) The second capacitor Cst2 can also be set to a capacitor with a large capacitance value, but if the capacitance value of the second capacitor Cst2 is large, during the light-emitting stage, current will pass through the driving voltage line loaded with the driving power supply voltage VDD, generating large noise, and the noise will be introduced into the fourth node NS, thereby making the potential of the fifth node NG unstable.

[0090] To address the above-mentioned issues, embodiments of the present disclosure provide a pixel driver circuit PDC for a display panel PNL. As shown in FIG5 , the pixel driver circuit PDC includes a driver transistor DT, a data write module M1, a first light emission control module M2, a reference voltage module M3, a second light emission control module M4, a voltage regulator module M6, a first capacitor Cst1, a second capacitor Cst2, and a third capacitor Cst3. A second end of the data write module M1, a second end of the reference voltage module M3, a first end Cst11 of the first capacitor, and a gate of the driver transistor DT are electrically connected to a fifth node NG. A second end of the first light emission control module M2 and a first electrode of the driver transistor DT are electrically connected to a first node N1. A second electrode of the driver transistor DT, a first end of the second light emission control module M4, a second end Cst12 of the first capacitor, and a second end Cst22 of the second capacitor are electrically connected to a fourth node NS. A second end of the voltage regulator module M6, a first end Cst21 of the second capacitor, and a first end Cst31 of the third capacitor are electrically connected to a third node N3.

[0091] The second terminal Cst32 of the third capacitor is used to load the driving power supply voltage VDD. The data writing module M1 is used to load the data voltage Vdata to the fifth node NG in response to the strobe level of the first scan signal G1. The reference voltage module M3 is used to load the reference voltage Vref to the fifth node NG in response to the strobe level of the second scan signal G2. The first light-emitting control module M2 is used to load the driving power supply voltage VDD to the first node N1 in response to the strobe level of the first light-emitting signal EM1. The voltage stabilizing module M6 is used to load the regulated voltage Vx to the third node N3 in response to the strobe level of the second reset signal RST2. The second light-emitting control module M4 is used to turn on in response to the strobe level of the second light-emitting signal EM2. The second terminal of the second light-emitting control module M4 is electrically connected to the light-emitting element through the second node N2.

[0092] In the embodiment of the present disclosure, a third capacitor Cst3 is provided in the pixel driving circuit PDC, so that the capacitor connected to the fourth node NS in the light emitting stage is the equivalent capacitance C of the second capacitor Cst2 and the third capacitor Cst3 connected in series. A According to C A =(C2*C3) / (C2+C3) It can be seen that because C A <C2 and C A <C3, then the equivalent capacitance value C A Compared with setting a single second capacitor Cst2, the capacitance of the capacitor Cst2 is smaller, and the noise introduced to the fourth node NS is reduced, so that the voltage of the fifth node NG remains stable.

[0093] The pixel driving circuit provided by the embodiment of the present disclosure is further described below with reference to a specific equivalent circuit diagram.

[0094] In one embodiment of the present disclosure, referring to FIG5 , the pixel driving circuit PDC further includes a reset module M5 . A second terminal of the reset module M5 is electrically connected to the second node N2 . The reset module M5 is configured to apply an initialization voltage Vinit to the second node N2 in response to a gate level of a first reset signal RST1 , thereby initializing the pixel electrode.

[0095] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG6 , the data writing module M1 includes a first transistor T1, wherein a first electrode of the first transistor T1 is electrically connected to a data voltage lead (for applying a data voltage Vdata), a second electrode of the first transistor T1 is electrically connected to a fifth node NG, and a gate of the first transistor T1 is electrically connected to a first scanning signal G1. The first transistor T1 is configured to respond to a gate level of the first scanning signal G1 to apply the data voltage Vdata to the fifth node NG.

[0096] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG6 , the reference voltage module M3 includes a third transistor T3, a first electrode of the third transistor T3 being electrically connected to the reference voltage lead, a second electrode of the third transistor T3 being electrically connected to the fifth node NG, and a gate of the third transistor T3 being electrically connected to the second scan signal lead. The third transistor T3 is configured to apply a reference voltage Vref to the fifth node NG in response to a gate level of the second scan signal G2.

[0097] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG6 , the first light emitting control module M2 includes a second transistor T2, wherein a first electrode of the second transistor T2 is electrically connected to the driving power supply voltage lead, a second electrode of the second transistor T2 is electrically connected to the first node N1, and a gate of the second transistor T2 is electrically connected to the first light emitting signal lead. The second transistor T2 is configured to respond to a gate level of the first light emitting signal EM1, thereby turning on the second transistor T2.

[0098] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG6 , the second light emitting control module M4 includes a fourth transistor T4, a first electrode of the fourth transistor T4 being electrically connected to the fourth node NS, a second electrode of the fourth transistor T4 being electrically connected to the second node N2, and a gate of the fourth transistor T4 being electrically connected to the second light emitting signal lead. The fourth transistor T4 is responsive to a gate level of the second light emitting signal EM2, thereby turning on the fourth transistor T4.

[0099] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in Figure 6, the reset module M5 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the initialization voltage lead, a second electrode of the fifth transistor T5 is electrically connected to the second node N2, and a gate of the fifth transistor T5 is electrically connected to the first reset signal lead.

[0100] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in Figure 6, the voltage stabilizing module M6 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is electrically connected to a regulated voltage lead (for loading a regulated voltage Vx), a second electrode of the sixth transistor T6 is electrically connected to the third node N3, and a gate of the sixth transistor T6 is electrically connected to a second reset signal lead (for loading a second reset signal RST2).

[0101] In some embodiments of the present disclosure, the regulated voltage Vx may be any one of the reference voltage Vref, the initialization voltage Vinit, and the driving power supply voltage VDD.

[0102] In some examples, the first transistor T1 and the third transistor T3 in the pixel driving circuit PDC may be metal oxide transistors. In some examples, the driving transistor DT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the pixel driving circuit PDC may all be metal oxide transistors.

[0103] As follows, taking the pixel driving circuit PDC shown in FIG6 as an example, referring to the timing diagram shown in FIG7 , the driving method of the pixel driving circuit PDC of this example is exemplarily described.

[0104] During the reset phase, referring to Figures 7 and 8-1 , the pixel driving circuit PDC is supplied with the gate level of the second scan signal G2, turning on the third transistor T3 and applying the reference voltage Vref to the fifth node NG. The pixel driving circuit PDC is supplied with the gate level of the second reset signal RST2, turning on the sixth transistor T6 and applying the regulated voltage Vx to the third node N3. The pixel driving circuit PDC is supplied with the gate level of the second emission signal EM2 and the gate level of the first reset signal RST1, turning on the fourth transistor T4 and the fifth transistor T5, applying the initialization voltage Vinit to the second node N2 and the fourth node NS, and resetting the pixel electrode. Furthermore, during this reset phase, the pixel driving circuit PDC is supplied with the off level of the first scan signal G1 and the off level of the first emission signal EM1, turning off the first transistor T1 and the second transistor T2.

[0105] In the compensation stage, referring to FIG7 and FIG8-2, the strobe level of the second scanning signal G2 is applied to the pixel driving circuit PDC, so that the third transistor T3 remains in the on state, and the voltage applied to the fifth node NG is the reference voltage Vref. The strobe level of the second reset signal RST2 is applied to the pixel driving circuit PDC, so that the sixth transistor T6 remains in the on state, and the driving power supply voltage VDD and the regulated voltage Vx are applied to both ends of the third capacitor Cst3 respectively. The strobe level of the first luminous signal EM1 is applied to the pixel driving circuit PDC, so that the second transistor T2 is turned on, thereby applying the driving power supply voltage VDD to the fourth node NS through the driving transistor DT until the driving transistor DT is turned off. At this time, V NG -V NS =Vth, that is, V NS =Vref-Vth. Furthermore, in the compensation phase, the pixel driving circuit PDC is supplied with the off-level of the first scanning signal G1 and the off-level of the second light emitting signal EM2, so that the first transistor T1 and the fourth transistor T4 are turned off.

[0106] In an example, during the compensation phase, the gate level of the first reset signal RST1 is applied to the pixel driving circuit PDC, so that the fifth transistor T5 remains turned on.

[0107] In the data writing phase, referring to FIG7 and FIG8-3, the gate level of the second reset signal RST2 is applied to the pixel driving circuit PDC, so that the sixth transistor T6 remains conductive, and the driving power supply voltage VDD and the regulated voltage Vx are applied to both ends of the third capacitor Cst3. The gate level of the first scan signal G1 is applied to the pixel driving circuit PDC, so that the first transistor T1 is conductive, and the data voltage Vdata is applied to the fifth node NG. At this time, based on the coupling effect between the first capacitor Cst1 and the second capacitor Cst2, the potential of the fourth node NS is: V NS =Vref-Vth+(Vdata-Vref)*C1 / (C1+C2), where C1 is the capacitance of the first capacitor Cst1 and C2 is the capacitance of the second capacitor Cst2. Furthermore, during the data writing phase, the first light-emitting signal EM1, the cut-off level of the second scanning signal G2, and the cut-off level of the second light-emitting signal EM2 are applied to the pixel driving circuit PDC, so that the second transistor T2, the third transistor T3, and the fourth transistor T4 are all cut off.

[0108] In an example, in the data writing phase, the gate level of the first reset signal RST1 is applied to the pixel driving circuit PDC, so that the fifth transistor T5 remains turned on.

[0109] In the light-emitting stage, referring to Figures 7 and 8-4, the gating level of the first light-emitting signal EM1 and the gating level of the second light-emitting signal EM2 are applied to the pixel driving circuit PDC, so that the second transistor T2 and the fourth transistor T4 are turned on. Under the control of the fifth node NG, the driving transistor DT outputs a driving current to the light-emitting element corresponding to the pixel driving circuit PDC, thereby controlling the brightness of the sub-pixel. At this time, the gate-source voltage difference Vgs of the driving transistor DT is: Vgs = Vdata - (Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)) = (Vdata - Vref) * (C2 / (C1 + C2)) + Vth; then the current I of the driving transistor DT is: I = K * (Vgs - Vth) 2 , that is, I=K*((Vdata-Vref)*(C2 / (C1+C2))) 2 .

[0110] Furthermore, in this light-emitting stage, the cut-off level of the first scanning signal G1, the cut-off level of the second scanning signal G2, the cut-off level of the first reset signal RST1 and the cut-off level of the second reset signal RST2 are loaded to the pixel driving circuit PDC, so that the first transistor T1, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are all in the cut-off state.

[0111] 8-4, in the light-emitting stage, the sixth transistor T6 is turned off, and the capacitance between the fourth node NS and the driving power supply voltage lead is the equivalent capacitance C of the second capacitor Cst2 and the third capacitor Cst3 in series. A According to C A =(C2*C3) / (C2+C3) It can be seen that C A <C2 and C A Therefore, the series connection of the second capacitor Cst2 and the third capacitor Cst3 can reduce the noise introduced into the fourth node NS by the driving power supply voltage lead, thereby reducing the fluctuation of the fifth node NG and improving the stability of the current of the driving transistor DT.

[0112] In one embodiment of the present disclosure, the relationship between the capacitance values ​​of the second capacitor Cst2 and the third capacitor Cst3 in the pixel driving circuit PDC is that the capacitance value of the third capacitor Cst3 is less than the capacitance value of the second capacitor Cst2. Thus, according to the calculation formula of the series capacitance, the equivalent capacitance value C of the second capacitor Cst2 and the third capacitor Cst3 connected in series is A The capacitance value of the fourth node NS is smaller than that of the third capacitor Cst3, which further reduces the introduction of noise at the fourth node NS and improves the stability of the current of the driving transistor DT.

[0113] In one embodiment of the present disclosure, referring to FIG. 6 and FIG. 9 , in the method of driving the pixel driving circuit PDC shown in FIG. 6 , the light emitting phase includes a first sub-light emitting phase EMA and a second sub-light emitting phase EMB.

[0114] As shown in Figures 9 and 10-1, during the first sub-emission phase EMA, the gate level of the second reset signal RST2 is applied to the pixel driving circuit PDC, turning on the sixth transistor T6. The driving power supply voltage VDD and the regulated voltage Vx are applied to the third capacitor Cst3, respectively. The gate level of the first reset signal RST1 and the gate level of the second emission signal EM2 are applied to the pixel driving circuit PDC, turning on the fifth transistor T5 and the fourth transistor T4, and applying the initialization voltage Vinit to the fourth node NS. Furthermore, during the first sub-emission phase EMA, the first scanning signal G1, the off-level of the first emission signal EM1, and the off-level of the second scanning signal G2 are applied to the pixel driving circuit PDC, turning off the first transistor T1, the second transistor T2, and the third transistor T3.

[0115] As shown in Figures 9 and 10-2, during the second sub-emission phase EMB, the gating level of the first emission signal EM1 and the gating level of the second emission signal EM2 are applied to the pixel driver circuit PDC, turning on the second transistor T2 and the fourth transistor T4. Under the control of the fifth node NG, the driver transistor DT outputs a drive current to the corresponding light-emitting element of the pixel driver circuit PDC, thereby controlling the brightness of the sub-pixel. Thus, during the first sub-emission phase EMA, the initialization voltage Vinit is applied to both the second node N2 and the fourth node NS. This prevents the potential jumps at the fourth node NS and the second node N2 from affecting the anode potential of the light-emitting element when the second transistor T2 and the fourth transistor T4 are turned on and the fifth transistor T5 is turned off during the second sub-emission phase EMB. This also reduces interference on the fourth node NS caused by the series connection of the second capacitor Cst2 and the third capacitor Cst3.

[0116] Furthermore, in the second sub-light-emitting phase EMB, the cut-off level of the first scanning signal G1, the cut-off level of the second scanning signal G2, the cut-off level of the first reset signal RST1, and the cut-off level of the second reset signal RST2 are loaded to the pixel driving circuit PDC, so that the first transistor T1, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all in the cut-off state.

[0117] In one embodiment of the present disclosure, referring to FIG11 , the pixel driving circuit PDC further includes a noise reduction module M7. A first end of the noise reduction module M7 is electrically connected to the first end Cst31 of the third capacitor, and a second end of the noise reduction module M7 is electrically connected to the third node N3. The noise reduction module M7 is configured to be turned on in response to the gate level of the second reset signal RST2.

[0118] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG11 , the data writing module M1 includes a first transistor T1, wherein a first electrode of the first transistor T1 is electrically connected to a data voltage lead, a second electrode of the first transistor T1 is electrically connected to a fifth node NG, and a gate of the first transistor T1 is electrically connected to a first scanning signal G1. The first transistor T1 is configured to respond to a gate level of the first scanning signal G1 to load a data voltage Vdata to the fifth node NG.

[0119] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG11 , the reference voltage module M3 includes a third transistor T3, a first electrode of the third transistor T3 being electrically connected to the reference voltage lead, a second electrode of the third transistor T3 being electrically connected to the fifth node NG, and a gate of the third transistor T3 being electrically connected to the second scan signal lead. The third transistor T3 is configured to respond to a gate level of the second scan signal G2 to apply a reference voltage Vref to the fifth node NG.

[0120] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG11 , the first light emitting control module M2 includes a second transistor T2, a first electrode of the second transistor T2 being electrically connected to the driving power supply voltage lead, a second electrode of the second transistor T2 being electrically connected to the first node N1, and a gate of the second transistor T2 being electrically connected to the first light emitting signal lead. The second transistor T2 is configured to respond to a gate level of the first light emitting signal EM1, thereby turning on the second transistor T2.

[0121] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG11 , the second light emitting control module M4 includes a fourth transistor T4, wherein a first electrode of the fourth transistor T4 is electrically connected to the fourth node NS, a second electrode of the fourth transistor T4 is electrically connected to the second node N2, and a gate of the fourth transistor T4 is electrically connected to the second light emitting signal lead. The fourth transistor T4 is turned on in response to a gate level of the second light emitting signal EM2.

[0122] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in Figure 11, the reset module M5 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is electrically connected to the initialization voltage lead, a second electrode of the fifth transistor T5 is electrically connected to the second node N2, and a gate of the fifth transistor T5 is electrically connected to the first reset signal lead.

[0123] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in Figure 11, the voltage stabilization module M6 includes a sixth transistor T6, a first electrode of the sixth transistor T6 is electrically connected to the stabilization voltage lead, a second electrode of the sixth transistor T6 is electrically connected to the third node N3, and a gate of the sixth transistor T6 is electrically connected to the second reset signal lead.

[0124] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in FIG11 , the noise reduction module M7 includes a seventh transistor T7, a first electrode of the seventh transistor T7 being electrically connected to the first end Cst31 of the third capacitor, a second electrode of the seventh transistor T7 being electrically connected to the third node N3, and a gate of the seventh transistor T7 being electrically connected to the second reset signal lead. The seventh transistor T7 is configured to turn on the seventh transistor T7 in response to a gate level of the second reset signal RST2.

[0125] Taking the pixel driving circuit PDC shown in FIG11 as an example, referring to the timing diagram of FIG7 , the driving method of the example pixel driving circuit PDC is exemplarily described.

[0126] During the reset phase, referring to Figures 7 and 12-1 , the pixel driving circuit PDC is supplied with the gate level of the second scan signal G2, turning on the third transistor T3 and applying the reference voltage Vref to the fifth node NG. The pixel driving circuit PDC is supplied with the gate level of the second reset signal RST2, turning on the sixth transistor T6 and the seventh transistor T7, and applying the regulated voltage Vx to the third node N3. The pixel driving circuit PDC is supplied with the gate level of the second emission signal EM2 and the gate level of the first reset signal RST1, turning on the fourth transistor T4 and the fifth transistor T5, and applying the initialization voltage Vinit to the second node N2 and the fourth node NS, resetting the pixel electrode. Furthermore, during this reset phase, the pixel driving circuit PDC is supplied with the off level of the first scan signal G1 and the off level of the first emission signal EM1, turning off the first transistor T1 and the second transistor T2.

[0127] In the compensation phase, referring to FIG7 and FIG12-2, the gate level of the second scanning signal G2 and the gate level of the second reset signal RST2 are applied to the pixel driving circuit PDC, so that the third transistor T3, the sixth transistor T6, and the seventh transistor T7 remain in the on state, and the driving power supply voltage VDD and the regulated voltage Vx are applied to both ends of the third capacitor Cst3, respectively. The gate level of the first luminous signal EM1 is applied to the pixel driving circuit PDC, so that the second transistor T2 is turned on, thereby applying the driving power supply voltage VDD to the fourth node NS through the driving transistor DT until the driving transistor DT is turned off. At this time, V NG -V NS =Vth, that is, V NS =Vref-Vth. Thus, during the compensation phase, noise from the driving power supply voltage line, after passing through the third capacitor Cst3, needs to pass through the seventh transistor T7 before reaching the third node N3. The smaller channel region of the seventh transistor T7 can filter the noise generated by the driving power supply voltage line, thereby making the voltage of the third node N3 more stable and preventing changes in the potential of the third node N3 from affecting the potential of the fourth node NS, which in turn affects the voltage of the fifth node NG. Furthermore, during the compensation phase, the pixel driving circuit PDC is applied with the off-level of the first scanning signal G1 and the off-level of the second emission signal EM2, thereby turning off the first transistor T1 and the fourth transistor T4.

[0128] In an example, in the compensation phase, the gate level of the first reset signal RST1 is applied to the pixel driving circuit PDC, so that the fifth transistor T5 remains turned on.

[0129] In the data writing phase, referring to FIG7 and FIG12-3, the gate level of the second reset signal RST2 is applied to the pixel driving circuit PDC, so that the sixth transistor T6 and the seventh transistor T7 remain conductive, and the driving power supply voltage VDD and the regulated voltage Vx are applied to both ends of the third capacitor Cst3, respectively. The gate level of the first scan signal G1 is applied to the pixel driving circuit PDC, so that the first transistor T1 is conductive, and the data voltage Vdata is applied to the fifth node NG. At this time, based on the coupling effect between the first capacitor Cst1 and the second capacitor Cst2, the potential of the fourth node NS is: V NS=Vref-Vth+(Vdata-Vref)*C1 / (C1+C2). Similarly, during the data writing phase, noise from the driving power supply voltage line passes through the third capacitor Cst3 and is filtered by the seventh transistor T7 before reaching the third node N3, making the voltage of the third node N3 more stable and improving the voltage stability of the fourth node NS and the fifth node NG. Furthermore, during this data writing phase, the second scanning signal G2, the off-level of the first emission signal EM1, and the off-level of the second emission signal EM2 are applied to the pixel driving circuit PDC, thereby turning off the second transistor T2, the third transistor T3, and the fourth transistor T4.

[0130] In an example, in the data writing phase, the gate level of the first reset signal RST1 is applied to the pixel driving circuit PDC, so that the fifth transistor T5 remains turned on.

[0131] In the light-emitting stage, referring to Figures 7 and 12-4, the gating level of the first light-emitting signal EM1 and the gating level of the second light-emitting signal EM2 are applied to the pixel driving circuit PDC, so that the second transistor T2 and the fourth transistor T4 are turned on. Under the control of the fifth node NG, the driving transistor DT outputs a driving current to the light-emitting element corresponding to the pixel driving circuit PDC, thereby controlling the light-emitting brightness of the sub-pixel. At this time, the gate-source voltage difference Vgs of the driving transistor DT is: Vgs = Vdata - (Vref - Vth + (Vdata - Vref) * Cst1 / (C1 + C2)) = (Vdata - Vref) * (Cst2 / (C1 + C2)) + threshold voltage Vth; then the current of the driving transistor DT is I = K * (Vgs - Vth) 2 , that is, I=K*((Vdata-Vref)*(Cst2 / (C1+C2))) 2 .

[0132] Furthermore, in the light-emitting stage, the first scanning signal G1, the second scanning signal G2, the cut-off level of the first reset signal RST1 and the cut-off level of the second reset signal RST2 are loaded to the pixel driving circuit PDC, so that the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all in the cut-off state.

[0133] In an example, the seventh transistor T7 may be a metal oxide transistor, or the seventh transistor T7 may also be a polysilicon transistor.

[0134] Referring to FIG12-4, in the light-emitting stage, the sixth transistor T6 and the seventh transistor T7 are turned off. Thus, there is a coupling capacitor C7 between the gate and source, and between the gate and drain of the seventh transistor T7. The capacitance of the fourth node NS is the equivalent capacitance C of the series connection of the second capacitor Cst2, the third capacitor Cst3 and the coupling capacitor C7. B , equivalent capacitance value C B Therefore, in the light-emitting stage of this embodiment, the series connection of multiple capacitors can further reduce the noise introduced into the fourth node NS by the driving power supply voltage lead, thereby reducing the fluctuation of the voltage of the fifth node NG and improving the stability of the current of the driving transistor DT.

[0135] Referring to Figures 11 to 12-4 , the inclusion of the seventh transistor T7 in the pixel driver circuit PDC reduces the impact of noise from the drive power supply voltage lead on the potential of the third node N3 during the compensation and data writing phases, thereby preventing voltage fluctuations at the fourth node NS and the fifth node NG during the compensation and data writing phases, thereby improving the accuracy of threshold voltage compensation and data writing. Furthermore, during the light-emitting phase, the seventh transistor T7 acts as a series connection between the second capacitor Cst2, the third capacitor Cst3, and the coupling capacitor C7, reducing voltage fluctuations at the fourth node NS and improving the voltage stability of the fifth node NG, thereby further stabilizing the current flowing through the driver transistor DT.

[0136] In one example, the capacitance value of the third capacitor Cst3 can be smaller than the capacitance value of the second capacitor Cst2, or the capacitance value of the third capacitor Cst3 can be smaller than the capacitance value of the second capacitor Cst2 and smaller than the capacitance value of the coupling capacitor C7. In this way, according to the calculation formula of the series capacitance, the equivalent capacitance value C B Selecting a third capacitor Cst3 with a smaller capacitance value than any of the series capacitors can further reduce the introduction of noise at the fourth node NS and improve the stability of the current of the driving transistor DT.

[0137] In one embodiment of the present disclosure, referring to the pixel driving circuit PDC shown in Figure 13, the noise reduction module M7 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the first end Cst31 of the third capacitor, a second electrode of the seventh transistor T7 is electrically connected to the third node N3, and a gate of the seventh transistor T7 is electrically connected to a third reset signal lead (for loading a third reset signal RST3).

[0138] Taking the pixel driving circuit PDC shown in FIG13 as an example, referring to the timing diagram of FIG14 , the driving method of the example pixel driving circuit PDC is exemplarily described.

[0139] During the reset phase, the pixel driving circuit PDC is supplied with the gate level of the second scan signal G2, turning on the third transistor T3 and applying the reference voltage Vref to the fifth node NG. The pixel driving circuit PDC is supplied with the gate levels of the second reset signal RST2 and the third reset signal RST3, turning on the sixth transistor T6 and the seventh transistor T7, and applying the regulated voltage Vx to the third node N3. The pixel driving circuit PDC is supplied with the gate level of the second emission signal EM2 and the gate level of the first reset signal RST1, turning on the fourth transistor T4 and the fifth transistor T5, and applying the initialization voltage Vinit to the second node N2 and the fourth node NS, resetting the pixel electrode. Furthermore, during the reset phase, the pixel driving circuit PDC is supplied with the off level of the first scan signal G1 and the off level of the first emission signal EM1, turning off the first transistor T1 and the second transistor T2.

[0140] During the compensation phase, the pixel driving circuit PDC is supplied with the gate level of the second scanning signal G2, the gate level of the second reset signal RST2, and the gate level of the third reset signal RST3, so that the third transistor T3, the sixth transistor T6, and the seventh transistor T7 remain in the on state, the fifth node NG is supplied with the reference voltage Vref, and the two ends of the third capacitor Cst3 are connected to the power supply voltage VDD and the regulated voltage Vx, respectively. The pixel driving circuit PDC is supplied with the gate level of the first light emitting signal EM1, so that the second transistor T2 is turned on, thereby supplying the driving power supply voltage VDD to the fourth node NS through the driving transistor DT until the driving transistor DT is turned off. At this time, V NG -V NS =Vth, that is, V NS =Vref-Vth. Thus, during the compensation phase, after the noise from the driving power supply voltage line passes through the third capacitor Cst3, it can be filtered by the seventh transistor T7, thereby making the voltage of the third node N3 more stable and preventing changes in the potential of the third node N3 from affecting the potential of the fourth node NS, which in turn affects the voltage of the fifth node NG. Furthermore, during this compensation phase, the pixel driving circuit PDC is supplied with the off-level of the first scanning signal G1 and the off-level of the second emission signal EM2, thereby turning off the first transistor T1 and the fourth transistor T4.

[0141] In an example, in the compensation phase, the gate level of the first reset signal RST1 is applied to the pixel driving circuit PDC, so that the fifth transistor T5 remains turned on.

[0142] During the data writing phase, the pixel driving circuit PDC is loaded with the strobe level of the second reset signal RST2 and the strobe level of the third reset signal RST3, so that the sixth transistor T6 and the seventh transistor T7 remain conductive, and the third capacitor Cst3 is connected to the power supply voltage VDD and the regulated voltage Vx, respectively. The pixel driving circuit PDC is loaded with the strobe level of the first scan signal G1, so that the first transistor T1 is conductive and the data voltage Vdata is loaded to the fifth node NG. At this time, based on the coupling effect between the first capacitor Cst1 and the second capacitor Cst2, the potential of the fourth node NS is: V NS =Vref-Vth+(Vdata-Vref)*C1 / (C1+C2). Similarly, during the data writing phase, noise from the driving power supply voltage line passes through the third capacitor Cst3 and is filtered by the seventh transistor T7 before reaching the third node N3, making the voltage of the third node N3 more stable and improving the voltage stability of the fourth node NS and the fifth node NG. Furthermore, during this data writing phase, the second scanning signal G2, the off-level of the first emission signal EM1, and the off-level of the second emission signal EM2 are applied to the pixel driving circuit PDC, thereby turning off the second transistor T2, the third transistor T3, and the fourth transistor T4.

[0143] In an example, in the data writing phase, the gate level of the first reset signal RST1 is applied to the pixel driving circuit PDC, so that the fifth transistor T5 remains turned on.

[0144] During the light-emitting phase, the pixel driving circuit PDC is loaded with the gating level of the third reset signal RST3, so that the seventh transistor T7 is turned on, thereby preventing the first end Cst21 of the second capacitor from being a floating capacitor. The pixel driving circuit PDC is loaded with the gating level of the first light-emitting signal EM1 and the gating level of the second light-emitting signal EM2, so that the second transistor T2 and the fourth transistor T4 are turned on. Under the control of the fifth node NG, the driving transistor DT outputs a driving current to the light-emitting element corresponding to the pixel driving circuit PDC, thereby controlling the brightness of the sub-pixel. At this time, the gate-source voltage difference Vgs of the driving transistor DT is: Vgs = Vdata - (Vref - Vth + (Vdata - Vref) * C1 / (C1 + C2)) = (Vdata - Vref) * (C2 / (C1 + C2)) + Vth; then the current of the driving transistor DT is I = K * (Vgs - Vth) 2 , that is, I=K*((Vdata-Vref)*(C2 / (C1+C2))) 2 .

[0145] Furthermore, in the light-emitting stage, the cut-off level of the first scanning signal G1, the cut-off level of the second scanning signal G2, the cut-off level of the first reset signal RST1 and the cut-off level of the second reset signal RST2 are loaded to the pixel driving circuit PDC, so that the first transistor T1, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are all in the cut-off state.

[0146] In the light emitting stage, the sixth transistor T6 is turned off and the seventh transistor T7 is turned on. Thus, the capacitance of the fourth node NS is the equivalent capacitance C of the second capacitor Cst2 and the third capacitor Cst3 in series. A According to C A =(C2*C3) / (C2+C3), C A <C2 and C A < C3, therefore, the series connection of the second capacitor Cst2 and the third capacitor Cst3 can reduce the noise introduced into the fourth node NS by the driving power supply voltage lead, thereby reducing the fluctuation of the fifth node NG and improving the stability of the current of the driving transistor DT.

[0147] Referring to Figures 13 and 14, by providing a seventh transistor T7 in the pixel driving circuit PDC and controlling the gate of the seventh transistor T7 via the third reset signal RST3, the effect of noise from the driving power supply voltage lead on the potential of the third node N3 can be reduced during the compensation and data writing stages, thereby avoiding voltage fluctuations at the fourth node NS and the fifth node NG during the compensation and data writing stages, thereby improving the accuracy of threshold voltage compensation and data writing. Furthermore, during the light-emitting stage, the seventh transistor T7 is turned on in response to the gate level of the third reset signal RST3, so that the capacitance of the fourth node NS is equal to the equivalent capacitance C of the second capacitor Cst2 and the third capacitor Cst3 connected in series. A , the noise introduced into the fourth node NS by the driving power supply voltage lead in the light emitting stage can be reduced, thereby reducing the fluctuation of the fifth node NG and improving the stability of the current of the driving transistor DT in the light emitting stage.

[0148] In one example, the capacitance value of the third capacitor Cst3 may be smaller than the capacitance value of the second capacitor Cst2. Thus, according to the calculation formula of the series capacitance, the equivalent capacitance value C A The capacitance value of the third capacitor Cst3 is smaller than that of any of the series capacitors, and the third capacitor Cst3 with a smaller capacitance value is selected, which can reduce the introduction of noise at the fourth node NS and improve the stability of the current of the driving transistor DT.

[0149] It should be noted that although the various processes of the driving method of the pixel driving circuit PDC in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in this specific order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0150] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A pixel driving circuit includes a driving transistor, a data writing module, a first light emitting control module, a reference voltage module, a second light emitting control module, a voltage stabilizing module, a first capacitor, a second capacitor and a third capacitor; wherein, The second terminal of the data writing module, the second terminal of the reference voltage module, the first terminal of the first capacitor, the gate of the driving transistor are electrically connected to the fifth node; the second terminal of the first light-emitting control module, the first pole of the driving transistor are electrically connected to the first node; the second pole of the driving transistor, the first terminal of the second light-emitting control module, the second terminal of the first capacitor, the second terminal of the second capacitor are electrically connected to the fourth node; the second terminal of the voltage stabilizing module, the first terminal of the second capacitor, the first terminal of the third capacitor are electrically connected to the third node; The second terminal of the third capacitor is used to load the driving power supply voltage; the data writing module is used to load the data voltage to the fifth node in response to the selected conduction level of the first scan signal; The reference voltage module is used to load the reference voltage to the fifth node in response to the selected conduction level of the second scan signal; The first light-emitting control module is used to load the driving power supply voltage to the first node in response to the selected conduction level of the first light-emitting signal; the voltage stabilizing module is used to load the voltage stabilizing voltage to the third node in response to the selected conduction level of the second reset signal; the second light-emitting control module is used to conduct in response to the selected conduction level of the second light-emitting signal.

2. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes a reset module; The second terminal of the reset module, the second terminal of the second light-emitting control module, the light-emitting element are electrically connected to the second node; the reset module is used to load the initialization voltage to the second node in response to the selected conduction level of the first reset signal.

3. The pixel driving circuit according to claim 1, wherein, The capacitance value of the third capacitor is less than the capacitance value of the second capacitor.

4. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes a noise reduction module; the first terminal of the noise reduction module is electrically connected to the first terminal of the third capacitor, and the second terminal of the noise reduction module is electrically connected to the third node; The noise reduction module is used to conduct in response to the selected conduction level of the second reset signal.

5. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit further includes a noise reduction module; the first terminal of the noise reduction module is electrically connected to the first terminal of the third capacitor, and the second terminal of the noise reduction module is electrically connected to the third node; The noise reduction module is used to conduct in response to the selected conduction level of the third reset signal.

6. The pixel driving circuit according to any one of claims 1 to 5, wherein, The voltage stabilizing voltage is one of the reference voltage, the initialization voltage and the driving power supply voltage.

7. The pixel driving circuit according to any one of claims 1 to 5, wherein, The data writing module includes a first transistor, the first pole of the first transistor is electrically connected to the data voltage lead, the second pole of the first transistor is electrically connected to the fifth node, and the gate of the first transistor is electrically connected to the first scan signal lead; The reference voltage module includes a third transistor, the first pole of the third transistor is electrically connected to the lead of the reference voltage, the second pole of the third transistor is electrically connected to the fifth node, and the gate of the third transistor is electrically connected to the second scan signal lead; The first light-emitting control module includes a second transistor, the first pole of the second transistor is electrically connected to the lead of the driving power supply voltage, the second pole of the second transistor is electrically connected to the first node, and the gate of the second transistor is electrically connected to the first light-emitting signal lead; The second light-emitting control module includes a fourth transistor. A first pole of the fourth transistor is electrically connected to the fourth node. A second pole of the fourth transistor is electrically connected to the second node. A gate of the fourth transistor is electrically connected to the second light-emitting signal lead. The voltage stabilizing module includes a sixth transistor. A first pole of the sixth transistor is electrically connected to the regulated voltage lead. A second pole of the sixth transistor is electrically connected to the third node. A gate of the sixth transistor is electrically connected to the second reset signal lead.

8. The pixel driving circuit according to claim 2, wherein, The reset module includes a fifth transistor. A first pole of the fifth transistor is electrically connected to the initialization voltage lead. A second pole of the fifth transistor is electrically connected to the second node. A gate of the fifth transistor is electrically connected to the first reset signal lead.

9. The pixel driving circuit according to claim 4, wherein, The noise reduction module includes a seventh transistor. A first pole of the seventh transistor is electrically connected to a first end of the third capacitor. A second pole of the seventh transistor is electrically connected to the third node. A gate of the seventh transistor is electrically connected to the second reset signal lead.

10. The pixel driving circuit according to claim 5, wherein, The noise reduction module includes a seventh transistor. A first pole of the seventh transistor is electrically connected to a first end of the third capacitor. A second pole of the seventh transistor is electrically connected to the third node. A gate of the seventh transistor is electrically connected to the third reset signal lead.

11. A driving method of a pixel driving circuit, applied to the pixel driving circuit described in any one of claims 1 to 10; wherein, The driving method of the pixel driving circuit includes: In a reset stage, applying a selected conduction level of the second scan signal to the pixel driving circuit so that the reference voltage is applied to the fifth node, and applying a selected conduction level of the second reset signal to the pixel driving circuit. In a compensation stage, applying selected conduction levels of the first light-emitting signal, the second scan signal, and the second reset signal to the pixel driving circuit. In a data writing stage, applying a selected conduction level of the first scan signal to the pixel driving circuit so that the data voltage is applied to the fifth node.

12. The driving method of the pixel driving circuit according to claim 11, wherein, In a light-emitting stage, applying selected conduction levels of the first light-emitting signal and the second light-emitting signal to the pixel driving circuit. The pixel driving circuit further includes a reset module. A second end of the reset module, a second end of the second light-emitting control module, and a light-emitting element are electrically connected to the second node. The reset module is configured to load the initialization voltage to the second node in response to a selected conduction level of the first reset signal. The driving method of the pixel driving circuit further includes: In a reset stage, applying selected conduction levels of the second light-emitting signal and the first 13. The driving method of the pixel driving circuit according to claim 12, wherein, reset signal to the pixel driving circuit so that the initialization voltage is applied to the fourth node. The driving method of the pixel driving circuit further includes:

14. The driving method of the pixel driving circuit according to claim 11, wherein, In the compensation stage and the data writing stage, applying a selected conduction level of the first reset signal to the pixel driving circuit. The pixel driving circuit further includes a noise reduction module. A first end of the noise reduction module is electrically connected to a first end of the third capacitor. A second end of the noise reduction module is electrically connected to the third node. The noise reduction module is configured to conduct in response to a selected conduction level of the third reset signal. The driving method of the pixel driving circuit further includes: During the light-emitting stage, the selected conduction level of the third reset signal is loaded onto the pixel driving circuit.

15. The driving method of the pixel driving circuit according to claim 11, wherein, The pixel driving circuit further includes a noise reduction module; a first end of the noise reduction module is electrically connected to a first end of the third capacitor, and a second end of the noise reduction module is electrically connected to the third node; the noise reduction module is configured to conduct in response to the selected conduction level of the third reset signal; The driving method of the pixel driving circuit further includes: During the light-emitting stage, the selected conduction level of the third reset signal is not loaded onto the pixel driving circuit.

16. A display panel, comprising the pixel driving circuit according to any one of claims 1 to 10.

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