Device management method and apparatus based on bus technology, and system

Abstract

Provided in the embodiments of the present application are a device management method and apparatus based on bus technology, and a system. Without the need for being initiated by a bus controller, a bus device can actively send device information thereof to the bus controller after being powered on, and after receiving the device information of the bus device, the bus controller allocates an address space of a bus to the bus device on the basis of the device information of the bus device, so that latency in terms of the bus controller discovering the bus device is reduced, and the efficiency in terms of the bus controller managing a bus network is improved.

Description

A device management method, device and system based on bus technology

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 26, 2024, with application number 202410117987.9 and application name “A bus device management method and bus controller”, and the Chinese patent application filed with the State Intellectual Property Office on June 3, 2024, with application number 202410711358.9 and application name “A device management method, device and system based on bus technology”, all of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a device management method, apparatus, and system based on bus technology. Background Art

[0003] Compared to traditional Ethernet, bus networks offer advantages such as lower latency and greater bandwidth. With the rapid development of information technology, data- and compute-intensive applications such as public cloud, artificial intelligence (AI), and autonomous driving are becoming increasingly prevalent, and the overall computing system is becoming increasingly complex. This will inevitably place increasing demands on interconnect buses, making it increasingly important to reduce bus network latency and improve bus network management efficiency.

[0004] Summary of the Invention

[0005] In existing bus network management mechanisms, bus controllers discover and register bus devices through enumeration scanning. As bus networks grow in size, the number of bus devices that the bus controller must scan increases. This not only increases the latency for the bus controller to discover bus devices, but also increases the load on the bus controller. This increases the probability of bus controller failure and reduces the reliability of the bus network.

[0006] In view of this, the present application provides a device management method, apparatus and system based on bus technology. After the bus device is powered on, it can actively send its own device information to the bus controller without waiting to receive the enumeration message sent by the bus controller. After the bus controller receives the device information of the bus device, it allocates the bus address space to the bus device according to the device information of the bus device. This is not only conducive to reducing the delay of the bus controller in discovering the bus device and improving the efficiency of the bus controller in managing the bus network, but also conducive to reducing the load of the bus controller and reducing the probability of failure of the bus controller, thereby improving the reliability of the bus network.

[0007] In a first aspect, the present application provides a device management method based on bus technology. The method is executed by a bus controller in a bus network, and the bus network includes multiple bus devices interconnected by a bus. The bus controller can be a bus device, or a partial component of a bus device (such as a processor, a chip or a chip system, etc.), or a logic module or software that implements all or part of the functions of a bus device. In this method, the bus controller receives device notification information, and the device notification information includes device information of a first bus device, wherein the device information of the first bus device is actively sent to the bus controller by the first bus device after power-on. Afterwards, the bus controller allocates the address space of the bus to the first bus device based on the device information of the first bus device, and then sends configuration information to the first bus device, and the configuration information includes address information for describing the address space.

[0008] Since the bus controller can allocate address space to the first bus device based on the device information actively sent by the first bus device after it is powered on, this not only helps to reduce the delay of the bus controller in discovering the bus device and improve the efficiency of the bus controller in managing the bus network, but also helps to reduce the load of the bus controller and reduce the probability of failure of the bus controller, thereby improving the reliability of the bus network.

[0009] Optionally, the first bus device actively sends its own device information to the bus controller after power-on. This does not limit the first bus device to not receiving information from the bus controller before sending its own device information to the bus controller. Rather, it means that the first bus device sending its own device information to the bus controller does not depend on receiving information from the bus controller (such as a message). Even if the first bus device has not received any information from the bus controller after power-on, the first bus device can still send its own device information to the bus controller.

[0010] In one possible implementation of the first aspect, the device information of the first bus device is sent from the first bus device and then forwarded to the bus controller via one or more bus devices in the bus network. In other words, the first bus device is not directly connected to the bus controller. The bus controller can allocate address space to the indirect-connected first bus device based on the device information actively sent by the indirect-connected first bus device, which helps reduce the latency of the bus controller in penetrating one or more bus devices to discover the first bus device, thereby improving the efficiency of the bus controller in managing large-scale bus networks (e.g., a bus network across computing devices).

[0011] In a possible implementation manner of the first aspect, the plurality of bus devices are provided in at least two computer devices.

[0012] In a possible implementation of the first aspect, the device notification information also includes path information, and the path information is used to indicate that the device information of the first bus device is forwarded through one or more bus devices. The bus controller can also determine the forwarding path of the device notification information between the first bus device and the bus controller based on the path information. The bus controller determines the forwarding route between the first bus device and itself, which is conducive to improving its own management of the bus network. In addition, the bus controller can determine the forwarding path between the first bus device and itself based on the device information actively sent by the first bus device after it is powered on, which is conducive to reducing the delay of the bus controller in determining the topological position of the first bus device in the bus network. This is not only conducive to improving the efficiency of the bus controller in managing the bus network, but also conducive to reducing the load of the bus controller, reducing the probability of failure of the bus controller, and thus improving the reliability of the bus network.

[0013] The present application does not limit the implementation method of including path information in the device notification information. Optionally, after receiving the device information of the first bus device, the bus device with forwarding function encapsulates the device information of the first bus device and the information for forwarding it together and forwards it.

[0014] This application does not limit all bus devices with forwarding functions to encapsulating the device information of the first bus device and the forwarding information thereof together after receiving the device information of the first bus device and then forwarding the information. Optionally, a bus device connected to the first bus device in the bus network may, after receiving the device information of the first bus device, encapsulate the device information of the first bus device and the forwarding information thereof together before forwarding the information.

[0015] In one possible implementation of the first aspect, when device information of a first bus device is forwarded to a bus controller via multiple bus devices in a bus network, multiple forwarding paths may exist between the bus controller and the first bus device. The bus controller may receive multiple device advertisement messages each including the device information of the first bus device. The device information of the first bus device in each of the multiple device advertisement messages is forwarded to the bus controller via different forwarding paths among the multiple forwarding paths. As described above, the device advertisement messages also include path information indicating that the device information of the first bus device in the device advertisement message was forwarded via one or more bus devices. The bus controller may then determine the corresponding multiple forwarding paths based on the path information in each of the multiple device advertisement messages.

[0016] The present application does not limit the implementation method of the device information of the first bus device in the multiple device notification information reaching the bus controller via multiple forwarding paths. Optionally, after receiving the device information of the first bus device, a bus device with a forwarding function in the bus network (such as a bus switch) can forward it by broadcasting. Alternatively, after receiving the device information of the first bus device, a bus device with a forwarding function in the bus network (such as a bus switch) can forward the device information of the first bus device to the opposite bus device and the bus controller with a forwarding function. For the opposite bus device that does not have a forwarding function and is not a bus controller, the device information of the first bus device may not be forwarded to it, which is beneficial to improving the security of the device information of the first bus device.

[0017] This application does not limit all bus devices with forwarding functions in the bus network to forward the received device information of the first bus device by broadcasting. Optionally, after receiving the device information of the first bus device, the bus device connected to the first bus device in the bus network forwards it by broadcasting.

[0018] Optionally, a single forwarding path passes through one or more bus devices in sequence, and different forwarding paths pass through different bus devices or ports of different bus devices or pass through different numbers of bus devices.

[0019] In a possible implementation of the first aspect, the bus controller sending configuration information to the first bus device may include: the bus controller determining a target forwarding path based on the multiple forwarding paths between the first bus device and the bus controller as determined above, and sending the configuration information to the first bus device via the target forwarding path. Compared to the bus controller sending the configuration information to the first bus device separately via the multiple forwarding paths, this method helps conserve bus transmission resources.

[0020] Optionally, the bus controller sends the configuration information to the first bus device via the target forwarding path, which may refer to sending the configuration information via a port located on the target forwarding path among its multiple ports, or carrying information of the target forwarding path in the configuration information to instruct other bus devices other than the first bus device to forward the configuration information according to the target forwarding path after receiving the configuration information.

[0021] In one possible implementation of the first aspect, the bus controller may further transmit device information of the bus controller to at least one bus device connected to the bus controller. The device information of the bus controller is used to instruct the at least one bus device to record information about the port used to connect to the bus controller. In this way, by transmitting its device information, the bus controller facilitates at least one connected bus device to record its port of connection to the bus controller, thereby improving the success rate of other bus devices sending information to the bus controller and enhancing the bus controller's efficiency in managing the bus network.

[0022] In a possible implementation of the first aspect, the bus controller can also receive device information of a second bus device in the bus network, and the device information of the second bus device is forwarded by at least one bus device according to the recorded information of the port connected to the bus controller. Similar to the above, the device information of the second bus device can be actively sent to the bus controller by the second bus device after it is powered on. After receiving the device information of the second bus device, at least one bus device forwards the device information according to the recorded information of the port connected to the bus controller. This helps to improve the success rate of the bus controller receiving the device information of the second bus device and helps to avoid at least one bus device sending the device information of the second bus device to each of its own ports via broadcast. This helps to reduce the load of the at least one bus device, save bus transmission resources, and improve the security of the second bus device.

[0023] In a possible implementation of the first aspect, the bus controller may also receive status notification information from a first bus device. The status notification information from the first bus device is used to indicate whether the first bus device is about to exit the bus network or is still connected to the bus network. The status notification information from the first bus device is forwarded by at least one bus device according to the recorded information of the port connected to the bus controller. The bus controller may then determine the connection status of the first bus device in the bus network based on the status notification information from the first bus device. This helps improve the success rate of the bus controller receiving status notification information, improves the bus controller's management efficiency of the bus network, and helps avoid at least one bus device sending the status notification information to each of its own ports separately via broadcast, thereby reducing the load on the at least one bus device and conserving bus transmission resources.

[0024] Optionally, the connection status of the first bus device in the bus network may be that the first bus device is about to exit the bus network, has exited the bus network, or is still connected to the bus network.

[0025] In a possible implementation of the first aspect, a bus device in a bus network that forwards device information of a first bus device includes a bus switch as a device type. Optionally, the bus device in a bus network that forwards device information of the first bus device may include other device types, such as a bus terminal that supports mapping its own storage space to an address space of the bus.

[0026] In a possible implementation of the first aspect, the device information of the first bus device includes an identifier of the first bus device, and the identifier of the first bus device includes at least one of a device type of the first bus device, a manufacturer identifier of the first bus device, and a device identifier of the first bus device.

[0027] In one possible implementation of the first aspect, the device information of the first bus device includes the size of the address space required by the first bus device. This facilitates the bus controller to allocate address space to the first bus device based on the size of the address space required by the first bus device, thereby improving the accuracy of the address space allocation by the bus controller to the first bus device. This not only helps avoid configuration errors caused by the bus controller allocating an address space larger than the first bus device's maximum available storage space, but also helps avoid wasting the first bus device's storage resources due to the bus controller allocating an address space far smaller than the first bus device's available storage space.

[0028] In the method provided in the first aspect, the first bus device can be any bus device in the bus network, or any bus device that supports mapping its own storage space to the address space of the bus. The first bus device can send its own device information through a message, and the bus controller can receive device notification information through a message. The message sent by the first bus device may be different from the message received by the bus controller. For example, the message sent by the first bus device may not include path information, while the message received by the bus controller may include path information in addition to the device information of the first bus device. Optionally, the device information and path information of the first bus device in the device notification information may also be encapsulated in different messages. The device notification information received by the bus controller may include device information of other bus devices in addition to the device information of the first bus device. The device information of different bus devices may be encapsulated in the same or different messages.

[0029] In a second aspect, the present application provides a device management method based on bus technology. The method is applied to a bus network, which includes multiple bus devices interconnected by a bus, and a bus controller runs in the bus network. The bus controller can be understood with reference to the bus controller introduced in the first aspect. In this method, the first bus device in the bus network actively sends the device information of the first bus device after power-on; the bus controller receives device notification information, which includes the device information of the first bus device; the bus controller allocates the address space of the bus to the first bus device according to the device information of the first bus device, and sends configuration information to the first bus device, which includes address information for describing the address space; the first bus device receives the configuration information and maps all or part of its own storage space to the address space described by the address information in accordance with the instructions of the configuration information.

[0030] In the method provided in the second aspect, possible steps executed by the bus controller, the first bus device and other bus devices in the bus network can be understood by referring to the steps executed by the corresponding devices in the first aspect, and will not be repeated here.

[0031] For example, in a possible implementation manner of the first aspect, the device information of the first bus device is sent from the first bus device and then forwarded to the bus controller via one or more bus devices in the bus network.

[0032] For example, in one possible implementation of the second aspect, a bus device connected to a first bus device in a bus network may, after receiving device information from the first bus device, forward the device information of the first bus device and information about the path by which it forwards the device information of the first bus device. The path information by which the bus device forwards the device information of the first bus device is used to indicate that the device information of the first bus device is forwarded by the bus device. Optionally, the bus device encapsulates the device information of the first bus device and the path information by which it forwards the device information of the first bus device into the same message and forwards the message.

[0033] For example, in a possible implementation of the second aspect, a bus device connected to the first bus device in the bus network receives the device information of the first bus device and then forwards it by broadcasting.

[0034] For example, in a possible implementation of the second aspect, the method further includes: the bus controller sends its own device information to at least one bus device connected to itself; and the at least one bus device records information of the port used to connect to the bus controller according to the indication of the device information of the bus controller.

[0035] For example, in a possible implementation of the second aspect, the method further includes: the second bus device in the bus network actively sends its own device information to the bus controller after power-on; the at least one bus device forwards the device information of the second bus device to the bus controller according to the port information of the bus controller; and the bus controller receives the device information of the second bus device.

[0036] For example, in a possible implementation of the second aspect, the method further includes: the first bus device sends its own status notification information to the bus controller, where the status notification information is used to indicate that the first bus device will exit the bus network or remain connected to the bus network; the at least one bus device forwards the status notification information to the bus controller according to information of the port of the bus controller; the bus controller receives the status notification information and determines the connection status of the first bus device in the bus network based on the status notification information.

[0037] In a third aspect, the present application provides a bus controller, which is deployed in a bus network that includes multiple bus devices connected via a bus. The bus controller can be a bus device, or a component of a bus device (such as a processor, chip, or chip system), or a logic module or software that implements all or part of the functions of a bus device.

[0038] The bus controller may include a transceiver module and a processing module. The transceiver module may be configured to receive device notification information, including device information of a first bus device. The device information of the first bus device is proactively sent to the bus controller by the first bus device after power-on. The processing module may be configured to allocate a bus address space to the first bus device based on the device information of the first bus device. The transceiver module may also be configured to send configuration information to the first bus device, the configuration information including address information describing the address space.

[0039] In a possible implementation manner of the third aspect, the device information of the first bus device is sent from the first bus device and then forwarded to the bus controller via one or more bus devices in the bus network.

[0040] In a possible implementation of the third aspect, the device announcement information further includes path information, where the path information indicates that the device information of the first bus device is forwarded through one or more bus devices. The processing module is further configured to determine, based on the path information, a forwarding path for the device announcement information between the first bus device and the bus controller.

[0041] In a possible implementation of the third aspect, when device information of a first bus device is forwarded to a bus controller via multiple bus devices in a bus network, the transceiver module is specifically configured to respectively receive multiple device notification messages, wherein the device information of the first bus device in the multiple device notification messages is forwarded via different paths. The processing module is configured to determine the corresponding multiple forwarding paths based on path information in each of the multiple device notification messages.

[0042] In a possible implementation manner of the third aspect, the transceiver module is specifically configured to determine a target forwarding path according to the multiple forwarding paths, and send the configuration information to the first bus device through the target forwarding path.

[0043] In a possible implementation of the third aspect, the transceiver module is further used to send device information of the bus controller to at least one bus device connected to the bus controller, and the device information of the bus controller is used to instruct at least one bus device to record information of a port used to connect to the bus controller.

[0044] In a possible implementation of the third aspect, the transceiver module is further used to receive device information of a second bus device in the bus network, where the device information of the second bus device is actively sent by the second bus device to the bus controller after power-on, and the device information of the second bus device is forwarded by at least one bus device according to the recorded information of the port connected to the bus controller.

[0045] In a possible implementation of the third aspect, the transceiver module is further used to receive status notification information of the first bus device, where the status notification information of the first bus device is used to indicate that the first bus device is about to exit the bus network or is still connected to the bus network, and the status notification information of the first bus device is forwarded by at least one bus device according to the recorded information of the port connected to the bus controller; the determination module is further used to determine the connection status of the first bus device in the bus network based on the status notification information of the first bus device.

[0046] In a possible implementation manner of the third aspect, a device type of the bus device that forwards the device information of the first bus device in the bus network includes a bus switch.

[0047] In a possible implementation of the third aspect, the device information of the first bus device includes an identifier of the first bus device, and the identifier of the first bus device includes at least one of a device type of the first bus device, a manufacturer identifier of the first bus device, and a device identifier of the first bus device.

[0048] In a possible implementation manner of the third aspect, the device information of the first bus device includes a size of an address space required by the first bus device.

[0049] In a possible implementation manner of the third aspect, the multiple bus devices are provided in at least two computer devices.

[0050] In a fourth aspect, the present application also provides a bus device, which includes a processor and a memory, the processor is coupled to the memory, and the processor is configured to execute the method described in the first aspect or any possible implementation of the first aspect based on instructions stored in the memory.

[0051] In a fifth aspect, the present application further provides a computer program product comprising computer-readable instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect or any possible implementation of the first aspect.

[0052] In a sixth aspect, the present application also provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a computer, the computer executes the method described in the first aspect or any possible implementation of the first aspect.

[0053] In a seventh aspect, the present application provides a chip comprising a processor. The processor is used to read and execute a computer program stored in a memory to execute the method in any possible implementation of any of the above aspects. Optionally, the chip includes a memory, and the memory is connected to the processor via a circuit or wire. Further optionally, the chip also includes a communication interface, and the processor is connected to the communication interface. The communication interface is used to receive data and / or information to be processed, the processor obtains the data and / or information from the communication interface, processes the data and / or information, and outputs the processing results through the communication interface. The communication interface can be an input and output interface.

[0054] In an eighth aspect, the present application provides a bus network, which includes multiple bus devices connected via a bus. A bus controller runs in the bus network, and the bus controller is used to execute the method as described in the first aspect and any of various possible implementation methods.

[0055] Among them, the implementation method and technical effects of the device provided in this application can refer to the technical effects brought about by the corresponding implementation method in the method provided in this application, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] FIG1 schematically shows a possible structure of a bus network;

[0057] FIG2 schematically shows another possible structure of a bus network;

[0058] FIG3 schematically illustrates a possible process of a device management method based on bus technology provided in an embodiment of the present application;

[0059] FIG4 schematically illustrates the process of bus switch 1 broadcasting the CPU notification message;

[0060] FIG5 schematically illustrates a forwarding path for a bus controller to send a configuration message 1 to a CPU via a bus switching network;

[0061] FIG6 schematically illustrates a method for managing a newly added SSD in a bus network;

[0062] FIG7 schematically illustrates a method for managing the exit of an SSD from a bus network;

[0063] FIG8 schematically shows the structure of a bus controller;

[0064] FIG9 schematically shows the structure of a bus device. DETAILED DESCRIPTION

[0065] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0066] A bus is a common communication line used to transmit information between various computer components (called bus devices). Based on the type of information transmitted, a computer bus can be divided into three types: a data bus, an address bus, and a control bus. These buses are used to transmit data, data addresses, and control signals, respectively.

[0067] A bus device refers to an electronic device or computer device that has a bus interface, supports a bus protocol, or can communicate with other devices through a bus. It can be a central processing unit (CPU), a network card, memory, a solid state drive (SSD), or an input / output device.

[0068] A bus network consists of multiple bus devices connected via a bus.

[0069] A bus controller is used to manage bus devices in a bus network. For example, it may be responsible for discovering and registering bus devices in a bus network. A bus controller may run on a bus device and may be implemented in software and / or hardware. This application does not limit the type of bus device in which the bus controller resides. For example, the bus controller may run on a bus device such as a CPU or a network card. Hereinafter, a bus controller may also refer to a bus device that has the aforementioned bus controller functionality.

[0070] A bus terminal can run on a bus device. It can be implemented through software and / or hardware and can support mapping all or part of the storage resources in the bus device to the bus address space for direct access by other bus devices. This application does not limit the type of bus device where the bus terminal is located. For example, the bus terminal can run on a bus device such as a CPU, network card, memory, SSD, or input / output device. Hereinafter, the bus terminal may also refer to a bus device that has the above-mentioned bus terminal functions.

[0071] A bus switch is used to implement bus interconnection and routing (or forwarding). A bus switch can run on a bus device and can be implemented through software and / or hardware. This application does not limit the type of bus device where the bus switch is located. For example, the bus switch can run on a bus device such as a CPU or a network card. Hereinafter, a bus switch may also refer to a bus device having the above-mentioned bus switch function. One or more bus switches can build one or more physical links or forwarding paths between other different bus devices, thereby enabling access between different bus devices.

[0072] A hybrid bus device can have multiple functions, for example, it can have two functions among the above bus controller, bus terminal and bus switch. The bus controller, bus terminal and bus switch mentioned below can be hybrid bus devices.

[0073] Network topology refers to the study of point-line relationships independent of size and shape in topology. The bus device in a bus network is abstracted as a point, and the transmission medium (such as a bus) is abstracted as a line. The geometric shape composed of these points and lines is the network topology (or topological structure) of the bus network. Types of network topologies include, but are not limited to, ring topology, tree topology, star topology, hybrid topology, and mesh topology.

[0074] This application does not limit the type of bus. For example, the bus can be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), or an NVIDIA link (NVLINK) bus, etc.

[0075] A bus network can include multiple bus devices of the same or different types, such as bus controllers, bus terminals, and bus switches. Bus domains must have uniform address assignments before they can access each other. Therefore, after power-up and initialization, bus terminals must first obtain the assigned address space from the bus controller before they can access each other.

[0076] In existing bus network management mechanisms, a bus controller discovers and registers bus terminals through enumeration scanning. Figure 1 schematically illustrates a possible bus network structure. As shown in Figure 1, the bus network includes a bus controller, a bus switch, and three bus terminals. In the figures of this application, a hexagon represents a bus switch, and the different sides of the hexagon represent the different ports of the bus switch. The connections between different bus devices in Figure 1 represent the bus. Assume that the bus shown in Figure 1 is a PCIe bus. As shown in Figure 1, the three different ports of the bus switch are respectively connected to two bus terminals and a bus controller, and the bus controller is also directly connected to a bus terminal. The bus controller can adopt a master-slave model to scan and discover each bus terminal in sequence. For example, the bus controller first performs PCIe link training, then uses enumeration scanning to read the registers of the bus terminal's configuration space (or PCIe space), receive the transaction layer packet (TLP) returned by the bus terminal in response to the enumeration message, write TLP configuration information, and then allocate and configure address space for the bus terminal to ensure normal use of the bus terminal.

[0077] However, in order to discover the bus terminals connected to the bus switch, the bus controller must first read and configure the bus switch's configuration space using enumeration messages. This allows the bus switch to determine the forwarding path to the bus controller, for example, determining which of the bus switch's ports leads to the bus controller. This allows the bus switch to forward the enumeration messages to the connected bus terminals according to the configured forwarding path and forward the TLPs to the bus controller. This means that the bus controller must first configure the bus switch before it can discover the bus terminals connected to the bus switch ports, which increases the bus controller's latency in discovering the bus terminals.

[0078] In addition, the scanning process can only be initiated by the CPU as the bus controller, and other bus devices act as slaves. Moreover, due to the limited configuration range, it is impossible to achieve the registration capability across multiple levels of bus switches (for example, 1K+ bus device nodes).

[0079] Furthermore, as the scale of bus networks continues to increase, bus networks include more and more bus switches and bus terminals. Bus devices in a bus network can be located in multiple computing devices (or computing device clusters). Figure 2 schematically illustrates another possible bus network structure. Figure 2 uses the example of a bus network comprising a bus controller, three bus terminals, and six bus switches. The three bus terminals are the CPU, network interface card, and memory, respectively, and the six bus switches are bus switches 1 through 6. For ease of description, bus switches 1 through 6 will be referred to as the bus switching network. The bus switching network has multiple ports for connecting to other bus devices in the bus network. Other bus devices include bus controllers, CPUs, network interfaces, and memory. The multiple ports of the bus switching network (ports in bold in Figure 2) include port 1 and port 3 of each of bus switches 1 through 4, as well as port 3 of bus switch 1 and port 3 of bus switch 6. Figure 2 schematically illustrates two computing devices (rack 1 and rack 2) including bus devices. Bus devices in a bus network can be located on a greater or lesser number of computing devices. FIG2 takes a rack-mounted server as an example of a computing device, but the computing device may be other types of devices.

[0080] As shown in Figure 2, there is at least one forwarding path between any two different external ports of the bus switching network. Each forwarding path passes through at least one bus switch, and the forwarding path between the bus controller and the bus terminal passes through at least two bus switches. As can be seen, as the scale of the bus network continues to increase, the bus controller needs to penetrate more and more bus switches to discover the bus terminal. This results in the bus controller needing to configure forwarding paths to itself for more and more bus switches before it can send message packets to the bus terminal connected to the bus switch and receive the returned TLPs. The delay in the bus controller discovering the bus terminal continues to increase, which is not conducive to ensuring the management efficiency of the bus network. In addition, because the bus controller needs to configure forwarding paths between different ports in multiple ports on each bus switch, the bus controller is heavily loaded, which increases the probability of failure of the bus controller and reduces the reliability of the bus network.

[0081] In view of this, the present application provides a device management method based on bus technology. After the bus device is powered on, it can actively send its own device information to the bus controller without waiting to receive the enumeration message sent by the bus controller. After the bus controller receives the device information of the bus device, it allocates the bus address space to the bus device according to the device information of the bus device. This is not only conducive to reducing the delay of the bus controller in discovering the bus device and improving the efficiency of the bus controller in managing the bus network, but also conducive to reducing the load of the bus controller and reducing the probability of failure of the bus controller, thereby improving the reliability of the bus network.

[0082] Based on the structure of the bus network shown in Figure 2, the following example introduces the method flow of the bus controller penetrating the bus switches 1 to 6 to manage the CPU. As shown in Figure 2, the bus controller is respectively connected to the port 3 of the bus switch 5 and the bus switch 6 in the bus switching network, and the CPU is respectively connected to the port 1 of the bus switch 1 and the port 3 of the bus switch 2 in the bus switching network. For the sake of convenience of description, the port 3 of the bus switch 5 and the port 3 of the bus switch 6 are collectively referred to as the first port of the bus switching network, and the port 1 of the bus switch 1 and the port 3 of the bus switch 2 are collectively referred to as the second port of the bus switching network. Figure 3 schematically shows the process of the method provided by the present application, which may include steps S301 to S305.

[0083] S301: The CPU sends its own notification message to the second port. Correspondingly, the bus switching network receives the notification message from the second port, wherein the notification message includes device information of the CPU.

[0084] The CPU can send its own notification message to the second port. Correspondingly, the bus switching network can receive the notification message from the second port. The notification message includes the device information of the CPU. The device information of the CPU may include the CPU identifier. This application does not limit the specific content of the CPU identifier, as long as the CPU identifier can be used to uniquely identify the CPU in the bus network. For example, the CPU identifier may include at least one of the CPU's device type, manufacturer identification (ID), and device ID.

[0085] The CPU device information may also include the size of the address space required by the CPU. The size of the address space required by the CPU may refer to the size of the address space in the CPU's memory space that is directly accessible to other bus devices in the bus network. This facilitates the bus controller to allocate address space to the CPU based on the size of the address space required by the CPU, thereby improving the accuracy of the address space allocation by the bus controller to the CPU.

[0086] Table 1 schematically illustrates the possible contents of a CPU notification message sent to the second port. As shown in Table 1, the CPU notification message includes six fields: device type, device ID, manufacturer ID, device required address space, device start address, and device end address. The value of the device type field indicates the device type, the value of the device ID field indicates the device ID, the value of the manufacturer ID field indicates the manufacturer ID, the value of the device required address space field indicates the size of the address space required by the device, and the values ​​of the device start address and device end address fields indicate the start and end addresses, respectively, of the address space allocated by the bus controller for the device.

[0087] Table 1

[0088] Table 1 also schematically illustrates the information indicated by the values ​​of the aforementioned fields in the CPU notification message through the content after the colon. As shown in Table 1, in the CPU notification message, the value of the device type field indicates that the device type of the bus device issuing the notification message is a CPU, the value of the device ID field indicates that the device ID of the bus device is D1, the value of the manufacturer ID field indicates that the manufacturer ID of the bus device is V1, the value of the device required address space field indicates that the size of the address space required by the bus device is 1KB, and the values ​​of the device starting address field and the device ending address field each indicate "NULL." "NULL" can refer to an invalid address or a default address. The default address is not used to describe the address space allocated by the bus controller for the bus device. The default address can be used to indicate that the bus controller has not yet allocated address space for the bus device.

[0089] The CPU can actively send its own notification message to the second port after powering on or initializing. This application does not limit the specific process of CPU initialization. For example, CPU initialization includes BIOS initialization and / or the connection (link) of its own port and the second port of the bus switching network through physical layer self-negotiation. This application does not limit the specific content of the self-negotiation between the CPU port and the second port of the bus switching network. For example, in the process of self-negotiation between the ports, the interface rate of the two ends of the docking, the link physical layer training serializer / deserializer (SERDES) parameters, clock alignment and channel bonding and other link establishment processes can be executed.

[0090] This application does not limit the CPU to sending its own notification message immediately after completing initialization. Optionally, the CPU can send its own notification message after a period of time after completing initialization.

[0091] The present application does not limit the CPU to sending a notification message to the second port once. Optionally, the CPU can send notification messages to the second port multiple times, which is beneficial to improving the probability of the bus controller successfully receiving the notification message from the CPU.

[0092] As previously described, the second ports may include port 1 of bus switch 1 and port 3 of bus switch 2. The CPU can send its own notification message to each of the second ports (e.g., port 1 of bus switch 1 and port 3 of bus switch 2). This helps increase the probability that the bus controller successfully receives the CPU's notification message. Optionally, the CPU can also send its own notification message to one of the second ports.

[0093] In practical applications, the present application does not limit the number of ports of the bus switching network to which the CPU is connected. For example, the port (ie, the first port) of the bus switching network to which the CPU is connected may include only one port or multiple ports.

[0094] S302: The bus switching network forwards the notification message by broadcasting, and accordingly, the bus controller receives the notification message from the first port;

[0095] After receiving the CPU's notification message from the second port, the bus switching network can forward the notification message via broadcast. When a forwarding path exists between the second port and all other ports of the bus switching network, the bus switching network can forward the notification message to all ports other than the second port (ports marked with triangles as shown in FIG4 ). Accordingly, based on the existence of a forwarding path between the second port connected to the CPU and the first port connected to the bus controller, the bus switching network can forward the CPU's notification message to the bus controller via the first port, and the bus controller can receive the CPU's notification message from the first port.

[0096] As shown in Figure 4, the bus switching network ports and the second port connected to the network card and memory both have forwarding paths. Therefore, the bus switching network can forward the CPU's notification message to the network card via port 3 of bus switch 1 and port 1 of bus switch 2, respectively. Furthermore, it can forward the CPU's notification message to the memory via port 1 of bus switch 3 and port 3 of bus switch 4, respectively. The network card and memory can each receive the notification message, or, because their device types are not bus controllers, they can refuse to receive or discard the CPU's notification message.

[0097] The bus switching network forwarding a notification message via broadcast can mean that each bus switch in the bus switching network that receives the notification message forwards the notification message via broadcast. Figure 4 shows a schematic diagram of bus switch 1 broadcasting the notification message after receiving it from the CPU. As shown by the dotted arrow lines in Figure 4, after bus switch 1 receives the CPU's notification message from its port 1, it replicates it to obtain three notification messages, and then forwards these three notification messages through its other ports (i.e., ports 2 through 4).

[0098] As shown in FIG4 , multiple forwarding paths may exist between the first port and the second port. These multiple forwarding paths include multiple forwarding paths between port 1 of bus switch 1 and port 3 of bus switch 5, multiple forwarding paths between port 1 of bus switch 1 and port 3 of bus switch 6, multiple forwarding paths between port 3 of bus switch 2 and port 3 of bus switch 6, and multiple forwarding paths between port 3 of bus switch 2 and port 3 of bus switch 6. In the multiple forwarding paths between port 1 of bus switch 1 and port 3 of bus switch 5, port 1 of bus switch 1 can be connected to port 3 of bus switch 5 via its own port 2 and port 1 of bus switch 5 in sequence, or port 1 of bus switch 1 can be connected to port 3 of bus switch 5 via its own port 4, port 5 of bus switch 6, port 4 of bus switch 6, port 4 of bus switch 2, port 2 of bus switch 2 and port 2 of bus switch 5 in sequence, or port 1 of bus switch 1 can be connected to port 3 of bus switch 5 via its own port 4, port 5 of bus switch 6, port 1 of bus switch 6, port 2 of bus switch 3, port 4 of bus switch 3 and port 5 of bus switch 5 in sequence, etc.

[0099] Therefore, after the bus switching network forwards the notification message by broadcasting, it can send multiple notification messages forwarded via different forwarding paths to the bus controller through the first port. The bus controller can receive one or all of the multiple notification messages.

[0100] S303, the bus controller allocates address space 1 to the CPU according to the device information of the CPU in the notification message;

[0101] After receiving the CPU's notification message, the bus controller can allocate an address space (denoted as address space 1) to the CPU based on the CPU's device information in the notification message. The bus controller can allocate address space 1 to bus devices from the global address space (or bus domain) of the bus network. In other words, the address space 1 allocated to bus devices is a subset of the global address space.

[0102] The global address space may refer to the maximum addressable space of an address bus in a bus network. For example, assuming the maximum addressable capacity of an address bus in a bus network is 4GB, the start and end addresses of the global address space (or bus domain) of the bus network may be 1 and 4GB, respectively.

[0103] As previously mentioned, the CPU's notification message can include the size of the address space required by the CPU. The bus controller can allocate address space 1 to the CPU based on the size of the address space required by the CPU in the notification message. As shown in Table 1, assuming that the address space required by the CPU is 1 KB, the bus controller can allocate address space 1 of 1 KB to the CPU from the global address space.

[0104] To ensure that the bus controller allocates distinct address spaces to different bus devices, it can maintain address allocation information. This address allocation information indicates unallocated address spaces within the global address space and the binding relationship between each allocated address space and the identifier of the assigned bus device. For example, assuming the CPU identifier in the CPU notification message is "CPU, D1, V1," the bus controller allocates address space 1 to the CPU based on the required address space size in the CPU's device information. The bus controller can then update the address allocation information based on address space 1 and the CPU identifier in the CPU's device information. This updated address allocation information can be used to indicate the binding relationship between address space 1 and "CPU, D1, V1."

[0105] S304: The bus controller sends a configuration message 1 to the CPU via the bus switching network. Correspondingly, the CPU receives the configuration message 1 via the bus switching network, wherein the configuration message 1 includes address information for describing the address space 1.

[0106] After the bus controller allocates address space 1 to the CPU, it can send configuration message 1 to the CPU via the bus switching network. Correspondingly, the CPU can receive configuration message 1 via the bus switching network. Configuration message 1 includes address information describing address space 1 allocated by the bus controller to the CPU. Configuration message 1 can be used to instruct the CPU to map all or part of its memory space to address space 1 described by the address information.

[0107] Address space 1 can be a continuous address range or multiple discontinuous address ranges. This application does not limit the specific manner in which the address information in configuration message 1 describes address space 1, as long as the address information can describe each address range in address space 1. For example, for any address range in address space 1, the address information can include at least one of the following information: the starting address, the ending address, and the length of the address range.

[0108] In addition to including address information describing address space 1, configuration message 1 may also include other information. For example, configuration message 1 may also include all or part of the information in the device information of the CPU (such as the CPU identifier). Table 2 schematically shows the possible contents of configuration message 1. The meaning and content of each field of configuration message 1 shown in Table 2 can be understood with reference to the relevant content of Table 1. However, the values ​​of the device start address field and the device end address field in configuration message 1 shown in Table 2 are different from the values ​​of the corresponding fields in Table 1. In the configuration message 1 shown in Table 2, the value of the device start address field can indicate the starting address of each address range in address space 1 (recorded as address 1), and the value of the device end address field can indicate the ending address of each address range in address space 1 (recorded as address 2).

[0109] Table 2

[0110] After the bus controller generates the configuration message 1, it can send the configuration message 1 to the first port of the bus switching network. When the first port includes multiple ports (such as port 3 of the bus switch 5 and bus switch 6 shown in Figure 4), the bus controller can send the configuration message 1 to each port in the first port, which is conducive to improving the probability of the CPU successfully receiving the configuration message 1. Alternatively, the bus controller can send the configuration message 1 to all or part of the ports in the first port that receive the CPU's notification message. Optionally, the bus controller can obtain and record multiple forwarding paths to the CPU to determine a part of the forwarding path to the CPU (such as the forwarding path with the minimum delay), and then send the configuration message 1 to the port located on the forwarding path (such as port 1 of the bus switching network 5). When there are multiple forwarding paths with the minimum delay, the bus controller can send the configuration message 1 to the ports on one or more of the forwarding paths. The possible ways for the bus controller to obtain each forwarding path to the CPU will be introduced later, which will not be expanded here.

[0111] This application does not limit the manner in which the bus switching network forwards the configuration message 1 to the CPU after receiving the configuration message 1 from the first port. In some examples, the bus switching network can forward the configuration message 1 by broadcasting, thereby forwarding the configuration message 1 to the second port connected to the CPU. Alternatively, in some instances, the bus switching network can forward the configuration message 1 to the CPU along a forwarding path to the CPU (e.g., the forwarding path indicated by the dotted line with an arrow in FIG5 ), which is beneficial for saving forwarding resources of the bus switching network and also beneficial for improving the security of the configuration message 1.

[0112] This application does not limit the manner in which the bus switching network determines the forwarding path to the CPU. Optionally, the bus switching network can associate and record the CPU's forwarding path with the CPU identifier in the notification message during the process of receiving and broadcasting the CPU's notification message. In this way, when the bus switching network receives configuration message 1 carrying the CPU identifier, it can determine the forwarding path associated with the CPU identifier and then forward configuration message 1 to the CPU according to the forwarding path.

[0113] This application does not limit the manner in which the bus switching network records the CPU's forwarding path during the process of receiving and broadcasting the CPU's notification message. For example, for each bus switch in the bus switching network that receives the CPU's notification message, it can associate and record the port that receives the notification message and the identifier of the bus device in the notification message. For example, after bus switch 5 receives the CPU's notification message from port 1, it can associate and record "CPU, D1, V1" and "Port 1". Later, after receiving configuration message 1 carrying "CPU, D1, V1" from its own port 3, it can send configuration message 1 to port 1.

[0114] As previously mentioned, since the bus switching network forwards the CPU's notification message by broadcasting, a single bus switch can receive the CPU's notification message from multiple ports. The bus switch can send configuration message 1 to each port that receives the notification message, or it can send configuration message 1 to one of the multiple ports. Optionally, the bus switch can obtain and record multiple forwarding paths to the CPU to determine a partial forwarding path to the CPU (for example, a forwarding path with the minimum latency), and then send configuration message 1 to the port on the forwarding path. When there are multiple forwarding paths with the minimum latency, the bus switch can forward configuration message 1 according to one or more of the forwarding paths. The possible ways for the bus switch to obtain multiple forwarding paths to the CPU will be introduced later, which will not be expanded here.

[0115] S305. The CPU maps its own memory space 1 to address space 1 according to the instructions of configuration message 1.

[0116] After receiving configuration message 1, the CPU can configure its own configuration space according to the instructions of configuration message 1. For example, the CPU can map its own memory space 1 to address space 1 according to the instructions of configuration message 1, thereby facilitating other bus devices in the bus network to directly address the CPU's memory space 1 according to address space 1, and read data from and / or write data to memory space 1.

[0117] The size of storage space 1 and address space 1 may be the same, but the values ​​of their start addresses and / or end addresses may be the same or different, and their distribution states may be the same or different. For example, storage space 1 and address space 1 may each correspond to a continuous address range, or storage space 1 may correspond to a continuous address range but address space 1 may correspond to multiple discontinuous address ranges, or storage space 1 may correspond to multiple discontinuous address ranges but address space 1 may correspond to a continuous address range, or both may correspond to multiple discontinuous address ranges.

[0118] The method flow shown in Figure 3 schematically illustrates the process of the bus controller discovering and registering the CPU. The bus controller can also discover and register other bus devices connected to the bus switching network. For example, it can also discover and register the network card and memory separately. The method flow of the bus controller discovering other bus devices can refer to the process shown in Figure 3.

[0119] After the bus controller discovers and registers the network card and memory, it updates the address allocation information described above. This updated address allocation information not only indicates the binding relationship between address space 1 and "CPU, D1, V1," but also between address space 2 and "network card, D2, V2," and between address space 3 and "memory, D3, V3." Address space 2 and address space 3 are separate address spaces in the global address space, excluding address space 1. D2 and V2 represent the device ID and vendor ID of the network card, respectively, while D3 and V3 represent the device ID and vendor ID of the memory, respectively.

[0120] After the bus device is powered on, it actively sends its own device information to the bus controller without waiting to receive the packet message sent by the bus controller. After the bus controller receives the device information of the bus device, it allocates the bus address space for the bus device according to the device information of the bus device. This not only helps to reduce the delay of the bus controller in discovering the bus device and improve the efficiency of the bus controller in managing the bus network, but also helps to reduce the load of the bus controller and reduce the probability of failure of the bus controller, thereby improving the reliability of the bus network.

[0121] Optionally, as shown in FIG3 , after S305 , the method flow may further include S306 and S307 .

[0122] S306. The CPU sends a notification message 1 to the bus controller via the bus switching network. The notification message 1 is used to instruct the CPU to configure its configuration space according to the instruction of the configuration message 1.

[0123] After the CPU configures its own configuration space according to the instructions of configuration message 1, it can send notification message 1 to the bus controller through the bus switching network. Notification message 1 is used to indicate the configuration result of the CPU's own configuration space according to the instructions of configuration message 1. The configuration result is used to indicate configuration success (pass) or configuration failure (fail).

[0124] S307: The bus controller sends an indication message 1 to the CPU via the bus switching network, where the indication message 1 is used to indicate that registration with the CPU is complete.

[0125] When Notification Message 1 indicates successful configuration, the bus controller can determine that the CPU's memory space is directly accessible. Optionally, the bus controller can expose all or part of the CPU's address space 1 to other bus devices (such as a network card or memory) in the bus network. The bus controller can then send Indication Message 1 to the CPU via the bus switching network, indicating that registration with the CPU is complete.

[0126] If Notification Message 1 indicates configuration failure, the bus controller can repeatedly send Configuration Message 1 until it receives a Notification Message from the CPU indicating successful configuration or times out. While the CPU is unconfigured, the bus controller does not allow other bus devices to access Address Space 1. If the bus controller times out without receiving a Notification Message from the CPU indicating successful configuration, it can reclaim Address Space 1 allocated to the CPU.

[0127] Optionally, as shown in FIG3 , after S305 , the method flow may further include S308 and S309 .

[0128] S308. The CPU sends a notification message 2 to the bus controller via the bus switching network. The notification message 2 is used to indicate that the CPU is ready.

[0129] When the CPU completes configuration according to the instructions of the configuration message 1, it can send a notification message 2 to the bus controller through the bus switching network. The notification message 2 is used to indicate that the CPU is in a ready state.

[0130] S309. The bus controller sends an indication message 2 to the CPU via the bus switching network, where the indication message 2 is used to indicate receipt of the notification message 2.

[0131] After receiving the notification message 2 , the bus controller may send an indication message 2 to the CPU via the bus switching network. The indication message 2 is used to indicate receipt of the notification message 2 .

[0132] Optionally, as shown in FIG3 , after S305 , the method flow may further include S310 and S311 .

[0133] S310, the bus controller sends a keep-alive message to the CPU via the bus switching network;

[0134] S311. The CPU sends a response message to the keep-alive message to the bus controller through the bus switching network.

[0135] If the bus controller receives a response message from the CPU to the keep-alive message within a predetermined time, the bus controller can determine that the CPU is in place. If the bus controller does not receive a response message from the CPU to the keep-alive message within a predetermined time, the bus controller can determine that the CPU has exited the bus network, deregister the CPU, and execute the device exit process for the CPU.

[0136] As previously described, a bus switching network can, while receiving and broadcasting notification messages from connected bus devices, associate and record the forwarding path to the bus device and the bus device identifier in the notification message. Similarly, in some examples, a bus controller can send its own notification message to the first port of the bus switching network. The bus controller's notification message includes the bus controller's device information, which indicates that its device type is a bus controller. The bus switching network can, while receiving and broadcasting the bus controller's notification message, record the forwarding path to the bus controller. The bus switching network can then forward messages sent to the bus controller according to this forwarding path, thereby conserving forwarding resources and improving message security.

[0137] In the method example corresponding to FIG3 , S302 takes the bus switching network forwarding the CPU notification message by broadcasting as an example. The present application does not limit the manner in which the bus switching network forwards the CPU notification message.

[0138] Optionally, the bus switch can obtain and record multiple forwarding paths to the bus controller to determine a partial forwarding path (e.g., the forwarding path with the lowest latency), and then send messages to the bus controller to ports located on that forwarding path. When multiple forwarding paths with the lowest latency exist, the bus switch can forward messages to the bus controller along one or more of these forwarding paths. The following section describes possible ways for a bus switch to obtain multiple forwarding paths to a bus controller.

[0139] Optionally, after receiving a notification message from a CPU, a bus switch in the bus switching network can add information about the bus switch's forwarding path to the CPU's notification message and then forward the notification message along the forwarding path. In this way, the bus controller can determine the forwarding path that the notification message traverses within the bus switching network based on the forwarding path information in the received notification message.

[0140] For example, after receiving the notification message from the CPU from its own port 1, the bus switch 1 can add the information of the forwarding path from its own port 1 to its own port 2 in the notification message, and then send the notification message with the information of the forwarding path added to its own port 2. Table 3 schematically shows this notification message with the information of the forwarding path added. The contents of the first two rows in Table 3 can be understood with reference to the notification message sent by the CPU shown in Table 1. The content of the third row in Table 3 is used to indicate the information (i.e., the forwarding path information) that the bus switch 1 forwards for the notification message or the device information therein. As shown in Table 3, the forwarding path information may include the device information of the bus switch, the information of the receiving port, and the information of the sending port. As described in Table 3, the forwarding path information may indicate that the bus switch 1 receives the notification message sent by the CPU from its own port 1, and forwards the notification message through its own port 2. The device information of the bus switch 1 may include the identifier of the bus switch 1. This application does not limit the specific content of the identifier of the bus switch 1, as long as the identifier of the bus switch 1 can be used to uniquely identify the bus switch 1 in the bus network or bus switching network. For example, the identification of bus switch 1 may include at least one of its device type, manufacturer identification (ID), and device ID. When the storage space of the bus switch is directly accessible to other bus devices in the bus network, the device information of the bus switch can be understood by referring to the content of the device information of the CPU. For example, the device information of the bus switch may also include the size of the address space required by the bus switch.

[0141] Table 3

[0142] For example, after bus switch 5 receives the CPU notification message forwarded by bus switch 1 from its own port 1, it can add the forwarding path information from its own port 1 to its own port 3 in the notification message, and then send the notification message with the added forwarding path information to its own port 3. Table 4 schematically shows this notification message with the added forwarding path information. The contents of the first three rows in Table 4 can be understood with reference to the CPU notification message sent by bus switch 1 to its own port 2 shown in Table 3. The content of the fourth row in Table 4 is used to indicate that bus switch 5 receives the notification message from its own port 1 and forwards the notification message through its own port 3. The device information of bus switch 5 can be understood with reference to the identifier of bus switch 1 introduced above.

[0143] Table 4

[0144] After the bus controller receives the notification message shown in Table 4 from port 3 of bus switch 5, it can be determined that the third and fourth rows of Table 4 are information about the forwarding path added by the bus switching network in the notification message. According to the contents of the third and fourth rows in Table 4, it can be determined that the CPU is connected to port 1 of bus switch 1 and is connected to port 3 of bus switch 5. In addition, the forwarding path of the CPU's notification message in the bus switching network is from port 1 of bus switch 1 through port 2 of bus switch 1 and port 1 of bus switch 5 to reach port 3 of bus switch 5.

[0145] As mentioned above, the bus switching network can forward the CPU's notification message by broadcasting. Therefore, the bus switching network can forward the CPU's notification message to the bus controller through multiple different forwarding paths, and the forwarding path information in the notification message forwarded through different forwarding paths can be different. In this way, the bus controller can determine the multiple forwarding paths between the CPU and itself by receiving the CPU's notification message forwarded through multiple different forwarding paths.

[0146] Similarly, the bus switch in the bus switching network can add forwarding path information in the notification messages forwarded by other bus devices (such as network cards and memory). In this way, the bus controller can separately determine multiple forwarding paths between the network card and itself and multiple forwarding paths between the memory and itself.

[0147] Optionally, the bus controller can determine the network topology of the bus network shown in Figure 2 based on the forwarding paths between the CPU, network card, memory and itself (i.e., the bus controller). This helps the bus controller manage the bus network more accurately and efficiently.

[0148] Optionally, the bus switch in the bus switching network can record the forwarding paths leading to the bus device based on the forwarding path information in each notification message of the bus device. This is beneficial for the bus switch to record multiple forwarding paths leading to each bus device after broadcasting the notification messages of the CPU, network card and memory respectively, and further beneficial for the bus switch to forward messages (such as configuration messages) to each bus device according to the optimal forwarding path (such as the forwarding path with the least delay).

[0149] Optionally, after receiving the notification message from the bus controller, the bus switch in the bus switching network can add information about the forwarding path of the bus switch to the notification message, and then forward the notification message according to the forwarding path. As previously described, the bus switching network can forward the notification message of the bus controller by broadcasting. Therefore, the bus switch in the bus switching network can receive notification messages from the bus controller forwarded from multiple different forwarding paths, and record multiple forwarding paths leading to the bus controller based on the information about the forwarding path in each notification message of the bus controller. This is beneficial for the bus switch to record multiple forwarding paths leading to each bus controller after broadcasting the notification message of the bus controller, and further helps the bus switch forward messages (such as the notification message of the newly added bus device and / or the exit notification message of the bus device described later) to the bus controller according to the optimal forwarding path (such as the forwarding path with the smallest delay).

[0150] After determining multiple forwarding paths to each bus device connected to it, the bus switch in the bus switching network can determine the network topology of the bus network (such as shown in Figure 2). This helps the bus controller forward messages more accurately and efficiently.

[0151] Because the bus switch records the network topology of the bus network or the forwarding path to the bus device, when the bus switch receives the configuration message of the bus device sent by the bus controller, it can associate the information of the bus device in the network topology or forwarding path with the address information of the address space of the bus device. This is beneficial for the bus switch to route the message according to the forwarding path to the bus device when it subsequently receives the message accessing the address space.

[0152] Optionally, a bus switch in the bus switching network can also send its own notification message, which can include the bus switch's device information. Furthermore, after receiving a notification message from another bus switch, a bus switch in the bus switching network can forward the notification message via broadcast.

[0153] As mentioned above, each bus device in the bus network can send its own notification message. In addition to sending its own notification message, the bus switch can also forward the notification messages received from other bus devices by broadcasting, and add forwarding path information to the forwarded notification message.

[0154] In one possible implementation, after receiving multiple notification messages, the bus switch can broadcast each of the notification messages separately. Alternatively, in another possible implementation, after receiving multiple notification messages, the bus switch can merge or aggregate the multiple notification messages and then broadcast them. This not only helps reduce the number of notification messages received by the bus controller, thus reducing its load, but also helps reduce repeated transmission of the same information, thus conserving bus network transmission resources.

[0155] This application does not limit the manner in which a bus switch receives aggregated notification messages. For example, when the device type of the peer device is a bus terminal and does not include a bus switch, after receiving the device information of the peer device, the bus switch can determine that it does not need to receive device information of other bus devices from the peer device. When the device type of the peer device includes a bus switch, after receiving the device information of the peer device, the bus switch can also wait to receive device information of other bus devices from the peer device. Afterwards, the bus switch can aggregate the received device information of multiple bus devices (for example, encapsulate them in the same message).

[0156] After bus switch 1 receives the CPU's notification message and the network card's notification message respectively, it can send the merged notification message to its own port 2 and port 4 respectively. Table 5 schematically shows the content of the merged notification message sent by bus switch 1 to its own port 2. The first row in Table 5 respectively represents the device information of bus switch 1, the port on bus switch 1 that received the notification message, and the port on bus switch 1 that sent the merged notification message. The second and third rows in Table 5 represent the content of the notification message sent by the CPU to port 1 (for example, the CPU's device information), and the fourth and fifth rows in Table 5 represent the content of the notification message sent by the network card to port 3 (for example, the network card's device information).

[0157] Table 5

[0158] Similarly, the bus switch 5 can also receive and merge the merged notification messages sent by the bus switch 2, bus switch 3 and bus switch 4 respectively. The merged notification message sent by the bus switch can include the content (such as device information) in the notification message of each bus terminal hanging under the bus switch. The bus switch 5 can send the merged notification message to its own port 3. Table 6 schematically shows the merged notification message sent by the bus switch 5 to its own port 3. The meaning of the first row in Table 6 can be understood with reference to the meaning of the first row in Table 5. The second row in Table 6 represents the content of the notification message received by the bus switch 5 from its own port 1, that is, the content of the merged notification message sent by the bus switch 1 to its own port 2 (that is, the content in Table 5). The third row in Table 6 represents the content of the notification message received by the bus switch 5 from its own port 2, that is, the content of the merged notification message sent by the bus switch 2 to its own port 2 (that can be understood with reference to the content in Table 5). The fourth row in Table 6 shows the content of the notification message received by bus switch 5 from its own port 5, that is, the content of the merged notification message sent by bus switch 3 to its own port 4 (refer to the content in Table 5 for understanding). The fifth row in Table 6 shows the content of the notification message received by bus switch 5 from its own port 4, that is, the content of the merged notification message sent by bus switch 4 to its own port 4 (refer to the content in Table 5 for understanding).

[0159] Table 6

[0160] The present application does not limit the number of notification messages merged in a single merged notification message sent by the bus switch, nor does it limit the timing of the bus switch sending the merged notification message. For example, the bus switch can first determine its own port connected to the bus terminal and the port connected to the bus switch. Afterwards, the bus switch can collect the notification messages of all the connected bus terminals, merge them, and forward them to its ports connected to other bus switches respectively. This helps the bus switch obtain the notification messages of each bus terminal in the bus network with a shorter delay. As for the ports connected to other bus switches, the bus switch can send the merged notification message to them after collecting and merging the notification messages of all bus devices in the bus network. This helps reduce the number of times the bus terminal receives notification messages and reduces its load.

[0161] The above tables are only examples, and the notification message may not include one or more fields therein.

[0162] After the above-mentioned broadcast notification message process, all bus device information in the bus domain can be synchronized to all devices. For example, in a small-scale environment with security and trust (such as a supercomputing scenario), all bus devices can obtain information about other devices, including device type, address space, device capabilities, etc. Optionally, in some scenarios (such as scenarios that require security isolation), the bus switch can determine the forwarding strategy based on the type of bus device it is connected to (called the peer device). For example, when the device type of the peer device includes a bus switch and / or a bus controller, the bus switch can forward the device information of other bus devices it has received to its peer device, and when the device type of the peer device is a bus terminal, and its device type does not include a bus switch and a bus controller, the bus switch may not forward the device information of other bus devices it has received to it. In this way, it is beneficial to improve the security of device information on the basis of ensuring that the bus controller obtains the device information of all bus devices in the bus network.

[0163] The bus controller can be generated through self-election or by designation (for example, a bus device of a certain type and / or address is designated as the bus controller). After collecting all device information, the bus controller can form a hierarchical bus topology information table and allocate the address space range of each bus device.

[0164] As previously mentioned, after the bus switching network records the forwarding path to the bus controller, it can forward messages sent to the bus controller according to the recorded forwarding path. The following describes several scenarios in which the bus switching network forwards messages to the bus controller according to the forwarding path to the bus controller.

[0165] First, a scenario where a new bus device is added to a bus network is introduced. Figure 6 schematically illustrates a possible method flow for this scenario. As shown in Figure 6, the method flow may include S601 to S605.

[0166] S601: The SSD sends its own notification message to a third port connected to the bus switching network. Correspondingly, the bus switching network receives the notification message from the SSD from the third port, wherein the notification message includes device information of the SSD.

[0167] S601 can be understood with reference to S301. For example, the CPU in S301 can be replaced with an SSD, and the second port can be replaced with a third port. As shown in FIG6 , the third port includes port 3 of bus switch 3 and port 1 of bus switch 4. FIG6 schematically illustrates the SSD sending its own notification message to port 1 of bus switch 4. Optionally, the SSD can also send its own message to port 3 of bus switch 3.

[0168] S602: The bus switching network forwards the notification message of the SSD to the bus controller according to the forwarding path from the third port to the first port. Correspondingly, the bus controller receives the notification message from the first port.

[0169] The method by which the bus switching network determines a forwarding path to the bus controller was previously described and will not be repeated here. The bus switching network may record one or more forwarding paths from the third port to the first port and may forward SSD notification messages according to all or part of these forwarding paths. Figure 6 schematically illustrates a forwarding path from port 1 of bus switch 4 to port 3 of bus switch 6. As an example, the bus switching network may forward SSD notification messages to the bus controller along this forwarding path.

[0170] Optionally, based on the fact that the bus switch can add forwarding path information in the forwarded notification message, the bus controller and / or the bus switching network can add SSD information to the network topology of the bus network based on the forwarding path information in the SSD notification message. The updated network topology adds a new node at the location of the SSD (i.e., the location connected to port 3 of bus switch 3 and port 1 of bus switch 4, respectively), and this node is the SSD.

[0171] S603: The bus controller allocates address space 4 to the SSD according to the device information of the SSD in the notification message;

[0172] Assume that the manufacturer ID and device ID of the SSD are D4 and V4 respectively, and the address space allocated by the bus controller to the SSD is address space 4 in the global address space. This application does not limit the size of the address space required by the SSD.

[0173] S603 can be understood with reference to S303. For example, the CPU in S303 can be replaced with SSD, address space 1 can be replaced with address space 4, and the CPU identifier "CPU, D1, V1" can be replaced with the SSD identifier "SSD, D4, V4".

[0174] S604: The bus controller sends a configuration message 4 to the SSD via the bus switching network. Accordingly, the SSD receives the configuration message 4 via the bus switching network, wherein the configuration message 4 includes address information for describing the address space 4.

[0175] S604 can be understood with reference to S304. For example, the CPU in S304 can be replaced with SSD, address space 1 can be replaced with address space 4, the CPU identifier "CPU, D1, V1" can be replaced with the SSD identifier "SSD, D4, V4", and configuration message 1 can be replaced with configuration message 4, etc.

[0176] Referring to the forwarding method described in S304, the bus switching network can forward configuration message 4 along all or part of the forwarding path to the SSD. FIG6 schematically illustrates a forwarding path from port 3 of bus switch 6 to port 1 of bus switch 4. As an example, the bus switching network can forward configuration message 4 to the SSD along this forwarding path.

[0177] S605 . The SSD maps its own storage space 4 to the address space 4 according to the instruction of the configuration message 4 .

[0178] Referring to the configuration method introduced in S305, the SSD can configure its own configuration space according to the instructions of the configuration message 4. For example, the SSD can map its own storage space 4 to the address space 4, which is beneficial for other bus devices in the bus network to directly address the SSD's storage space 4 according to the address space 4, read data from the storage space 4 and / or write data to the storage space 4.

[0179] Different from the method flow described in FIG3 , in the method flow described in FIG6 , after the bus switching network receives the notification message of the newly added bus device, it can forward the notification message according to the forwarding path to the bus controller, which is conducive to saving forwarding resources and improving the security of the notification message. The newly added bus device can refer to a bus device that is newly connected to the bus switching network after the bus switching network records the forwarding path to the bus controller, or it can refer to a bus device that is newly connected to the bus switching network after the bus network completes initialization. The completion of initialization of the bus network can refer to the bus controller experiencing a preset time length after startup, or no longer receiving notification messages from bus devices within the preset time length, etc. Before the bus network completes initialization, the bus switching network can generally record the forwarding path to the bus controller.

[0180] Optionally, after receiving the notification message of the newly added bus device, the bus switching network may forward the notification message by broadcasting.

[0181] The following describes a scenario where a bus network deregisters a bus device. Figure 7 schematically illustrates a possible method flow for this scenario. As shown in Figure 7, the method flow may include S701 to S705.

[0182] S701: The SSD sends its own exit notification message to the third port. Correspondingly, the bus switching network receives the exit notification message of the SSD from the third port, wherein the exit notification message is used to indicate that the SSD will exit the bus network.

[0183] When the SSD is about to exit from the bus network, for example, when the SSD receives an exit instruction issued by the user, the SSD can send its own exit notification message to the third port of the connected bus switching network. Correspondingly, the bus switching network receives the exit notification message of the SSD from the third port, wherein the exit notification message is used to indicate that the SSD is about to exit the bus network.

[0184] FIG7 schematically shows that the SSD sends its own exit notification message to port 1 of the bus switch 4 . Optionally, the SSD may also send its own exit notification message to port 3 of the bus switch 3 .

[0185] S702: The bus switching network forwards the SSD exit notification message to the bus controller according to the forwarding path from the third port to the first port. Correspondingly, the bus controller receives the SSD exit notification message from the first port.

[0186] The method by which the bus switching network determines a forwarding path to the bus controller was previously described and will not be repeated here. The bus switching network may record one or more forwarding paths from the third port to the first port and may forward the SSD's exit notification message according to all or part of these forwarding paths. Figure 7 schematically illustrates a forwarding path from port 1 of bus switch 4 to port 3 of bus switch 6. As an example, the bus switching network may forward the SSD's exit notification message to the bus controller according to this forwarding path.

[0187] S703: The bus controller reclaims address space 4 allocated to the SSD according to the exit notification message of the SSD.

[0188] After receiving the SSD's exit notification message, the bus controller can deregister the SSD based on the SSD's exit notification message. For example, the bus controller can reclaim address space 4 allocated to the SSD. Furthermore, the bus controller can deregister or delete the SSD's information from the bus network topology, with the updated network topology indicating that the node where the SSD is located is empty or that no bus device exists.

[0189] S704: The bus controller sends a cancellation confirmation message to the SSD via the bus switching network. Correspondingly, the SSD receives the cancellation confirmation message via the bus switching network. The cancellation confirmation message is used to indicate that the bus controller has reclaimed the address space allocated to the SSD.

[0190] Referring to the forwarding method described in S304, the bus switching network can forward the deregistration confirmation message along all or part of the forwarding path to the SSD. Figure 7 schematically illustrates a forwarding path from port 3 of bus switch 6 to port 1 of bus switch 4. As an example, the bus switching network can forward the deregistration confirmation message to the SSD along this forwarding path.

[0191] S705. The SSD completes the deregistration according to the deregistration confirmation message.

[0192] After receiving the deregistration confirmation message, the SSD can confirm that the bus controller has successfully received its exit notification message. The SSD can then proceed with deregistration and remove itself from the bus network. For example, the SSD can delete its registration information, such as the address space configured for the device, and / or disconnect from port 3 of bus switch 3 and port 1 of bus switch 4.

[0193] Optionally, after receiving the deregistration confirmation message, the SSD may send a deregistration completion notification message to the bus controller via the bus switching network to notify the bus controller that it has successfully received the deregistration confirmation message and completed the deregistration.

[0194] This application does not limit the type of bus. For example, the bus can be a PCIe bus. As public cloud services develop, the ability to combine different resources is required. Therefore, the bus can also be a CXL bus or an NVLINK bus.

[0195] This application does not limit the number of bus devices in a bus network, nor does it limit the types of bus devices. For example, bus devices in a bus network may include at least one of a variety of types, such as a CPU, memory, network card, SSD, graphics processing unit (GPU), neural network processing unit (NPU), bus switch, and field-programmable gate array (FPGA). The bus switch mentioned in this application can be replaced with other types of bus devices with forwarding functions.

[0196] The device notification information described above may refer to one or more notification messages or all or part of the information in one or more notification messages. Alternatively, the bus switching network forwarding a notification message proactively sent by a bus device may refer to the bus switching network forwarding a portion of the information in the notification message (e.g., device information of the bus device). The path information described above may include information about the forwarding path described above.

[0197] Regarding the above method embodiment, it should be noted that:

[0198] (1) The step numbers in the flowcharts described in the embodiments are merely examples of the execution process and do not limit the order in which the steps are executed. In the embodiments of the present application, there is no strict execution order for steps that have no temporal dependencies. Furthermore, not all steps shown in the flowcharts are mandatory steps, and steps may be added or deleted based on actual needs.

[0199] (2) In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0200] The above describes in detail the method provided by the embodiments of the present application. The following describes in detail the device and chip system provided by the embodiments of the present application. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment. Therefore, for matters not described in detail, please refer to the method embodiment above. For the sake of brevity, they are not repeated here.

[0201] In the above, the bus controller can be a bus device, or a device deployed on a bus device. The above method is mainly introduced from the perspective of the interaction between the bus controller, the bus terminal and the bus switch. It can be understood that in order to realize the above functions, any bus device includes a hardware structure and / or software module corresponding to each function. In order to realize the functions in the above embodiments, the bus controller, the bus terminal and the bus switch respectively include a hardware structure and / or software module corresponding to each function. It should be easy for those skilled in the art to realize that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application scenario and design constraints of the technical solution.

[0202] Figure 8 is a diagram illustrating a structure of a bus controller provided by the present application. As shown in Figure 8, the bus controller includes: a transceiver module configured to receive notification messages broadcasted by the bus switching network; a processing module configured to execute S303; and the transceiver module further configured to execute S304.

[0203] Optionally, the transceiver module is further configured to execute one or more steps in S306 to S311.

[0204] Optionally, the processing module is further configured to execute S603, and the transceiver module is further configured to execute S604.

[0205] Optionally, the processing module is further configured to execute S703, and the transceiver module is further configured to execute S704.

[0206] The transceiver module and the processing module can be implemented in software or hardware. For example, the implementation of the transceiver module will be described below using the transceiver module as an example. Similarly, the implementation of the processing module can refer to the implementation of the transceiver module.

[0207] As an example of a software functional unit, a transceiver module includes code running on a computing instance. The computing instance may include at least one of a physical host (computing device), a virtual machine, and a container. Furthermore, the computing instance may be one or more. For example, the transceiver module may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed in the same region or in different regions. Furthermore, the multiple hosts / virtual machines / containers used to run the code may be distributed in the same availability zone or in different availability zones, each availability zone including one data center or multiple geographically close data centers. Typically, a region may include multiple availability zones.

[0208] As an example of a hardware functional unit, a transceiver module may include at least one computing device, such as a server. Alternatively, the transceiver module may be implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD may be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0209] It should be noted that, in other embodiments, the transceiver module can be used to execute any step in the method of the embodiment of the present application, and the processing module can be used to execute any step in the method of the embodiment of the present application. The steps that the transceiver module and the processing module are responsible for implementing can be specified as needed, and the full functionality of the bus controller can be achieved by having the transceiver module and the processing module respectively implement different steps in the method of the embodiment of the present application.

[0210] Please refer to Figure 9, which is a schematic diagram of the structure of a bus device provided in an embodiment of the present application. As shown in Figure 9, the bus device 9 includes: a processor 901, a memory 902, a communication interface 903, and a bus 904. The processor 901, the memory 902, and the communication interface 903 are coupled via a bus (not labeled in the figure). The memory 902 stores instructions. When the execution instructions in the memory 902 are executed, the bus device 9 executes the method executed by the bus controller, bus switch, or bus terminal (such as a CPU or SSD) in the above method embodiment.

[0211] The bus device 9 may be one or more integrated circuits configured to implement the above method, such as one or more application specific integrated circuits (ASICs), one or more microprocessors (DSPs), one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. For example, when the unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call a program. For example, these units can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0212] The processor 901 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0213] The memory 902 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0214] Memory 902 stores executable program code. Processor 901 executes this executable program code to implement the functions of the method executed by the aforementioned bus controller, bus switch, or bus terminal (e.g., a CPU or SSD), thereby implementing the aforementioned bus-based device management method. In other words, memory 902 stores instructions for executing the aforementioned management method.

[0215] The communication interface 903 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the bus device 9 and other devices.

[0216] In addition to the data bus, bus 904 may also include a power bus, a control bus, and a status signal bus. The bus may be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a unified bus (Ubus or UB), a Compute Express Link (CXL), or a Cache Coherent Interconnect for Accelerators (CCIX). Buses can be categorized as address buses, data buses, and control buses.

[0217] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0218] The present application also provides a computer-readable storage medium storing computer instructions for implementing the methods performed by a bus controller, bus switch, or bus terminal (e.g., a CPU or SSD) in each of the above method embodiments. For example, when the computer program is executed by a computer, the computer can implement the methods performed by the corresponding devices in each of the above method embodiments.

[0219] An embodiment of the present application also provides a computer program product comprising instructions, which, when executed by a computer, implement the methods performed by a bus controller or a bus switch or a bus terminal (such as a CPU or an SSD) in the above-mentioned method embodiments.

[0220] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0221] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0222] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. For example, the computer can be a personal computer, a server, or a network device, etc. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)). For example, the aforementioned available medium includes, but is not limited to, various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0223] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A device management method based on bus technology, characterized in that The method is applied to a bus controller that operates in a bus network. The bus network includes a plurality of bus devices interconnected by a bus. The method includes: Receiving device announcement information, where the device announcement information includes device information of the first bus device, and the device information of the first bus device is actively sent by the first bus device to the bus controller after power-on; Allocating an address space of the bus to the first bus device according to the device information of the first bus device; Sending configuration information to the first bus device, where the configuration information includes address information for describing the address space.

2. The method according to claim 1, wherein The device information of the first bus device is forwarded to the bus controller via one or more bus devices in the bus network after being sent from the first bus device.

3. The method according to claim 2, wherein The device announcement information further includes path information, where the path information is used to indicate information about the forwarding of the device information of the first bus device through one or more bus devices. The method further includes: Determining a forwarding path of the device announcement information between the first bus device and the bus controller according to the path information.

4. The method according to claim 3, characterized in that When the device information of the first bus device is forwarded to the bus controller via a plurality of bus devices in the bus network, the receiving of the device announcement information includes: Receiving a plurality of device announcement information respectively, where the device information of the first bus device in the plurality of device announcement information has different forwarding paths; Determining a plurality of forwarding paths according to the path information in each device announcement information in the plurality of device announcement information.

5. The method according to claim 4, wherein The sending of the configuration information to the first bus device includes: Determining a target forwarding path according to the plurality of forwarding paths, and sending the configuration information to the first bus device through the target forwarding path.

6. The method according to any one of claims 2-5, characterized in that, The method further includes: Sending device information of the bus controller to at least one bus device connected to the bus controller, where the device information of the bus controller is used to instruct the at least one bus device to record information about the port for connecting to the bus controller.

7. The method according to claim 6, characterized in that, The method further includes: Receiving device information of a second bus device in the bus network, where the device information of the second bus device is actively sent by the second bus device to the bus controller after power-on, and the device information of the second bus device is forwarded by the at least one bus device according to the information about the port of the bus controller.

8. The method according to claim 6 or 7, characterized in that, The method further includes: Receiving status announcement information of the first bus device, where the status announcement information of the first bus device is used to indicate that the first bus device will exit the bus network or is still connected to the bus network, and the status announcement information of the first bus device is forwarded by the at least one bus device according to the recorded information about the port for connecting to the bus controller; Determining the connection status of the first bus device in the bus network according to the status announcement information of the first bus device.

9. The method according to any one of claims 2-8, characterized in that, The device type of the bus device that forwards the device information of the first bus device in the bus network includes a bus switch.

10. The method according to any one of claims 1-9, characterized in that, The device information of the first bus device includes the identifier of the first bus device, and the identifier of the first bus device includes at least one of the device type of the first bus device, the manufacturer identifier of the first bus device, and the device identifier of the first bus device.

11. The method according to any one of claims 1 to 10, characterized in that, The device information of the first bus device includes the size of the address space required by the first bus device.

12. The method according to any one of claims 1-11, characterized in that, The multiple bus devices are arranged in at least two computer devices.

13. A device management method based on bus technology, characterized in that, A bus network includes multiple bus devices interconnected by a bus, and a bus controller runs in the bus network. The method includes: After power-on, the first bus device in the bus network actively sends the device information of the first bus device; The bus controller receives device announcement information, and the device announcement information includes the device information of the first bus device; The bus controller allocates the address space of the bus for the first bus device according to the device information of the first bus device, and sends configuration information to the first bus device. The configuration information includes address information for describing the address space; The first bus device receives the configuration information, and maps all or part of its storage space to the address space described by the address information according to the indication of the configuration information.

14. The method according to claim 13, wherein The device information of the first bus device is forwarded from the first bus device and then forwarded to the bus controller via one or more bus devices in the bus network.

15. The method according to claim 14, characterized in that The method further includes: After receiving the device information of the first bus device, the bus device connecting the first bus device in the bus network forwards the device information of the first bus device and path information. The path information is used to indicate the information that the device information of the first bus device is forwarded through one or more bus devices.

16. The method according to claim 14 or 15, characterized in that, The method further includes: After receiving the device information of the first bus device, the bus device connecting the first bus device in the bus network forwards it in a broadcast manner.

17. The method according to any one of claims 14-16, characterized in that The method further includes: The bus controller sends its own device information to at least one bus device connected to it; The at least one bus device records the information of the port used to connect the bus controller according to the indication of the device information of the bus controller.

18. The method according to claim 17, wherein The method further includes: After power-on, the second bus device in the bus network actively sends its own device information to the bus controller; The at least one bus device forwards the device information of the second bus device to the bus controller according to the information of the port of the bus controller; The bus controller receives the device information of the second bus device.

19. The method according to claim 17 or 18, characterized in that, The method further includes: The first bus device sends its own status announcement information to the bus controller. The status announcement information is used to indicate that the first bus device will exit the bus network or is still connected to the bus network; The at least one bus device forwards the status announcement information to the bus controller according to the information of the port of the bus controller; The bus controller receives the status notification information and determines the connection status of the first bus device in the bus network according to the status notification information.

20. A bus controller, characterized in that, The bus controller operates in a bus network, the bus network includes a plurality of bus devices interconnected by a bus, and the bus controller includes: a transceiver module, configured to receive device notification information, the device notification information includes device information of the first bus device, and the device information of the first bus device is actively sent by the first bus device to the bus controller after power-on; a processing module, configured to allocate an address space of the bus for the first bus device according to the device information of the first bus device; The transceiver module is further configured to send configuration information to the first bus device, and the configuration information includes address information for describing the address space.

21. A bus device, characterized in that, The bus device includes a processor and a bus interface, and the processor is configured to execute the method according to any one of claims 1-12 based on instructions stored in a memory.

22. A cluster of computing devices, characterized in that, The computing device cluster includes at least one computing device, and each computing device in the at least one computing device includes one or more bus devices, and the one or more bus devices are connected to the bus device according to claim 21.

23. A bus network, characterized in that, The bus network includes a plurality of bus devices interconnected by a bus, and a bus controller operates in the bus network, and the bus controller is configured to execute the method according to any one of claims 1 to 12.

24. A computer program product, characterized in that, including computer-readable instructions that, when run on a computer, cause the computer to execute the method according to any one of claims 1 to 12.

25. A computer-readable storage medium, characterized in that, Instructions are stored in the computer-readable storage medium, and when the instructions are run on a computer, cause the computer to execute the method according to any one of claims 1 to 12.

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