Semiconductor device, manufacturing method therefor, power amplifier chip and electronic apparatus

Abstract

Provided in the present application are a semiconductor device, a manufacturing method therefor, a power amplifier chip and an electronic apparatus. The semiconductor device comprises: a semiconductor substrate, an epitaxial layer and a first electrode, wherein a first recess is provided in the surface of the epitaxial layer, one part of the first electrode is located in the first recess, and the other part of the first electrode protrudes from the surface of the side of the epitaxial layer facing away from the semiconductor substrate. The first electrode is a source or a drain; and the first electrode comprises: a contact layer, a metal isolation layer and an anti-oxidation metal layer, the contact layer being in contact with the epitaxial layer on an inner wall of the first recess, the metal isolation layer being located between the contact layer and the anti-oxidation metal layer, and the thickness of the surface of the anti-oxidation metal layer that protrudes from the side of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of a channel layer. The anti-oxidation metal layer in the present application is relatively thick, and during an annealing treatment process, the thick anti-oxidation metal layer can fully isolate air, forms a good and reliable ohmic contact and reduces the resistivity of the ohmic contact.

Description

Semiconductor device, manufacturing method thereof, power amplifier chip and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on January 24, 2024, with application number 202410103088.3 and application name “A semiconductor device and its manufacturing method”, the entire contents of which are incorporated by reference into this application; this application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on March 4, 2024, with application number 202410248257.2 and application name “Semiconductor device, its manufacturing method, power amplifier chip and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of radio frequency devices, and in particular to a semiconductor device, a manufacturing method thereof, a power amplifier chip, and an electronic device. Background Art

[0004] GaN / GaAs-based high electron mobility transistors (HEMTs) are used as RF front-end devices, offering the advantages of high output power and high efficiency. During HEMT fabrication, a metal stack is deposited on the surface of the epitaxial layer. Annealing forms an ohmic contact at the interface between the epitaxial layer and the metal stack. However, in related art, the ohmic contact of HEMT devices has a high resistivity, which affects the device's output power, efficiency, and other performance characteristics.

[0005] Summary of the Invention

[0006] The present invention provides a semiconductor device, a method for manufacturing the same, a power amplifier chip, and an electronic device for reducing the resistivity of the ohmic contacts of the semiconductor device. The semiconductor device in the present invention can be used in radio frequency (RF) applications, particularly in portable devices such as mobile phones, tablet computers, and laptop computers.

[0007] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device provided by an embodiment of the present application may include:

[0008] Step 1: forming an epitaxial layer on a semiconductor substrate, and patterning the epitaxial layer to form a first groove on a surface of the epitaxial layer facing away from the semiconductor substrate; wherein the epitaxial layer includes: a channel layer;

[0009] Step 2: forming a first electrode having a portion located within the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate; wherein the first electrode is a source electrode or a drain electrode, and comprises: a contact layer, a metal isolation layer, and an anti-oxidation metal layer; the contact layer contacts the epitaxial layer on an inner wall of the first groove; the anti-oxidation metal layer is located on a side of the contact layer facing away from the semiconductor substrate; and the metal isolation layer is located between the contact layer and the anti-oxidation metal layer; the thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer;

[0010] Step 3: performing annealing treatment on the structure after forming the anti-oxidation metal layer to obtain a semiconductor device.

[0011] In the method for manufacturing a semiconductor device provided by an embodiment of the present application, during the process of manufacturing the first electrode, the thickness of the anti-oxidation metal layer formed is greater than or equal to 400nm and greater than or equal to twice the thickness of the channel layer, that is, a thicker anti-oxidation metal layer is formed in the first electrode, and then the structure after the anti-oxidation metal layer is formed is annealed. In this way, during the annealing process, the thicker anti-oxidation metal layer can fully isolate the air, prevent the air from reacting with the metal in the first electrode, and avoid the formation of holes in the ohmic contact area, so that the contact layer and the epitaxial layer can react well, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. Moreover, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer can diffuse into the epitaxial layer to participate in the ohmic contact reaction, that is, the metal elements in the anti-oxidation metal layer can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, compared with the manufacturing process of the related art, the manufacturing method provided by the embodiment of the present application can also save the subsequent metal thickening process, avoid multiple metal deposition processes, and avoid stability problems caused by interface exposure. It should be explained that ohmic contact means that when the first electrode contacts the epitaxial layer, a very small contact barrier is formed at the contact interface, or no contact barrier is formed at the contact interface. In other words, the contact resistivity of ohmic contact is low.

[0012] Moreover, in the method for manufacturing a semiconductor device provided in an embodiment of the present application, a first groove is formed on the surface of the epitaxial layer facing away from the semiconductor substrate, and a portion of the subsequently formed first electrode is located within the first groove. This can increase the contact area between the contact layer in the first electrode and the epitaxial layer, thereby further reducing the resistivity of the ohmic contact between the first electrode and the epitaxial layer.

[0013] In the embodiment of the present application, the semiconductor substrate may be made of a high-resistance semiconductor material. For example, the semiconductor substrate may include a Si material with a resistivity greater than 5000Ω.cm. For example, the semiconductor substrate may include a Si material with a resistivity greater than 1e4 Ω.cm Si material; alternatively, the semiconductor substrate may include a resistivity greater than 1e 6 Ω.cm; or, the semiconductor substrate may include a GaN material with a resistivity greater than 1e4Ω.cm; or, the semiconductor substrate may include a sapphire material with a resistivity greater than 1e11Ω.cm. Of course, the semiconductor substrate in the embodiments of the present application may also be made of other high-resistance semiconductor materials, and this application is not limited thereto.

[0014] In step 1, forming an epitaxial layer on a semiconductor substrate may specifically include forming a channel layer having a thickness in the range of 100 nm to 400 nm on the semiconductor substrate. For example, the channel layer may be formed using an undoped gallium nitride (GaN) material. Subsequently, forming a barrier layer having a thickness in the range of 4 nm to 35 nm on the channel layer. For example, the barrier layer may be formed using an aluminum gallium nitride (AlGaN) material having a thickness in the range of 10 nm to 35 nm. For another example, the barrier layer may be formed using aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN) material having a thickness in the range of 4 nm to 10 nm.

[0015] In one possible implementation, in the above step one, forming an epitaxial layer on the semiconductor substrate may also include: forming a cap layer with a thickness in the range of 1 nm to 5 nm on the barrier layer. For example, the cap layer may be formed using materials such as gallium nitride (GaN) and in-situ silicon nitride (SiN).

[0016] In a possible implementation, in the above step 1, an epitaxial layer is formed on the semiconductor substrate, and the step may further include: before forming the channel layer, a nucleation layer, a transition layer, and a buffer layer are sequentially formed on the semiconductor substrate. Specifically, aluminum nitride (AlN) material can be used to form a nucleation layer with a thickness in the range of 100nm to 300nm. Aluminum gallium nitride (AlGaN) material can be used to form a transition layer with a thickness in the range of 100nm to 500nm. The buffer layer can be made of a high-resistance semiconductor material, for example, a high-resistance gallium nitride (GaN) material can be used to form the buffer layer. The buffer layer can be doped with a concentration greater than 1e 17 ~2e 19 Alternatively, the buffer layer may be doped with carbon (C) at a concentration greater than 1e 17 The thickness of the buffer layer can be in the range of 0.5um to 2um.

[0017] In a possible implementation, each film layer in the epitaxial layer may be fabricated using an epitaxial growth process such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD).

[0018] In step 1 above, the epitaxial layer can be patterned to form a first groove on the surface of the epitaxial layer. In specific implementation, the depth of the first groove is related to factors such as the material of the contact layer to be formed later and the annealing temperature of the subsequent annealing process, which will be described in detail below with reference to the accompanying drawings.

[0019] In some embodiments of the present application, the contact layer may be made of a metal material and annealed at a relatively high temperature. For example, the annealing temperature may be in the range of 500°C to 1000°C. The bottom of the first recess may be located inside the barrier layer. The epitaxial layer may be patterned using the following methods:

[0020] A photoresist layer is formed on the surface of the epitaxial layer, and the photoresist layer is subjected to processes such as photolithography and development to pattern the photoresist layer so that the pattern of the photoresist layer covers the area outside the first groove to be formed and exposes the area of ​​the first groove to be formed. The epitaxial layer is etched using the pattern of the photoresist layer as a shield. For example, an inductively coupled plasma (ICP) etching process can be used to etch the epitaxial layer. Specifically, an inductively coupled plasma process containing a Cl-based gas can be used to etch the epitaxial layer. During the etching process, the etching depth can be controlled by adjusting parameters such as the time and power of the etching process, thereby forming a first groove extending from the surface of the epitaxial layer away from the semiconductor substrate to the interior of the barrier layer.

[0021] In the case where the contact layer is made of metal material, the above step 2 may specifically include:

[0022] A contact layer is formed using a metal material, with a portion of the contact layer located within the first recess and another portion extending to the surface of the epitaxial layer outside the first recess. A second recess is formed on the surface of the contact layer facing away from the semiconductor substrate. The contact layer can contact the epitaxial layer at the inner wall of the first recess. This arrangement can increase the contact area between the contact layer and the epitaxial layer, thereby reducing the resistivity of the ohmic contact between the contact layer and the epitaxial layer. For example, the contact layer can be made of titanium (Ti) and have a thickness ranging from 4 nm to 20 nm.

[0023] A metal isolation layer is formed using a metal material, with a portion of the metal isolation layer positioned within the second groove and another portion extending to an area above the contact layer excluding the second groove. A third groove is formed on the surface of the metal isolation layer facing away from the semiconductor substrate. Forming the metal isolation layer on the surface of the contact layer prevents material from the subsequently formed anti-oxidation metal layer from diffusing into the contact layer, thus preventing excessive downward diffusion of metal elements from the anti-oxidation metal layer, which could cause reliability issues in the semiconductor device. Specifically, the metal isolation layer can include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and the thickness of the metal isolation layer can be in the range of 20 nm to 100 nm. In one possible implementation, after forming the contact layer and before forming the metal isolation layer, the method may further include forming a first metal layer on the surface of the contact layer, with a portion of the first metal layer positioned within the second groove and another portion extending to an area above the contact layer excluding the second groove. A groove is also formed on the surface of the first metal layer facing away from the semiconductor substrate. Subsequently, the metal isolation layer can be formed on the surface of the first metal layer, with a portion of the metal isolation layer positioned within the groove on the surface of the first metal layer and another portion extending to an area above the surface of the first metal layer excluding the groove. For example, the first metal layer may include aluminum (Al) material, and the thickness of the first metal layer may be between 80 nm and 200 nm. During the subsequent annealing process, the first metal layer may diffuse downward, for example, into the channel layer, and participate in the ohmic contact reaction, thereby forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0024] An anti-oxidation metal layer is formed using a metal material, and a portion of the anti-oxidation metal layer is located in the third groove, and the other portion protrudes from the surface of the metal isolation layer on the side facing away from the semiconductor substrate. In an embodiment of the present application, a thicker anti-oxidation metal layer is formed before annealing, and the anti-oxidation metal layer can fill the third groove, and the surface of the anti-oxidation metal layer facing away from the semiconductor substrate can be a flat surface, and the thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400nm and greater than or equal to twice the thickness of the channel layer. In one possible implementation, the anti-oxidation metal layer can be made of an inert metal material such as gold (Au) or platinum (Pt) that is not easily oxidized during the annealing process (annealing temperature is in the range of 200°C to 1000°C); and / or, the anti-oxidation metal layer can be made of an alloy material with anti-oxidation properties, for example, titanium nitride (TiN) material with good conductive properties and good stability can be used.

[0025] Furthermore, to prevent damage to the anti-oxidation metal layer during the subsequent etching process of the dielectric layer, step 2 may further include forming an etch barrier layer on the anti-oxidation metal layer. For example, a metal material such as Ti or Ni with slow etching characteristics for F-based reactive ion etching (RIE) may be used, and the thickness of the etch barrier layer may be greater than or equal to 20 nm.

[0026] After forming the etching stop layer, the above-mentioned step 2 may further include: patterning the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer and the etching stop layer, removing the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer and the etching stop layer in the area outside the first groove, and then removing the photoresist layer to obtain the first electrode, that is, the pattern of the first electrode is consistent with the area of ​​the first groove. In addition, the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer and the etching stop layer can be patterned using the same composition process. In this way, in the first electrode obtained, the outer edges of the contact layer, the first metal layer, the metal isolation layer, the anti-oxidation metal layer and the etching stop layer are flush, which can make the morphology of the first electrode better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiment of the present application, due to the level limitation of the manufacturing process, the outer edges of certain film layers in the first electrode are flush, which means that the outer edges of these film layers are basically flush within a certain error range. In an embodiment of the present application, the semiconductor device may include at least one transistor, each transistor may include a source, a drain and a gate, and the first electrode in the embodiment of the present application may be a source or a drain.

[0027] In the case of using metal materials to make the contact layer, the above-mentioned step three may specifically include: using a temperature in the range of 500°C to 1000°C to anneal the structure after the oxidation-resistant metal layer is formed. Since the temperature of the annealing treatment is relatively high, during the annealing process, the contact layer reacts with the epitaxial layer, and the metal elements in the contact layer can penetrate into the channel layer through the barrier layer, thereby forming a good and reliable ohmic contact. Specifically, the annealing treatment can be performed using a rapid thermal processing (RTP) process, laser annealing, and other processes. Moreover, during the annealing process, the metal elements in the oxidation-resistant metal layer and the first metal layer can also diffuse into the channel layer and participate in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0028] In other embodiments of the present application, the contact layer includes a semiconductor doping layer and a second metal layer, and is annealed at a relatively low temperature. For example, the annealing temperature may be in the range of 200°C to 500°C. The bottom of the first recess may be located inside the channel layer. The epitaxial layer may be patterned using the following methods:

[0029] A hard mask layer is formed on the surface of the epitaxial layer. In a possible implementation, the hard mask layer can be made of silicon oxide (SiOx) material or silicon nitride (SiNx) material.

[0030] The hard mask layer is patterned so that the pattern of the hard mask layer covers the area outside the first groove to be formed, exposing the area of ​​the first groove to be formed. The epitaxial layer is etched using the pattern of the hard mask layer as a shield. For example, an inductively coupled plasma (ICP) etching process can be used to etch the epitaxial layer. Specifically, an inductively coupled plasma process containing a Cl-based gas can be used to etch the epitaxial layer. During the etching process, the etching depth can be controlled by adjusting parameters such as the time and power of the etching process, thereby forming a first groove extending from the surface of the epitaxial layer away from the semiconductor substrate to the interior of the channel layer.

[0031] In the case where the contact layer includes a semiconductor doped layer and a second metal layer, the above step 2 may specifically include:

[0032] A semiconductor doped layer is formed using a semiconductor material doped with impurities, so that the semiconductor doped layer fills the first groove. In one possible implementation, the semiconductor doped layer can be formed using a gallium nitride (GaN) material doped with a high concentration of N-type impurities. In a specific implementation, in order to ensure that the semiconductor doped layer formed by the epitaxial process can fill the first groove, the formed semiconductor doped layer is generally slightly higher than the surface of the epitaxial layer (i.e., the surface of the cap layer).

[0033] Afterwards, the hard mask layer on the surface of the epitaxial layer (ie, the surface of the cap layer) is removed. For example, a wet etching process may be used to remove the hard mask layer.

[0034] A second metal layer is formed on the semiconductor doped layer using a metal material. The second metal layer can serve as a reactant in an ohmic contact reaction. By forming the semiconductor doped layer within the first recess of the epitaxial layer, the semiconductor doped layer can reduce the potential barrier between the epitaxial layer and the second metal layer, facilitating ohmic contact formation. For example, the second metal layer can include titanium (Ti).

[0035] A metal isolation layer is then formed on the surface of the second metal layer, that is, on the surface of the contact layer. Forming the metal isolation layer on the surface of the contact layer prevents materials in the subsequently formed anti-oxidation metal layer from diffusing into the contact layer, thus preventing excessive downward diffusion of metal elements in the anti-oxidation metal layer, which could cause reliability issues in the semiconductor device. In one possible implementation, the metal isolation layer may include platinum (Pt).

[0036] Then, an anti-oxidation metal layer is formed on the metal isolation layer using a metal material. The thickness of the formed anti-oxidation metal layer is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. In one possible implementation, the anti-oxidation metal layer can be made of an inert metal material such as gold (Au) or platinum (Pt) that is not easily oxidized during an annealing process (annealing temperature is within the range of 200°C to 1000°C); and / or the anti-oxidation metal layer can be made of an alloy material with anti-oxidation properties, for example, TiN material with good conductivity and good stability.

[0037] Furthermore, to prevent damage to the anti-oxidation metal layer during the subsequent etching process of the dielectric layer, step 2 may further include forming an etch barrier layer on the anti-oxidation metal layer. For example, a metal material such as Ti or Ni with slow etching characteristics for F-based reactive ion etching (RIE) may be used, and the thickness of the etch barrier layer may be greater than or equal to 20 nm.

[0038] During the manufacturing process, the second metal layer, the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer can be deposited on the entire surface. Then, the second metal layer, the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer are patterned to remove the portion of the second metal layer, the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer in the area outside the first groove to obtain the first electrode. In other words, the pattern of the first electrode is consistent with the area of ​​the first groove. In addition, the second metal layer, the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer can be patterned using the same composition process. In this way, in the first electrode obtained, the outer edges of the second metal layer, the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer are flush, which can make the morphology of the first electrode better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiment of the present application, due to the level limitation of the manufacturing process, the outer edges of certain film layers in the first electrode are flush, which means that the outer edges of these film layers are basically flush within a certain error range. In an embodiment of the present application, the semiconductor device may include at least one transistor, each transistor may include a source, a drain and a gate, and the first electrode in the embodiment of the present application may be a source or a drain.

[0039] In the case where the contact layer includes a semiconductor doped layer and a second metal layer, the above step three may specifically include: annealing the structure after forming the anti-oxidation metal layer at a temperature in the range of 200°C to 500°C. Since the bottom of the first groove is located inside the channel layer in the embodiment of the present application, the semiconductor doped layer in the contact layer can be in direct contact with the channel layer. Therefore, a good and reliable ohmic contact can be formed by using a lower annealing temperature. Specifically, the annealing process can be performed using a rapid thermal processing (RTP) process, laser annealing, or other processes.

[0040] In the case where a metal material is used to make the contact layer and the contact layer includes a semiconductor doped layer and a second metal layer, after the above step 3, the process may further include: forming an interconnect structure in contact with the etch stop layer. The specific process is as follows:

[0041] A passivation layer covering the first electrode is formed. For example, the passivation layer may be made of silicon nitride (SiN) material.

[0042] The passivation layer is patterned to form a fourth groove penetrating the passivation layer in a region where a gate is to be formed, wherein a bottom surface of the fourth groove is a portion of the surface of the epitaxial layer.

[0043] A gate contact metal layer is formed on the sidewalls and bottom surface of the fourth groove of the passivation layer, and a metal material is filled in the fourth groove to form a gate interconnection structure. The gate interconnection structure fills the portion of the fourth groove other than the gate contact metal layer and protrudes from the surface of the passivation layer. For example, a metal material such as nickel (Ni) or tungsten (W) can be used to make the gate contact metal layer, the gate contact metal layer can serve as the gate of the transistor, and the gate contact metal layer can contact the epitaxial layer to form a Schottky contact. It should be explained that Schottky contact refers to the case where the gate contact metal layer and the epitaxial layer are in contact, and the energy band of the epitaxial layer at the contact interface is bent to form a contact barrier (which can be called a Schottky barrier). In one possible implementation, a gold (Au) material can be used to make the gate interconnection structure, and the gate interconnection structure can play the role of leading out the gate contact metal layer, and the gate interconnection structure can also have an anti-oxidation effect and reduce the gate resistance.

[0044] A dielectric layer covering the gate interconnect structure is formed, and the dielectric layer covers the passivation layer in the area where the first electrode is located. For example, the dielectric layer can be made of silicon nitride (SiN) material. Then, an etching process is used to pattern the dielectric layer and the passivation layer to expose the first electrode. Since the surface of the anti-oxidation metal layer has an etch barrier layer, during the etching process, the etch barrier layer can protect the anti-oxidation metal layer and prevent the anti-oxidation metal layer from being damaged during the etching process. In a specific implementation, the upper surface of the etch barrier layer can be a flat surface, or, during the etching process, the upper surface of the etch barrier layer may be etched, that is, a groove may be formed on the upper surface of the etch barrier layer.

[0045] The grooves on the surfaces of the passivation layer and the dielectric layer are filled with a metal material, for example, gold (Au), to form an interconnect structure that contacts and connects to the etch stop layer, thereby electrically connecting the interconnect structure to the first electrode. The interconnect structure is used to lead out the first electrode. In a direction parallel to the surface of the semiconductor substrate, the width of the grooves on the surfaces of the passivation layer and the dielectric layer is smaller than the width of the oxidation-resistant metal layer. Thus, the width of the formed interconnect structure is smaller than the width of the oxidation-resistant metal layer.

[0046] In a second aspect, an embodiment of the present application further provides a semiconductor device. The semiconductor device provided by the embodiment of the present application may include: a semiconductor substrate, an epitaxial layer, and a first electrode. In the embodiment of the present application, the semiconductor device may include at least one transistor, each of which may include a source, a drain, and a gate. The first electrode in the embodiment of the present application may be a source or a drain. The epitaxial layer is located on the semiconductor substrate, and a first groove is provided on the surface of the epitaxial layer facing away from the semiconductor substrate. A portion of the first electrode is located within the first groove, and another portion protrudes from the surface of the epitaxial layer facing away from the semiconductor substrate. The first electrode may include: a contact layer, a metal isolation layer, and an anti-oxidation metal layer. The contact layer contacts the epitaxial layer on the inner wall of the first groove. The anti-oxidation metal layer is located on the side of the contact layer facing away from the semiconductor substrate. The metal isolation layer is located between the contact layer and the anti-oxidation metal layer. The thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer.

[0047] In the semiconductor device provided in the embodiment of the present application, the first electrode includes a contact layer, a metal isolation layer, and an anti-oxidation metal layer. The thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. The thickness of the anti-oxidation metal layer in the embodiment of the present application is relatively thick. During the annealing process, the thicker anti-oxidation metal layer can fully isolate the air, prevent the air from reacting with the metal in the first electrode, and avoid the formation of holes in the ohmic contact area, so that the contact layer and the epitaxial layer can react well, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. In addition, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer can diffuse into the epitaxial layer to participate in the ohmic contact reaction. In other words, the metal elements in the anti-oxidation metal layer can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, a first groove is provided on the surface of the epitaxial layer on the side facing away from the semiconductor substrate. A portion of the first electrode is located within the first groove, and the contact layer contacts the epitaxial layer on the inner wall of the first groove. In this way, the contact area between the contact layer and the epitaxial layer can be increased, thereby further reducing the resistivity of the ohmic contact between the first electrode and the epitaxial layer.

[0048] In one possible implementation, the semiconductor device provided in the embodiment of the present application can be manufactured using the manufacturing method in the first aspect mentioned above. Of course, in some cases, the semiconductor device in the embodiment of the present application can also be manufactured using other manufacturing methods, which is not limited in this application.

[0049] In the embodiment of the present application, the semiconductor substrate may include a high-resistance semiconductor material. For example, the semiconductor substrate may include a Si material with a resistivity greater than 5000 Ω.cm. For example, the semiconductor substrate may include a Si material with a resistivity greater than 1e 4 Ω.cm Si material; alternatively, the semiconductor substrate may include a resistivity greater than 1e 6 Ω.cm; or, the semiconductor substrate may include a GaN material with a resistivity greater than 1e4 Ω.cm; or, the semiconductor substrate may include a sapphire material with a resistivity greater than 1e11 Ω.cm. Of course, the semiconductor substrate in the embodiment of the present application may also include other high-resistance semiconductor materials, which is not limited in this application.

[0050] In one possible implementation, the epitaxial layer may include: a channel layer and a barrier layer, wherein the barrier layer is located on the side of the channel layer facing away from the semiconductor substrate. For example, the channel layer may include undoped gallium nitride (GaN) material, and the thickness of the channel layer may be in the range of 100nm to 400nm. The barrier layer may include aluminum gallium nitride (AlGaN) material, aluminum nitride (AlN), indium aluminum nitride (InAlN) or indium gallium nitride (InGaN) and the like, and the thickness of the barrier layer may be in the range of 4nm to 35nm. For example, when the barrier layer includes aluminum gallium nitride (AlGaN) material, the thickness of the barrier layer may be in the range of 10nm to 35nm. For another example, when the barrier layer includes aluminum nitride (AlN), indium aluminum nitride (InAlN) or indium gallium nitride (InGaN) and the like, the thickness of the barrier layer may be in the range of 4nm to 10nm.

[0051] In addition, the epitaxial layer may further include a cap layer located on a side of the barrier layer facing away from the semiconductor substrate, with the first groove extending through the cap layer in a direction perpendicular to the surface of the semiconductor substrate. For example, the cap layer may include materials such as gallium nitride (GaN) and in-situ silicon nitride (SiN), and the thickness of the cap layer may be in the range of 1 nm to 5 nm.

[0052] In a specific configuration, the epitaxial layer may further include: a nucleation layer located between the semiconductor substrate and the channel layer, a transition layer located between the nucleation layer and the channel layer, and a buffer layer between the transition layer and the channel layer. Specifically, the nucleation layer may include aluminum nitride (AlN) material, and the thickness of the nucleation layer may be in the range of 100nm to 300nm. The transition layer may include aluminum gallium nitride (AlGaN) material, and the thickness of the transition layer may be in the range of 100nm to 500nm. The buffer layer may include high-resistance gallium nitride (GaN) material, and the buffer layer may be doped with a concentration greater than 1e 17 ~2e 19 Alternatively, the buffer layer may be doped with carbon at a concentration greater than 1e 17The thickness of the buffer layer can be in the range of 0.5um to 2um.

[0053] In one possible implementation, the first electrode may further include: an etch barrier layer located on the side of the anti-oxidation metal layer facing away from the semiconductor substrate, and the etch barrier layer may include a metal material. For example, the etch barrier layer may include titanium (Ti) or nickel (Ni), and the thickness of the etch barrier layer may be greater than or equal to 20 nm. The etch barrier layer may protect the anti-oxidation metal layer and prevent the anti-oxidation metal layer from being damaged during the etching process of the dielectric layer. During the etching process of the dielectric layer, the upper surface of the etch barrier layer may be etched, resulting in a groove on the upper surface of the etch barrier layer. Of course, in some cases, the upper surface of the etch barrier layer may also be a flat surface.

[0054] In one possible implementation, the semiconductor device provided in an embodiment of the present application may further include: an interconnect structure located on a side of the first electrode facing away from the semiconductor substrate, the interconnect structure being in contact with the etch stop layer so as to electrically connect the interconnect structure to the first electrode, and the interconnect structure being used to lead out the first electrode. For example, the interconnect structure may include a metal material such as gold (Au). In a specific configuration, the width of the interconnect structure may be less than the width of the anti-oxidation metal layer in a direction parallel to the surface of the semiconductor substrate.

[0055] In addition, the semiconductor device in the embodiment of the present application may further include: a passivation layer, a gate contact metal layer and a gate interconnection structure. For example, the passivation layer may include a silicon nitride (SiN) material. The passivation layer has a fourth groove, which penetrates the passivation layer in a direction perpendicular to the surface of the semiconductor substrate, and the bottom surface of the fourth groove is a part of the surface of the epitaxial layer. The gate contact metal layer covers the sidewalls and bottom surface of the fourth groove, and the gate interconnection structure fills the portion of the fourth groove except the gate contact metal layer, and protrudes from the surface of the passivation layer. For example, the gate contact metal layer may include a metal material such as nickel (Ni) or tungsten (W), and the gate contact metal layer may serve as the gate of the transistor. The gate contact metal layer may contact the epitaxial layer to form a Schottky contact. It should be explained that the Schottky contact refers to the case where the gate contact metal layer and the epitaxial layer are in contact, and the energy band of the epitaxial layer at the contact interface is bent to form a contact barrier (which may be called a Schottky barrier). In a possible implementation, the gate interconnect structure may include a gold (Au) material. The gate interconnect structure may serve to lead out a gate contact metal layer. In addition, the gate interconnect structure may also have an anti-oxidation effect and reduce gate resistance.

[0056] In the embodiment of the present application, the depth of the first groove on the surface of the epitaxial layer is related to factors such as the material of the contact layer and the annealing temperature of the annealing process.

[0057] In some embodiments of the present application, the contact layer may include a metal material, and the first groove extends from the surface of the epitaxial layer facing away from the semiconductor substrate to the interior of the barrier layer. During the manufacturing process, a relatively high temperature annealing process may be used. For example, the annealing temperature may be in the range of 500°C to 1000°C. Due to the relatively high annealing temperature, the contact layer reacts with the epitaxial layer during the annealing process, and the metal elements in the contact layer can penetrate into the channel layer through the barrier layer, thereby forming a good and reliable ohmic contact.

[0058] In the case where the contact layer comprises a metal material, the first electrode may be arranged in the following manner.

[0059] Specifically, a portion of the contact layer is located within the first recess, while another portion protrudes from the surface of the epitaxial layer facing away from the semiconductor substrate. The contact layer also has a second recess on the surface facing away from the semiconductor substrate. The contact layer can contact the epitaxial layer at the inner wall of the first recess. This arrangement can increase the contact area between the contact layer and the epitaxial layer, thereby reducing the resistivity of the ohmic contact between the contact layer and the epitaxial layer. Exemplarily, the contact layer can include titanium (Ti) material, and the thickness of the contact layer can be in the range of 4nm to 20nm.

[0060] A portion of the metal isolation layer is located within the second groove, while another portion protrudes from the surface of the contact layer facing away from the semiconductor substrate. The metal isolation layer also has a third groove on the surface facing away from the semiconductor substrate. Providing the metal isolation layer on the surface of the contact layer prevents materials in the anti-oxidation metal layer from diffusing into the contact layer, thus preventing excessive metal elements in the anti-oxidation metal layer from diffusing downward and causing reliability issues in the semiconductor device. Specifically, the metal isolation layer can include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and the thickness of the metal isolation layer can be in the range of 20 nm to 100 nm. In one possible implementation, the first electrode may further include a first metal layer located between the contact layer and the metal isolation layer, with a portion of the first metal layer located within the second groove and another portion extending to an area of ​​the contact layer surface excluding the second groove. The first metal layer also has a groove on the side facing away from the semiconductor substrate. A portion of the metal isolation layer is located within the groove on the surface of the first metal layer and another portion extends to an area of ​​the first metal layer surface excluding the groove. Exemplarily, the first metal layer may include aluminum (Al) material, and the thickness of the first metal layer may be between 80 nm and 200 nm. During the annealing process, the first metal layer may diffuse downward, for example, may diffuse into the channel layer, and participate in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0061] A portion of the anti-oxidation metal layer is located in the third groove, and another portion protrudes from the surface of the metal isolation layer on the side facing away from the semiconductor substrate. The anti-oxidation metal layer can fill the third groove, and the surface of the anti-oxidation metal layer on the side facing away from the semiconductor substrate can be a flat surface. The thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400nm and greater than or equal to twice the thickness of the channel layer. In one possible implementation, the anti-oxidation metal layer may include: an inert metal material. For example, the anti-oxidation metal layer may include: an inert metal material such as gold (Au) or platinum (Pt). The inert metal material is not easily oxidized during the annealing process (annealing temperature is in the range of 200°C to 1000°C), so that the anti-oxidation metal layer can play a better role in isolating from air. And / or, the anti-oxidation metal layer may include: an alloy material with anti-oxidation properties. For example, the anti-oxidation metal layer may include titanium nitride (TiN) material. The anti-oxidation alloy material is not easily oxidized during annealing (annealing temperature is within the range of 200°C to 1000°C), and can also enable the anti-oxidation metal layer to effectively isolate the air. Of course, in some cases, the anti-oxidation metal layer may also be made of other anti-oxidation materials, which is not limited in this application.

[0062] In other embodiments of the present application, the contact layer may include a semiconductor doping layer and a second metal layer, and the first groove extends from the surface of the epitaxial layer facing away from the semiconductor substrate to the interior of the channel layer. During the manufacturing process, a lower temperature can be used for annealing. For example, the annealing temperature can be in the range of 200°C to 500°C. Since the bottom of the first groove is located inside the channel layer in the embodiment of the present application, the semiconductor doping layer in the contact layer can be in direct contact with the channel layer. Therefore, a good and reliable ohmic contact can be formed by using a lower annealing temperature.

[0063] In the case where the contact layer includes a semiconductor doping layer and a second metal layer, the first electrode may be arranged in the following manner.

[0064] Specifically, the semiconductor doping layer may include a semiconductor material doped with impurities. For example, the semiconductor doping layer may include a gallium nitride (GaN) material doped with a high concentration of N-type impurities. The semiconductor doping layer may fill the first groove. In one possible implementation, the surface of the semiconductor doping layer may be flush with the upper surface of the epitaxial layer, or the surface of the semiconductor doping layer may be slightly higher than the upper surface of the epitaxial layer. The second metal layer is located on the side of the semiconductor doping layer away from the semiconductor substrate. For example, the second metal layer may include titanium (Ti) material. The second metal layer may serve as a reactant for an ohmic contact reaction. By filling the semiconductor doping layer in the first groove of the epitaxial layer, the semiconductor doping layer may reduce the potential barrier between the epitaxial layer and the second metal layer, thereby facilitating the formation of an ohmic contact.

[0065] A metal isolation layer is provided on the side of the contact layer facing away from the semiconductor substrate. The metal isolation layer prevents materials in the anti-oxidation metal layer from diffusing into the contact layer, thus preventing excessive metal elements in the anti-oxidation metal layer from diffusing downward and causing reliability issues in the semiconductor device. In one possible implementation, the metal isolation layer may include platinum (Pt).

[0066] An anti-oxidation metal layer is provided on the side of the metal isolation layer facing away from the semiconductor substrate. The thickness of the anti-oxidation metal layer is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer. In one possible implementation, the anti-oxidation metal layer may include: an inert metal material, for example, the anti-oxidation metal layer may include: an inert metal material such as gold (Au) or platinum (Pt). The inert metal material is not easily oxidized during annealing (annealing temperature is in the range of 200°C to 1000°C), which can enable the anti-oxidation metal layer to effectively isolate the air. And / or, the anti-oxidation metal layer may include: an alloy material with anti-oxidation properties, for example, the anti-oxidation metal layer may include titanium nitride (TiN). The alloy material with anti-oxidation properties is not easily oxidized during annealing (annealing temperature is in the range of 200°C to 1000°C), which can also enable the anti-oxidation metal layer to effectively isolate the air. Of course, in some cases, the anti-oxidation metal layer may also be made of other anti-oxidation materials, which is not limited in this application.

[0067] In the case where the contact layer includes a metal material and the contact layer includes a semiconductor doping layer and a second metal layer, the first electrode may also be arranged in the following manner.

[0068] In one possible implementation, the outer edges of the anti-oxidation metal layer and the metal isolation layer in the first electrode are flush. In this way, the morphology of the first electrode can be improved, and the electrical performance of the semiconductor device can be improved. During the manufacturing process, the metal isolation layer and the anti-oxidation metal layer can be patterned using the same composition process to make the outer edges of the anti-oxidation metal layer and the metal isolation layer flush. In some embodiments of the present application, the first electrode may also include an etch barrier layer. In a specific setting, the edge of the etch barrier layer can also be set to be flush with the edge of the anti-oxidation metal layer. In this way, the morphology of the first electrode can be improved, and the electrical performance of the semiconductor device can be improved. During the manufacturing process, the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer can be patterned using the same composition process to make the outer edges of the metal isolation layer, the anti-oxidation metal layer and the etch barrier layer flush.

[0069] During the manufacturing process, the metal film layers of the first electrode can be deposited sequentially, and then the metal film layers can be patterned using a single patterning process to ensure that the outer edges of the metal film layers of the first electrode are aligned. Specifically, if the contact layer comprises a metal material, the contact layer, the first metal layer, the metal barrier layer, the anti-oxidation metal layer, and the etch barrier layer can be deposited on the entire surface, and then patterned using a single patterning process to ensure that the outer edges of the contact layer, the first metal layer, the metal barrier layer, the anti-oxidation metal layer, and the etch barrier layer of the first electrode are aligned. If the contact layer comprises a semiconductor doped layer and a second metal layer, the second metal layer, the metal barrier layer, the anti-oxidation metal layer, and the etch barrier layer can be deposited on the entire surface, and then patterned using a single patterning process to ensure that the outer edges of the second metal layer, the metal barrier layer, the anti-oxidation metal layer, and the etch barrier layer of the first electrode are aligned. It can be understood that in the embodiment of the present application, due to the level limitation of the manufacturing process, the outer edges of certain film layers in the first electrode are flush, which means that the outer edges of these film layers are basically flush within a certain error range.

[0070] In a third aspect, embodiments of the present application further provide a power amplifier chip. The power amplifier chip in the embodiments of the present application may include any of the semiconductor devices described in the second aspect, or may include a semiconductor device fabricated using the fabrication method described in the first aspect. Because the ohmic contacts of the semiconductor devices in the embodiments of the present application have low resistivity, the power amplifier chip including the semiconductor devices has excellent electrical performance.

[0071] Fourthly, embodiments of the present application further provide an electronic device. The electronic device in the embodiments of the present application may include the aforementioned power amplifier chip, and the electronic device is a portable terminal device. For example, the electronic device in the embodiments of the present application may be a mobile phone, a tablet computer, a laptop computer, or the like. Because the power amplifier chip in the embodiments of the present application has excellent electrical performance, the electronic device including the power amplifier chip also has excellent performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a schematic diagram of a manufacturing process of a semiconductor device in the related art;

[0073] FIG2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0074] Figures 3 to 23 are schematic structural diagrams corresponding to the steps of the manufacturing method provided in the embodiments of the present application;

[0075] FIG24 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0076] FIG25 is a schematic diagram comparing the technical solution of the related art and the technical solution of the present application.

[0077] Reference numerals:

[0078] 101, 10-semiconductor substrate; 102-epitaxial layer; 103-stacked metal; 11-epitaxial layer; 111-channel layer; 112-barrier layer; 113-cap layer; 114-nucleation layer; 115-transition layer; 116-buffer layer; 12-first electrode; 121-contact layer; 121a-semiconductor doping layer; 121b-second metal layer; 122-metal isolation layer; 123-anti-oxidation metal layer; 124-etching barrier layer; 125-first metal layer; 13-gate contact metal layer; 14-gate interconnection structure; 15-interconnection structure; 301-photoresist layer; 302-passivation layer; 303-dielectric layer; 304-hard mask layer; M1-surface metal layer; M2-thickened metal layer; U1-first groove; U2-second groove; U3-third groove; T-fourth groove. DETAILED DESCRIPTION

[0079] In order to reduce the resistivity of the ohmic contact of a semiconductor device, embodiments of the present application provide a semiconductor device, a method for manufacturing the same, a power amplifier chip, and an electronic device. The semiconductor device in the embodiments of the present application can be a high electron mobility transistor device. For example, the semiconductor device in the embodiments of the present application can be a GaN / GaAs-based high electron mobility transistor device. Of course, in some cases, the semiconductor device in the embodiments of the present application can also be other types of transistor devices, which is not limited in this application.

[0080] The semiconductor device in the embodiment of the present application can be applied to a radio frequency application device, and the drain supply voltage of the radio frequency application device can be in the range of 5V to 48V. The radio frequency application device in the embodiment of the present application can be a terminal radio frequency power amplifier device, a base station radio frequency power amplifier device, etc. For example, the semiconductor device in the embodiment of the present application can be applied to a power amplifier chip, and the power amplifier chip can be applied to various types of electronic devices, for example, terminal portable devices such as mobile phones, tablet computers, and laptop computers.

[0081] In order to make the purpose, technical solutions and advantages of this application clearer, this application will be further described in detail below with reference to the accompanying drawings.

[0082] It should be noted that the drawings in this application are only used to illustrate relative positional relationships and do not represent true proportions. The same reference numerals in the drawings in this application represent the same or similar structures, and thus their repeated descriptions will be omitted.

[0083] Words expressing position and direction described in this application, such as the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., are all explained based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on this application. Changes can also be made as needed, and all changes are included in the scope of protection of this application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0084] FIG1 is a schematic diagram of the manufacturing process of a semiconductor device in the related art. As shown in (1) in FIG1 , after forming an epitaxial layer 102 on a semiconductor substrate 101, a laminated metal 103 is deposited on the surface of the epitaxial layer 102. The surface metal layer M1 of the laminated metal 103 is generally made of gold (Au) material, and the thickness of the surface metal layer M1 is about 150 nm. The total thickness of the laminated metal 103 is within 300 nm. Then, an ohmic contact can be formed at the interface between the epitaxial layer 102 and the laminated metal 103 through annealing. As shown in (2) in FIG1 , after the annealing, the laminated metal 103 is thickened a second time, that is, a thickened metal layer M2 is formed on the surface metal layer M1. Because the surface metal layer M1 of the metal stack 103 formed before the annealing process is relatively thin, the surface metal layer M1 is insufficiently shielded from air during the annealing process, causing impurities such as oxygen (O) to diffuse downward, easily forming voids in the ohmic contact area. This results in a higher resistivity of the ohmic contact, thereby affecting the performance of the semiconductor device, such as its output power and efficiency.

[0085] Based on this, in order to reduce the resistivity of the ohmic contact of the semiconductor device, an embodiment of the present application provides a method for manufacturing a semiconductor device. FIG2 is a flow chart of the method for manufacturing a semiconductor device provided in an embodiment of the present application. As shown in FIG2 , the method for manufacturing a semiconductor device provided in an embodiment of the present application may include:

[0086] S201, forming an epitaxial layer on a semiconductor substrate, and patterning the epitaxial layer to form a first groove on a surface of the epitaxial layer facing away from the semiconductor substrate; wherein the epitaxial layer includes: a channel layer;

[0087] S202, forming a first electrode having a portion located within the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate; wherein the first electrode is a source electrode or a drain electrode, and comprises: a contact layer, a metal isolation layer, and an anti-oxidation metal layer; the contact layer contacts the epitaxial layer on an inner wall of the first groove; the anti-oxidation metal layer is located on a side of the contact layer facing away from the semiconductor substrate; and the metal isolation layer is located between the contact layer and the anti-oxidation metal layer; the thickness of the anti-oxidation metal layer protruding from the surface of the metal isolation layer facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer;

[0088] S203 , performing annealing treatment on the structure after the anti-oxidation metal layer is formed to obtain a semiconductor device.

[0089] In the method for manufacturing a semiconductor device provided by an embodiment of the present application, during the process of manufacturing the first electrode, the thickness of the anti-oxidation metal layer formed is greater than or equal to 400nm and greater than or equal to twice the thickness of the channel layer, that is, a thicker anti-oxidation metal layer is formed in the first electrode, and then the structure after the anti-oxidation metal layer is formed is annealed. In this way, during the annealing process, the thicker anti-oxidation metal layer can fully isolate the air, prevent the air from reacting with the metal in the first electrode, and avoid the formation of holes in the ohmic contact area, so that the contact layer and the epitaxial layer can react well, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. Moreover, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer can diffuse into the epitaxial layer to participate in the ohmic contact reaction, that is, the metal elements in the anti-oxidation metal layer can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, compared with the manufacturing process of the related art, the manufacturing method provided by the embodiment of the present application can also save the subsequent metal thickening process, avoid multiple metal deposition processes, and avoid stability problems caused by interface exposure. It should be explained that ohmic contact means that when the first electrode contacts the epitaxial layer, a very small contact barrier is formed at the contact interface, or no contact barrier is formed at the contact interface. In other words, the contact resistivity of ohmic contact is low.

[0090] Moreover, in the method for manufacturing a semiconductor device provided in an embodiment of the present application, a first groove is formed on the surface of the epitaxial layer facing away from the semiconductor substrate, and a portion of the subsequently formed first electrode is located within the first groove. This can increase the contact area between the contact layer in the first electrode and the epitaxial layer, thereby further reducing the resistivity of the ohmic contact between the first electrode and the epitaxial layer.

[0091] Figures 3 to 23 are structural schematic diagrams corresponding to each step in the manufacturing method provided in the embodiment of the present application. The manufacturing method of the semiconductor device provided in the embodiment of the present application is described in detail below in conjunction with the accompanying drawings.

[0092] As shown in FIG3 , the semiconductor substrate 10 in the embodiment of the present application may be made of a high-resistance semiconductor material. For example, the semiconductor substrate 10 may include a Si material with a resistivity greater than 5000 Ω.cm. For example, the semiconductor substrate 10 may include a Si material with a resistivity greater than 1e 4 Ω.cm Si material; alternatively, the semiconductor substrate 10 may include a resistivity greater than 1e 6 Ω.cm; or, the semiconductor substrate 10 may include a GaN material with a resistivity greater than 1e4 Ω.cm; or, the semiconductor substrate 10 may include a sapphire material with a resistivity greater than 1e11 Ω.cm. Of course, the semiconductor substrate 10 in the embodiment of the present application may also be made of other high-resistance semiconductor materials, which is not limited in this application.

[0093] In the above-mentioned step S201, forming the epitaxial layer 11 on the semiconductor substrate 10 may specifically include: forming a channel layer 111 with a thickness in the range of 100nm to 400nm on the semiconductor substrate 10. For example, the channel layer 111 may be formed of an undoped gallium nitride (GaN) material. Then, forming a barrier layer 112 with a thickness in the range of 4nm to 35nm on the channel layer 111. For example, the barrier layer 112 with a thickness in the range of 10nm to 35nm may be formed of an aluminum gallium nitride (AlGaN) material. For another example, the barrier layer 112 with a thickness in the range of 4nm to 10nm may be formed of aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN) material.

[0094] In one possible implementation, in the above step S201, an epitaxial layer 11 is formed on the semiconductor substrate 10, and the step S201 may also include: forming a cap layer 113 with a thickness in the range of 1 nm to 5 nm on the barrier layer 112. For example, the cap layer 113 can be formed by materials such as gallium nitride (GaN) and in-situ silicon nitride (SiN).

[0095] In a possible implementation, in the above step S201, an epitaxial layer 11 is formed on the semiconductor substrate 10, and the step S201 may further include: before forming the channel layer 111, a nucleation layer 114, a transition layer 115, and a buffer layer 116 are sequentially formed on the semiconductor substrate 10. Specifically, an aluminum nitride (AlN) material may be used to form a nucleation layer 114 with a thickness in the range of 100nm to 300nm. An aluminum gallium nitride (AlGaN) material may be used to form a transition layer 115 with a thickness in the range of 100nm to 500nm. The buffer layer 116 may be made of a high-resistance semiconductor material, for example, a high-resistance gallium nitride (GaN) material may be used to form the buffer layer 116. The buffer layer 116 may be doped with a concentration greater than 1e 17 ~2e19 Alternatively, the buffer layer 116 may be doped with a concentration greater than 1e 17 The thickness of the buffer layer 116 may be in the range of 0.5 μm to 2 μm.

[0096] In a possible implementation, each film layer in the epitaxial layer 11 may be formed by an epitaxial growth process such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or atomic layer deposition (ALD).

[0097] In step S201, the epitaxial layer 11 may be patterned to form a first groove (not shown in FIG3 ) on the surface of the epitaxial layer 11. In specific implementations, the depth of the first groove is related to factors such as the material of the contact layer to be formed subsequently and the annealing temperature of the subsequent annealing process, which will be described in detail below with reference to the accompanying drawings.

[0098] In some embodiments of the present application, the contact layer may be made of a metal material and annealed at a relatively high temperature. For example, the annealing temperature may be in the range of 500°C to 1000°C. The bottom of the first recess may be located inside the barrier layer. The epitaxial layer may be patterned using the following methods:

[0099] As shown in FIG4 , a photoresist layer 301 is formed on the surface of the epitaxial layer 11, and the photoresist layer 301 is subjected to processes such as photolithography and development to pattern the photoresist layer 301 so that the pattern of the photoresist layer 301 covers the area outside the first groove to be formed and exposes the area of ​​the first groove to be formed. As shown in FIG5 , the epitaxial layer 11 is etched using the pattern of the photoresist layer 301 as a shield. The direction indicated by the arrow in FIG5 can be the etching direction. For example, an inductively coupled plasma (ICP) etching process can be used to etch the epitaxial layer 11. Specifically, an inductively coupled plasma process containing a Cl-based gas can be used to etch the epitaxial layer 11. During the etching process, the etching depth can be controlled by adjusting parameters such as the time and power of the etching process, thereby forming a first groove U1 extending from the surface of the epitaxial layer 11 away from the semiconductor substrate 10 to the interior of the barrier layer 112.

[0100] As shown in FIG6 , in the case where the contact layer 121 is made of metal material, the above step S202 may specifically include:

[0101] A contact layer 121 is formed using a metal material, with a portion of the contact layer 121 located within the first recess U1 and another portion extending to the surface of the epitaxial layer 11 outside the first recess U1. A second recess U2 is formed on the surface of the contact layer 121 facing away from the semiconductor substrate 10. The contact layer 121 can contact the epitaxial layer 11 at the inner wall of the first recess U1. This arrangement increases the contact area between the contact layer 121 and the epitaxial layer 11, thereby reducing the resistivity of the ohmic contact between the contact layer 121 and the epitaxial layer 11. For example, the contact layer 121 can be made of titanium (Ti) and have a thickness ranging from 4 nm to 20 nm.

[0102] A metal isolation layer 122 is formed using a metal material. A portion of the metal isolation layer 122 is positioned within the second recess U2, while another portion extends to the area above the contact layer 121, excluding the second recess U2. A third recess U3 is formed on the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10. Forming the metal isolation layer 122 on the surface of the contact layer 121 prevents material from the subsequently formed anti-oxidation metal layer 123 from diffusing into the contact layer 121, thus preventing excessive downward diffusion of metal elements from the anti-oxidation metal layer 123, which could cause reliability issues in the semiconductor device. Specifically, the metal isolation layer 122 can include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and can have a thickness ranging from 20 nm to 100 nm. In one possible implementation, after forming the contact layer 121 and before forming the metal isolation layer 122, the process may further include: forming a first metal layer 125 on the surface of the contact layer 121, wherein a portion of the first metal layer 125 is located within the second groove U2, and another portion extends to the surface of the contact layer 121 other than the second groove U2, and a groove is also formed on the side of the first metal layer 125 facing away from the semiconductor substrate 10. Thereafter, the metal isolation layer 122 may be formed on the surface of the first metal layer 125, wherein a portion of the metal isolation layer 122 is located within the groove on the surface of the first metal layer 125, and another portion extends to the surface of the first metal layer 125 other than the groove. For example, the first metal layer 125 may include aluminum (Al) material, and the thickness of the first metal layer 125 may be between 80 nm and 200 nm. During the subsequent annealing process, the first metal layer 125 may diffuse downward, for example, may diffuse into the channel layer 111, participate in the ohmic contact reaction, facilitate the formation of a good and reliable ohmic contact, and further reduce the resistivity of the ohmic contact.

[0103] The anti-oxidation metal layer 123 is formed of a metal material, with a portion of the anti-oxidation metal layer 123 positioned within the third recess U3 and another portion protruding from the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10. In the embodiment of the present application, a relatively thick anti-oxidation metal layer 123 is formed before the annealing process. The anti-oxidation metal layer 123 can completely fill the third recess U3. Furthermore, the surface of the anti-oxidation metal layer 123 facing away from the semiconductor substrate 10 can be flat. The thickness of the anti-oxidation metal layer 123 protruding from the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In one possible implementation, the anti-oxidation metal layer 123 can be made of inert metal materials such as gold (Au) and platinum (Pt) that are not easily oxidized during annealing (annealing temperature is in the range of 200°C to 1000°C); and / or, the anti-oxidation metal layer 123 can be made of alloy materials with anti-oxidation properties, for example, titanium nitride (TiN) material with good conductive properties and good stability can be used.

[0104] Furthermore, to prevent the subsequent etching process of the dielectric layer from damaging the anti-oxidation metal layer 123, step S202 may further include forming an etch stop layer 124 on the anti-oxidation metal layer 123. For example, a metal material such as Ti or Ni having a slow etching characteristic of F-based reactive ion etching (RIE) may be used, and the thickness of the etch stop layer 124 may be greater than or equal to 20 nm.

[0105] As shown in Figure 7, after the etching stop layer 124 is formed, the above-mentioned step S202 may also include: patterning the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etching stop layer 124, removing the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etching stop layer 124 in the area outside the first groove U1, and then removing the photoresist layer to obtain the first electrode 12, that is, the pattern of the first electrode 12 is consistent with the area of ​​the first groove U1. Furthermore, the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etch barrier layer 124 can be patterned using the same patterning process. In this way, in the first electrode 12 manufactured, the outer edges formed by the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etch barrier layer 124 are flush, which can make the morphology of the first electrode 12 better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiment of the present application, due to the level limitation of the manufacturing process, the outer edges of certain film layers in the first electrode 12 are flush, which means that the outer edges of these film layers are basically flush within a certain error range. In the embodiment of the present application, the semiconductor device may include at least one transistor, each transistor may include a source, a drain and a gate, and the first electrode 12 in the embodiment of the present application may be a source or a drain.

[0106] Continuing with reference to FIG7 , in the case where the contact layer 121 is made of a metal material, the above-mentioned step S203 may specifically include: annealing the structure after the anti-oxidation metal layer 123 is formed at a temperature in the range of 500° C. to 1000° C. Due to the high temperature of the annealing treatment, during the annealing process, the contact layer 121 reacts with the epitaxial layer 11, and the metal elements in the contact layer 121 can penetrate into the channel layer 111 through the barrier layer 112, thereby forming a good and reliable ohmic contact. Specifically, the annealing treatment can be performed using a rapid thermal processing (RTP) process, laser annealing, or other processes. Moreover, during the annealing process, the metal elements in the anti-oxidation metal layer 123 and the first metal layer 125 can also diffuse into the channel layer 111 and participate in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact.

[0107] In the case where the contact layer 121 is made of metal material, after the above step S203, the following step may be further performed: forming an interconnection structure in contact with the etch stop layer. The specific process is as follows:

[0108] As shown in FIG8 , a passivation layer 302 is formed to cover the first electrode 12 . For example, the passivation layer 302 may be made of silicon nitride (SiN) material.

[0109] As shown in FIG. 9 , the passivation layer 302 is patterned to form a fourth groove T penetrating the passivation layer 302 in the region where the gate is to be formed. The bottom surface of the fourth groove T is a portion of the surface of the epitaxial layer 11 .

[0110] As shown in Figure 10, a gate contact metal layer 13 is formed on the sidewalls and bottom surface of the fourth groove T of the passivation layer 302, and a metal material is filled in the fourth groove T to form a gate interconnection structure 14. The gate interconnection structure 14 fills the portion of the fourth groove T except the gate contact metal layer 13, and protrudes from the surface of the passivation layer 302. For example, the gate contact metal layer 13 can be made of a metal material such as nickel (Ni) or tungsten (W), and the gate contact metal layer 13 can serve as the gate of the transistor. The gate contact metal layer 13 can contact the epitaxial layer 11 to form a Schottky contact. It should be explained that Schottky contact refers to the case where the gate contact metal layer 13 and the epitaxial layer 11 are in contact, and the energy band of the epitaxial layer 11 at the contact interface is bent to form a contact barrier (which can be called a Schottky barrier). In a possible implementation, the gate interconnection structure 14 can be made of gold (Au) material. The gate interconnection structure 14 can serve to lead out the gate contact metal layer 13. In addition, the gate interconnection structure 14 can also have an anti-oxidation effect and reduce the gate resistance.

[0111] As shown in Figure 11, a dielectric layer 303 is formed to cover the gate interconnect structure 14. The dielectric layer 303 covers the passivation layer 302 in the area where the first electrode 12 is located. For example, the dielectric layer 303 can be made of silicon nitride (SiN) material.

[0112] As shown in FIG12 , an etching process is used to pattern the dielectric layer 303 and the passivation layer 302, thereby exposing the first electrode 12. Because the surface of the anti-oxidation metal layer 123 includes an etch stop layer 124, the etch stop layer 124 protects the anti-oxidation metal layer 123 during the etching process, preventing the anti-oxidation metal layer 123 from being damaged during the etching process. In a specific implementation, the upper surface of the etch stop layer 124 can be a flat surface, or the upper surface of the etch stop layer 124 can be etched during the etching process, i.e., a groove can be formed on the upper surface of the etch stop layer 124.

[0113] As shown in FIG13 , the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 are filled with a metal material, for example, gold (Au), to form an interconnect structure 15 that contacts and connects to the etch stop layer 124. This electrically connects the interconnect structure 15 to the first electrode 12. The interconnect structure 15 is used to lead out the first electrode 12. In a direction parallel to the surface of the semiconductor substrate 10, the width of the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 is smaller than the width of the anti-oxidation metal layer 123. Therefore, the width of the formed interconnect structure 15 is smaller than the width of the anti-oxidation metal layer 123.

[0114] In other embodiments of the present application, the contact layer includes a semiconductor doping layer and a second metal layer, and is annealed at a relatively low temperature. For example, the annealing temperature may be in the range of 200°C to 500°C. The bottom of the first recess may be located inside the channel layer. The epitaxial layer may be patterned using the following methods:

[0115] As shown in Figure 14, a hard mask layer 304 is formed on the surface of the epitaxial layer 11. In a possible implementation, the hard mask layer 304 can be made of silicon oxide (SiOx) material or silicon nitride (SiNx) material.

[0116] As shown in FIG15 , the hard mask layer 304 is patterned so that the pattern of the hard mask layer 304 covers the area outside the first groove U1 to be formed, exposing the area of ​​the first groove U1 to be formed. Using the pattern of the hard mask layer 304 as a shield, the epitaxial layer 11 is etched. The direction indicated by the arrow in FIG15 can be the etching direction. For example, an inductively coupled plasma (ICP) etching process can be used to etch the epitaxial layer 11. Specifically, an inductively coupled plasma process containing a Cl-based gas can be used to etch the epitaxial layer 11. During the etching process, the etching depth can be controlled by adjusting parameters such as the etching process time and power, thereby forming a first groove U1 extending from the surface of the epitaxial layer 11 on the side away from the semiconductor substrate 10 to the interior of the channel layer 111.

[0117] In the case where the contact layer includes a semiconductor doped layer and a second metal layer, the above step S202 may specifically include:

[0118] As shown in FIG16 , a semiconductor material doped with impurities is used to form a semiconductor doping layer 121a, so that the semiconductor doping layer 121a completely fills the first recess U1. In one possible implementation, the semiconductor doping layer 121a can be made of a gallium nitride (GaN) material doped with a high concentration of N-type impurities. In a specific implementation, in order to ensure that the semiconductor doping layer 121a formed by the epitaxial process can completely fill the first recess U1, the formed semiconductor doping layer 121a is generally slightly higher than the surface of the epitaxial layer (i.e., the surface of the cap layer 113).

[0119] Afterwards, the hard mask layer 304 on the surface of the epitaxial layer (ie, the surface of the cap layer 113 ) is removed. For example, a wet etching process may be used to remove the hard mask layer 304 to obtain the structure shown in FIG. 17 .

[0120] As shown in FIG18 , a second metal layer 121b is formed on the semiconductor doped layer 121a using a metal material. The second metal layer 121b can serve as a reactant for an ohmic contact reaction. By forming the semiconductor doped layer 121a within the first recess U1 of the epitaxial layer, the semiconductor doped layer 121a can reduce the potential barrier between the epitaxial layer and the second metal layer 121b, thereby facilitating the formation of an ohmic contact. For example, the second metal layer 121b can include titanium (Ti) material.

[0121] Subsequently, a metal isolation layer 122 is formed on the surface of the second metal layer 121b, that is, on the surface of the contact layer 121. Forming the metal isolation layer 122 on the surface of the contact layer 121 prevents the material in the subsequently formed anti-oxidation metal layer 123 from diffusing into the contact layer 121, thus preventing excessive metal elements in the anti-oxidation metal layer 123 from diffusing downward and causing reliability issues in the semiconductor device. In one possible implementation, the metal isolation layer 122 may include platinum (Pt).

[0122] Then, an anti-oxidation metal layer 123 is formed on the metal isolation layer 122 using a metal material. The thickness of the formed anti-oxidation metal layer 123 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In one possible implementation, the anti-oxidation metal layer 123 can be formed using an inert metal material such as gold (Au) or platinum (Pt) that is not easily oxidized during an annealing process (annealing temperature is within the range of 200°C to 1000°C); and / or the anti-oxidation metal layer 123 can be formed using an alloy material having anti-oxidation properties, for example, TiN material with good conductivity and good stability.

[0123] Furthermore, to prevent the subsequent etching process of the dielectric layer from damaging the anti-oxidation metal layer 123, step S202 may further include forming an etch stop layer 124 on the anti-oxidation metal layer 123. For example, a metal material such as Ti or Ni having a slow etching characteristic of F-based reactive ion etching (RIE) may be used, and the thickness of the etch stop layer 124 may be greater than or equal to 20 nm.

[0124] During the manufacturing process, the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etching barrier layer 124 can be deposited on the entire surface. Then, the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etching barrier layer 124 are patterned to remove the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123 and the etching barrier layer 124 in the area outside the first groove U1 to obtain the first electrode 12. That is, the pattern of the first electrode 12 is consistent with the area of ​​the first groove U1. Furthermore, the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etching stopper layer 124 can be patterned using the same patterning process. In this way, in the first electrode 12 manufactured, the outer edges formed by the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etching stopper layer 124 are flush, which can make the morphology of the first electrode 12 better and improve the electrical performance of the semiconductor device. It can be understood that in the embodiment of the present application, due to the level limitation of the manufacturing process, the outer edges of certain film layers in the first electrode 12 are flush, which means that the outer edges of these film layers are basically flush within a certain error range. In the embodiment of the present application, the semiconductor device may include at least one transistor, each transistor may include a source, a drain, and a gate, and the first electrode 12 in the embodiment of the present application may be a source or a drain.

[0125] Continuing with FIG. 18 , in the case where the contact layer includes a semiconductor doped layer and a second metal layer, step S203 may specifically include: performing an annealing treatment on the structure after forming the anti-oxidation metal layer 123 at a temperature in the range of 200° C. to 500° C. Since, in the embodiment of the present application, the bottom of the first recess U1 is located within the channel layer 111, the semiconductor doped layer 121a in the contact layer 121 can be in direct contact with the channel layer 111. Therefore, a relatively low annealing temperature can be used to form a good and reliable ohmic contact. Specifically, the annealing treatment may be performed using a rapid thermal processing (RTP) process, laser annealing, or other processes.

[0126] In the case where the contact layer includes a semiconductor doped layer and a second metal layer, after the above step S203, the process may further include: forming an interconnection structure in contact with the etch stop layer. The specific process is as follows:

[0127] As shown in FIG. 19 , a passivation layer 302 is formed to cover the first electrode 12 . For example, the passivation layer 302 may be made of silicon nitride (SiN) material.

[0128] As shown in FIG. 20 , the passivation layer 302 is patterned to form a fourth groove T penetrating the passivation layer 302 in the region where the gate is to be formed. The bottom surface of the fourth groove T is a portion of the surface of the epitaxial layer 11 .

[0129] As shown in Figure 21, a gate contact metal layer 13 is formed on the sidewalls and bottom surface of the fourth groove T of the passivation layer 302, and a metal material is filled in the fourth groove T to form a gate interconnection structure 14. The gate interconnection structure 14 fills the portion of the fourth groove T except the gate contact metal layer 13, and protrudes from the surface of the passivation layer 302. For example, the gate contact metal layer 13 can be made of a metal material such as nickel (Ni) or tungsten (W), and the gate contact metal layer 13 can serve as the gate of the transistor. The gate contact metal layer 13 can contact the epitaxial layer 11 to form a Schottky contact. It should be explained that the Schottky contact refers to the case where the gate contact metal layer 13 and the epitaxial layer 11 are in contact, and the energy band of the epitaxial layer 11 at the contact interface is bent to form a contact barrier (which can be called a Schottky barrier). In a possible implementation, the gate interconnection structure 14 can be made of gold (Au) material. The gate interconnection structure 14 can serve to lead out the gate contact metal layer 13. In addition, the gate interconnection structure 14 can also have an anti-oxidation effect and reduce the gate resistance.

[0130] As shown in FIG22 , a dielectric layer 303 is formed covering the gate interconnect structure 14, and the dielectric layer 303 covers the passivation layer 302 in the area where the first electrode 12 is located. For example, the dielectric layer 303 can be made of silicon nitride (SiN) material. Then, an etching process is used to pattern the dielectric layer 303 and the passivation layer 302, thereby exposing the first electrode 12. Since the surface of the anti-oxidation metal layer 123 has an etch barrier layer 124, during the etching process, the etch barrier layer 124 can protect the anti-oxidation metal layer 123 and prevent the anti-oxidation metal layer 123 from being damaged during the etching process. In a specific implementation, the upper surface of the etch barrier layer 124 can be a flat surface, or, during the etching process, the upper surface of the etch barrier layer 124 may be etched, that is, a groove may be formed on the upper surface of the etch barrier layer 124.

[0131] As shown in FIG23 , the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 are filled with a metal material, for example, gold (Au), to form an interconnect structure 15 that contacts and connects to the etch stop layer 124. This electrically connects the interconnect structure 15 to the first electrode 12. The interconnect structure 15 is used to lead out the first electrode 12. In a direction parallel to the surface of the semiconductor substrate 10, the width of the grooves on the surfaces of the passivation layer 302 and the dielectric layer 303 is smaller than the width of the anti-oxidation metal layer 123. Therefore, the width of the formed interconnect structure 15 is smaller than the width of the anti-oxidation metal layer 123.

[0132] Based on the same technical concept, an embodiment of the present application also provides a semiconductor device. FIG24 is a schematic structural diagram of the semiconductor device provided by the embodiment of the present application. As shown in FIG24 , the semiconductor device provided by the embodiment of the present application may include: a semiconductor substrate 10, an epitaxial layer 11, and a first electrode 12. In the embodiment of the present application, the semiconductor device may include at least one transistor, each of which may include a source, a drain, and a gate. The first electrode 12 in the embodiment of the present application may be either a source or a drain. The epitaxial layer 11 is located on the semiconductor substrate 10. A first recess U1 is defined on the surface of the epitaxial layer 11 facing away from the semiconductor substrate 10. A portion of the first electrode 12 is located within the first recess U1, while another portion protrudes from the surface of the epitaxial layer 11 facing away from the semiconductor substrate 10. The first electrode 12 may include: a contact layer 121, a metal isolation layer 122, and an anti-oxidation metal layer 123. The contact layer 121 contacts the epitaxial layer 11 on the inner wall of the first recess U1. The anti-oxidation metal layer 123 is located on the side of the contact layer 121 facing away from the semiconductor substrate 10. The metal isolation layer 122 is located between the contact layer 121 and the anti-oxidation metal layer 123. The thickness of the anti-oxidation metal layer 123 protruding from the surface of the metal isolation layer 122 facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111 .

[0133] In the semiconductor device provided in the embodiment of the present application, the first electrode 12 includes a contact layer 121, a metal isolation layer 122, and an anti-oxidation metal layer 123. The thickness of the anti-oxidation metal layer 123, which protrudes from the surface of the metal isolation layer 122 on the side facing away from the semiconductor substrate 10, is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In the embodiment of the present application, the anti-oxidation metal layer 123 is relatively thick. During the annealing process, the thick anti-oxidation metal layer 123 can fully isolate the air, preventing air from reacting with the metal in the first electrode 12 and avoiding the formation of holes in the ohmic contact area. This allows the contact layer 121 to react well with the epitaxial layer 11, thereby forming a good and reliable ohmic contact and reducing the resistivity of the ohmic contact. Furthermore, during the annealing process, a small amount of metal elements in the anti-oxidation metal layer 123 can diffuse into the epitaxial layer 11 and participate in the ohmic contact reaction. In other words, the metal elements in the anti-oxidation metal layer 123 can also serve as reactants in the ohmic contact reaction, which is conducive to forming a good and reliable ohmic contact and further reducing the resistivity of the ohmic contact. In addition, a first recess U1 is provided on the surface of the epitaxial layer 11 facing away from the semiconductor substrate 10. A portion of the first electrode 12 is located within the first recess U1, and the contact layer 121 contacts the epitaxial layer 11 along the inner wall of the first recess U1. This increases the contact area between the contact layer 121 and the epitaxial layer 11, thereby further reducing the resistivity of the ohmic contact between the first electrode 12 and the epitaxial layer 11.

[0134] In one possible implementation, the semiconductor device provided in the embodiment of the present application can be manufactured using the above-mentioned manufacturing method. Of course, in some cases, the semiconductor device in the embodiment of the present application can also be manufactured using other manufacturing methods, which is not limited in this application.

[0135] In the embodiment of the present application, the semiconductor substrate 10 may include a high-resistance semiconductor material. For example, the semiconductor substrate 10 may include a Si material with a resistivity greater than 5000 Ω.cm. For example, the semiconductor substrate 10 may include a Si material with a resistivity greater than 1e 4 Ω.cm Si material; alternatively, the semiconductor substrate 10 may include a resistivity greater than 1e 6 The semiconductor substrate 10 may include a SiC material with a resistivity greater than 1e4 Ω.cm; or, the semiconductor substrate 10 may include a GaN material with a resistivity greater than 1e4 Ω.cm; or, the semiconductor substrate 10 may include a sapphire material with a resistivity greater than 1e11 Ω.cm. Of course, the semiconductor substrate 10 in the embodiment of the present application may also include other high-resistance semiconductor materials, which is not limited in this application.

[0136] In one possible implementation, the epitaxial layer 11 may include: a channel layer 111 and a barrier layer 112, wherein the barrier layer 112 is located on the side of the channel layer 111 facing away from the semiconductor substrate 10. For example, the channel layer 111 may include undoped gallium nitride (GaN) material, and the thickness of the channel layer 111 may be in the range of 100 nm to 400 nm. The barrier layer 112 may include aluminum gallium nitride (AlGaN) material, aluminum nitride (AlN), indium aluminum nitride (InAlN), or indium gallium nitride (InGaN), and the thickness of the barrier layer 112 may be in the range of 4 nm to 35 nm. For example, when the barrier layer 112 includes aluminum gallium nitride (AlGaN) material, the thickness of the barrier layer 112 can be in the range of 10nm to 35nm. For example, when the barrier layer 112 includes materials such as aluminum nitride (AlN), indium aluminum nitride (InAlN) or indium gallium nitride (InGaN), the thickness of the barrier layer 112 can be in the range of 4nm to 10nm.

[0137] In addition, the epitaxial layer 11 may further include a cap layer 113 located on a side of the barrier layer 112 facing away from the semiconductor substrate 10, and the first recess U1 penetrates the cap layer 113 in a direction perpendicular to the surface of the semiconductor substrate 10. For example, the cap layer 113 may include materials such as gallium nitride (GaN) and in-situ silicon nitride (SiN), and the thickness of the cap layer 113 may be in the range of 1 nm to 5 nm.

[0138] In a specific configuration, the epitaxial layer 11 may further include: a nucleation layer 114 located between the semiconductor substrate 10 and the channel layer 111, a transition layer 115 located between the nucleation layer 114 and the channel layer 111, and a buffer layer 116 between the transition layer 115 and the channel layer 111. Specifically, the nucleation layer 114 may include an aluminum nitride (AlN) material, and the thickness of the nucleation layer 114 may be in the range of 100nm to 300nm. The transition layer 115 may include an aluminum gallium nitride (AlGaN) material, and the thickness of the transition layer 115 may be in the range of 100nm to 500nm. The buffer layer 116 may include a high-resistance gallium nitride (GaN) material, and the buffer layer 116 may be doped with a concentration greater than 1e 17 ~2e 19 Alternatively, the buffer layer 116 may be doped with a concentration greater than 1e 17 The thickness of the buffer layer 116 may be in the range of 0.5 μm to 2 μm.

[0139] In one possible implementation, the first electrode 12 may further include: an etch stop layer 124 located on the side of the anti-oxidation metal layer 123 facing away from the semiconductor substrate 10, and the etch stop layer 124 may include a metal material. For example, the etch stop layer 124 may include titanium (Ti) or nickel (Ni), and the thickness of the etch stop layer 124 may be greater than or equal to 20 nm. The etch stop layer 124 may protect the anti-oxidation metal layer 123 and prevent the anti-oxidation metal layer 123 from being damaged by the etching process of the dielectric layer. During the etching process of the dielectric layer, the upper surface of the etch stop layer 124 may be etched, resulting in a groove on the upper surface of the etch stop layer 124. Of course, in some cases, the upper surface of the etch stop layer 124 may also be a flat surface.

[0140] In one possible implementation, the semiconductor device provided in an embodiment of the present application may further include: an interconnect structure 15 located on a side of the first electrode 12 facing away from the semiconductor substrate 10, the interconnect structure 15 being in contact with the etch stop layer 124 so as to electrically connect the interconnect structure 15 to the first electrode 12, and the interconnect structure 15 being used to lead out the first electrode 12. For example, the interconnect structure 15 may include a metal material such as gold (Au). In a specific configuration, the width of the interconnect structure 15 may be smaller than the width of the anti-oxidation metal layer 123 in a direction parallel to the surface of the semiconductor substrate 10.

[0141] In addition, the semiconductor device in the embodiment of the present application may further include: a passivation layer 302, a gate contact metal layer 13 and a gate interconnection structure 14. For example, the passivation layer 302 may include a silicon nitride (SiN) material. The passivation layer 302 has a fourth groove T, which penetrates the passivation layer 302 in a direction perpendicular to the surface of the semiconductor substrate 10, and the bottom surface of the fourth groove T is a portion of the surface of the epitaxial layer 11. The gate contact metal layer 13 covers the sidewalls and bottom surface of the fourth groove T, and the gate interconnection structure 14 fills the portion of the fourth groove T except the gate contact metal layer 13, and protrudes from the surface of the passivation layer 302. For example, the gate contact metal layer 13 may include a metal material such as nickel (Ni) or tungsten (W). The gate contact metal layer 13 can serve as the gate of the transistor, and the gate contact metal layer 13 can contact the epitaxial layer 11 to form a Schottky contact. It should be explained that a Schottky contact refers to the bending of the energy band of the epitaxial layer 11 at the contact interface when the gate contact metal layer 13 and the epitaxial layer 11 are in contact, forming a contact barrier (which may be called a Schottky barrier). In one possible implementation, the gate interconnect structure 14 may include gold (Au) material. The gate interconnect structure 14 can serve to lead out the gate contact metal layer 13. In addition, the gate interconnect structure 14 can also provide anti-oxidation and reduce gate resistance.

[0142] In the embodiment of the present application, the depth of the first groove U1 on the surface of the epitaxial layer 11 is related to factors such as the material of the contact layer 121 and the annealing temperature of the annealing process.

[0143] In some embodiments of the present application, as shown in FIG24 , the contact layer 121 may comprise a metal material, and the first recess U1 extends from the surface of the epitaxial layer 11 on the side facing away from the semiconductor substrate 10 to the interior of the barrier layer 112. During the fabrication process, a relatively high temperature annealing process may be employed. For example, the annealing temperature may be within a range of 500° C. to 1000° C. Due to the relatively high annealing temperature, the contact layer 121 reacts with the epitaxial layer 11 during the annealing process, and the metal elements in the contact layer 121 may penetrate into the channel layer 111 through the barrier layer 112, thereby forming a good and reliable ohmic contact.

[0144] In the case where the contact layer 121 includes a metal material, the first electrode 12 may be configured as follows.

[0145] Specifically, a portion of the contact layer 121 is located within the first recess U1, while another portion protrudes from the surface of the epitaxial layer facing away from the semiconductor substrate 10. The contact layer 121 has a second recess U2 on the surface facing away from the semiconductor substrate 10. The contact layer 121 can contact the epitaxial layer 11 at the inner wall of the first recess U1. This arrangement can increase the contact area between the contact layer 121 and the epitaxial layer 11, thereby reducing the resistivity of the ohmic contact between the contact layer 121 and the epitaxial layer 11. Exemplarily, the contact layer 121 can include titanium (Ti) material, and the thickness of the contact layer 121 can be in the range of 4 nm to 20 nm.

[0146] A portion of the metal isolation layer 122 is located within the second recess U2, while another portion protrudes from the surface of the contact layer 121 facing away from the semiconductor substrate 10. The metal isolation layer 122 also has a third recess U3 on the surface facing away from the semiconductor substrate 10. Providing the metal isolation layer 122 on the surface of the contact layer 121 prevents the anti-oxidation metal layer 123 from diffusing into the contact layer 121, thus preventing excessive metal elements in the anti-oxidation metal layer 123 from diffusing downward and causing reliability issues in the semiconductor device. Specifically, the metal isolation layer 122 can include at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and can have a thickness in the range of 20 nm to 100 nm. In one possible implementation, the first electrode 12 may further include: a first metal layer 125 located between the contact layer 121 and the metal isolation layer 122, a portion of the first metal layer 125 being located in the second groove U2, and another portion extending to the surface of the contact layer 121 excluding the second groove U2, and the first metal layer 125 also having a groove on the side facing away from the semiconductor substrate 10, a portion of the metal isolation layer 122 being located in the groove on the surface of the first metal layer 125, and another portion extending to the surface of the first metal layer 125 excluding the groove. Exemplarily, the first metal layer 125 may include aluminum (Al) material, and the thickness of the first metal layer 125 may be between 80 nm and 200 nm. During the annealing process, the first metal layer 125 may diffuse downward, for example, may diffuse into the channel layer 111, participate in the ohmic contact reaction, facilitate the formation of a good and reliable ohmic contact, and further reduce the resistivity of the ohmic contact.

[0147] A portion of the anti-oxidation metal layer 123 is located within the third groove U3, and another portion protrudes from the surface of the metal isolation layer 122 on the side facing away from the semiconductor substrate 10. The anti-oxidation metal layer 123 can fill the third groove U3, and the surface of the anti-oxidation metal layer 123 on the side facing away from the semiconductor substrate 10 can be a flat surface. The thickness of the anti-oxidation metal layer 123 protruding from the surface of the metal isolation layer 122 on the side facing away from the semiconductor substrate 10 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In one possible implementation, the anti-oxidation metal layer 123 may include an inert metal material. For example, the anti-oxidation metal layer 123 may include an inert metal material such as gold (Au) or platinum (Pt). The inert metal material is not easily oxidized during annealing (annealing temperature is within the range of 200°C to 1000°C), so that the anti-oxidation metal layer 123 can effectively isolate the anti-oxidation metal layer 123 from the air. Alternatively, the anti-oxidation metal layer 123 may include an alloy material having anti-oxidation properties. For example, the anti-oxidation metal layer 123 may include titanium nitride (TiN). The anti-oxidation alloy material is not easily oxidized during annealing (annealing temperature is within the range of 200° C. to 1000° C.), and can also effectively isolate the anti-oxidation metal layer 123 from air. Of course, in some cases, the anti-oxidation metal layer 123 may also be made of other anti-oxidation materials, which is not limited in this application.

[0148] In other embodiments of the present application, as shown in FIG23 , the contact layer 121 may include a semiconductor doping layer 121a and a second metal layer 121b, and the first groove U1 extends from the surface of the epitaxial layer away from the semiconductor substrate 10 (i.e., the upper surface of the cap layer 113 in the figure) to the interior of the channel layer 111. During the manufacturing process, a lower temperature may be used for annealing. For example, the temperature of the annealing may be in the range of 200°C to 500°C. Since in the embodiment of the present application, the bottom of the first groove U1 is located inside the channel layer 111, the semiconductor doping layer 121a in the contact layer 121 may be in direct contact with the channel layer 111. Therefore, a good and reliable ohmic contact may be formed by using a lower annealing temperature.

[0149] In the case where the contact layer 121 includes the semiconductor doping layer 121 a and the second metal layer 121 b , the first electrode 12 may be configured as follows.

[0150] Specifically, the semiconductor doping layer 121a may include a semiconductor material doped with impurities. For example, the semiconductor doping layer 121a may include a gallium nitride (GaN) material doped with a high concentration of N-type impurities. The semiconductor doping layer 121a may fill the first groove U1. In one possible implementation, the surface of the semiconductor doping layer 121a may be flush with the upper surface of the epitaxial layer, or the surface of the semiconductor doping layer 121a may be slightly higher than the upper surface of the epitaxial layer. The second metal layer 121b is located on the side of the semiconductor doping layer 121a facing away from the semiconductor substrate 10. For example, the second metal layer 121b may include titanium (Ti) material. The second metal layer 121b may serve as a reactant for an ohmic contact reaction. By filling the semiconductor doping layer 121a in the first groove U1 of the epitaxial layer, the semiconductor doping layer 121a may reduce the potential barrier between the epitaxial layer and the second metal layer 121b, thereby facilitating the formation of an ohmic contact.

[0151] A metal isolation layer 122 is provided on the side of the contact layer 121 facing away from the semiconductor substrate 10. The metal isolation layer 122 prevents the material in the anti-oxidation metal layer 123 from diffusing into the contact layer 121, thereby preventing excessive metal elements in the anti-oxidation metal layer 123 from diffusing downward and causing reliability issues in the semiconductor device. In one possible implementation, the metal isolation layer 122 may include platinum (Pt).

[0152] An anti-oxidation metal layer 123 is provided on the side of the metal isolation layer 122 facing away from the semiconductor substrate 10. The thickness of the anti-oxidation metal layer 123 is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer 111. In one possible implementation, the anti-oxidation metal layer 123 may include an inert metal material, such as gold (Au) or platinum (Pt). The inert metal material is not easily oxidized during annealing (annealing temperature is within the range of 200°C to 1000°C), allowing the anti-oxidation metal layer 123 to effectively isolate the metal from the air. Alternatively, the anti-oxidation metal layer 123 may include an alloy material with anti-oxidation properties, such as titanium nitride (TiN). The alloy material with anti-oxidation properties is not easily oxidized during annealing (annealing temperature is within the range of 200°C to 1000°C), allowing the anti-oxidation metal layer 123 to effectively isolate the metal from the air. Of course, in some cases, the anti-oxidation metal layer 123 may also be made of other anti-oxidation materials, which is not limited in this application.

[0153] As shown in FIG. 23 and FIG. 24 , in the case where the contact layer 121 includes a metal material and includes a semiconductor doping layer 121 a and a second metal layer 121 b , the first electrode 12 may also be provided in the following manner.

[0154] In one possible implementation, the outer edges of the anti-oxidation metal layer 123 and the metal isolation layer 122 in the first electrode 12 are flush. This improves the morphology of the first electrode 12 and enhances the electrical performance of the semiconductor device. During the manufacturing process, the metal isolation layer 122 and the anti-oxidation metal layer 123 can be patterned using the same patterning process to ensure that the outer edges of the anti-oxidation metal layer 123 and the metal isolation layer 122 are flush. In some embodiments of the present application, the first electrode 12 may further include an etch stop layer 124. In specific configurations, the edge of the etch stop layer 124 may also be configured to be flush with the edge of the anti-oxidation metal layer 123. This improves the morphology of the first electrode 12 and enhances the electrical performance of the semiconductor device. During the manufacturing process, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 can be patterned using the same patterning process to ensure that the outer edges of the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 are flush.

[0155] During the manufacturing process, the metal film layers of the first electrode 12 can be deposited sequentially, and then the metal film layers can be patterned using a single patterning process to make the outer edges of the metal film layers of the first electrode 12 aligned. Specifically, as shown in FIG24 , when the contact layer 121 comprises a metal material, the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 can be deposited on the entire surface, and then the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 can be patterned using a single patterning process to make the outer edges of the contact layer 121, the first metal layer 125, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 of the first electrode 12 aligned. As shown in FIG23 , in the case where the contact layer 121 includes a semiconductor doped layer 121a and a second metal layer 121b, the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 can be deposited on the entire surface, and the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 can be patterned using the same patterning process to make the outer edges of the second metal layer 121b, the metal isolation layer 122, the anti-oxidation metal layer 123, and the etch stop layer 124 in the first electrode 12 aligned. It will be understood that in the embodiments of the present application, due to the limitations of the manufacturing process, the outer edges of certain film layers in the first electrode are aligned, which means that the outer edges of these film layers are substantially aligned within a certain error range.

[0156] FIG25 is a schematic diagram comparing the technical solution of the related art and the technical solution of the present application, wherein (1) in FIG25 is a schematic diagram showing the relationship between the current and voltage of the semiconductor device in the related art, (2) in FIG25 is a schematic diagram showing the relationship between the resistivity and distance of the semiconductor device in the related art, (3) in FIG25 is a schematic diagram showing the relationship between the current and voltage of the semiconductor device in the present application, and (4) in FIG25 is a schematic diagram showing the relationship between the resistivity and distance of the semiconductor device in the present application. In the semiconductor device provided in the embodiment of the present application, the thickness of the anti-oxidation metal layer in the first electrode is greater than or equal to 400 nm, while in the technical solution in the related art, the thickness of the anti-oxidation metal layer in the first electrode is about 50 nm. By comparing (1) and (3) and (2) and (4) in FIG25, it can be clearly seen that in the embodiment of the present application, the use of a thicker anti-oxidation metal layer can play a better anti-oxidation role and can significantly reduce the resistivity of the ohmic contact of the semiconductor device.

[0157] Based on the same technical concept, embodiments of the present application also provide a power amplifier chip. The power amplifier chip in the embodiments of the present application may include any of the aforementioned semiconductor devices, or may include a semiconductor device fabricated using the aforementioned fabrication method. Because the ohmic contacts of the semiconductor devices in the embodiments of the present application have low resistivity, the power amplifier chip including the semiconductor devices has excellent electrical performance.

[0158] Based on the same technical concept, embodiments of the present application also provide an electronic device. The electronic device in the embodiments of the present application may include the aforementioned power amplifier chip, and the electronic device is a portable terminal device. For example, the electronic device in the embodiments of the present application may be a mobile phone, a tablet computer, a laptop computer, or the like. Because the power amplifier chip in the embodiments of the present application has excellent electrical performance, the electronic device including the power amplifier chip also has excellent performance.

[0159] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0160] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor substrate; An epitaxial layer located above the semiconductor substrate, with a first groove provided on the surface of the epitaxial layer on the side facing away from the semiconductor substrate; the epitaxial layer includes: a channel layer; A first electrode, which is a source electrode or a drain electrode, with a part of the first electrode located inside the first groove and another part protruding from the surface of the epitaxial layer on the side facing away from the semiconductor substrate; The first electrode includes: a contact layer, a metal isolation layer, and an antioxidant metal layer. The contact layer contacts the epitaxial layer on the inner wall of the first groove. The antioxidant metal layer is located on the side of the contact layer facing away from the semiconductor substrate, and the metal isolation layer is located between the contact layer and the antioxidant metal layer; the thickness of the antioxidant metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer.

2. The semiconductor device according to claim 1, wherein The outer edges formed by the antioxidant metal layer and the metal isolation layer in the first electrode are flush.

3. The semiconductor device according to claim 1, characterized in that, The antioxidant metal layer includes: an inert metal material; and / or, the antioxidant metal layer includes: an alloy material with antioxidant properties.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, Further comprising: An interconnect structure located on the side of the first electrode facing away from the semiconductor substrate; The first electrode further includes: an etching stop layer located on the side of the antioxidant metal layer facing away from the semiconductor substrate; The etching stop layer includes a metal material, and the interconnect structure is in contact connection with the etching stop layer; The edge of the etching stop layer is flush with the edge of the antioxidant metal layer.

5. The semiconductor device according to claim 4, wherein, In the direction parallel to the surface of the semiconductor substrate, the width of the interconnect structure is smaller than the width of the antioxidant metal layer; The etching stop layer includes Ti or Ni, and the thickness of the etching stop layer is greater than or equal to 20 nm.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The epitaxial layer further includes: a barrier layer, and the barrier layer is located on the side of the channel layer facing away from the semiconductor substrate; The thickness of the channel layer is in the range of 100 nm to 400 nm, and the thickness of the barrier layer is in the range of 4 nm to 35 nm.

7. The semiconductor device according to claim 6, wherein, The contact layer includes a metal material; The first groove extends from the surface of the epitaxial layer on the side facing away from the semiconductor substrate to the inside of the barrier layer; A part of the contact layer is located inside the first groove, and another part protrudes from the surface of the epitaxial layer on the side facing away from the semiconductor substrate, and the contact layer has a second groove on the surface facing away from the semiconductor substrate; A part of the metal isolation layer is located inside the second groove, and another part protrudes from the surface of the contact layer on the side facing away from the semiconductor substrate, and the metal isolation layer has a third groove on the surface facing away from the semiconductor substrate; A part of the antioxidant metal layer is located inside the third groove, and another part protrudes from the surface of the metal isolation layer on the side facing away from the semiconductor substrate.

8. The semiconductor device according to claim 7, wherein The contact layer includes Ti material, and the thickness of the contact layer is in the range of 4 nm to 20 nm; The metal isolation layer includes at least one of Ti, Ni, Mo, Pt, Mo, Ir, and Nb, and the thickness of the metal isolation layer is in the range of 20 nm to 100 nm.

9. The semiconductor device according to claim 7 or 8, characterized in that, The first electrode further includes a first metal layer located between the contact layer and the metal isolation layer. The first metal layer includes Al material, and the thickness of the first metal layer is between 80 nm and 200 nm.

10. The semiconductor device according to claim 6, wherein The contact layer includes a semiconductor doped layer and a second metal layer; The semiconductor doped layer includes a semiconductor material doped with impurities. The semiconductor doped layer fills the first groove, and the second metal layer is located on the side of the semiconductor doped layer facing away from the semiconductor substrate; The first groove extends from the surface of the epitaxial layer on the side facing away from the semiconductor substrate into the interior of the channel layer.

11. The semiconductor device according to claim 10, wherein, The semiconductor doped layer includes GaN material doped with N-type impurities, and the second metal layer includes Ti material; the metal isolation layer includes Pt material.

12. The semiconductor device according to any one of claims 6 to 11, characterized in that, The epitaxial layer further includes a cap layer located on the side of the barrier layer facing away from the semiconductor substrate; The first groove penetrates the cap layer in a direction perpendicular to the surface of the semiconductor substrate; The cap layer includes GaN material, and the thickness of the cap layer is in the range of 1 nm to 5 nm.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The epitaxial layer further includes a nucleation layer located between the semiconductor substrate and the channel layer, a transition layer located between the nucleation layer and the channel layer, and a buffer layer between the transition layer and the channel layer; The nucleation layer includes AlN material, and the thickness of the nucleation layer is in the range of 100 nm to 300 nm; The transition layer includes AlGaN material, and the thickness of the transition layer is in the range of 100 nm to 500 nm; The buffer layer includes GaN material; the buffer layer is doped with carbon element with a concentration greater than 1e 17 ~2e 19 ; alternatively, the buffer layer is doped with iron element with a concentration greater than 1e 17 ; the thickness of the buffer layer ranges from 0.5 um to 2 um.

14. The semiconductor device according to any one of claims 1 to 13, characterized in that, The semiconductor substrate includes Si material with a resistivity greater than 5000 Ω.cm; alternatively, the semiconductor substrate includes SiC material with a resistivity greater than 1e 6 Ω.cm; alternatively, the semiconductor substrate includes GaN material with a resistivity greater than 1e4 Ω.cm; alternatively, the semiconductor substrate includes sapphire material with a resistivity greater than 1e11 Ω.cm.

15. A method for manufacturing a semiconductor device, characterized in that, including: forming an epitaxial layer on a semiconductor substrate, and performing patterning on the epitaxial layer to form a first groove on the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein, the epitaxial layer includes a channel layer; forming a first electrode with a part located inside the first groove and another part protruding from the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein, the first electrode is a source electrode or a drain electrode, and the first electrode includes a contact layer, a metal isolation layer, and an antioxidant metal layer. The contact layer contacts the epitaxial layer on the inner wall of the first groove, the antioxidant metal layer is located on the side of the contact layer facing away from the semiconductor substrate, and the metal isolation layer is located between the contact layer and the antioxidant metal layer; the thickness of the antioxidant metal layer protruding from the surface of the metal isolation layer on the side facing away from the semiconductor substrate is greater than or equal to 400 nm and greater than or equal to twice the thickness of the channel layer; [[ID= 16. The manufacturing method according to claim 15, characterized in that, ​ ​ forming a barrier layer having a thickness in the range of 4 nm to 35 nm on the channel layer; Performing patterning on the epitaxial layer to form the first groove extending from a surface of the epitaxial layer facing away from the semiconductor substrate to an interior of the barrier layer; The forming of the first electrode having a portion located inside the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate specifically includes: A contact layer is formed using a metal material, with a portion of the contact layer located inside the first groove and another portion extending to a region of the surface of the epitaxial layer excluding the first groove, and a second groove is formed on a surface of the contact layer facing away from the semiconductor substrate; A metal isolation layer is formed using a metal material, with a portion of the metal isolation layer being located within the second groove and another portion extending to an area above the contact layer excluding the second groove, and a third groove being provided on a surface of the metal isolation layer facing away from the semiconductor substrate; forming an anti-oxidation metal layer using a metal material, with a portion of the anti-oxidation metal layer being located within the third groove and another portion protruding from a surface of the metal isolation layer facing away from the semiconductor substrate; The annealing treatment of the structure after forming the anti-oxidation metal layer specifically includes: The structure after forming the anti-oxidation metal layer is annealed at a temperature within a range of 500° C. to 1000° C.

17. The manufacturing method according to claim 15, characterized in that, The step of forming an epitaxial layer on a semiconductor substrate and patterning the epitaxial layer to form a first groove on a surface of the epitaxial layer facing away from the semiconductor substrate specifically includes: forming the channel layer with a thickness ranging from 100 nm to 400 nm on the semiconductor substrate; forming a barrier layer having a thickness in the range of 4 nm to 35 nm on the channel layer; Performing patterning on the epitaxial layer to form the first groove extending from a surface of the epitaxial layer facing away from the semiconductor substrate to an interior of the channel layer; The contact layer includes: a semiconductor doping layer and a second metal layer; the first electrode formed with a portion located inside the first groove and another portion protruding from the surface of the epitaxial layer facing away from the semiconductor substrate specifically includes: forming the semiconductor doping layer using a semiconductor material doped with impurities, so that the semiconductor doping layer fills the first groove; forming the second metal layer, the metal isolation layer and the anti-oxidation metal layer in sequence on the semiconductor doping layer; The annealing treatment of the structure after forming the anti-oxidation metal layer specifically includes: The structure after forming the anti-oxidation metal layer is annealed at a temperature within a range of 200° C. to 500° C.

18. The manufacturing method according to any one of claims 15 to 17, characterized in that, The forming of the first electrode having a portion located inside the first groove and another portion protruding from a surface of the epitaxial layer facing away from the semiconductor substrate further includes: forming an etch stop layer on the anti-oxidation metal layer; After the structure after forming the anti-oxidation metal layer is annealed, the method further includes: An interconnection structure in contact with the etch stop layer is formed.

19. A power amplifier chip, characterized in that, include: The semiconductor device according to any one of claims 1 to 14, or the semiconductor device manufactured by the manufacturing method according to any one of claims 15 to 18.

20. An electronic device, characterized in that, Comprising a power amplifier chip according to claim 19, the electronic device being a terminal portable device.

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