Semiconductor device and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductors. Disclosed are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, wherein a shallow trench isolation (STI) structure is provided on the substrate; a first polycrystalline silicon structure layer, an isolation dielectric layer and a second polycrystalline silicon structure layer are sequentially stacked on the STI structure; the first polycrystalline silicon structure is undoped polycrystalline silicon, and the second polycrystalline silicon structure layer is polycrystalline silicon that is heavily doped with boron; and the first polycrystalline silicon structure layer is provided with a contact hole, and the contact hole structure is used for monitoring a target doping concentration of boron in the first polycrystalline silicon structure layer when the second polycrystalline silicon structure layer is subjected to high-concentration boron ion implantation and annealing for activation. The present application optimizes a diffusion process in integrated circuit manufacturing, thereby improving the reliability of integrated circuit devices.

Description

Semiconductor device and method for manufacturing the same Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In semiconductor-related integrated circuit manufacturing processes, in order to obtain P-type semiconductors, semiconductor materials are usually doped with boron. Doping is a common method used to change the electrical conductivity of semiconductor materials. For P-type semiconductors, boron (B) is a commonly used donor impurity that can introduce positive charge carriers (holes), thereby making the material exhibit P-type conductivity. However, because the mass of boron atoms is relatively small, their diffusion behavior in semiconductor materials is affected by many factors. During the annealing activation process, high temperature will cause boron atoms to diffuse from high-concentration areas to low-concentration areas to achieve equilibrium. This diffusion process may be affected by factors such as impurities, lattice defects and interfaces, thereby posing challenges to the stability and reliability of integrated circuits. Therefore, it is necessary to design a semiconductor device for monitoring the diffusion of boron elements during the integrated circuit manufacturing process to optimize the diffusion process of integrated circuit preparation and thus improve the reliability of integrated circuit devices. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor device and a method for manufacturing the same, so as to optimize the diffusion process for manufacturing integrated circuits, thereby improving the reliability of integrated circuit devices.

[0004] To achieve the above objectives, according to the first aspect, the technical solution adopted is:

[0005] A semiconductor device comprises: a substrate, on which an STI shallow isolation structure is provided; a first polysilicon structure layer, an isolation dielectric layer, and a second polysilicon structure layer are sequentially stacked on the STI shallow isolation structure; the first polysilicon structure is undoped polysilicon, and the second polysilicon structure layer is polysilicon heavily doped with boron; a contact hole structure is provided on the first polysilicon structure layer, and the contact hole structure is used to monitor the target doping concentration of the boron element in the first polysilicon structure layer when high-concentration boron ion implantation and annealing activation are performed on the second polysilicon structure layer.

[0006] The present application is further configured such that: the isolation dielectric layer includes a silicon dioxide film.

[0007] The present application is further configured as follows: the contact hole structure is arranged on both sides of the first polysilicon structure layer and is respectively kept at a distance from the second polysilicon structure layer; a contact electrode is provided in the contact hole structure, and the contact electrode is used to connect the potential of the first polysilicon structure layer and measure the resistivity of the first polysilicon structure layer after being doped with the boron element.

[0008] According to the second aspect, the technical solution adopted is:

[0009] A method for preparing a semiconductor device, wherein the method for preparing a semiconductor device prepares the semiconductor device of any of the above embodiments, comprising:

[0010] Providing a substrate for integrated circuit fabrication, and forming an STI shallow isolation structure on the substrate;

[0011] forming a first polysilicon structure layer on the STI shallow isolation structure;

[0012] forming an isolation dielectric layer on the first polysilicon structural layer, wherein the isolation dielectric layer covers the first polysilicon structural layer;

[0013] forming a second polysilicon structure layer corresponding to the first polysilicon structure layer on the isolation dielectric layer;

[0014] Performing high-concentration boron ion implantation on the second polysilicon structure layer and annealing activation;

[0015] forming a contact hole structure on the first polysilicon structure layer, and monitoring a target doping concentration of the boron element in the first polysilicon structure layer through the contact hole structure;

[0016] Based on the target doping concentration, the parameter conditions of the boron element annealing activation are optimized.

[0017] The present application is further configured as follows: forming an STI shallow isolation structure on the substrate specifically includes:

[0018] performing a first cleaning process on the substrate;

[0019] Photolithography and etching the substrate to define the position and shape of the STI shallow isolation region on the substrate;

[0020] Performing a second cleaning process on the STI shallow isolation area;

[0021] A sacrificial oxide layer is formed by oxidation in the STI shallow isolation region, and is planarized by a CMP chemical mechanical polishing process to obtain the STI shallow isolation structure.

[0022] The present application is further configured as follows: forming an isolation dielectric layer on the first polysilicon structure layer specifically includes:

[0023] The first polysilicon structure layer is subjected to thermal oxidation treatment, and a silicon surface of the first polysilicon structure layer reacts with oxygen to form a silicon dioxide film, and the silicon dioxide film covers the first polysilicon structure layer.

[0024] The present application is further configured as follows: forming the second polysilicon structure layer specifically includes:

[0025] forming a second polysilicon film on the isolation dielectric layer by chemical vapor deposition;

[0026] Photolithography and etching of the second polysilicon film to define the position and shape of the second polysilicon structure layer on the isolation dielectric layer;

[0027] The portion of the isolation dielectric layer not covered by the second polysilicon structure layer is photolithographically and etched to expose the electrode region of the first polysilicon structure layer.

[0028] The present application is further configured as follows: forming a contact hole structure on the first polysilicon structure layer specifically includes:

[0029] Photolithography and etching the electrode region of the first polysilicon structure layer to define the position and size of the contact hole structure on the electrode region;

[0030] forming a metallization layer on the contact hole structure;

[0031] Photolithography and etching the metallization layer to form a contact electrode, wherein the contact electrode is used to connect the potential of the first polysilicon structure layer and measure the resistivity of the first polysilicon structure layer after being doped with the boron element;

[0032] Based on the resistivity, a target doping concentration of the boron element in the first polysilicon structure layer is obtained.

[0033] The present application is further configured as follows: the contact hole structure is provided on both sides of the first polysilicon structure layer and is respectively kept at a distance from the second polysilicon structure layer.

[0034] The present application is further configured as follows: the parameter conditions for the boron element annealing activation include the temperature and time of the annealing activation.

[0035] To summarize, compared with the prior art, the present application discloses a semiconductor device and a method for preparing the same, wherein an STI shallow isolation structure is provided on the substrate of the semiconductor device, and a first polysilicon structure layer, an isolation dielectric layer and a second polysilicon structure layer are sequentially stacked on the STI shallow isolation structure, wherein the first polysilicon structure is undoped polysilicon, and the second polysilicon structure layer is polysilicon heavily doped with boron elements, and a contact hole structure is provided on the first polysilicon structure layer. When the second polysilicon structure layer is subjected to high-concentration boron ion implantation and annealing activation, the contact hole structure monitors the target doping concentration of the boron element in the first polysilicon structure layer, that is, through the above-mentioned setting, the diffusion process of integrated circuit preparation is optimized, thereby improving the reliability of the integrated circuit device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to illustrate the implementation of the present application and, together with the text description, to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0037] FIG1 is a flow chart of a method for preparing a semiconductor device according to the present embodiment;

[0038] FIG2 is a schematic structural diagram of a first semiconductor device according to this embodiment;

[0039] FIG3 is a schematic structural diagram of a second semiconductor device according to this embodiment;

[0040] FIG4 is a schematic structural diagram of a third semiconductor device according to this embodiment;

[0041] FIG5 is a schematic structural diagram of a fourth semiconductor device according to this embodiment;

[0042] FIG6 is a schematic structural diagram of a fifth semiconductor device according to this embodiment;

[0043] FIG. 7 is a schematic top view of the semiconductor device according to this embodiment. DETAILED DESCRIPTION

[0044] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0046] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0047] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0048] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0049] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0050] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0051] Please refer to Figures 6 and 7. The semiconductor device includes: a substrate 1 for preparing an integrated circuit, an STI shallow isolation structure 2 is provided on the substrate 1, and a first polysilicon structure layer 3, an isolation dielectric layer 4 and a second polysilicon structure layer 5 are stacked in sequence on the STI shallow isolation structure 2, wherein the first polysilicon structure layer 3 is undoped polysilicon, and the second polysilicon structure layer 5 is polysilicon heavily doped with boron.

[0052] Furthermore, a contact hole structure 6 is provided on the first polysilicon structure layer 3 , and the contact hole structure 6 is used to monitor the target doping concentration of the boron element in the first polysilicon structure layer 3 when the second polysilicon structure layer 5 is subjected to high-concentration boron ion implantation and annealing activation.

[0053] Among them, the contact hole structure 6 is arranged on both sides of the first polysilicon structure layer 3 and is respectively kept at a distance from the second polysilicon structure layer 5. A contact electrode 7 is provided in the contact hole structure 6. The contact electrode 7 is used to connect the potential of the first polysilicon structure layer 3 and measure the resistivity of the first polysilicon structure layer 3 after boron doping.

[0054] In the specific implementation process, the resistivity of the first polysilicon structure layer 3 after boron doping is measured to monitor the target doping concentration of the boron element in the first polysilicon structure layer 3, and the temperature and time of the boron element annealing activation are optimized based on the stable state of the target doping concentration.

[0055] Based on the semiconductor device, this embodiment discloses a method for manufacturing a semiconductor device. Please refer to Figures 1 and 7. Figure 1 is a flow chart of the method for manufacturing a semiconductor device of this embodiment, and Figure 7 is a schematic diagram of a top view of the semiconductor device of this embodiment. The method for manufacturing a semiconductor device of this embodiment specifically includes:

[0056] S101 , providing a substrate 1 for integrated circuit fabrication, and forming an STI shallow isolation structure 2 on the substrate 1 .

[0057] In the specific implementation process, the material of the substrate 1 of this embodiment can be single crystal silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium and the like. The substrate 1 can also be a silicon germanium substrate, a III-V group element compound substrate, a silicon carbide substrate or its stacked structure, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates known to those skilled in the art.

[0058] In some embodiments, a buried layer and an epitaxial layer stacked in sequence may be formed on the substrate 1 , and in this case, all functional layers of the semiconductor device may be formed on the epitaxial layer.

[0059] 2 , forming an STI shallow isolation structure 2 on a substrate 1 may specifically include:

[0060] A. Perform a first cleaning treatment on the substrate 1, wherein, before forming the STI shallow isolation structure 2, the substrate 1 is cleaned to remove surface impurities and contaminants. Optional cleaning methods in this embodiment include acid cleaning, solvent cleaning, and gas purging. For example, the substrate 1 is cleaned with a chemical reagent to remove a natural oxide layer, surface particles, metal ions, etc. on the surface of the substrate 1. The chemical reagent may include a combination of one or more of sulfuric acid, hydrochloric acid, nitric acid, and hydrofluoric acid. That is, the acidic solution may include any one of the above-mentioned solutions, or may include a combination of any two or more of the above-mentioned solutions. This embodiment does not limit this.

[0061] B. Photolithography and etching of substrate 1 to define the position and shape of the STI shallow isolation region 2a on substrate 1, that is, etching a series of shallow and wide trenches on substrate 1. These trenches will be used to isolate different devices and can isolate the active area of ​​substrate 1 through the STI shallow isolation region 2a.

[0062] C. Perform a second cleaning process on the STI shallow isolation region 2a. It is understood that the process of the second cleaning process can be the same as that of the first cleaning process.

[0063] D. Oxidation is performed in the STI shallow isolation region 2 a to form a sacrificial oxide layer, and planarization is performed through a CMP chemical mechanical polishing process, so that the STI shallow isolation region 2 a is flush with the surface around the substrate 1 , thereby obtaining the STI shallow isolation structure 2 .

[0064] S102 , forming a first polysilicon structure layer 3 on the STI shallow isolation structure 2 .

[0065] Specifically, referring to Figure 3, polysilicon is grown on the STI shallow isolation structure 2, wherein the polysilicon can be grown by chemical vapor deposition (CVD) or physical vapor deposition (PECVD). During the growth process, silicon source gas (such as silane) and carrier gas can be introduced into the reaction chamber, and silicon is deposited on the STI shallow isolation structure 2 at a set temperature and pressure to form a first polysilicon structure layer 3.

[0066] The first polysilicon structure layer 3 produced in this step can be regarded as an undoped polysilicon structure.

[0067] S103 , forming an isolation dielectric layer 4 on the first polysilicon structural layer 3 , wherein the isolation dielectric layer 4 covers the first polysilicon structural layer 3 .

[0068] In the specific implementation process, referring to Figures 4 and 5, the formation of the isolation dielectric layer 4 may specifically include: performing thermal oxidation treatment on the first polysilicon structure layer 3, and the silicon surface of the first polysilicon structure layer 3 reacts with oxygen to form a silicon dioxide film 4a, and the silicon dioxide film 4a covers the first polysilicon structure layer 3.

[0069] Among them, before the thermal oxidation treatment, the first polysilicon structure layer 3 can still be cleaned for the third time, and the cleaned first polysilicon structure layer 3 is placed in a high-temperature environment to introduce an oxygen (O2) atmosphere. At high temperature, the silicon surface atoms of the first polysilicon structure layer 3 react with oxygen to form a silicon dioxide film 4a. It can be understood that the silicon dioxide film 4a grows on the surface of the first polysilicon structure layer 3. This layer of silicon dioxide film can cover and wrap the first polysilicon structure layer 3 to provide protection and insulation functions.

[0070] That is, the isolation dielectric layer 4 is formed on the first polysilicon structure layer 3 by forming a silicon dioxide film 4a through thermal oxidation.

[0071] S104 , forming a second polysilicon structure layer 5 corresponding to the first polysilicon structure layer 3 on the isolation dielectric layer 4 .

[0072] In a specific implementation process, referring to FIG5 and FIG6 , forming the second polysilicon structure layer 5 may specifically include:

[0073] I. Forming a second polysilicon film 5 a on the isolation dielectric layer 4 by chemical vapor deposition. It is understandable that the deposition process of the second polysilicon film 5 a can be the same as the formation process of the first polysilicon structure layer 3 .

[0074] II. Photolithography and etching of the second polysilicon film 5 a to define the position and shape of the second polysilicon structure layer 5 on the isolation dielectric layer 4 , wherein the position of the second polysilicon structure layer 5 corresponds to the first polysilicon structure layer 3 through the isolation dielectric layer 4 .

[0075] III. Photolithography and etching of the portion of the isolation dielectric layer 4 not covered by the second polysilicon structure layer 5 to expose the electrode region 3a of the first polysilicon structure layer 3, thereby providing a basis for the subsequent preparation of the contact hole structure 6 through the electrode region 3a.

[0076] S105 , implanting high-concentration boron ions into the second polysilicon structure layer 5 , and performing annealing for activation.

[0077] Among them, after boron ions are injected into the second polysilicon structure layer 5, the boron ions diffuse in the second polysilicon structure layer 5. Through the annealing process, the injected boron ions are activated and given electrical properties, that is, the boron ions combine with the silicon atoms in the polysilicon to form electrons and holes, so that the second polysilicon structure layer 5 is polysilicon heavily doped with boron elements.

[0078] S106 , forming a contact hole structure 6 on the first polysilicon structure layer 3 , and monitoring a target doping concentration of the boron element in the first polysilicon structure layer 3 through the contact hole structure 6 .

[0079] In a specific implementation process, the formation of the contact hole structure 6 may specifically include:

[0080] a. Photolithography and etching of the electrode region 3a of the first polysilicon structure layer 3, defining the position and size of the contact hole structure 6 on the electrode region 3a. Specifically, a photolithography mask can be designed and manufactured, and the photolithography mask includes a required pattern for defining the contact hole structure 6. The photolithography mask can be prepared by exposing and developing the photoresist using photolithography technology, and the photoresist is coated on the electrode region 3a to form a uniform photoresist film. The photolithography mask is aligned with the photoresist layer and exposed and developed, and then the unexposed part or the exposed photoresist is removed to form the required contact hole pattern, so as to etch the electrode region 3a to form the contact hole structure 6.

[0081] b. Form a metallization layer on the contact hole structure 6. The metallization layer may be formed by metal deposition. The metal material may include aluminum (Al) or copper (Cu).

[0082] c. Photolithography and etching of the metallization layer to form a contact electrode 7 , wherein the contact electrode 7 is used to connect the potential of the first polysilicon structure layer 3 and measure the resistivity of the first polysilicon structure layer 3 after boron doping.

[0083] d. Based on the resistivity, a target doping concentration of the boron element in the first polysilicon structure layer 3 is obtained.

[0084] Among them, the contact hole structure 6 is arranged on both sides of the first polysilicon structure layer 3 and is respectively kept at a distance from the second polysilicon structure layer 5, so as to facilitate the external connection of the contact electrode 7 on the contact hole structure 6, thereby measuring the resistivity of the first polysilicon structure layer 3 after boron doping.

[0085] S107, optimizing the parameter conditions for annealing activation of the boron element based on the target doping concentration.

[0086] The parameter conditions for the boron element annealing activation include the annealing activation temperature and time.

[0087] This embodiment is based on the structural design of the first polysilicon structure layer 3 and the second polysilicon structure layer 5. After boron ions are implanted into the second polysilicon structure layer 5, annealing is performed to activate the boron ions so that they pass through the isolation dielectric layer 4 and diffuse into the undoped first polysilicon structure layer 3. Under this premise, the resistivity change of the first polysilicon structure layer 3 can be tested through the contact electrode 7 on the contact hole structure 6, and the target doping concentration of the boron element in the first polysilicon structure layer 3 can be monitored. The temperature and time of the boron element annealing activation can be optimized based on this target doping concentration.

[0088] It should be emphasized that the first polysilicon structure layer 3 has a set length, which can be 10 μm, and the isolation dielectric layer 4 has a set thickness, which can be 2 nm. During the monitoring process of boron ion diffusion, the resistance of the first polysilicon structure layer 3 with a size of 1 μm and 11 μm can be tested respectively, so as to obtain the resistivity of the first polysilicon structure layer 3 with a length of 10 μm. As for the thickness of the isolation dielectric layer 4, by changing the thickness of the isolation dielectric layer 4 to 2 nm, 7 nm, and 14 nm respectively, it is found that when the thickness of the isolation dielectric layer 4 is 2 nm, the resistance value of the first polysilicon structure layer 3 decreases significantly. That is, when the thickness of the isolation dielectric layer 4 is 2 nm, the boron ions pass through the isolation dielectric layer 4 and diffuse into the first polysilicon structure layer 3. Then, the thickness of the isolation dielectric layer 4 is fixed at 2 nm. By real-time monitoring the target doping concentration of the boron element in the first polysilicon structure layer 3, the parameter conditions for the boron element annealing activation can be optimized, thereby optimizing the diffusion process of integrated circuit preparation and improving the reliability of integrated circuit devices.

[0089] In summary, the present application forms an STI shallow isolation structure 2 on the substrate 1 through a substrate 1 for integrated circuit preparation, and forms a first polysilicon structure layer 3 on the STI shallow isolation structure 2, and forms an isolation dielectric layer 4 covering the first polysilicon structure layer 3 based on the first polysilicon structure layer 3, and forms a second polysilicon structure layer 5 corresponding to the first polysilicon structure layer 3 on the isolation dielectric layer 4, wherein the second polysilicon structure layer 5 is ion-implanted with high-concentration boron elements and annealed for activation, and a contact hole structure 6 is formed on the first polysilicon structure layer 3, and the target doping concentration of the boron element in the first polysilicon structure layer 3 is monitored through the contact hole structure 6, and based on the target doping concentration, the parameter conditions for the annealing activation of the boron element are optimized, thereby optimizing the diffusion process of the integrated circuit preparation, thereby improving the reliability of the integrated circuit device.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: a substrate, on which an STI shallow isolation structure is provided; a first polysilicon structure layer, an isolation dielectric layer, and a second polysilicon structure layer are sequentially stacked on the STI shallow isolation structure; the first polysilicon structure is undoped polysilicon, and the second polysilicon structure layer is polysilicon heavily doped with boron element; a contact hole structure is provided on the first polysilicon structure layer, and the contact hole structure is used to monitor the target doping concentration of the boron element in the first polysilicon structure layer when performing high-concentration boron element ion implantation and annealing activation on the second polysilicon structure layer.

2. The semiconductor device according to claim 1, characterized in that, The isolation dielectric layer includes a silicon dioxide thin film.

3. The semiconductor device according to claim 1, wherein The contact hole structure is provided on both sides of the first polysilicon structure layer and is respectively spaced from the second polysilicon structure layer. A contact electrode is provided in the contact hole structure, and the contact electrode is used to connect the potential of the first polysilicon structure layer and measure the resistivity of the first polysilicon structure layer after boron element doping.

4. A method for manufacturing a semiconductor device, the method for manufacturing the semiconductor device manufacturing the semiconductor device according to any one of claims 1 to 3, characterized in that, Including: Providing a substrate for integrated circuit fabrication, and forming an STI shallow isolation structure on the substrate; Forming a first polysilicon structure layer on the STI shallow isolation structure; Forming an isolation dielectric layer on the first polysilicon structure layer, and the isolation dielectric layer covers the first polysilicon structure layer; Forming a second polysilicon structure layer corresponding to the first polysilicon structure layer on the isolation dielectric layer; Performing high-concentration boron element ion implantation on the second polysilicon structure layer, and annealing and activating; Forming a contact hole structure on the first polysilicon structure layer, and monitoring the target doping concentration of the boron element in the first polysilicon structure layer through the contact hole structure; Based on the target doping concentration, optimizing the parameter conditions for boron element annealing activation.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The forming of the STI shallow isolation structure on the substrate specifically includes: Performing a first cleaning process on the substrate; Photolithographing and etching the substrate to define the position and shape of the STI shallow isolation region on the substrate; Performing a second cleaning process on the STI shallow isolation region; Oxidizing to form a sacrificial oxide layer in the STI shallow isolation region, and performing planarization treatment through a CMP chemical mechanical polishing process to obtain the STI shallow isolation structure.

6. The method for manufacturing a semiconductor device according to claim 4, wherein, The forming of the isolation dielectric layer on the first polysilicon structure layer specifically includes: Performing a thermal oxidation process on the first polysilicon structure layer, and the silicon surface of the first polysilicon structure layer reacts with oxygen to form a silicon dioxide thin film, and the silicon dioxide thin film covers the first polysilicon structure layer.

7. The method for manufacturing a semiconductor device according to claim 4, wherein, The forming of the second polysilicon structure layer specifically includes: Forming a second polysilicon thin film on the isolation dielectric layer by chemical vapor deposition; Photolithographing and etching the second polysilicon thin film to define the position and shape of the second polysilicon structure layer on the isolation dielectric layer; Photolithographing and etching the portion of the isolation dielectric layer that is not covered by the second polysilicon structure layer to expose the electrode region of the first polysilicon structure layer.

8. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The forming of the contact hole structure on the first polysilicon structure layer specifically includes: Lithographically pattern and etch the electrode region of the first polysilicon structure layer to define the position and size of the contact hole structure on the electrode region; Form a metallization layer on the contact hole structure; Lithographically pattern and etch the metallization layer to form a contact electrode, which is used to connect the potential of the first polysilicon structure layer and measure the resistivity of the first polysilicon structure layer after doping with boron element; Based on the resistivity, obtain the target doping concentration of boron element in the first polysilicon structure layer.

9. The method for manufacturing a semiconductor device according to claim 7, wherein, The contact hole structures are arranged on both sides of the first polysilicon structure layer and are respectively kept at a distance from the second polysilicon structure layer.

10. The method for manufacturing a semiconductor device according to claim 4, wherein, The parameter conditions for annealing and activation of the boron element include the temperature and time of annealing and activation.

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