Semiconductor device

Abstract

This semiconductor device (10) comprises a switching element (100) and a wiring element (200) that are joined to a base plate (11). The wiring element comprises a plurality of pads (214, 215a, 215b, 217, 218, 219, 221) that are on the upper surface of a semiconductor substrate (201) and a rear surface electrode (208) that is on the lower surface of the semiconductor substrate (201). A P-type well (203) connected to a GND electrode (213) and a P-type anode layer (204) of an overcurrent detection diode (Dd) are formed apart from each other in a surface layer part on the upper surface side of the semiconductor substrate. The plurality of pads include a DESAT anode pad (219) of the overcurrent detection diode (Dd). In a state in which the rear surface electrode is at a higher electric potential than the plurality of pads, the plurality of pads are electrically insulated from the rear surface electrode.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device equipped with a plurality of power switching elements.

[0002] For example, Patent Document 1 below discloses a semiconductor device including a power switching element that constitutes an inverter circuit and a level shift circuit that converts the level of a control signal of the power switching element. In the semiconductor device of Patent Document 1, the resistors and switching elements that constitute the level shift circuit and a bootstrap diode (Schottky diode) are integrated on the same wide-gap semiconductor substrate to form a single integrated chip.

[0003] International Publication No. 2006 / 022387

[0004] In the semiconductor device of Patent Document 1, the integrated chip is mounted on a conductive plate on which a power switching element is mounted via an insulating plate (or chip capacitor). Therefore, the number of components and manufacturing steps required to ensure insulation between the conductive plate and the integrated chip increase, resulting in increased manufacturing costs. Furthermore, since the integrated chip does not include a temperature detection element or short-circuit detection element for the power switching element, in order to enhance the functionality of the semiconductor device, these elements must be provided separately from the integrated chip, which poses challenges in terms of miniaturization of the semiconductor device and flexibility of layout.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a technology that can reduce the number of components while achieving high functionality in a semiconductor device equipped with multiple power switching elements.

[0006] a P-type anode layer formed in the surface layer portion of the upper surface side of the semiconductor substrate and spaced from the P-type well; and an overcurrent detection diode having a DESAT anode pad, which is one of the plurality of pads and electrically connected to the P-type anode layer, as an anode electrode, and the back electrode as a cathode electrode. When the back electrode is at a higher potential than the plurality of pads, the plurality of pads are electrically insulated from the back electrode.

[0007] According to the present disclosure, in a semiconductor device including a plurality of power switching elements, it is possible to reduce the number of components while achieving high functionality.

[0008] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0009] 1 is a plan view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of a semiconductor device according to the first embodiment. FIG. 3 is a plan view of a wiring element according to the first embodiment. FIG. 4 is a cross-sectional view of a semiconductor substrate constituting the wiring element according to the first embodiment. FIG. 5 is a cross-sectional view of a wiring element according to the first embodiment. FIG. 6 is a circuit diagram of a semiconductor device according to the first embodiment. FIG. 7 is a plan view of a semiconductor device according to a second embodiment. FIG. 8 is a cross-sectional view of a semiconductor substrate constituting the wiring element according to the second embodiment. FIG. 9 is a cross-sectional view of a wiring element according to the second embodiment. FIG. 10 is a cross-sectional view of a wiring element according to the second embodiment. FIG. 11 is a circuit diagram of a semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view of a wiring element according to the second embodiment. 10 is a graph showing the relationship between the resistance value of the current limiting resistor and the voltage generated in the current limiting resistor due to the displacement current generated when the switching element is turned off. FIG. 11 is a plan view of a semiconductor device according to a fifth embodiment. FIG. 12 is a plan view of a wiring element according to the fifth embodiment. FIG. 13 is a cross-sectional view of the wiring element according to the fifth embodiment. FIG. 14 is a circuit diagram of a semiconductor device according to the fifth embodiment.

[0010] An embodiment of the technology according to the present disclosure will be described. In the drawings shown below, the same or corresponding elements are designated by the same reference numerals. Therefore, the description of elements designated by the same reference numerals as those described above will be omitted as appropriate.

[0011] 1 and 2 are configuration diagrams of a semiconductor device 10 according to a first embodiment. Fig. 1 is a plan view of the semiconductor device 10, and Fig. 2 is a cross-sectional view of the semiconductor device 10.

[0012] The semiconductor device 10 includes a conductive base plate 11, a switching element 100 and a wiring element 200 mounted on the base plate 11, a main terminal 12, a control terminal 13, and a sealing resin 14 (not shown in FIG. 1 ) that seals these elements. Portions of the main terminal 12 and the control terminal 13 protrude from the sealing resin 14 for connection to the outside.

[0013] The switching element 100 is, for example, a power switching element that constitutes an inverter circuit, and is, for example, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), etc. In the following description, the switching element 100 will be described as a MOSFET.

[0014] The semiconductor device 10 of this embodiment includes, as switching elements 100, a first switching element 110 and a second switching element 120. The first switching element 110 includes, as surface electrodes on its upper surface (front surface), a source electrode 111, a gate electrode 112, and a Kelvin source electrode 113, and as a back electrode on its lower surface (back surface). The second switching element 120 includes, as surface electrodes on its upper surface, a source electrode 121, a gate electrode 122, and a Kelvin source electrode 123, and as a back electrode on its lower surface (back surface).

[0015] The wiring element 200 has a plurality of wire bond pads as surface electrodes on its upper surface and a back electrode on its lower surface. The wiring element 200 will be described in detail later.

[0016] The back surface electrode (drain electrode) of the first switching element 110, the back surface electrode of the second switching element 120, and the back surface electrode of the wiring element 200 are joined to the base plate 11 by a conductive bonding material 15. The source electrode 111 of the first switching element 110 and the source electrode 121 of the second switching element 120 are joined to the main terminal 12 by the bonding material 15. Thus, the base plate 11 functions as the drain terminal of the semiconductor device 10, and the main terminal 12 functions as the source terminal of the main terminal 12.

[0017] The gate electrode 112 and Kelvin source electrode 113 of the first switching element 110 are connected to the wiring element 200, the gate electrode 122 and Kelvin source electrode 123 of the second switching element 120 are connected to the wiring element 200, and the wiring element 200 is connected to the control terminal 13, respectively, by conductive wiring material 16. As a result, the gate electrode 112 and Kelvin source electrode 113 of the first switching element 110 and the gate electrode 122 and Kelvin source electrode 123 of the second switching element 120 are connected to the control terminal 13 through the wiring element 200.

[0018] The details of the wiring element 200 will be described. Figures 3 to 6 are configuration diagrams of the wiring element 200 according to the first embodiment. Figure 3 is a plan view of the wiring element 200, Figure 4 is a plan view of a semiconductor substrate 201 that constitutes the wiring element 200, Figure 5 is a cross-sectional view taken along line A1-A2 in Figure 3, and Figure 6 is a cross-sectional view taken along line B1-B2 in Figure 3. Also, a circuit diagram of a semiconductor device 10 including the wiring element 200 is shown in Figure 7.

[0019] In the following explanation, "N-type" and "P-type" refer to the conductivity type of a semiconductor. ＋ ", and N-type with a relatively low impurity concentration is called "N － ", and P-type with a relatively high impurity concentration is called "P ＋ ", and P-type with a relatively low impurity concentration is called "P － The impurity concentration of each region is defined by the peak concentration. That is, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0020] The wiring element 200 is formed using a semiconductor substrate 201 made of silicon. －4, an N-type field stop layer 206 is formed on the semiconductor substrate 201. In the surface layer portion on the upper surface side of the semiconductor substrate 201, a P-type well 203, a P-type anode layer 204, and a P-type guard ring 205 are formed as P-type regions. As shown in FIG. 4, the P-type well 203 and the P-type anode layer 204 are formed spaced apart from each other, and the P-type guard ring 205 is formed so as to surround the outside of the P-type well 203 and the P-type anode layer 204. Furthermore, an N-type field stop layer 206 is formed further outside the P-type guard ring 205.

[0021] The surface layer of the lower side of the semiconductor substrate 201 is formed of N ＋ A N-type cathode layer 207 is formed on the lower surface of the semiconductor substrate 201. ＋ A back electrode 208 is formed on the P-type cathode layer 207. － Mold layer 202 and N ＋ The cathode layer 207 constitutes a high-voltage diode corresponding to the DESAT diode Dd shown in Fig. 7. The DESAT diode Dd is an overcurrent detection diode that detects the saturated states of the first switching element 110 and the second switching element 120, thereby detecting overcurrents in the first switching element 110 and the second switching element 120.

[0022] The diode Dp shown in FIG. 7 is formed by a P-type well 203 and an N － Mold layer 202 and N ＋ The parasitic diode is formed by the cathode layer 207 .

[0023] A thermal oxide film 209 is formed on the upper surface of the semiconductor substrate 201. As shown in Fig. 6, a first gate resistor 210a and a second gate resistor 210b made of polysilicon (polycrystalline silicon) are formed on the thermal oxide film 209. The first gate resistor 210a corresponds to the gate resistor Rg1 of the first switching element 110 shown in Fig. 7, and the second gate resistor 210b corresponds to the gate resistor Rg2 of the temperature sense anode wiring 220 shown in Fig. 7.

[0024] 5, a temperature sensing diode 211 made of P-type polysilicon 211p and N-type polysilicon 211n is formed on the thermal oxide film 209. The temperature sensing diode 211 corresponds to the temperature sensing diode Dt shown in FIG. 7. The temperature sensing diode Dt can detect the temperature of the semiconductor device 10.

[0025] An interlayer insulating film 212 is formed on the thermal oxide film 209, the first gate resistor 210a, the second gate resistor 210b, and the temperature sensing diode 211. Contact holes are formed in the thermal oxide film 209 and the semiconductor substrate 201, reaching the P-type well 203, the P-type anode layer 204, the N-type field stop layer 206, the first gate resistor 210a, the second gate resistor 210b, the P-type polysilicon 211p, and the N-type polysilicon 211n, respectively.

[0026] On the interlayer insulating film 212, a ground (GND) electrode 213, a GND electrode pad 214, a first gate pad 215a, a second gate pad 215b, a gate wiring 216, a gate wiring pad 217, a Kelvin source pad 218, a DESAT anode pad 219, a temperature sense anode wiring 220, a temperature sense anode wiring pad 221, and a field stop electrode 222 are formed.

[0027] The GND electrode 213 is connected to the P-type well 203 and the N-type polysilicon 211n of the temperature sense diode 211 through contact holes. The GND electrode pad 214 and the Kelvin source pad 218 are wire bond pads provided on the GND electrode 213. The first gate pad 215a is connected to the first gate resistor 210a through a contact hole. The second gate pad 215b is connected to the second gate resistor 210b through a contact hole. The gate wiring 216 is connected to the first gate resistor 210a and the second gate resistor 210b through contact holes. The gate wiring pad 217 is a wire bond pad provided on the gate wiring 216. The DESAT anode pad 219 is connected to the P-type anode layer 204 through a contact hole. The temperature sense anode wiring 220 is connected to the temperature sense diode 211b of the temperature sense diode 211 through a contact hole. The temperature sense anode wiring pad 221 is a wire bond pad provided on the temperature sense anode wiring 220. The field stop electrode 222 is connected to the N-type field stop layer 206 through a contact hole.

[0028] 1 , the first gate pad 215a is connected to the gate electrode 112 of the first switching element 110. The second gate pad 215b is connected to the gate electrode 122 of the second switching element 120. The Kelvin source pad 218 is connected to the Kelvin source electrode 113 of the first switching element 110 and the Kelvin source electrode 123 of the second switching element 120.

[0029] Furthermore, the control terminal 13 of the semiconductor device 10 is connected to the GND electrode pad 214, the gate wiring pad 217, the DESAT anode pad 219, and the temperature sense anode wiring pad 221. Specifically, the Kelvin source terminal 13k is connected to the GND electrode pad 214. The gate terminal 13g is connected to the gate wiring pad 217. The DESAT anode pad 219 is connected to the DESAT terminal 13d. The temperature sense anode wiring pad 221 is connected to the temperature sense anode terminal 13a.

[0030] In the wiring element 200 configured as described above, when the back electrode 208 is at a higher potential than the wire bond pads (GND electrode pad 214, first gate pad 215a, second gate pad 215b, gate wiring pad 217, Kelvin source pad 218, DESAT anode pad 219, and temperature sense anode wiring pad 221) formed on the upper surface of the wiring element 200, the back electrode 208 and the wire bond pads are electrically insulated from each other. This allows multiple switching elements 100 and the wiring element 200 to be mounted on the same base plate 11 using bonding material 15. Because there is no need to provide an insulating material between the wiring element 200 and the base plate 11, the number of components and manufacturing steps can be reduced, contributing to reduced manufacturing costs and improved layout flexibility for the semiconductor device 10.

[0031] In addition, the wiring element 200 is equipped with a temperature sensing diode 211 for overheat protection of the switching element 100 and a high-voltage diode for short-circuit protection (overcurrent protection), making it possible to reduce the number of components in the semiconductor device 10 while increasing its functionality.

[0032] Furthermore, by mounting the switching element 100 and the wiring element 200 on the base plate 11 using a bonding material 15 or adhesive with good thermal conductivity and by setting the gap between the switching element 100 and the wiring element 200 to about 1 mm, it is possible to minimize the delay in heat transfer from the switching element 100 to the wiring element 200. This improves the accuracy of temperature detection of the switching element 100 by the temperature sensing diode 211.

[0033] Furthermore, in the wiring element 200, the P-type anode layer 204, which is the anode region of the high-voltage diode, is separated from the P-type well 203, which is grounded through the GND electrode 213. This reduces the PN junction area in the high-voltage diode, making it possible to reduce the junction capacitance of the high-voltage diode and achieve faster short-circuit protection for the switching element 100.

[0034] <Second Embodiment> For example, in the case where the switching element 100 of the semiconductor device 10 is a MOSFET (SiC-MOSFET) made of silicon carbide (SiC), when a reflux current during inverter operation flows through a body diode (BD) of the MOSFET, crystal defects present in the drift layer and the SiC substrate may expand, which may lead to fluctuations in characteristics (hereinafter referred to as "BD degradation") such as an increase in on-voltage and an increase in leakage current between the drain and source.

[0035] Therefore, in the second embodiment, the semiconductor substrate 201 constituting the wiring element 200 is made of a wide-gap semiconductor, and a Schottky barrier diode (SBD) that can be used as a freewheel diode for the switching element 100 is mounted thereon.

[0036] 8 and 9 are configuration diagrams of a semiconductor device 10 according to the second embodiment. FIG. 8 is a plan view of the semiconductor device 10, and FIG. 9 is a cross-sectional view of the semiconductor device 10. Also, FIGS. 10 to 13 are configuration diagrams of a wiring element 200 provided in the semiconductor device 10 according to the second embodiment. FIG. 10 is a plan view of the wiring element 200, FIG. 11 is a plan view of a semiconductor substrate 201 that constitutes the wiring element 200, FIG. 12 is a cross-sectional view taken along line A1-A2 in FIG. 10, and FIG. 13 is a cross-sectional view taken along line B1-B2 in FIG. 10. Also, FIG. 14 shows a circuit diagram of the semiconductor device 10 including the wiring element 200.

[0037] The wiring element 200 according to the second embodiment has N － 13, the N type layer 202 is formed in a region where the N type well 203 is not formed and reaches the upper surface of the semiconductor substrate 201. － The GND electrode 213 is connected to the mold layer 202 via a Schottky connection. － The portion of the GND electrode 213 that is Schottky-connected to the type layer 202 serves as the SBD anode electrode 223. － Mold layer 202 and N ＋ The cathode layer 207 constitutes a Schottky barrier diode.

[0038] 8, the main terminal 12 is connected across the source electrode 111 of the first switching element 110, the source electrode 121 of the second switching element 120, and the SBD anode electrode 223 of the wiring element 200. As a result, the SBD anode electrode 223, N － Mold layer 202 and N ＋ The Schottky barrier diode formed by the cathode layer 207 is connected in parallel to the first switching element 110 and the second switching element 120 like the Schottky barrier diode Ds shown in FIG. 14, and functions as a freewheel diode.

[0039] According to the semiconductor device 10 of the second embodiment, the reflux current during inverter operation flows to the Schottky barrier diode as a freewheel diode, thereby suppressing BD degradation of the switching element 100. In other words, the wiring element 200 alone has the functions of detecting the temperature of the switching element 100, protecting it from short circuits, and suppressing BD degradation, which contributes to the miniaturization and high reliability of the semiconductor device 10. Furthermore, by using a wide-gap semiconductor for the semiconductor substrate 201 of the wiring element 200, stable characteristics can be achieved even at high temperatures.

[0040] Third Embodiment Figure 15 is a cross-sectional view showing the configuration of a wiring element 200 included in a semiconductor device 10 according to a third embodiment. The overall configuration of the semiconductor device 10 and the planar configuration of the wiring element 200 are the same as those of the second embodiment (Figures 8 to 10). Figure 15 is a cross-sectional view taken along line B1-B2 in Figure 10. The cross-sectional view taken along line A1-A2 in Figure 10 is the same as Figure 12.

[0041] In the wiring element 200 according to the third embodiment, as shown in FIG. 15, a plurality of P ＋ The SBD anode electrode 223, N － Mold layer 202, P ＋ Mold region 224 and N ＋ The cathode layer 207 constitutes a Schottky barrier diode with a JBS (Junction Barrier Schottky) structure.

[0042] In the semiconductor device 10 of the second embodiment, when a reverse bias is applied to the Schottky barrier diode in the wiring element 200, there is a concern that a leak current will occur due to the electric field concentrating at the interface of the Schottky junction, resulting in an unstable breakdown voltage. If the Schottky barrier diode in the wiring element 200 has a JBS structure as in the third embodiment, the electric field concentration point when a reverse bias is applied will be P ＋ Since the mold is located in the mold region 224, the occurrence of the above problem can be prevented.

[0043] <Fourth Embodiment> Fig. 16 is a plan view showing the configuration of a semiconductor device 10 according to a fourth embodiment. Also, Figs. 17 to 20 are configuration diagrams of a wiring element 200 provided in the semiconductor device 10 according to the fourth embodiment. Fig. 17 is a plan view of the wiring element 200, Fig. 18 is a plan view of a semiconductor substrate 201 constituting the wiring element 200, Fig. 19 is a cross-sectional view taken along line A1-A2 in Fig. 17, and Fig. 20 is a cross-sectional view taken along line B1-B2 in Fig. 17. Also, Fig. 21 shows a circuit diagram of the semiconductor device 10 including the wiring element 200.

[0044] In the wiring element 200 of the first embodiment, the GND electrode 213 (including the GND electrode pad 214 and the Kelvin source pad 218) is directly connected to the P-type well 203 formed in the semiconductor substrate 201. In contrast, in the wiring element 200 of the fourth embodiment, as shown in FIG. 19 , the GND electrode 213 is connected to the P-type well 203 via a current limiting resistor 225. The current limiting resistor 225 is made of polysilicon formed on the thermal oxide film 209, and has a resistance value of 50 Ω or more and 1000 Ω or less. The current limiting resistor 225 corresponds to the current limiting resistor Rcl shown in FIG. 21 .

[0045] In the semiconductor device 10 of the first embodiment, during the recovery operation of the switching element 100, part of the reflux current flows into the parasitic diode formed between the GND electrode 213 and the back electrode 208 of the wiring element 200, which may result in destruction of the wiring element 200.

[0046] In contrast, in the semiconductor device 10 of the fourth embodiment, the current limiting resistor 225 is interposed between the anode of the parasitic diode of the wiring element 200 and the GND electrode 213, so that the reflux current flowing into the parasitic diode during the recovery operation of the switching element 100 is suppressed to approximately several tens of milliamperes to several hundred milliamperes, thereby preventing destruction of the wiring element 200. Figure 22 is a graph showing the relationship between the forward current (IF)-forward voltage (VF) characteristics of the parasitic diode in the wiring element 200 and the resistance value of the current limiting resistor 225. From this graph, it can be seen that the reflux current flowing into the parasitic diode can be sufficiently suppressed by setting the resistance value of the current limiting resistor 225 to 50 Ω or more.

[0047] Furthermore, by setting the resistance value of the current limiting resistor 225 to be 50 Ω or more and 1000 Ω or less, even if the internal potential of the current limiting resistor 225 rises due to the displacement current flowing into the current limiting resistor 225 when the switching element 100 is turned off, the voltage applied to the thermal oxide film 209 can be suppressed to be equal to or less than the dielectric strength voltage of the thermal oxide film 209. Figure 23 is a graph showing the relationship between the voltage (internal potential) generated when the displacement current generated when the switching element 100 is turned off flows into the current limiting resistor, and the resistance value of the current limiting resistor 225. It can also be seen from this graph that the voltage generated in the current limiting resistor can be sufficiently suppressed by setting the resistance value of the current limiting resistor 225 to be 1000 Ω or less.

[0048] Fifth Preferred Embodiment Fig. 24 is a plan view showing the configuration of a semiconductor device 10 according to a fifth preferred embodiment. Figs. 25 and 26 are configuration diagrams of a wiring element 200 included in the semiconductor device 10 according to the fifth preferred embodiment. Fig. 25 is a plan view of the wiring element 200, and Fig. 26 is a cross-sectional view taken along line A1-A2 in Fig. 25. The plan view of a semiconductor substrate 201 constituting the wiring element 200 is the same as Fig. 18, and the cross-sectional view taken along line B1-B2 in Fig. 25 is the same as Fig. 20. Fig. 27 shows a circuit diagram of the semiconductor device 10 including the wiring element 200.

[0049] The configuration of the semiconductor device 10 of the fifth embodiment is such that the current limiting resistor 225 provided in the wiring element 200 of the fourth embodiment is replaced with a current limiting diode 226. That is, in the wiring element 200 of the fifth embodiment, as shown in FIG. 26 , the GND electrode 213 is connected to the P-type well 203 via the current limiting diode 226. The current limiting diode 226 is a Zener diode constituted by P-type polysilicon 226p and N-type polysilicon 226n formed on the thermal oxide film 209, with the P-type polysilicon 226p serving as the anode connected to the P-type well 203 side and the N-type polysilicon 226n serving as the cathode connected to the GND electrode 213 side. The current limiting diode 226 corresponds to the current limiting diode Dcl shown in FIG. 27 .

[0050] By interposing the current limiting diode 226 between the anode of the parasitic diode of the wiring element 200 and the GND electrode 213, the reflux current flowing into the parasitic diode during the recovery operation of the switching element 100 is suppressed, as in the fourth embodiment, and destruction of the wiring element 200 is prevented.

[0051] It should be noted that the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

[0052] The above description is illustrative in all respects, and it is understood that countless variations not illustrated can be envisioned.

[0053] 10 semiconductor device, 11 base plate, 12 main terminal, 13 control terminal, 13d DESAT terminal, 13k Kelvin source terminal, 13g gate terminal, 13a temperature sense anode terminal, 14 sealing resin, 15 bonding material, 16 wiring material, 100 switching element, 110 first switching element, 111 source electrode, 112 gate electrode, 113 Kelvin source electrode, 120 second switching element, 121 source electrode, 122 gate electrode, 123 Kelvin source electrode, 200 wiring element, 201 semiconductor substrate, 202 N － 203 P-type well; 204 P-type anode layer; 205 P-type guard ring; 206 N-type field stop layer; 207 N ＋type cathode layer, 208 back surface electrode, 209 thermal oxide film, 210a first gate resistor, 210b second gate resistor, 211 temperature sense diode, 211p P-type polysilicon, 211n N-type polysilicon, 212 interlayer insulating film, 213 GND electrode, 214 GND electrode, 215a first gate pad, 215b second gate pad, 216 gate wiring, 217 gate wiring pad, 218 Kelvin source pad, 219 DESAT anode pad, 220 temperature sense anode wiring, 221 temperature sense anode wiring pad, 222 field stop electrode, 223 SBD anode electrode, 224 P ＋ type region, 225 current limiting resistor, 226 current limiting diode, 226p P-type polysilicon, 226n N-type polysilicon, Dd DESAT diode, Dp parasitic diode, Dt temperature sense diode, Ds Schottky barrier diode, Dcl current limiting diode, Rg1 gate resistor, Rg2 gate resistor, Rcl current limiting resistor.

Claims

1. A semiconductor device comprising a base plate, a switching element and a wiring element joined to the base plate, wherein the wiring element includes a semiconductor substrate, an insulating film formed on the upper surface of the semiconductor substrate, a plurality of pads formed on the insulating film, a back surface electrode formed on the lower surface of the semiconductor substrate and joined to the base plate, a P-type well formed in the surface layer portion on the upper surface side of the semiconductor substrate, a GND electrode formed on the insulating film and electrically connected to the P-type well and one of the plurality of pads, which is a GND electrode pad, a P-type anode layer formed in the surface layer portion on the upper surface side of the semiconductor substrate and separated from the P-type well, and an overcurrent detection diode having, as an anode electrode, a DESAT anode pad which is one of the plurality of pads and is electrically connected to the P-type anode layer, and, as a cathode electrode, the back surface electrode, wherein the plurality of pads are electrically insulated from the back surface electrode in a state where the back surface electrode has a higher potential than the plurality of pads.

2. The semiconductor device according to claim 1, wherein the wiring element further includes a gate resistor made of polysilicon formed on the insulating film and connected to the gate electrode of the switching element through a gate pad which is one of the plurality of pads.

3. The semiconductor device according to claim 1 or 2, wherein the wiring element further includes a temperature sense diode made of polysilicon formed on the insulating film.

4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor substrate is formed of a wide-gap semiconductor, and the GND electrode is in Schottky connection with an N-type layer of the semiconductor substrate and is electrically connected to the source electrode of the switching element.

5. The semiconductor device according to claim 4, wherein a P-type region is partially formed in the N-type layer of the semiconductor substrate which is in Schottky connection with the GND electrode.

6. The semiconductor device according to any one of claims 1 to 5, wherein the GND electrode is connected to the P-type well through a current limiting resistor made of polysilicon formed on the insulating film.

7. The semiconductor device according to any one of claims 1 to 5, wherein the GND electrode is connected to the P-type well via a current limiting diode made of polysilicon formed on the insulating film.

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