Semiconductor device, and manufacturing method for same
The semiconductor device enhances connection reliability and miniaturization by using a connector with one end on the semiconductor element and the other end directly above a wiring member, addressing the complexity and size challenges in existing semiconductor packages.
Patent Information
- Application Number
- PCT/JP2024/046033
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-01-24
- Filing Date
- 2024-12-25
- Publication Date
- 2025-07-31
AI Technical Summary
Existing semiconductor packages face challenges in improving the reliability of connections between the semiconductor element encapsulated in the package and external circuits, particularly due to the complexity and size constraints imposed by the number of members and joining operations.
A semiconductor device design that incorporates a semiconductor package with a connector having one end joined to the semiconductor element and the other end directly above a wiring member, along with a reduced number of members and simplified joining operations, enhancing the reliability and miniaturization by using a clip or bonding wire as the connector.
The design improves connection reliability and reduces the size of the semiconductor device by minimizing the number of members and joining operations, while allowing for flexible arrangement and increased freedom in layout.
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Figure JP2024046033_31072025_PF_FP_ABST
Abstract
Description
Semiconductor device and manufacturing method thereof
[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.
[0002] Conventionally, various methods have been considered for mounting a semiconductor package in which a semiconductor element is sealed to an external circuit, etc. For example, Patent Document 1 describes a semiconductor package in which cross sections of bonding wires are exposed on the side surface. An external substrate is provided with a conductive rubber member that presses the semiconductor package against the side surface, and is responsible for fixing and electrically connecting (hereinafter sometimes simply referred to as "connection") the semiconductor package.
[0003] JP 2011-124341 A
[0004] The semiconductor package of Patent Document 1 has a bonding wire, one end of which is bonded to a semiconductor element, with its cross section exposed on the side of the semiconductor package to serve as a terminal. This reduces the number of components between the semiconductor element and the side of the semiconductor package, and is expected to improve the reliability of connections within the semiconductor package. However, there are cases where further improvement in reliability of connections to external circuits, etc. is required. The present invention has been made to solve this problem, and an object of the present invention is to provide a semiconductor device that improves the reliability of connections from a semiconductor element encapsulated in a semiconductor package to external circuits, etc.
[0005] In order to solve such problems, the semiconductor device of the present invention comprises a plurality of wiring members and a semiconductor package arranged on the wiring members and sealing a semiconductor element with a first sealing member, wherein the semiconductor package has a connector, one end of which is located on the semiconductor element and is joined to an electrode of the semiconductor element, and the other end of the connector is located directly above the wiring members.
[0006] According to the present invention, it is possible to provide a semiconductor device that improves the reliability of the connection from a semiconductor element sealed in a semiconductor package to an external circuit or the like.
[0007] 1A is a perspective view illustrating an outline of a semiconductor device according to a first embodiment; FIG. 1B is a perspective view illustrating a see-through sealing member in FIG. 1A; FIG. 2A is a perspective view illustrating a see-through sealing member in FIG. 2A; FIG. 3A is a plan view illustrating an outline of a portion of a semiconductor device according to a first embodiment; FIG. 4 is a bottom view illustrating an outline of a portion of a semiconductor device according to a first embodiment; FIG. 5 is a plan view illustrating an outline of a portion of a semiconductor device according to a first embodiment; FIG. 6 is a cross-sectional view taken along line IV-IV in FIG. 3A; FIG. 7 is a flowchart illustrating an outline of a manufacturing method according to a first embodiment; FIG. 8 is a perspective view illustrating an outline of a first metal plate and a wiring metal plate in a semiconductor package forming step in the manufacturing method according to a first embodiment; FIG. 9 is a perspective view illustrating an outline of a state in which a semiconductor element, a control IC, and a capacitor are arranged in a semiconductor package forming step in the manufacturing method according to a first embodiment; FIG. 10 is a perspective view illustrating an outline of a state in which connectors are arranged in a semiconductor package forming step in the manufacturing method according to a first embodiment; FIG. 11 is a perspective view illustrating an outline of a state in which a semiconductor device is sealed with a first sealing member in a semiconductor package forming step in the manufacturing method according to a first embodiment; 1 is a perspective view illustrating an outline of a state in which a semiconductor package is arranged in the manufacturing method of the first embodiment; FIG. 2 is a perspective view illustrating an outline of a state in which a semiconductor package is sealed with a second sealing member in the manufacturing method of the first embodiment; FIG. 3 is a cross-sectional view illustrating an outline of a part of a semiconductor device according to a second embodiment; FIG. 4 is a perspective view illustrating an outline of a state in which a second metal plate and a connector are arranged in a semiconductor package forming step in the manufacturing method of the second embodiment; FIG. 5 is a perspective view illustrating an outline of a state in which a semiconductor package is sealed with a first sealing member in a semiconductor package forming step in the manufacturing method of the second embodiment; FIG. 6 is a perspective view illustrating an outline of a state in which a semiconductor package is sealed with a second sealing member in the manufacturing method of the second embodiment.
[0008] The present invention will be described with reference to the drawings. Note that the present invention is not limited to these embodiments. In addition, in the drawings, some components may be omitted, and the size, shape, and positional relationship of each component may be exaggerated.
[0009] [Semiconductor Device (First Embodiment)] A semiconductor device 1 according to a first embodiment will be described with reference to FIGS. 1A to 4. The semiconductor device 1 is, for example, a bridge rectifier having a function similar to that of a known bridge diode, and can be used to full-wave rectify AC to obtain DC. As illustrated in FIG. 1A, the semiconductor device 1 is sealed with a second sealing member 7 and can be connected to the outside via a total of four connection pins 9, two for AC input and two for DC output. As illustrated in FIG. 1B, the semiconductor device 1 includes multiple wiring members 3 and semiconductor packages 5. The semiconductor device 1 can include multiple semiconductor packages 5, and here includes four semiconductor packages 5. The semiconductor device 1 also includes a second sealing member 7. Each component of the semiconductor device 1 will be described below.
[0010] (Wiring Member) The wiring member 3 is a member that connects the built-in electronic component to an external circuit or the like. Here, the wiring member 3 is a lead frame, and the built-in electronic component is a semiconductor package 5. The semiconductor device 1 includes a plurality of wiring members 3 that are separated from one another. Here, the number of wiring members 3 is four. One end side of each of the plurality of wiring members 3 is formed in a predetermined shape. Furthermore, the top surfaces of the one end sides of the plurality of wiring members 3 are on the same plane. The semiconductor package 5 is placed on these wiring members 3 on the one end side. This makes it easy to place the semiconductor package 5 on the wiring member 3. Note that the top surface is the surface on the upper side in FIG. 1B .
[0011] The other ends of the multiple wiring members 3 are arranged parallel to one another at a predetermined interval, forming connection pins 9. Here, the wiring member 3 is bent in a stepped manner from one end to the other end toward the side where the semiconductor package 5 is disposed, i.e., upward in FIG. 1B . The other end of the wiring member 3 extends linearly at a position higher than the top surface of the one end. The material of the wiring member 3 can be a metal such as gold, silver, or copper, or an alloy containing these, and is copper in this example. The shape of one end of the wiring member 3 and the spacing between the other ends can vary depending on the application.
[0012] (Semiconductor Package) The semiconductor package 5 is an electronic component in which a semiconductor element is sealed. The semiconductor package 5 is disposed on a wiring member 3, and the semiconductor element 50 is sealed by a first sealing member 80. The semiconductor package 5 has a plurality of terminals 40 on one side, with bonding surfaces exposed from the first sealing member 80, and is disposed so as to bridge between different wiring members 3. As illustrated in FIGS. 2A and 2B , the semiconductor package 5 is rectangular and has two terminals 40 on one side. The terminals 40 have bonding surfaces 40A exposed from the first sealing member 80. The semiconductor package 5 is a rectifying element that can determine the high / low voltage relationship between the two terminals 40 and switch between a conductive state and a non-conductive state. Note that the shape of the semiconductor package 5 is not limited to a rectangular parallelepiped shape.
[0013] 2B and 2C , the semiconductor package 5 includes a semiconductor element 50, a first metal plate 21, connectors 30, and terminals 40. Here, the semiconductor package 5 also includes a control IC 60 and a capacitor 70. These elements and components of the semiconductor package 5 are sealed with a first sealing member 80. The control IC 60 and capacitor 70 are disposed on a wiring metal plate 23 and connected to the semiconductor element 50. The wiring metal plate 23 has a plurality of metal pieces in a predetermined pattern and is a member that forms the wiring inside the semiconductor package 5. The wiring metal plate 23 can be made of the same material as the wiring member 3. Note that the pattern of the wiring metal plate 23 and the wiring inside the semiconductor package 5 are partially omitted in the drawings.
[0014] (Terminal) The terminal 40 is a member or a part of a member that serves as an entrance / exit on the semiconductor package 5 side for connection to an external circuit or the like. In this case, the external circuit or the like to be connected is the wiring member 3. The outer surface of the terminal 40 serves as a bonding surface 40A that is bonded to the wiring member 3, and the bonding surface 40A is exposed from the first sealing member 80.
[0015] (Semiconductor Element) The semiconductor element 50 is a circuit element formed on a semiconductor substrate. In this example, the semiconductor element 50 is a MOSFET that can switch between a conductive state and a non-conductive state using a gate voltage. The gate voltage is controlled by a control IC 60 to either a high level or a low level based on the voltage relationship between two terminals 40. The operating power supply voltage of the control IC 60 is maintained by a capacitor 70. The semiconductor element 50 has a first electrode 51 on a first surface 50A, which is the surface facing the wiring member 3 of the semiconductor device 1, and a second electrode 52 on a second surface 50B, which is the surface opposite the wiring member 3. The semiconductor element 50 performs switching between the first electrode 51 and the second electrode 52. The first surface 50A faces the surface of the semiconductor package 5 that has the terminals 40, and the second surface 50B is the surface opposite the first surface 50A.
[0016] (First Metal Plate) The first metal plate 21 is a member that serves as the terminal 40 of the semiconductor package 5. The semiconductor package 5 includes the first metal plate 21, which is bonded to the first electrode 51 of the semiconductor element 50 and faces the first electrode 51. As illustrated in FIG. 3A , the first metal plate 21 has a rectangular shape that is slightly larger than the semiconductor element 50 in a plan view and is a flat plate with a constant thickness. One surface of the first metal plate 21 faces the first electrode 51 of the semiconductor element 50 and is bonded to the wiring member 3. The other surface is exposed from the first sealing member 80 as the bonding surface 40A of the terminal 40 and is bonded to the wiring member 3. The first metal plate 21 is located directly above the wiring member 3. The first electrode 51 of the semiconductor element 50 is located directly above the wiring member 3 via the first metal plate 21. As illustrated in FIG. 4 , the first metal plate 21 is bonded to the first electrode 51 and the wiring member 3 via bonding members 90. The bonding members 90 are, for example, solder. The first metal plate 21 can be made of the same material as the wiring member 3 .
[0017] (Connector) The connector 30 is a member that relays the connection between the semiconductor element 50 and other members. As illustrated in FIGS. 3A and 3B , one end of the connector 30 is located on the semiconductor element 50. The connector 30 is bonded to an electrode of the semiconductor element 50, and the other end is located directly above the wiring member 3. As illustrated in FIGS. 2C and 4 , the connector 30 is a clip 31, one end 31A of which is located on the semiconductor element 50 and bonded to the second electrode 52. The clip 31 has a shape similar to a bent plate-like member. The clip 31 extends in a direction away from the semiconductor element 50 at the height of the second surface 50B, which is the upper surface of the semiconductor element 50 in FIG. 4 , and is bent downward in a stepped manner. The lower surface of the other end 31B of the clip 31 is at the same height as the lower surface of the first metal plate 21. This allows the lower surfaces of the first metal plate 21 and the other end 31B of the clip 31 to face parallel to the upper surfaces of different wiring members 3 that are on the same plane. The second sealing member 7 is omitted from FIGS. 3A to 3C and 4.
[0018] In the semiconductor package 5, the other end 31B of the clip 31, which is bonded to the second electrode 52, serves as another terminal 40. The outer surface of the semiconductor package 5 at the other end 31B of the clip 31, i.e., the lower surface, is a bonding surface 40A exposed from the first sealing member 80 and is bonded to the wiring member 3. The clip 31 makes surface contact with the wiring member 3, thereby widening the bonding surface. This reduces resistance, increases allowable current, and improves connection reliability. As illustrated in FIG. 4 , the clip 31 is bonded to both the second electrode 52 and the wiring member 3 via bonding members 90. The clip 31 can be made of the same material as the wiring member 3.
[0019] (First Sealing Member) The first sealing member 80 is a member that seals together the elements and the like that constitute the semiconductor package 5. The first sealing member 80 exposes the bonding surfaces 40A of the terminals 40 and forms the outer surface of the semiconductor package 5. The first sealing member 80 fills the interior of the semiconductor package 5 and provides a solid seal. This fixes the relative positional relationship between the semiconductor element 50, the control IC 60, the capacitor 70, the first metal plate 21, the wiring metal plate 23, and the clip 31. The material of the first sealing member 80 can be, for example, a thermosetting epoxy resin.
[0020] The surface of the semiconductor package 5 having two terminals 40 faces the wiring member 3, and the bonding surfaces 40A of the terminals 40 are bonded to the upper surface of the wiring member 3. As illustrated in Fig. 4, both ends of the semiconductor package 5 are bonded to two different wiring members 3. In this way, the semiconductor package 5 is located above the wiring members 3 and is arranged so as to bridge the spaced-apart wiring members 3.
[0021] (Second Sealing Member) The semiconductor device 1 may further include a second sealing member 7. The second sealing member 7 is a member that seals the wiring member 3 and the semiconductor package 5 together. Here, the second sealing member 7 seals one end of the wiring member 3 and the semiconductor package 5. The other end of the wiring member 3 is exposed from the second sealing member 7 and is arranged at a predetermined interval. The second sealing member 7 is filled so as to contact the first sealing member 80 of the semiconductor package 5 and the wiring member 3, thereby providing a solid seal. This makes it possible to fix the relative positional relationship between the semiconductor package 5 and the wiring member 3. The second sealing member 7 can be made of the same material as the first sealing member 80.
[0022] The first sealing member 80 does not seal the wiring member 3. The first sealing member 80 and the wiring member 3 may be in contact with each other or may be spaced apart. The first sealing member 80 and the second sealing member 7 are in contact with each other, with a boundary surface at the outer surface of the semiconductor package 5. The arrangement that bridges different wiring members 3 may be such that the wiring members 3 to which the semiconductor package 5 is bonded are adjacent to each other, as exemplified in FIG. 3B, or such that another wiring member 3 is present between the bonded wiring members 3, as exemplified in FIG. 3C. In either case, the bonding surface 40A is included in the wiring member 3 in a plan view.
[0023] In the semiconductor device 1 having the above configuration, the semiconductor package 5 has a connector 30, one end of which is located on the semiconductor element 50 and is bonded to an electrode of the semiconductor element 50, and the other end of the connector 30 is located directly above the wiring member 3, thereby reducing the number of components and the number of bonding operations from the semiconductor element 50 to the position directly above the wiring member 3. Furthermore, a cross-sectional area can be increased from the position directly above the wiring member 3 to the wiring member 3, allowing connection to the wiring member 3, thereby improving the reliability of connections from the semiconductor element to external circuits, etc. In the semiconductor device 1, the semiconductor package 5 has, on one side thereof, multiple terminals 40, whose bonding surface 40A is exposed from the first sealing member 80, and which are arranged to bridge between different wiring members 3, thereby improving the degree of freedom in the arrangement (layout) of elements and components within the semiconductor device.
[0024] The semiconductor device 1 includes a semiconductor package 5 in which the semiconductor element 50 and the connector 30 are sealed with a first sealing member 80, thereby fixing the relative positions of the semiconductor element 50 and the connector 30 and improving connection reliability. The semiconductor device 1 has a clip 31, one end of which is located on the semiconductor element 50 and joined to an electrode of the semiconductor element 50, as the connector 30, and the other end of which serves as a terminal of the semiconductor package 5, thereby reducing the number of members and the number of joints from the semiconductor element 50 to the wiring member 3 and further improving reliability.
[0025] In the past, a member such as clip 31 was provided outside the semiconductor package, with one end of the clip attached to a terminal on the top surface of the semiconductor package and the other end attached to a wiring member at the same height as the bottom surface of the semiconductor package. In this case, the clip became large, making the semiconductor device larger and imposing significant limitations on layout. In the semiconductor device 1, by including clip 31 in the semiconductor package 5, layout freedom is improved and the semiconductor device can be made smaller.
[0026] Furthermore, the semiconductor package is formed to a height that allows it to encapsulate other elements, such as a capacitor 70, that are thicker than the semiconductor element 50. Therefore, if a terminal is provided on the top surface of the semiconductor package, a separate member is required to connect the terminal to the second electrode 52 of the semiconductor element 50. The semiconductor device 1 includes the clip 31 in the semiconductor package 5, eliminating the need for terminals on the top surface of the semiconductor package, thereby reducing the number of components and making the semiconductor package more compact. The semiconductor device 1 includes multiple terminals on one surface of the semiconductor package 5 that expose their bonding surfaces from the first sealing member 80 and are arranged to bridge between different wiring members 3, allowing the semiconductor package 5 to be bonded to the wiring members 3 below itself, thereby reducing the layout area.
[0027] [Method for Manufacturing Semiconductor Device (First Embodiment)] Next, a method for manufacturing a semiconductor device S1 according to a first embodiment will be described with reference to FIGS. 5 to 7C. As illustrated in FIG. 5, the method for manufacturing a semiconductor device S1 includes a wiring member preparation step S10, a semiconductor package formation step S21, and an arrangement step S30, and further includes a sealing step S40. Each component of the method for manufacturing a semiconductor device S1 will be described below. Note that the wiring member preparation step S10 and the semiconductor package formation step S21 can be performed independently in parallel, and may be performed before the arrangement step S30. Below, the semiconductor package formation step S21 and the wiring member preparation step S10 will be described in that order.
[0028] (Semiconductor Package Forming Process) The semiconductor package forming process S21 is a process of sealing a semiconductor element 50 with a first sealing member 80 to form a semiconductor package 5 to be placed on the wiring member 3. The semiconductor package forming process S21 seals a semiconductor element 50, which has a first electrode 51 and a second electrode 52 on opposite sides, with the first sealing member 80 to form a semiconductor package 5 having a plurality of terminals 40 on one side, with a bonding surface 40A exposed from the first sealing member 80. The semiconductor package 5 has a first metal plate 21 bonded to the first electrode 51 and a connector 30, one end of which is located on the semiconductor element 50 and bonded to the second electrode 52, and the other ends of the first metal plate 21 and the connector 30 are terminals 40. In this case, the connector 30 is a clip 31. The semiconductor package forming process S21 includes a metal plate preparing process, an element arranging process, and an element sealing process.
[0029] The metal plate preparation process is a process of preparing a first metal plate 21 and a wiring metal plate 23. FIG. 6A illustrates an example of the first metal plate 21 and the wiring metal plate 23 included in one semiconductor package 5. This will be described as a set of metal plates. The wiring metal plate 23 is composed of multiple metal pieces separated from each other. In the metal plate preparation process, the first metal plate 21 and the wiring metal plate 23 are prepared while the relative positional relationship of the set of metal plates is fixed. For example, the metal plate preparation process may be performed by extending portions of the metal pieces of the first metal plate 21 and the wiring metal plate 23 to form extended portions, and then connecting the extended portions to each other to prepare an integrated metal plate connected body. The metal plate connected body may also connect multiple sets of metal plates. After the element encapsulation process, a package singulation process may be performed in which the extended portions exposed from the first encapsulation member 80 are cut to separate the semiconductor packages 5.
[0030] The element placement process is a process of placing the semiconductor element 50, control IC 60, and capacitor 70 on the prepared first metal plate 21 and wiring metal plate 23, and then placing the clip 31. As illustrated in FIG. 6B , the semiconductor element 50 is placed on the first metal plate 21 with the first surface 50A having the first electrode 51 facing the first metal plate 21. Before placing the semiconductor element 50, a bonding material in paste form is applied to the first metal plate 21. The bonding material in paste form is, for example, cream solder. Furthermore, the bonding material in paste form is applied to the wiring metal plate 23, and the control IC 60 and capacitor 70 are placed on it.
[0031] Next, a pasty bonding material is applied to the second electrode 52 on the second surface 50B of the semiconductor element 50, which is the upper surface in Fig. 6B. Then, as illustrated in Fig. 6C, one end 31A is positioned on the second surface 50B, and the clip 31 is placed so that it faces the second electrode 52. Next, the pasty bonding material is melted by a reflow method to bond the first metal plate 21 and the clip 31 to the semiconductor element 50, and to bond the wiring metal plate 23 to the control IC 60 and the capacitor 70.
[0032] The element encapsulation process is a process of encapsulating the first metal plate 21, wiring metal plate 23, semiconductor element 50, control IC 60, capacitor 70, and clip 31 with a first encapsulating member 80. In the element encapsulation process, the first encapsulating member 80 is melted before hardening, covers the first metal plate 21 and other components joined in the element placement process, and is then shaped using a rectangular parallelepiped mold or the like and hardened. Note that the extended portions of the metal plate connection body are exposed during encapsulation. The lower surface of the first metal plate 21 and the lower surface of the other end 31B of the clip 31 are surfaces to be bonded to the terminals of the semiconductor package 5 and are exposed from the first encapsulating member 80. Note that the lower surface is the lower surface in FIG. 6C .
[0033] In the metal plate assembly, an extended portion is exposed from the hardened first sealing member 80, and a package singulation process is performed to cut this extended portion. Then, as shown in Figure 6D, a semiconductor package 5 having a rectangular parallelepiped outer shape is obtained, completing the semiconductor package formation process S21. The semiconductor package 5 has two electrodes on its underside, with the electrode bonding surfaces exposed.
[0034] (Wiring Member Preparation Step) The wiring member preparation step S10 is a step of fixing and preparing multiple wiring members 3. FIG. 7A illustrates multiple wiring members 3 included in the semiconductor device 1. Here, the multiple wiring members 3 are four lead frames separated from one another. This will be described as a set of wiring members 3. In the wiring member preparation step S10, the wiring members 3 are prepared in a state in which the relative positional relationship of the set of wiring members 3 is fixed. For example, the other end sides 3B of the wiring members 3 can be extended to form extended portions, and the extended portions can be connected to each other to prepare an integrated wiring member linked body. The wiring member linked body may also be formed by connecting multiple sets of wiring members 3. When preparing a wiring member linked body, the arrangement step S30 is performed in the state of the wiring member linked body, and after the sealing step S40, a singulation step is performed in which the wiring member linked body is cut at positions that will become the ends of the wiring members 3 to singulate the semiconductor devices 1. It should be noted that the extending wiring member 3 may have other connected portions in addition to the other end side 3B, and these portions can also be cut in the singulation step.
[0035] (Placement Process) The placement process S30 is a process of placing semiconductor packages 5 on the wiring member 3. In the placement process S30, the semiconductor packages 5 are placed on one end side 3A of the wiring member 3 so that the surfaces having terminals of the semiconductor packages 5 face the wiring member 3 and bridge different wiring members 3. As illustrated in FIG. 7B , four semiconductor packages 5 are placed on the upper surface of the wiring member 3 with the surfaces having terminals facing the wiring member 3. Before placing the semiconductor packages 5, a bonding material in paste form is applied to the upper surface of the wiring member 3. Then, the bonding material in paste form is melted by a reflow method to bond the wiring member 3 and the semiconductor packages 5.
[0036] (Sealing Process) The sealing process S40 is a process of sealing one end side 3A of the wiring member 3 and the semiconductor package 5 with a second sealing member 7. In the sealing process S40, the unhardened second sealing member 7 is melted to cover the one end side 3A of the wiring member 3 and the semiconductor package 5 joined in the placement process S30, and then molded using a mold or the like of a predetermined shape and hardened. The other end side 3B of the wiring member 3 is exposed from the hardened second sealing member 7. If a wiring member connected body is prepared, the other end side 3B is extended and connected. In this case, a singulation process is performed in which the other end side 3B is cut to a predetermined length. Any other connected portions are also cut. Note that FIG. 7C illustrates an example of the semiconductor device 1 after singulation.
[0037] The manufacturing method S1 of a semiconductor device having the above configuration forms a semiconductor package 5 having a plurality of terminals on one side, and positions the semiconductor package 5 so that the side having the terminals faces the wiring member 3 and bridges between different wiring members 3. This allows the semiconductor package 5 to be smoothly bonded to lead frames that are spaced apart by a reflow method. Even when the semiconductor package 5 has two terminals 40, bonding to the spaced apart wiring member 3 can be smoothly performed, improving connection reliability. Furthermore, by positioning one end of the semiconductor package 5 on the semiconductor element 50 and using the other end of the clip 31 that is bonded facing the second electrode 52 as a terminal, the number of components and the number of bonding steps can be reduced to form the terminal, improving connection reliability.
[0038] As mentioned above, in the past, a member such as the clip 31 was sometimes provided outside the semiconductor package. In this case, there was a problem that misalignment was likely to occur when the wiring member, the semiconductor package, and one end of the clip were stacked in this order and joined by a reflow method. In the semiconductor device manufacturing method S1, by providing the clip 31 in the semiconductor package 5, the relative positional relationship between the semiconductor element 50 and the clip 31 is fixed, preventing misalignment and improving the reliability of the connection.
[0039] [Semiconductor Device (Second Embodiment)] Next, a semiconductor device 2 according to a second embodiment will be described with reference to FIGS. 8 to 9C. The semiconductor device 2 differs from the semiconductor device 1 of the first embodiment in that it includes a semiconductor package 6 instead of the semiconductor package 5, but is otherwise the same. The semiconductor package 6 will now be described. As illustrated in FIG. 8, the connectors 30 of the semiconductor package 6 are bonding wires 32 rather than clips. The semiconductor package 6 also includes a second metal plate 22 as another of the terminals 40. The semiconductor package 6 is otherwise the same as the semiconductor package 5. Note that the second sealing member 7 is not shown in FIG. 8.
[0040] (Bonding Wire) The bonding wire 32 is the connector 30 in the semiconductor package 6. One end 32A of the bonding wire 32 is located on the semiconductor element 50 and is bonded to the second electrode 52. The other end 32B of the bonding wire 32 is bonded to the second metal plate 22. The other end 32B is located directly above the wiring member 3. The bonding wire 32 may be a known bonding wire used for connections in the semiconductor field.
[0041] (Second Metal Plate) The second metal plate 22 is a member that becomes the terminal 40 of the semiconductor package 6. Here, the second metal plate 22 is rectangular in plan view and has a flat plate shape with a constant thickness. A bonding wire 32 is bonded to one surface of the second metal plate 22, which is the top surface in FIG. 8 . The other surface is the outer surface of the semiconductor package 6, is exposed from the first sealing member 80 as the bonding surface 40A of the terminal 40, and is bonded to the wiring member 3 while facing the wiring member 3. The second metal plate 22 is located directly above the wiring member 3. The other end 32B of the bonding wire 32 is located directly above the wiring member 3 via the second metal plate 22. The lower surface of the second metal plate 22 is at the same height as the lower surface of the first metal plate 21. This allows the lower surfaces of the first metal plate 21 and the second metal plate 22 to face parallel to the upper surfaces of different wiring members 3 that are on the same plane.
[0042] The shape, thickness, and placement position of the second metal plate 22 can be adjusted to match the shape and placement of the wiring member 3. Furthermore, by adjusting the shape and position of the second metal plate 22 so that the semiconductor package 6 is small, and by adjusting the shape, etc. of the wiring member 3 to match the semiconductor package 6, it is possible to reduce the size of the semiconductor device 2. The second metal plate 22 is joined to the wiring member 3 via a joining member 90. The second metal plate can be made of the same material as the wiring member 3.
[0043] In the semiconductor device 2, the semiconductor package 6 has a second metal plate 22 as another of the terminals, and the connector 30 is a bonding wire 32, one end of which is located on the semiconductor element 50 and bonded to an electrode of the semiconductor element 50, and the other end of which is bonded to the second metal plate. This increases the degree of freedom in terminal arrangement and allows for flexible adaptation to the shape and arrangement of the wiring member 3, while improving reliability as in the first embodiment. This also enables further miniaturization of the semiconductor package 6, allowing for adjustment of the shape and arrangement of the wiring member 3 to achieve miniaturization of the semiconductor device. Furthermore, by using the second metal plate 22 as the terminal 40 in the semiconductor package 6, even when the connector 30 is a bonding wire 32, it is possible to bond with the wiring member 3 over a wide area, improving the reliability of the connection with the wiring member 3. Furthermore, inside the semiconductor package 6, the bonding wire 32 and the second metal plate 22 are fixed and protected by the first sealing member 80. This allows the semiconductor device 2 to increase the degree of freedom in terminal arrangement of the semiconductor package while improving the reliability of the connection.
[0044] [Semiconductor Device Manufacturing Method (Second Embodiment)] Next, a semiconductor device manufacturing method S2 according to a second embodiment will be described with reference to FIGS. 5 and 9A to 9C . The semiconductor device manufacturing method S2 differs from the semiconductor device manufacturing method S1 of the first embodiment in that it includes a semiconductor package forming step S22 instead of the semiconductor package forming step S21, but is otherwise the same. Therefore, the semiconductor package forming step S22 will be described. As in the first embodiment, the wiring member preparing step S10 and the semiconductor package forming step S22 can be performed independently in parallel, and may be performed before the placement step S30. As in the first embodiment, the semiconductor package forming step S22 encapsulates a semiconductor element 50 having a first electrode 51 and a second electrode 52 on opposite sides with a first sealing member 80 to form a semiconductor package 6 having a plurality of terminals 40 on one side, the bonding surface 40A of which is exposed through the first sealing member 80.
[0045] The semiconductor package 6 to be formed includes a first metal plate 21 bonded to the first electrode 51, a connector 30 having one end located on the semiconductor element 50 and bonded to the second electrode 52, and a second metal plate 22 to which the other end of the connector 30 is bonded, the first metal plate 21 and the second metal plate 22 being terminals 40. Here, the connector 30 is a bonding wire 32. As with the first embodiment, the semiconductor package formation process S22 of the second embodiment includes a metal plate preparation process, an element placement process, and an element encapsulation process, and may also include a package singulation process. Of these, the metal plate preparation process, element placement process, and element encapsulation process are different from those of the first embodiment, but the rest are common.
[0046] 9A , in the metal plate preparation step of the second embodiment, a second metal plate 22 is prepared in addition to a first metal plate 21 and a wiring metal plate 23. Here, the second metal plate 22 is disposed at the position of the other end of the clip in the semiconductor package 5 of the first embodiment. The second metal plate 22 may also be disposed at a position different from the other end of the clip. A portion of the second metal plate 22 may also be extended to form an extended portion, and the extended portion may be connected to the first metal plate 21 or the wiring metal plate 23 to form a metal plate combination. Note that the first metal plate 21 and the wiring metal plate 23 are similar to the metal plate preparation step of the first embodiment.
[0047] 9B , the element placement process of the second embodiment is different from that of the first embodiment in that bonding wires 32 are placed instead of clips, but the rest is common. One end of the bonding wire 32 is bonded to the second electrode 52 of the semiconductor element 50. The other end is bonded to the upper surface of the second metal plate 22. As in the first embodiment, the first metal plate 21 and the semiconductor element 50 are bonded by a reflow method, and the wiring metal plate 23 is bonded to the control IC 60 and the capacitor 70. In the element sealing process of the second embodiment, the lower surface of the second metal plate 22 is exposed from the first sealing member 80 instead of the lower surface of the other end of the clip. The rest is common to the first embodiment.
[0048] Then, as illustrated in Figure 9C, the formed semiconductor package 6 is placed on the wiring member 3, and one end side of the wiring member 3 and the semiconductor package 6 are sealed with a second sealing member 7 to form the semiconductor device 2 according to the second embodiment.
[0049] In the semiconductor device manufacturing method S2, the position of the second metal plate 22 can be changed in the semiconductor package forming step S22, and changes in the shape and arrangement of the wiring member 3 can be easily accommodated.
[0050] The semiconductor device is not limited to a bridge rectifier, and the semiconductor package does not have to be a rectifying element. The semiconductor device may have only one semiconductor package, not multiple ones. The semiconductor package may have three or more terminals, and may have both a clip and a bonding wire. The wiring member may also be provided on an insulating substrate. In this case, the second sealing member can be omitted. Instead of sealing with the second sealing member, one end of the wiring member and the semiconductor package may be sealed in a hollow space using an insulating substrate and a cap-shaped member or the like.
[0051] REFERENCE SIGNS LIST 1 Semiconductor device (first embodiment) 2 Semiconductor device (second embodiment) 3 Wiring member 5 Semiconductor package (first embodiment) 6 Semiconductor package (second embodiment) 7 Second sealing member 9 Connection pin 21 First metal plate 22 Second metal plate 23 Wiring metal plate 30 Connector 31 Clip 32 Bonding wire 40 Terminal 50 Semiconductor element 51 First electrode 52 Second electrode 60 Control IC 70 Capacitor 80 First sealing member 90 Bonding member
Claims
1. A semiconductor device comprising: a plurality of wiring members; and a semiconductor package disposed on the wiring members and sealing a semiconductor element with a first sealing member, wherein the semiconductor package has a connector having one end located on the semiconductor element and joined to an electrode of the semiconductor element, and the other end of the connector is located directly above the wiring member.
2. The semiconductor device according to claim 1, wherein the semiconductor package has a plurality of terminals exposing a bonding surface from the first sealing member on one surface side, and is arranged to bridge between different ones of the wiring members.
3. The semiconductor device according to claim 2, wherein the semiconductor element has a first electrode on a surface on the wiring member side, and the semiconductor package has a first metal plate joined facing the first electrode as one of the terminals.
4. The semiconductor device according to claim 3, wherein the semiconductor element has a second electrode on a surface opposite to the wiring member side, and the semiconductor package has the other end of the connector joined to the second electrode as the other one of the terminals.
5. The semiconductor device according to claim 3, wherein the semiconductor element has a second electrode on a surface opposite to the wiring member side, the semiconductor package has a second metal plate as the other one of the terminals, and the other end of the connector is joined to the second metal plate.
6. The semiconductor device according to any one of claims 1 to 5, further comprising a second sealing member for sealing one end side of the wiring member and the semiconductor package, wherein the semiconductor package is disposed on one end side of the wiring member, and the other end side of the wiring member is exposed from the second sealing member and arranged side by side at a predetermined interval.
7. The semiconductor device according to claim 6, comprising a plurality of the semiconductor packages.
8. A method for manufacturing a semiconductor device, comprising: a wiring member preparation step of fixing and preparing a plurality of wiring members; a semiconductor package formation step of sealing a semiconductor element having a first electrode and a second electrode on opposite surfaces with a first sealing member to form a semiconductor package having a plurality of terminals with a bonding surface exposed from the first sealing member on one surface side; and an arrangement step of arranging the semiconductor package on one end side of the wiring members so that a surface having the terminals faces the wiring members and bridges between different wiring members, wherein the semiconductor package has a first metal plate bonded to face the first electrode and a connector having one end located on the semiconductor element and bonded to face the second electrode, and the other ends of the first metal plate and the connector are used as the terminals.
9. A method for manufacturing a semiconductor device, comprising: a wiring member preparation step of fixing and preparing a plurality of wiring members; a semiconductor package formation step of sealing a semiconductor element having a first electrode and a second electrode on opposite surfaces with a first sealing member to form a semiconductor package having a plurality of terminals with a bonding surface exposed from the first sealing member on one surface side; and an arrangement step of arranging the semiconductor package on one end side of the wiring members so that a surface having the terminals faces the wiring members and bridges between different wiring members, wherein the semiconductor package has a first metal plate bonded to face the first electrode, a connector having one end located on the semiconductor element and bonded to the second electrode, and a second metal plate to which the other end of the connector is bonded, and the first metal plate and the second metal plate are used as the terminals.
10. The method for manufacturing a semiconductor device according to claim 8 or claim 9, further comprising a sealing step of sealing one end side of the wiring members and the semiconductor package with a second sealing member.
Citation Information
Patent Citations
Semiconductor device and mounting method thereof
JP2002040095A
Semiconductor device
JP2005217072A