Semiconductor device and electronic apparatus

Abstract

The present invention relates to a semiconductor device and an electronic apparatus capable of miniaturizing pixels. This semiconductor device includes first and second transistors formed on an upper part of a semiconductor substrate and connected in series. Channels of the first and second transistors are formed above the semiconductor substrate. A source of the first transistor and a drain of the second transistor are formed in one semiconductor region above the semiconductor substrate. The technology disclosed herein can be applied to, for example, a light detection device or the like that photoelectrically converts incident light and outputs a signal corresponding to the amount of received light.

Description

Semiconductor devices and electronic devices

[0001] The present disclosure relates to a semiconductor device and an electronic device, and more particularly to a semiconductor device and an electronic device that enable miniaturization of pixels.

[0002] CMOS image sensors, which read out signal charges accumulated in photodiodes via MOS transistors, are mainly used as imaging elements in cameras on mobile devices such as smartphones. CMOS image sensors for mobile devices are required to be compact yet capable of capturing high-quality images in a variety of scenes. To achieve a high pixel count of tens of megapixels, pixel size must be miniaturized to 1.0 μm or less.

[0003] In order to accommodate miniaturization of pixel size, for example, Patent Document 1 discloses a solid-state imaging device that employs a stacked structure of two substrates, in which a photodiode and a transfer transistor are formed on a first substrate, an amplification transistor that reads out the photodiode, a selection transistor, etc. are formed on a second substrate, and the first substrate and the second substrate are bonded together.

[0004] International Publication No. 2019 / 131965

[0005] There is a demand for a structure that allows pixels to be miniaturized, not just a stacked structure in which multiple substrates are stacked.

[0006] The present disclosure has been made in view of the above circumstances, and aims to enable miniaturization of pixels in a pixel structure formed on a single substrate.

[0007] A semiconductor device according to a first aspect of the present disclosure includes first and second transistors formed on an upper portion of a semiconductor substrate and connected in series, wherein channels of the first and second transistors are formed above the semiconductor substrate, and a source of the first transistor and a drain of the second transistor are formed in a single semiconductor region above the semiconductor substrate.

[0008] An electronic device according to a second aspect of the present disclosure comprises a semiconductor device having first and second transistors formed on an upper portion of a semiconductor substrate and connected in series, wherein channels of the first and second transistors are formed above the semiconductor substrate, and a source of the first transistor and a drain of the second transistor are formed in a single semiconductor region above the semiconductor substrate.

[0009] In the first and second aspects of the present disclosure, first and second transistors are formed on an upper portion of a semiconductor substrate and connected in series, the channels of the first and second transistors are formed above the semiconductor substrate, and the source of the first transistor and the drain of the second transistor are formed in a single semiconductor region above the semiconductor substrate.

[0010] The semiconductor device and electronic device may be an independent device or a module incorporated into another device.

[0011] 1 is a diagram illustrating a schematic configuration of a photodetection device to which the technology of the present disclosure is applied; FIG. 2 is a diagram illustrating an example of a circuit configuration of each pixel of the photodetection device; FIG. 3 is a cross-sectional view showing a first pixel structure of a pixel of the photodetection device; FIG. 4 is a plan view showing the first pixel structure of the photodetection device; FIG. 5 is a cross-sectional view showing a first modified example of the first pixel structure; FIG. 6 is a cross-sectional view showing a second modified example of the first pixel structure; FIG. 7 is a cross-sectional view showing a third modified example of the first pixel structure; FIG. 8 is a cross-sectional view showing a second pixel structure of a pixel of the photodetection device; FIG. 9 is a cross-sectional view showing a third pixel structure of a pixel of the photodetection device; FIG. 10 is a cross-sectional view showing a modified example of the third pixel structure; FIG. 11 is a cross-sectional view showing a fourth pixel structure of a pixel of the photodetection device; FIG. 12 is a cross-sectional view showing a fifth pixel structure of a pixel of the photodetection device; FIG. 13 is a cross-sectional view showing a sixth pixel structure of a pixel of the photodetection device; FIG. 14 is a plan view showing the sixth pixel structure of a pixel of the photodetection device; FIG. 15 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure; FIG. 16 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure; FIG. 17 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure; 1 is a diagram illustrating a method for manufacturing a pixel according to a first pixel structure. FIG. 2 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure. FIG. 3 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure. FIG. 4 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure. FIG. 5 is a diagram illustrating a method for manufacturing a pixel according to the first pixel structure. FIG. 6 is a diagram illustrating an example of the schematic configuration of a photodetector configured with a stacked structure of three substrates. FIG. 7 is a diagram illustrating an example of the configuration of a sensor pixel and a readout circuit. FIG. 8 is a block diagram illustrating an example of the configuration of an electronic device. FIG. 9 is a diagram illustrating an example of the use of an image sensor. FIG. 10 is a diagram illustrating an example of the schematic configuration of an endoscopic surgery system. FIG. 11 is a block diagram illustrating an example of the functional configuration of a camera head and a CCU. FIG. 12 is a block diagram illustrating an example of the schematic configuration of a vehicle control system. FIG. 13 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0012] Modes for carrying out the technology of the present disclosure (hereinafter referred to as embodiments) will be described below with reference to the accompanying drawings. The description will be given in the following order: 1. Example of a schematic configuration of a photodetector 2. Equivalent circuit of a pixel 3. First pixel structure 4. First modified example of the first pixel structure 5. Second modified example of the first pixel structure 6. Third modified example of the first pixel structure 7. Second pixel structure 8. Third pixel structure 9. Modified example of the third pixel structure 10. Fourth pixel structure 11. Fifth pixel structure 12. Sixth pixel structure 13. Manufacturing method of the first pixel structure 14. Summary 15. Example of a stacked configuration using multiple substrates 16. Example of a configuration of an electronic device 17. Example of use of an image sensor 18. Example of application to an endoscopic surgery system 19. Example of application to a moving body

[0013] In this specification and drawings, identical or similar parts are denoted by identical or similar reference numerals, and redundant explanations are omitted as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, there may be parts in which the dimensional relationships and ratios differ between the drawings.

[0014] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted.

[0015] In the drawings described below, regarding the p-type impurity concentration, "p+" indicates that the impurity concentration is higher than "p." Regarding the n-type impurity concentration, "n+" indicates that the impurity concentration is higher than "n."

[0016] While the technology disclosed herein can be applied to semiconductor devices in general, the following describes an example in which the technology disclosed herein is applied to a photodetector having a pixel array in which pixels are arranged two-dimensionally in a matrix, which photoelectrically converts incident light and outputs a signal corresponding to the amount of received light. The light detected by the photodetector as the target of photoelectric conversion may be light in the visible light range including wavelengths such as R (Red), G (Green), and B (Blue), or light in the non-visible light range such as infrared light. Alternatively, the light may be light in both the visible and non-visible light ranges. The photodetector can be used as a solid-state imaging device that generates and outputs an image signal corresponding to the amount of incident light, or as a light receiving device (ranging sensor) in a ranging system that receives light (reflected light) that is emitted as active light from an object and reflects infrared light off the object, thereby measuring the distance to the object using a direct ToF or indirect ToF method.

[0017] 1. Schematic Configuration Example of Photodetector> FIG. 1 is a diagram showing a schematic configuration of a photodetector to which the technology of the present disclosure is applied.

[0018] 1 is configured to include a pixel array section 3 in which pixels 2 are arranged two-dimensionally in a matrix on a semiconductor substrate 21 made of, for example, silicon (Si) as a semiconductor, and a peripheral circuit section around the pixel array section 3. The peripheral circuit section includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc.

[0019] The pixel 2 includes a photodiode, which is a photoelectric conversion unit, and a plurality of pixel transistors, each of which is made up of, for example, a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is made up of a MOS transistor (MOS FET).

[0020] The pixels 2 may also have a shared pixel structure. This shared pixel structure is composed of multiple photodiodes, multiple transfer transistors, one shared floating diffusion, and one other pixel transistor each. That is, in the shared pixel structure, a photodiode and a transfer transistor are disposed in each pixel 2, and the other pixel transistors are shared by multiple pixels 2.

[0021] The control circuit 8 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0022] The vertical drive circuit 4 is configured by, for example, a shift register, selects a predetermined pixel drive wiring 10, supplies a pulse for driving the pixels 2 to the selected pixel drive wiring 10, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 selects and scans each pixel 2 of the pixel array unit 3 row by row in the vertical direction, and supplies a signal based on a signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 9.

[0023] The column signal processing circuits 5 are arranged for each column of pixels 2, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 2. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) for removing fixed pattern noise specific to each pixel and AD conversion.

[0024] The horizontal drive circuit 6 is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in turn, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0025] The output circuit 7 processes and outputs signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11. The output circuit 7 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0026] The photodetector 1 configured as described above has a structure known as a column AD system, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged for each column. The photodetector 1 generates a signal corresponding to the amount of light received by each pixel 2 in the pixel array section 3 and outputs the signal to the outside. The photodetector 1 can be used, for example, as a solid-state imaging device that detects the distribution of incident light amounts of infrared light or visible light and captures an image, or as a light receiving device in a distance measurement system that receives light (reflected light) that is irradiated as active light from an object and reflects it, using a direct ToF system or an indirect ToF system to measure the distance to the object.

[0027] 2. Equivalent Circuit of Pixel> FIG. 2 shows an equivalent circuit of the pixel 2.

[0028] The pixel 2 includes, for example, a photodiode PD as a photoelectric conversion unit, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG. The pixel 2 also includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are each configured, for example, by an n-type MOS transistor (MOS FET).

[0029] The photodiode PD photoelectrically converts incident light and generates an electric charge (signal charge) according to the amount of incident light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TG, and the anode is electrically connected to a reference potential line (e.g., ground).

[0030] The transfer transistor TG controls the transfer of charges generated in the photodiode PD. When the transfer transistor TG is turned on, it transfers the charges generated in the photodiode PD to the floating diffusion FD. The drain of the transfer transistor TG is electrically connected to the floating diffusion FD, and the gate is electrically connected to a pixel drive wiring. This pixel drive wiring is part of the pixel drive wiring 10 described in FIG. 1.

[0031] The floating diffusion FD is a charge storage unit that temporarily stores the charge transferred from the photodiode PD, and a charge-voltage converter that generates a voltage according to the amount of charge. The floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the reset transistor RST.

[0032] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive wiring supplied to its gate, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. This pixel drive wiring is part of the pixel drive wiring 10 described in FIG. 1. When the potential of the floating diffusion FD is reset, the reset transistor RST is also controlled to the on state at the same time.

[0033] The amplification transistor AMP generates a pixel signal having a voltage corresponding to the level of charge accumulated in the floating diffusion FD. The amplification transistor AMP is connected in series with the selection transistor SEL and connected to a vertical signal line 9 via the selection transistor SEL. The amplification transistor AMP forms a source follower together with a load circuit section in the column signal processing circuit 5 connected to the vertical signal line 9. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit 5 via the vertical signal line 9. The drain of the amplification transistor AMP is connected to a power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.

[0034] The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to a vertical signal line 9, and the gate of the selection transistor SEL is connected to a pixel drive line. When the selection transistor SEL is turned on by the pixel drive line supplied to its gate, it outputs the pixel signal from the amplification transistor AMP to the vertical signal line 9. This pixel drive line is part of the pixel drive line 10 described in FIG. 1.

[0035] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP. The source of the amplification transistor AMP (the output terminal of the pixel 2) is electrically connected to the vertical signal line 9, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0036] The pixel 2 configured as above photoelectrically converts incident light under the control of the vertical drive circuit 4 and outputs a pixel signal according to the amount of received light to the column signal processing circuit 5 via the vertical signal line 9 .

[0037] The pixel structure employed in the pixel 2 of the photodetector 1 will be described below.

[0038] 3. First Pixel Structure Fig. 3 is a cross-sectional view showing the first pixel structure of pixel 2 of photodetector 1, and Fig. 4 is a plan view showing the first pixel structure of pixel 2 of photodetector 1. Fig. 3A is a cross-sectional view taken along line Y-Y' in the plan view of Fig. 4, and Fig. 3B is a cross-sectional view taken along line XX' in Fig. 3A.

[0039] 3A, the semiconductor substrate 21 is formed of a low-concentration p-type semiconductor region 41 using a substrate that uses, for example, silicon (Si) as a semiconductor, and an n-type semiconductor region 42 is formed in the p-type semiconductor region 41 as a substrate region, thereby forming a pn junction photodiode PD for each pixel. The p-type semiconductor regions 41 facing both the front and back surfaces of the semiconductor substrate 21 also serve as hole charge accumulation regions for suppressing dark current.

[0040] 3A is the back surface side of the semiconductor substrate 21, which is the light incident surface (light receiving surface) onto which light is incident. Therefore, the photodetector 1 having the pixels 2 is a back-illuminated photodetector in which light is incident from the back surface side of the semiconductor substrate 21.

[0041] A gate electrode 43 of the transfer transistor TG and a floating diffusion FD are formed on the front surface side of the semiconductor substrate 21. The floating diffusion FD is formed of a highly doped n-type semiconductor region 44. The transfer transistor TG has a vertical transistor structure in which the gate electrode 43 is not only located on the front surface of the semiconductor substrate 21 but also has a trench portion dug to a predetermined depth into the substrate, but may also have a planar transistor structure. A gate insulating film 46 is formed between the gate electrode 43 of the transfer transistor TG and the p-type semiconductor region 41.

[0042] On the front surface side of the semiconductor substrate 21 in a region different from the region in which the gate electrode 43 of the transfer transistor TG and the floating diffusion FD are formed, an amplifier transistor AMP and a select transistor SEL are stacked in the substrate depth direction. The amplifier transistor AMP and the select transistor SEL are formed in a wiring layer 61 on the front surface side of the semiconductor substrate 21, and the peripheries of the amplifier transistor AMP and the select transistor SEL are covered with an interlayer insulating film 62. In a region near the front surface of the semiconductor substrate 21 below the region in which the amplifier transistor AMP and the select transistor SEL are formed, a highly doped p-type semiconductor region 45 is formed in order to reduce leakage from the two stacked pixel transistors.

[0043] The amplifier transistor AMP is disposed on the lower side of the two stacked pixel transistors and has a gate electrode 63, a drain 64, and a source / drain 65. The source / drain 65 is a semiconductor region shared with the select transistor SEL, serving as the source for the amplifier transistor AMP and the drain for the select transistor SEL. The drain 64 and the source / drain 65 are composed of a highly doped n-type semiconductor region (n-type diffusion layer). As shown in the cross-sectional view of line X-X' in FIG. 3B, the gate electrode 63 of the amplifier transistor AMP is formed so as to surround a plate-shaped (sheet-shaped) p-type semiconductor region 66 formed inside. The p-type semiconductor region 66 is a region where a channel is formed. A gate insulating film 67 is disposed between the internal plate-shaped p-type semiconductor region 66 and the outer gate electrode 63. In FIG. 3A, the gate electrode 63 is separated from the drain 64 and the source / drain 65 by spacers 68 formed of, for example, a SiO2 film. A gate electrode 63 of the amplifier transistor AMP is connected to the n-type semiconductor region 44, which is the floating diffusion FD, by a metal wiring 81. A drain 64 is connected to the power supply line VDD by a metal wiring 82.

[0044] The select transistor SEL is disposed on the upper side of the two stacked pixel transistors and includes a gate electrode 71, a source 72, and a source / drain 65. The source / drain 65 is a semiconductor region shared with the amplifier transistor AMP and serves as the drain for the select transistor SEL. The source 72 and the source / drain 65 are composed of a highly doped n-type semiconductor region (n-type diffusion layer). As shown in the cross-sectional view of line X-X' in FIG. 3B, the gate electrode 71 of the select transistor SEL is formed so as to surround a plate-shaped (sheet-shaped) p-type semiconductor region 73 formed inside. The p-type semiconductor region 73 is a region where a channel is formed. A gate insulating film 67 is disposed between the internal plate-shaped p-type semiconductor region 73 and the outer gate electrode 71. In FIG. 3A, the gate electrode 71 is separated from the source 72 and the source / drain 65 by spacers 68 formed of, for example, a SiO2 film. The gate electrode 71 of the selection transistor SEL is connected via a metal wiring 84 to a pixel drive wiring 10 connected to the vertical drive circuit 4. The source 72 is connected via a metal wiring 83 to a vertical signal line 9.

[0045] The gate electrode 63 of the amplification transistor AMP and the gate electrode 71 of the selection transistor SEL are made of polysilicon formed by, for example, CVD (vapor phase growth) or the like. The p-type semiconductor region 66 inside the gate electrode 63 and the p-type semiconductor region 73 inside the gate electrode 71 are made of, for example, silicon formed by epitaxial growth. The gate insulating film 67 is made of, for example, an SiO2 film or the like.

[0046] As shown in FIG. 4 , a pixel 2 has a pixel separator 91 separating the photodiode PD from each other on the periphery of a rectangular (e.g., square) pixel region, which is the boundary between adjacent pixels. The pixel separator 91 is formed by embedding an insulating film such as SiO2. The pixel separator 91 may also be formed by further embedding a metal material such as tungsten, aluminum, silver, or copper inside the insulating film. The transfer transistor TG, the amplifier transistor AMP, and the select transistor SEL are disposed inside the pixel separator 91. More specifically, the gate electrode 43 of the transfer transistor TG and the high-concentration n-type semiconductor region 44 constituting the floating diffusion FD are disposed at a predetermined corner of the rectangle surrounded by the pixel separator 91. The amplifier transistor AMP and the select transistor SEL are disposed inside the pixel separator 91, e.g., approximately in the center. The amplifier transistor AMP and the select transistor SEL are disposed overlapping each other in a plan view, with the area of ​​the lower amplifier transistor AMP being larger than that of the upper select transistor SEL. At least a part of the upper portion of each of the gate electrode 63 of the amplification transistor AMP and the gate electrode 71 of the selection transistor SEL is exposed. This ensures that the gate electrode 63 of the amplification transistor AMP has a contact region for a metal wiring 81 connected to the floating diffusion FD (n-type semiconductor region 44), and that the gate electrode 71 of the selection transistor SEL has a contact region for a metal wiring 84 connected to the vertical drive circuit 4 via the pixel drive wiring 10.

[0047] Although the reset transistor RST is not particularly shown, the reset transistor RST is appropriately disposed in the pixel region other than the transfer transistor TG, the amplification transistor AMP, and the selection transistor SEL.

[0048] According to the first pixel structure configured as described above, two serially connected pixel transistors, the amplifier transistor AMP and the select transistor SEL, are stacked vertically in the wiring layer 61 above the front surface of the semiconductor substrate 21 on which the photodiode PD is formed. More specifically, the gate electrode 63 of the amplifier transistor AMP and the gate electrode 71 of the select transistor SEL are stacked. The gate electrode 63 of the lower amplifier transistor AMP has a gate-around structure (gate-all-around structure) that surrounds, via a gate insulating film 67, the periphery of the p-type semiconductor region 66 in which a channel is formed. The gate electrode 71 of the upper select transistor SEL also has a gate-around structure that surrounds, via a gate insulating film 67, the periphery of the p-type semiconductor region 73 in which a channel is formed. Therefore, in the amplifier transistor AMP and the select transistor SEL, the p-type semiconductor region 66 in which a channel is formed and the p-type semiconductor region 73 are also stacked. This structure allows two pixel transistors, the amplifier transistor AMP and the select transistor SEL, to be arranged in the region where one pixel transistor is formed, thereby enabling the pixel 2 to be miniaturized.

[0049] Therefore, according to the first pixel structure, the pixels 2 can be miniaturized in a pixel structure formed on one semiconductor substrate 21 .

[0050] For example, if the n-type semiconductor region 42 of the photodiode PD is expanded to a shallower position (near the front surface) in order to improve the saturation charge amount and transfer characteristics of the photodiode PD, there is a concern that the isolation performance with the amplifier transistor AMP and the select transistor SEL disposed above the photodiode PD may be degraded. According to the first pixel structure, the amplifier transistor AMP and the select transistor SEL are formed in the wiring layer 61 on the front surface side of the semiconductor substrate 21 on which the photodiode PD is formed, so the n-type semiconductor region 42 of the photodiode PD can be expanded to a shallower position without degrading the isolation performance. As a result, even when the pixel 2 is miniaturized, the saturation charge amount and transfer characteristics can be improved, and high-quality images can be obtained.

[0051] 4. First Modification of First Pixel Structure> Fig. 5 is a cross-sectional view showing a first modification of the first pixel structure. Fig. 5A is a cross-sectional view corresponding to line Y-Y' in the plan view of Fig. 4, and Fig. 5B is a cross-sectional view taken along line XX' in Fig. 5A.

[0052] In the first modification, the gate electrode 63 of the amplifier transistor AMP and the gate electrode 71 of the select transistor SEL in FIG. 3 are replaced with gate electrodes 63′ and 71′, respectively. Furthermore, the gate insulating film 67 is replaced with gate insulating film 67′. The difference between the first pixel structure of FIG. 3 and the first modification is the materials used. While the gate electrodes 63 and 71 of the first pixel structure of FIG. 3 are formed of polysilicon, the gate electrodes 63′ and 71′ are formed of a metal material such as titanium (Ti) or tungsten (W). While the gate insulating film 67 of the first pixel structure of FIG. 3 is formed of, for example, an SiO2 film, the gate insulating film 67′ is formed of a high-dielectric-constant insulating film (high-k film) using a high-dielectric-constant insulating material such as hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), or STO (strontium titanium oxide). By using such materials to form the amplifier transistor AMP and the select transistor SEL, it is possible to suppress the degradation of transistor performance due to gate depletion, improve the transconductance gm, and suppress the RTS (Random Telegraph Signal) noise of the amplifier transistor AMP and the thermal noise of the select transistor SEL.

[0053] 6 is a cross-sectional view showing a second modification of the first pixel structure. Fig. 6A is a cross-sectional view corresponding to the line Y-Y' in the plan view of Fig. 4, and Fig. 6B is a cross-sectional view taken along the line XX' in Fig. 6A.

[0054] In the second modification, the arrangement of the stacked amplifier transistor AMP and select transistor SEL is opposite to that of the first pixel structure shown in FIG. 3 . That is, the select transistor SEL is arranged on the lower side of the two stacked pixel transistors, and the amplifier transistor AMP is arranged on the upper side of the select transistor SEL. The positions of the source 72 of the select transistor SEL and the drain 64 of the amplifier transistor AMP are also swapped with respect to the first pixel structure shown in FIG. 3 . As described above, the amplifier transistor AMP and the select transistor SEL, which are stacked on the front surface of the semiconductor substrate 21, may be arranged on either the upper or lower side. However, in terms of the operating characteristics of the pixel 2, it is preferable to increase the transistor size of the amplifier transistor AMP. As can be seen from the cross-sectional views of FIG. 3A and FIG. 6A, the upper pixel transistor is formed with a smaller planar size than the lower pixel transistor in order to make contact with the gate electrode. Therefore, it is more preferable to arrange the amplifier transistor AMP on the lower side.

[0055] 7 is a cross-sectional view showing a third modified example of the first pixel structure, taken along line X-X' in A of Fig. 3. The cross-sectional view taken along line Y-Y' in A of Fig. 3 and the plan view of Fig. 4 are similar to those of the first pixel structure described above.

[0056] In the third modification, the channel width W of the p-type semiconductor region 73 surrounded by the gate electrode 71 of the upper select transistor SEL, which is stacked vertically, is shorter than the channel width W of the p-type semiconductor region 66 surrounded by the gate electrode 63 of the lower amplifier transistor AMP. In this manner, the channel widths W of the upper p-type semiconductor region 73 and the lower p-type semiconductor region 66 may be formed to be different widths. Making the channel width W of the upper p-type semiconductor region 73 shorter than the channel width W of the lower p-type semiconductor region 66 ensures a larger space above the gate electrode 63 located below, making it easier to make contact with the gate electrode 63 of the amplifier transistor AMP. For example, this also facilitates the contact between the metal wiring 81 connected to the floating diffusion FD (n-type semiconductor region 44) and the gate electrode 63, as well as the processing required for contact formation.

[0057] Note that the above-described first to third modified examples can be appropriately combined to adopt a configuration. For example, the first modified example and the third modified example may be combined to form the amplifier transistor AMP and the select transistor SEL as gate electrodes 63' and 71' made of a metal material, and the channel widths W of the lower p-type semiconductor region 66 and the upper p-type semiconductor region 73 may be formed to be different widths. Alternatively, the first modified example and the second modified example may be combined to form the amplifier transistor AMP and the select transistor SEL as gate electrodes 63' and 71' made of a metal material, and the amplifier transistor AMP may be arranged on the upper side and the select transistor SEL on the lower side.

[0058] 7. Second Pixel Structure Fig. 8 is a cross-sectional view showing a second pixel structure of pixel 2 of the photodetector 1. Fig. 8A is a cross-sectional view corresponding to line Y-Y' in the plan view of Fig. 4, and Fig. 8B is a cross-sectional view taken along line X-X' of Fig. 8A. The second pixel structure of Fig. 8 will be described focusing on parts that are different from the first pixel structure described above, and descriptions of common parts will be omitted as appropriate.

[0059] The second pixel structure differs in that the p-type semiconductor regions 66, 73 in which channels are formed are each composed of two layers in the amplifier transistor AMP and the select transistor SEL. As shown in B of Fig. 8, in the amplifier transistor AMP, a gate electrode 63 is formed around each of the two p-type semiconductor regions 66 with a gate insulating film 67 interposed therebetween. In the select transistor SEL, a gate electrode 71 is formed around each of the two p-type semiconductor regions 73 with the gate insulating film 67 interposed therebetween.

[0060] According to the second pixel structure configured as described above, similarly to the first pixel structure, the stacked structure of the amplifier transistor AMP and the select transistor SEL makes it possible to miniaturize the pixel 2 and suppress deterioration of the isolation performance between the n-type semiconductor region 42 of the photodiode PD and the amplifier transistor AMP or the select transistor SEL.

[0061] Furthermore, by configuring the p-type semiconductor regions 66, 73 in which the channels are formed as two layers, the effective channel width W can be increased without increasing the plane area. Increasing the effective channel width W of the amplifier transistor AMP can further suppress the RTS noise of the amplifier transistor AMP. Suppressing the RTS noise can, for example, obtain a high-quality image with less noise. Instead of configuring the p-type semiconductor regions of both the amplifier transistor AMP and the select transistor SEL as two layers, the p-type semiconductor region of only one of the amplifier transistor AMP and the select transistor SEL may be configured as two layers.

[0062] In the above example, the p-type semiconductor regions 66 and 73 are configured with two layers, but it goes without saying that they may be configured with three or more layers. By increasing the number of layers, the effective channel width W can be increased without increasing the area.

[0063] 9 is a cross-sectional view showing a third pixel structure of pixel 2 of photodetector 1, which is a cross-sectional view corresponding to line Y-Y' in the plan view of Fig. 4. The third pixel structure in Fig. 9 will also be described by focusing on parts that are different from the first and second pixel structures described above, and a description of common parts will be omitted as appropriate.

[0064] 9 differs from the first pixel structure described above in that not only a select transistor SEL but also a reset transistor RST is arranged above the amplifier transistor AMP. The select transistor SEL and the reset transistor RST are arranged on the same plane, i.e., at the same height, above the semiconductor substrate 21, and both are arranged within the transistor region of the amplifier transistor AMP in a planar view. In other words, the amplifier transistor AMP, the select transistor SEL, and the reset transistor RST are arranged in a stacked configuration, with the select transistor SEL arranged in a first region above the amplifier transistor AMP and the reset transistor RST arranged in a second region above the amplifier transistor AMP that is different from the first region.

[0065] The reset transistor RST has a drain 64, a source 101, and a gate electrode 102. The drain 64 of the reset transistor RST is shared with the amplifier transistor AMP and serves as the drain of the amplifier transistor AMP. The source 101 is composed of a heavily doped n-type semiconductor region (n-type diffusion layer). The gate electrode 102 of the reset transistor RST is formed to surround the periphery of a plate-shaped (sheet-shaped) p-type semiconductor region 103 formed inside, similar to the gate electrode 71 of the select transistor SEL in the X-X' cross-sectional view of FIG. 3B. A gate insulating film 104 is disposed between the internal plate-shaped p-type semiconductor region 103 and the outer gate electrode 102. The gate electrode 102 is separated from the drain 64 and source 101 by spacers 105 formed of, for example, a SiO2 film. The gate electrode 102 of the reset transistor RST is connected to the pixel drive wiring 10 connected to the vertical drive circuit 4 via a metal wiring 111. The source 101 is connected to the floating diffusion FD (n-type semiconductor region 44 ) and the gate electrode 63 of the amplification transistor AMP via a metal wiring 81 .

[0066] According to the third pixel structure configured as described above, similarly to the first pixel structure, the stacked structure of the amplifier transistor AMP and the select transistor SEL makes it possible to miniaturize the pixel 2 and suppress deterioration of the isolation performance between the n-type semiconductor region 42 of the photodiode PD and the amplifier transistor AMP or the select transistor SEL.

[0067] Furthermore, by stacking and arranging the reset transistor RST above the amplification transistor AMP, the layout area of ​​the pixel transistor can be reduced, and an even smaller area can be achieved, which makes it possible to further accommodate miniaturization of the pixel 2.

[0068] 9. Modification of Third Pixel Structure FIG. 10 is a cross-sectional view showing a modification of the third pixel structure, and is a cross-sectional view corresponding to the line YY′ in the plan view of FIG.

[0069] In the third pixel structure variation shown in FIG. 10 , the portion indicated by the solid-line oval in FIG. 10 , i.e., the source 101 of the reset transistor RST, is directly connected to the gate electrode 63 of the amplifier transistor AMP disposed thereunder. As a result, in the third pixel structure shown in FIG. 9 , the metal wiring 81 connects the floating diffusion FD (n-type semiconductor region 44), the gate electrode 63 of the amplifier transistor AMP, and the source 101 of the reset transistor RST. However, in the third pixel structure shown in FIG. 10 , the metal wiring 81 connects only the floating diffusion FD (n-type semiconductor region 44) and the source 101 of the reset transistor RST. In other words, the wiring connecting the gate electrode 63 of the amplifier transistor AMP and the source 101 of the reset transistor RST is omitted. According to the third pixel structure variation, in addition to the effects of the third pixel structure described above, the wiring capacitance (FD capacitance) generated by routing the wiring can be reduced, thereby improving conversion efficiency.

[0070] 10. Fourth Pixel Structure A of Fig. 11 is a cross-sectional view showing a fourth pixel structure of pixel 2 of photodetector 1, and is a cross-sectional view corresponding to line Y-Y' in the plan view of Fig. 4, and B of Fig. 11 is a cross-sectional view taken along line X-X' of A of Fig. 11. The fourth pixel structure of Fig. 11 will be described focusing on parts that are different from the first pixel structure described above, and descriptions of common parts will be omitted as appropriate.

[0071] In the fourth pixel structure, the gate electrode 63 of the amplifier transistor AMP and the gate electrode 71 of the select transistor SEL in the first pixel structure are changed to a gate electrode 63" and a gate electrode 71", respectively. The gate electrode 63 of the amplifier transistor AMP in the first pixel structure was formed around the periphery of the p-type semiconductor region 66 in which a channel is formed, i.e., on four sides: the top surface, the bottom surface, and two side surfaces. However, the gate electrode 63" in the fourth pixel structure is formed only on the top surface of the p-type semiconductor region 66, as shown in FIGS. 11A and 11B. A gate insulating film 67 is formed between the gate electrode 63" and the p-type semiconductor region 66. Similarly, the gate electrode 71" of the select transistor SEL is formed only on the top surface of the p-type semiconductor region 73 in which a channel is formed. A gate insulating film 67 is formed between the gate electrode 71" and the p-type semiconductor region 73. In this way, the gate electrodes of the amplifier transistor AMP and the select transistor SEL may not be gate electrodes with a gate-around structure that surrounds the peripheries of the p-type semiconductor regions 66, 73, but may be planar gate electrodes formed only on the upper surfaces of the p-type semiconductor regions 66, 73. Even in this case, the stacked structure of the amplifier transistor AMP and the select transistor SEL makes it possible to miniaturize the pixel 2 and suppress deterioration of the isolation performance between the n-type semiconductor region 42 of the photodiode PD and the amplifier transistor AMP or the select transistor SEL. Note that the gate electrode of either the amplifier transistor AMP or the select transistor SEL may have a gate-around structure, and the gate electrode of the other may be planar.

[0072] 12 is a cross-sectional view showing a fifth pixel structure of pixel 2 of photodetector 1, which is a cross-sectional view corresponding to line Y-Y' in the plan view of Fig. 4. The fifth pixel structure of Fig. 12 will also be described by focusing on parts that are different from the first pixel structure described above, and a description of common parts will be omitted as appropriate.

[0073] While the first pixel structure shown in FIG. 3 has a stacked structure of the amplifier transistor AMP and the select transistor SEL, the fifth pixel structure has a structure in which the amplifier transistor AMP and the select transistor SEL are arranged side by side in a planar direction. More specifically, in the first pixel structure, the source / drain 65 shared by the amplifier transistor AMP and the select transistor SEL is arranged at one end, and the drain 64 of the amplifier transistor AMP and the source 72 of the select transistor SEL, which are not shared, are arranged at the other end, so that the amplifier transistor AMP and the select transistor SEL are folded back at the source / drain 65. In contrast, in the fifth pixel structure, the drain 64 of the amplifier transistor AMP and the source 72 of the select transistor SEL, which are not shared, are arranged at both ends, and the shared source / drain 65 is arranged between them, so that the amplifier transistor AMP and the select transistor SEL are arranged in a linear manner. Similar to the first pixel structure, the amplifier transistor AMP and the select transistor SEL each have a gate-around structure in which the periphery of the p-type semiconductor regions 66 and 73, in which channels are formed, is surrounded by a gate insulating film 67.

[0074] According to the fifth pixel structure, the amplification transistor AMP and the selection transistor SEL, which are two pixel transistors connected in series, are arranged in the wiring layer 61 above the front surface side of the semiconductor substrate 21 on which the photodiode PD is formed, thereby reducing the plane area and enabling miniaturization of the pixel 2. The pixel 2 can be miniaturized in a pixel structure formed on a single semiconductor substrate 21.

[0075] 12. Sixth Pixel Structure Fig. 13 is a cross-sectional view showing a sixth pixel structure of pixel 2 of the photo-detecting device 1, and Fig. 14 is a plan view showing the sixth pixel structure of pixel 2 of the photo-detecting device 1. A of Fig. 13 is a cross-sectional view taken along line Y-Y' in the plan view of Fig. 14, and B of Fig. 13 is a cross-sectional view taken along line Y2-Y2' in the plan view of Fig. 14.

[0076] The sixth pixel structure is a pixel structure in which one pixel has two transfer transistors TG and two floating diffusions FD. The configuration in which one pixel has two transfer transistors TG and two floating diffusions FD is adopted, for example, when the photodetector 1 is a device that measures the distance to a subject using an indirect ToF method.

[0077] In the indirect ToF method, the signal charge generated by photoelectric conversion using a photodiode PD is distributed to two floating diffusions FD (charge storage units) using, for example, two transfer transistors TG, and the distance is calculated from the distribution ratio of these signal charges.

[0078] In the sixth pixel structure, the two transfer transistors TG and two floating diffusions FD provided in the pixel 2 are referred to as transfer transistors TG1 and TG2 and floating diffusions FD1 and FD2. In order to distribute signal charges evenly, it is desirable that the transfer transistor TG1 and floating diffusion FD1 on one side and the transfer transistor TG2 and floating diffusion FD2 on the other side are arranged symmetrically with respect to a predetermined position. For example, as shown in the plan view of FIG. 14 , the transfer transistor TG1 and floating diffusion FD1 on one side are arranged at a predetermined corner of a rectangle surrounded by the pixel separation portion 91, and the transfer transistor TG2 and floating diffusion FD2 on the other side are arranged at the other corner of the same side, equidistant from the center of the pixel 2.

[0079] The amplifier transistor AMP and the select transistor SEL are configured in the same manner as in the first pixel structure described above. In the examples of Figures 13 and 14, as in the first pixel structure, only one pair of the amplifier transistor AMP and the select transistor SEL is provided, but two pairs of the amplifier transistor AMP and the select transistor SEL may be provided above the semiconductor substrate 21 on which the photodiode PD is formed, corresponding to two transfer transistors TG and two floating diffusions FD. Alternatively, a pixel structure in which more than two pairs of the transfer transistor TG and the floating diffusion FD, for example, four pairs, are provided and signal charges are distributed to four floating diffusions FD (charge storage sections) may be used.

[0080] In the sixth pixel structure as well, the stacked structure of the amplification transistor AMP and the selection transistor SEL makes it possible to miniaturize the pixel 2 and suppress deterioration of the isolation performance between the n-type semiconductor region 42 of the photodiode PD and the amplification transistor AMP or the selection transistor SEL.

[0081] 13. Manufacturing Method of First Pixel Structure Next, a method of manufacturing the pixel 2 according to the above-described first pixel structure will be described with reference to FIGS.

[0082] First, as shown in A of FIG. 15 , n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted from the front surface side of the semiconductor substrate 21 into a predetermined region within each pixel 2 of the semiconductor substrate 21, which is formed with a low-concentration p-type semiconductor region 41, to form an n-type semiconductor region 42. This results in a pn junction photodiode PD consisting of the p-type semiconductor region 41 and the n-type semiconductor region 42. The n-type semiconductor region 42 is formed in a region deeper than the vicinity of the front and back interfaces of the semiconductor substrate 21, and the p-type semiconductor region 41 facing both the front and back surfaces of the semiconductor substrate 21 also serves as a hole charge accumulation region for suppressing dark current. Furthermore, p-type impurities such as boron (B) or gallium (Ga) are ion-implanted from the front surface side into a region near the front surface of the semiconductor substrate 21, where the stacked structure of the amplifier transistor AMP and select transistor SEL in the pixel is formed, to form a highly-concentrated p-type semiconductor region 45.

[0083] 15B, a dummy semiconductor layer 201A, a p-type semiconductor region 66, a dummy semiconductor layer 201B, and a p-type semiconductor region 73 are formed in that order by epitaxial growth on the front surface of the semiconductor substrate 21. The p-type semiconductor regions 66 and 73 are made of, for example, silicon (Si). The dummy semiconductor layers 201A and 201B are made of, for example, silicon germanium (SiGe).

[0084] Next, as shown in FIG. 15C, the dummy semiconductor layer 201A, the p-type semiconductor region 66, the dummy semiconductor layer 201B, and the p-type semiconductor region 73 in the region 202 other than the channel formation region are removed by etching or the like so as to leave the channel formation regions of the amplification transistor AMP and the select transistor SEL in a stacked structure.

[0085] 16A, after a dummy gate film 203 is formed on the upper surface of the p-type semiconductor region 73 in the channel formation region, spacers 68 are formed on both ends of each of the dummy semiconductor layer 201A, the dummy semiconductor layer 201B, and the dummy gate film 203. The dummy gate film 203 can be formed of, for example, a SiN film, and the spacers 68 can be formed of, for example, a SiO2 film.

[0086] 16B, a drain 64 and a source / drain 65 are formed on both sides of the channel formation region using a high-concentration n-type semiconductor region. The drain 64 and the source / drain 65 can be formed by epitaxial growth using the p-type semiconductor region 66, the p-type semiconductor region 73, and the p-type semiconductor region 45 as seeds. Thereafter, an interlayer insulating film 62 is formed over the entire front surface of the semiconductor substrate 21.

[0087] 16C, the interlayer insulating film 62 in the region 212 where the gate electrode 43 of the transfer transistor TG and the floating diffusion FD are to be formed is removed by etching or the like to form an opening. Taking into account process variations and the like, the region 212 is secured to be wider than the actual regions of the gate electrode 43 and the floating diffusion FD.

[0088] Next, as shown in A of Figure 17, in the region 212 where the interlayer insulating film 62 is opened, the p-type semiconductor region 41 in the portion where the gate electrode 43 of the transfer transistor TG is to be formed is removed to a predetermined depth by etching, and a trench 213 is formed.

[0089] Next, as shown in FIG. 17B, the interlayer insulating film 62 is formed again in the region 212 including the trench 213 to fill it up, and then the interlayer insulating film 62 and the dummy gate film 203 in the gate region 214 are removed.

[0090] 17C, the dummy semiconductor layers 201A and 201B in the gate region 214 are selectively etched and removed. The dummy semiconductor layers 201A and 201B formed of SiGe layers can be selectively removed using an etchant such as HF+CHCOOH+H2O2 or HF+HNO3+H2O.

[0091] 18A, the interlayer insulating film 62 in the gate region 221 where the gate electrode 43 of the transfer transistor TG and the floating diffusion FD are to be formed is removed by etching or the like to form an opening. Taking into account process variations and the like, the gate region 221 is secured to be wider than the actual regions of the gate electrode 43 and the floating diffusion FD. Thereafter, an oxidation process is performed on the surface of the semiconductor substrate 21 in the gate region 221 using, for example, the ISSG method, to form an oxide film, thereby forming the gate insulating film 46. A gate insulating film 67 is formed on the surfaces of the p-type semiconductor regions 66 and 73 in the gate region 214.

[0092] 18B, a polysilicon layer is formed on the upper surface of the gate insulating film 46 by, for example, LPCVD, to form the gate electrode 43 of the transfer transistor TG. Also, a polysilicon layer is formed on the upper surface of each of the four peripheral sides of the gate insulating film 67 of the gate region 214, to form the gate electrode 63 of the amplifier transistor AMP and the gate electrode 71 of the select transistor SEL.

[0093] Next, as shown in FIG. 18C, the interlayer insulating film 62 is formed again to fill in the opened gate region 221 and gate region 214.

[0094] 19A, a hard mask 231 using, for example, a SiN film is formed on the upper surface of the interlayer insulating film 62, and then the hard mask 231 is patterned (opened) in a region 232 aligned with the arrangement of the source 72 of the select transistor SEL. The underlying interlayer insulating film 62 is removed according to the patterned hard mask 231.

[0095] Next, as shown in Fig. 19B, the gate electrode 71, the p-type semiconductor region 73, the spacer 68, etc. in the region 232 are removed by etching, and then the source 72 of the select transistor SEL is formed as shown in Fig. 19C. The source 72 is formed by epitaxial growth using the p-type semiconductor region 73 as a seed, and is composed of a high-concentration n-type semiconductor region.

[0096] Next, as shown in A of FIG. 20, an interlayer insulating film 62 is formed in the region 232 after the source 72 has been formed, and then, as shown in B of FIG. 20, the interlayer insulating film 62 in the gate region 241 in which the gate electrode 43 of the transfer transistor TG and the floating diffusion FD are formed is removed by etching or the like to form an opening.

[0097] 20C, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted from the front surface side of the semiconductor substrate 21 into the region where the floating diffusion FD is to be formed, thereby forming an n-type semiconductor region 44. The impurities are then activated using a technique such as RTA (Rapid Thermal Anneal).

[0098] As a result of the above, in the first pixel structure, the transfer transistor TG and the floating diffusion FD (n-type semiconductor region 44) can be formed, and the amplification transistor AMP and the selection transistor SEL, which are connected in series, can be stacked on the semiconductor substrate 21.

[0099] The formation of the amplifier transistor AMP and the select transistor SEL formed on the semiconductor substrate 21 will be further described with reference to Figures 21 to 25. In Figures 21 to 25, cross-sectional views in the channel length direction (hereinafter referred to as the L length direction) are shown in the upper rows, and cross-sectional views in the channel width direction (hereinafter referred to as the W width direction) are shown in the lower rows. The cross-sectional views in the W width direction are cross-sectional views corresponding to line X-X' of the cross-sectional views in the channel length direction.

[0100] 21A, a dummy semiconductor layer 201A, a p-type semiconductor region 66, a dummy semiconductor layer 201B, and a p-type semiconductor region 73 are formed in that order by epitaxial growth on the front surface of a semiconductor substrate 21 that will become the wiring layer 61. The p-type semiconductor region 66 and the p-type semiconductor region 73 are made of, for example, silicon (Si). The dummy semiconductor layers 201A and 201B are made of, for example, silicon germanium (SiGe).

[0101] Next, as shown in B of FIG. 21, the dummy semiconductor layer 201A, the p-type semiconductor region 66, the dummy semiconductor layer 201B, and the p-type semiconductor region 73 other than the channel formation region are removed by etching or the like so as to leave the channel formation region of the amplification transistor AMP and the select transistor SEL having a stacked structure.

[0102] 21C, a dummy gate film 203 is formed on the upper surface of the p-type semiconductor region 73 in the channel formation region, and then spacers 68 are formed on both ends in the L-length direction of the dummy semiconductor layer 201A, the dummy semiconductor layer 201B, and the dummy gate film 203. The dummy gate film 203 can be formed of, for example, a SiN film, and the spacers 68 can be formed of, for example, a SiO2 film. As seen in a cross-sectional view in the W-width direction, the dummy gate film 203 is formed not only on the upper surface of the p-type semiconductor region 73, but also on the side surfaces of the dummy semiconductor layer 201A to the p-type semiconductor region 73.

[0103] Next, as shown in Fig. 22A, a drain 64 and a source / drain 65 are formed on both sides of the channel formation region in the L-length direction using a high-concentration n-type semiconductor region. The drain 64 and the source / drain 65 are formed by epitaxial growth using p-type semiconductor regions 66, 73, etc. as seeds. Thereafter, as shown in Fig. 22B, an interlayer insulating film 62 is formed on the upper surface of the channel formation region.

[0104] 22C, the interlayer insulating film 62 and the dummy gate film 203 in the gate region 214 are removed by etching, thereby exposing the dummy semiconductor layers 201A and 201B on the side surfaces in the W width direction.

[0105] 23A, the dummy semiconductor layers 201A and 201B in the gate region 214 are selectively etched and removed. The dummy semiconductor layers 201A and 201B formed of SiGe layers can be selectively removed using an etchant such as HF+CHCOOH+H2O2 or HF+HNO3+H2O.

[0106] Next, as shown in B of FIG. 23, an oxidation process is performed on the surface of the semiconductor substrate 21 in the gate region 214 and the surfaces of the p-type semiconductor regions 66 and 73 using, for example, the ISSG method, and an oxide film is formed, thereby forming a gate insulating film 67.

[0107] Next, as shown in C of FIG. 23, a polysilicon layer is formed on the upper surface of each of the four peripheral sides of the gate insulating film 67 of the gate region 214, for example, using the LPCVD method, to form the gate electrode 63 of the amplification transistor AMP and the gate electrode 71 of the selection transistor SEL.

[0108] Next, as shown in FIG. 24A, the interlayer insulating film 62 is formed again to fill in the opened gate region 214 .

[0109] 24B, after a hard mask 231 using, for example, a SiN film is formed on the upper surface of the interlayer insulating film 62, the hard mask 231 is patterned (opened) in a region 232 aligned with the arrangement of the source 72 of the select transistor SEL. The interlayer insulating film 62 is removed according to the patterned hard mask 231.

[0110] Next, as shown in C of Fig. 24, the gate electrode 71, the p-type semiconductor region 73, the spacer 68, etc. in the region 232 are further removed by etching, and then the source 72 of the select transistor SEL is formed as shown in A of Fig. 25. The source 72 is formed by epitaxial growth using the p-type semiconductor region 73 as a seed, and is composed of a highly doped n-type semiconductor region.

[0111] 25B, an interlayer insulating film 62 is formed in the region 232 after the source 72 has been formed, and the region 232 is filled with the source 72. In this way, the amplifier transistor AMP and the select transistor SEL are formed on the semiconductor substrate 21.

[0112] The pixel 2 according to the first pixel structure described above can be manufactured as described above.

[0113] <14. Summary> The photodetector 1 has pixels 2 each including a photodiode PD (photoelectric conversion unit) formed on a semiconductor substrate 21, and an amplifier transistor AMP and a select transistor SEL (first and second transistors) connected in series and formed above the semiconductor substrate 21, with the channels (p-type semiconductor regions 66, 73) of the amplifier transistor AMP and the select transistor SEL being formed above the semiconductor substrate 21, and the source of the amplifier transistor and the drain of the select transistor SEL being formed in a single semiconductor region (a high-concentration n-type semiconductor region constituting the source / drain 65) above the semiconductor substrate 21. This structure enables miniaturization of the pixels 2 in a pixel structure formed on a single semiconductor substrate 21.

[0114] 15. Example of a Stacked Structure Using Multiple Substrates In the above-described embodiment, an example has been described in which the photodetector 1 is configured using one substrate (semiconductor substrate 21). The photodetector 1 may be configured by stacking two or three substrates. With reference to FIG. 26 , a case in which the photodetector 1 is configured with a stacked structure of three substrates will be described.

[0115] Fig. 26 shows a schematic configuration example of the photodetector 1 when configured with a stacked structure of three substrates. In Fig. 26, parts corresponding to those in the configuration described above are given the same reference numerals, and their description will be omitted as appropriate.

[0116] 26 has a three-dimensional structure in which a first substrate 411, a second substrate 412, and a third substrate 413 are bonded together. The first substrate 411, the second substrate 412, and the third substrate 413 are stacked in this order.

[0117] The first substrate 411 has a semiconductor substrate 441 made of, for example, silicon (Si), and a pixel region 512 in which a plurality of sensor pixels 511 are two-dimensionally arranged in a matrix is ​​formed on the semiconductor substrate 441. The sensor pixel 511 includes at least the above-mentioned photodiode PD and transfer transistor TG.

[0118] The second substrate 412 has a semiconductor substrate 442 made of, for example, silicon (Si), and a readout circuit 521 is formed on the semiconductor substrate 442. The readout circuit 521 outputs pixel signals based on charges generated in the sensor pixels 511. The readout circuit 521 corresponds to, for example, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL described above, and when a shared pixel structure is adopted, one readout circuit 521 is arranged for multiple sensor pixels 511. A plurality of pixel drive wirings 522 extending in the row direction and a plurality of vertical signal lines 523 extending in the column direction are also formed on the second substrate 412.

[0119] The third substrate 413 has a semiconductor substrate 443 made of, for example, silicon (Si), and a logic circuit 541 that processes pixel signals is formed on the semiconductor substrate 443. The logic circuit 541 includes, for example, a vertical drive circuit 551, a column processing circuit 552, a horizontal drive circuit 553, and a system control circuit 554. The vertical drive circuit 551, the column processing circuit 552, the horizontal drive circuit 553, and the system control circuit 554 have functions similar to those of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the control circuit 8 in FIG. 1, respectively. The horizontal drive circuit 553 sequentially selects the column signal processing circuits in the column processing circuit 552, and pixel signals acquired from each column signal processing circuit are output from an output terminal 555.

[0120] FIG. 27 shows an example of the configuration of the sensor pixels 511 and the readout circuit 521. FIG. 27 describes a case where four sensor pixels 511 share one readout circuit 521. Here, "shared" means that the outputs of the four sensor pixels 511 are input to a common readout circuit 521. When distinguishing between the four sensor pixels 511 that share one readout circuit 521, they are referred to as sensor pixels 511A, 511B, 511C, and 511D, as shown in FIG. 27. The sensor pixels 511A, 511B, 511C, and 511D are formed on the first substrate 411, for example, and the readout circuit 521 is formed on the second substrate 412, for example.

[0121] The sensor pixels 511A, 511B, 511C, and 511D have common components. Hereinafter, when distinguishing between the components of the sensor pixels 511A, 511B, 511C, and 511D, the reference numerals of the components of the sensor pixel 511A will be suffixed with "a," the reference numerals of the components of the sensor pixel 511B will be suffixed with "b," the reference numerals of the components of the sensor pixel 511C will be suffixed with "c," and the reference numerals of the components of the sensor pixel 511D will be suffixed with "d." When it is not necessary to distinguish between the components of the sensor pixels 511A, 511B, 511C, and 511D, the identification symbols "a," "b," "c," and "d" at the end of the reference numerals of the components of the sensor pixels 511A, 511B, 511C, and 511D will be omitted.

[0122] Each sensor pixel 511 includes, for example, a photodiode PD serving as a photoelectric conversion unit, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG. The cathodes of the photodiodes PD (PDa, PDb, PDc, and PDd) are electrically connected to the sources of the transfer transistors TG (TGa, TGb, TGc, and TGd), and the anodes are electrically connected to a reference potential line (e.g., ground). The photodiodes PD photoelectrically convert incident light and generate signal charges corresponding to the amount of received light. The transfer transistors TG are, for example, n-type metal-oxide semiconductor (MOS) transistors. The drains of the transfer transistors TG are electrically connected to the floating diffusions FD (FDa, FDb, FDc, and FDd), and the gates are electrically connected to pixel drive wiring. The pixel drive wiring is part of multiple pixel drive wirings 522 ( FIG. 26 ) connected to a single readout circuit 521. The transfer transistors TG transfer the charges generated by the photodiodes PD to the floating diffusions FD. The floating diffusion FD is composed of, for example, an n-type semiconductor region formed in a p-type semiconductor region. The floating diffusion FD is a charge storage section that temporarily stores the signal charge transferred from the photodiode PD, and also a charge-voltage conversion section that generates a voltage according to the amount of charge.

[0123] The four floating diffusions FDa, FDb, FDc, and FDd included in one readout circuit 521 are electrically connected to each other and to the gate of the amplifier transistor AMP and the source of the reset transistor RST. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to a pixel drive line. This pixel drive line is part of the multiple pixel drive lines 522 connected to one readout circuit 521. The gate of the amplifier transistor AMP is connected to the floating diffusions FDa, FDb, FDc, and FDd, the drain of the amplifier transistor AMP is connected to a power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 523, and the gate of the selection transistor SEL is connected to the pixel drive line. This pixel drive line is part of the multiple pixel drive lines 522 connected to one readout circuit 521.

[0124] The selection transistor SEL controls the output timing of the pixel signal from the readout circuit 521. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD. The amplification transistor AMP is connected to the vertical signal line 523 via the selection transistor SEL. This amplification transistor AMP forms a source follower together with a load circuit section in the column processing circuit 552 connected to the vertical signal line 523. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column processing circuit 552 via the vertical signal line 523. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, n-type MOS transistors.

[0125] The select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to the pixel drive wiring 522. The source of the amplifier transistor AMP (the output terminal of the readout circuit 521) is electrically connected to the vertical signal line 523, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST.

[0126] The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL that constitute the readout circuit 521 are formed on the second substrate 412 in any one of the first to sixth pixel structures described above.

[0127] Although not shown in the drawings, the number of sensor pixels 511 that share one readout circuit 521 may be other than four. For example, two or eight sensor pixels 511 may share one readout circuit 521. Alternatively, instead of a configuration in which the readout circuit 521 is shared by a plurality of sensor pixels 511, a readout circuit 521 may be provided for each pixel.

[0128] 16. Configuration Examples of Electronic Devices The above-described photodetector 1 can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0129] FIG. 28 is a block diagram showing an example of the configuration of an electronic device.

[0130] 28 , electronic device 601 includes an optical system 602, a photodetector 603, a DSP (Digital Signal Processor) 604, a display device 605, an operation system 606, a memory 607, a recording device 608, and a power supply system 609. DSP 604, display device 605, operation system 606, memory 607, recording device 608, and power supply system 609 are interconnected via a bus 610. Electronic device 601 is, for example, an imaging device capable of capturing still images and moving images.

[0131] The optical system 602 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 603 , forming an image on the light-receiving surface (sensor portion) of the photodetector 603 .

[0132] The photodetector 603 has the same configuration as the photodetector 1 described above. Electrons are accumulated as signal charges in the photodetector 603 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 602. A signal corresponding to the electrons accumulated in the photodetector 603 is then supplied to the DSP 604.

[0133] The DSP 604 performs various signal processing on the signal from the photodetector 603 to generate an image, and temporarily stores the image data in a memory 607. The image data stored in the memory 607 is recorded in a recording device 608 or supplied to a display device 605 to display the image. In addition, an operation system 606 accepts various operations by the user and supplies operation signals to each block of the electronic device 601, and a power supply system 609 supplies the power necessary to drive each block of the electronic device 601.

[0134] In the electronic device 601 configured as above, miniaturization of pixels can be realized by applying the above-described photodetector 1 as the photodetector 603. Therefore, high-quality captured images can be generated while the electronic device is miniaturized.

[0135] 17. Example of Use of Image Sensor FIG. 29 is a diagram showing an example of use of the above-described photodetector 1 as an image sensor.

[0136] When the above-described photodetector 1 is an image sensor, it can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0137] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0138] 18. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0139] FIG. 30 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0140] 30 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0141] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0142] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0143] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0144] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0145] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0146] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0147] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0148] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0149] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0150] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0151] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0152] FIG. 31 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0153] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0154] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0155] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0156] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0157] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0158] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0159] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0160] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0161] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0162] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0163] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0164] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0165] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0166] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0167] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0168] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0169] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102 in the above-described configuration. Specifically, the above-described light detection device 1 can be used as the imaging unit 11402. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to obtain clearer images of the surgical site while miniaturizing the camera head 11102.

[0170] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0171] 19. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0172] FIG. 32 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0173] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 32, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0174] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0175] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0176] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0177] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0178] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0179] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0180] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0181] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0182] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 32, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0183] FIG. 33 is a diagram showing an example of the installation position of the imaging unit 12031.

[0184] In FIG. 33, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0185] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0186] 33 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0187] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for detecting a phase difference.

[0188] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0189] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into categories such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0190] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0191] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the image capture unit 12031 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied as the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to obtain a more easily visible captured image and acquire distance information while still reducing the size of the image capture unit 12031. Furthermore, using the obtained captured image and distance information, it is possible to reduce driver fatigue and increase the safety of the driver and the vehicle.

[0192] In the above example, a photodetector in which the first conductivity type is p-type and the second conductivity type is n-type and electrons are used as signal charges has been described, but the present disclosure can also be applied to a photodetector in which holes are used as signal charges. That is, the first conductivity type can be n-type and the second conductivity type can be p-type, and the aforementioned semiconductor regions can be configured with semiconductor regions of opposite conductivity types.

[0193] Furthermore, the present disclosure is not limited to application to photodetection devices that detect the distribution of incident light amount of visible light and capture it as an image, but is also applicable to photodetection devices that capture the distribution of incident amounts of infrared rays, X-rays, particles, etc. as an image, and in a broad sense, to photodetection devices in general (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure or capacitance and capture it as an image.

[0194] The technology of the present disclosure is not limited to photodetectors, but can be applied to semiconductor devices in general that include other semiconductor integrated circuits.

[0195] In this specification, a system refers to a collection of multiple components (devices, modules (components), etc.), regardless of whether all of the components are contained in the same housing. Therefore, multiple devices housed in separate housings and connected via a network, and a single device housed in a single housing with multiple modules, are both systems.

[0196] Furthermore, the embodiments of the technology of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the technology of the present disclosure. For example, it is possible to adopt a configuration in which some of the first to sixth pixel structures described above are appropriately selected and combined.

[0197] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0198] The technology disclosed herein may employ the following configurations: (1) A semiconductor device including first and second transistors formed on a semiconductor substrate and connected in series, wherein channels of the first and second transistors are formed above the semiconductor substrate, and the source of the first transistor and the drain of the second transistor are formed in a single semiconductor region above the semiconductor substrate. (2) The semiconductor device described in (1), wherein the semiconductor regions in which the channels of the first and second transistors are formed are stacked above the semiconductor substrate. (3) The semiconductor device described in (1) or (2), wherein at least one of the first and second transistors has a structure in which a gate electrode surrounds the semiconductor region in which the channel is formed. (4) The semiconductor device described in (1) or (2), wherein at least one of the first and second transistors has a structure in which a planar gate electrode is formed on the upper surface of the semiconductor region in which the channel is formed. (5) The semiconductor device described in any of (1) to (4), wherein at least one of the first and second transistors has two or more layers of semiconductor regions in which the channel is formed. (6) The semiconductor device according to any one of (1) to (5), wherein the width of the semiconductor region in which the channel is formed is different between the first and second transistors. (7) The semiconductor device according to any one of (1) to (6), further comprising a third transistor on the upper part of the semiconductor substrate, wherein the third transistor is arranged on the same plane as the upper transistor of the first and second transistors arranged in a stack. (8) The semiconductor device according to (7), wherein the drain of the first transistor and the drain of the third transistor are formed by a single semiconductor region, and wherein the source of the third transistor is directly connected to the gate electrode of the lower transistor of the first and second transistors arranged in a stack. (9) The semiconductor device according to any one of (1) to (8), wherein the gate electrodes of the first and second transistors are formed of a metal material, and the gate insulating films of the first and second transistors are formed of a high-dielectric-constant insulating film.(10) The semiconductor device according to any one of (1) to (9), wherein the first and second transistors are an amplification transistor and a selection transistor. (11) The semiconductor device according to (10), further comprising two or more transfer transistors and two or more charge storage units. (12) The semiconductor device according to any one of (1) to (11), wherein the first and second transistors are arranged side by side in a planar direction above the semiconductor substrate. (13) The semiconductor device according to any one of (1) to (12), further comprising the semiconductor substrate on which a photoelectric conversion unit is formed, wherein the semiconductor device is a photodetector that photoelectrically converts incident light in the photoelectric conversion unit and outputs a signal according to the amount of received light. (14) An electronic device comprising a semiconductor device having first and second transistors formed above a semiconductor substrate and connected in series, wherein channels of the first and second transistors are formed above the semiconductor substrate, and wherein the source of the first transistor and the drain of the second transistor are arranged above the semiconductor substrate by a single semiconductor region.

[0199] REFERENCE SIGNS LIST 1 Photodetector, 2 Pixel, 3 Pixel array section, 21 Semiconductor substrate, 41 p-type semiconductor region, 42 n-type semiconductor region, 43 Gate electrode, 44 n-type semiconductor region, 45 p-type semiconductor region, 46 Gate insulating film, 51 Gate electrode, 61 Wiring layer, 62 Interlayer insulating film, 63, 63' Gate electrode, 64 Drain, 65 Drain, 66 p-type semiconductor region, 67, 67' Gate insulating film, 68 Spacer, 71, 71' Gate electrode, 72 Source, 73 p-type semiconductor region, 91 Pixel separation section, 101 Source, 102 Gate electrode, 103 p-type semiconductor region, 105 Spacer, 411 First substrate, 412 Second substrate, 413 Third substrate, 441 Semiconductor substrate, 442 Semiconductor substrate 443 Semiconductor substrate, 511 Sensor pixel, 601 Electronic device, 603 Photodetector, PD Photodiode, TG, TG1, TG2 Transfer transistor, FD Floating diffusion, AMP Amplifying transistor, RST Reset transistor, SEL Select transistor

Claims

1. A semiconductor device formed on top of a semiconductor substrate, having first and second transistors connected in series, wherein channels of the first and second transistors are formed above the semiconductor substrate, and a source of the first transistor and a drain of the second transistor are formed as one semiconductor region above the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein a semiconductor region in which the channels of the first and second transistors are formed is configured by being stacked above the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein at least one of the first and second transistors has a structure in which a periphery of a semiconductor region in which a channel is formed is surrounded by a gate electrode.

4. The semiconductor device according to claim 1, wherein at least one of the first and second transistors has a structure in which a planar gate electrode is formed on an upper surface of a semiconductor region in which a channel is formed.

5. The semiconductor device according to claim 1, wherein at least one of the first and second transistors has two or more semiconductor regions in which channels are formed.

6. The semiconductor device according to claim 1, wherein widths of semiconductor regions in which channels are formed are different between the first and second transistors.

7. The semiconductor device according to claim 1, further having a third transistor on top of the semiconductor substrate, wherein the third transistor is arranged on the same plane as an upper transistor of the first and second transistors arranged in a stacked manner.

8. The semiconductor device according to claim 7, wherein a drain of the first transistor and a drain of the third transistor are configured by one semiconductor region, and a source of the third transistor and a gate electrode of a lower transistor of the first and second transistors arranged in a stacked manner are directly connected.

9. The semiconductor device according to claim 1, wherein gate electrodes of the first and second transistors are formed of a metal material, and gate insulating films of the first and second transistors are formed of high-k insulating films.

10. The semiconductor device according to claim 1, wherein the first and second transistors are an amplification transistor and a selection transistor.

11. The semiconductor device according to claim 10, further having two or more transfer transistors and two or more charge storage parts respectively.

12. The semiconductor device according to claim 1, wherein the first and second transistors are arranged side by side in a planar direction on the upper part of the semiconductor substrate.

13. The semiconductor device according to claim 1, further comprising the semiconductor substrate on which a photoelectric conversion unit is formed, the semiconductor device being a photodetector that photoelectrically converts incident light by the photoelectric conversion unit and outputs a signal corresponding to the amount of received light.

14. An electronic device comprising a semiconductor device having first and second transistors formed on the upper part of a semiconductor substrate and connected in series, wherein channels of the first and second transistors are formed above the semiconductor substrate, and a source of the first transistor and a drain of the second transistor are formed in one semiconductor region above the semiconductor substrate.

Images