Semiconductor device and method for producing semiconductor device

Abstract

This semiconductor device is provided with: a semiconductor substrate; a semiconductor layer which is positioned on the semiconductor substrate in the thickness direction of the semiconductor substrate and in which a first device region is established; a surface oxide film provided on a part of the surface of the semiconductor layer; and a silicon nitride film positioned on the surface oxide film in the thickness direction. In the first device region, there is disposed a PNP transistor having a p-type emitter, a p-type collector surrounding the emitter when viewed from the thickness direction, and an n-type base surrounding the collector when viewed from the thickness direction. The semiconductor device further comprises a spacer which is between the emitter and the collector when viewed from the thickness direction and which is positioned between the surface oxide film and the silicon nitride film in the thickness direction.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 discloses a lateral bipolar transistor having a collector region and an emitter region arranged side by side above a base region, characterized in that the collector region and the emitter region are formed by diffusing P-type or N-type impurities contained in a silicon germanium layer within the base region.

[0003] Japanese Patent Application Laid-Open No. 2004-111575

[0004] [Summary] An object according to one aspect of the present disclosure is to provide a semiconductor device that can suppress leakage current between an emitter and a collector while achieving miniaturization, and a method for manufacturing the semiconductor device.

[0005] A semiconductor device according to one aspect of the present disclosure comprises a semiconductor substrate, a semiconductor layer located on the semiconductor substrate in a thickness direction of the semiconductor substrate and in which a first device region is set, a surface oxide film provided on a portion of the surface of the semiconductor layer, and a silicon nitride film located on the surface oxide film in the thickness direction, wherein a PNP transistor is formed in the first device region, the PNP transistor having a p-type emitter, a p-type collector surrounding the emitter as viewed in the thickness direction, and an n-type base surrounding the collector as viewed in the thickness direction, and further comprising a spacer located between the emitter and the collector as viewed in the thickness direction, and between the surface oxide film and the silicon nitride film in the thickness direction.

[0006] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes a first step of forming a semiconductor layer on a semiconductor substrate, a second step of forming a surface oxide film on a surface of the semiconductor layer, a third step of forming a p-type first well region in a first device region of the semiconductor layer, a p-type second well region surrounding the first well region as viewed in the thickness direction of the semiconductor substrate, and an n-type third well region surrounding the second well region as viewed in the thickness direction, and also forming a first conductivity type fourth well region and a second conductivity type fifth well region in a second device region of the semiconductor layer, and a third step of forming a gate insulating film in the second device region. a fourth step of forming polysilicon on an insulating portion of the surface oxide film located in the first device region and simultaneously forming a gate on the gate insulating film; a sixth step of forming a p-type emitter in the first well region, a p-type collector in the second well region, and an n-type base in the third well region, as well as forming a source region in the fourth well region and a drain region in the fifth well region; and a seventh step of forming a silicon nitride film covering the polysilicon and the gate, wherein in the fifth step, the insulating portion is located between the emitter and the collector when viewed in the thickness direction.

[0007] FIG. 1 is a plan view showing a chip of a semiconductor device according to an embodiment. FIG. 2 is an enlarged view of region II shown in FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a schematic cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5A is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5B is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5C is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5D is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5E is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5F is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5G is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 5H is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 6 is a graph showing the base voltage-collector current characteristics of an L-PNP transistor according to a reference example. FIG. 7 is a graph showing the base voltage-base current characteristics of an L-PNP transistor included in a semiconductor device according to an embodiment. FIG. 8 is a graph showing the Early voltage of each L-PNP transistor.

[0008] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, identical elements or elements having the same functions will be designated by the same reference numerals, and duplicate explanations will be omitted. In this specification, the term "same" and similar words are not limited to "completely identical." Furthermore, since the drawings are intended to conceptually explain the embodiments, the dimensions and ratios of the components shown may differ from the actual dimensions.

[0009] FIG. 1 is a plan view showing a chip of a semiconductor device according to this embodiment. FIG. 2 is an enlarged view of region II shown in FIG. 1. FIG. 3 is a schematic cross-sectional view taken along line III-III shown in FIG. 2. FIG. 4 is a schematic cross-sectional view taken along line IV-IV shown in FIG. 1. The wiring shown in FIG. 2 is omitted in FIGS. 1 and 3. As shown in FIG. 1, the semiconductor device 1A includes a silicon chip 2 (semiconductor chip) having a rectangular parallelepiped shape. The chip 2 is one of multiple devices formed on a silicon wafer having a diameter of, for example, 300 mm (approximately 12 inches).

[0010] The chip 2 has a pair of main surfaces, a first main surface 3 and a second main surface 4, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D connecting the first main surface 3 and the second main surface 4. Hereinafter, the extension direction of the first side surface 5A and the second side surface 5B in a plan view is referred to as a first direction X, the extension direction of the third side surface 5C and the fourth side surface 5D in a plan view is referred to as a second direction Y, and the normal direction of the first main surface 3 and the second main surface 4 is referred to as a third direction Z. The second direction Y is a direction intersecting the first direction X in a plan view, and the third direction Z corresponds to the thickness direction of the chip 2. Note that in this specification, "plan view" corresponds to viewing from the third direction Z.

[0011] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from the third direction Z, but are not limited to this. In this embodiment, the first main surface 3 is the top surface, and the second main surface 4 is the bottom surface. Therefore, a configuration located near the first main surface 3 in the third direction Z corresponds to a configuration located on the top surface side (upper side) of the semiconductor device 1A, and a configuration located near the second main surface 4 in the third direction Z corresponds to a configuration located on the bottom surface side (lower side) of the semiconductor device 1A.

[0012] The semiconductor device 1A includes a first semiconductor region 6 located in an upper region within the chip 2. The first semiconductor region 6 is a region having a layer shape extending along the first main surface 3. For this reason, the first semiconductor region 6 is sometimes also referred to as a semiconductor layer. The first semiconductor region 6 is at least a part of an epitaxial semiconductor layer. The first semiconductor region 6 is exposed from, for example, a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The thickness of the first semiconductor region 6 is, for example, not less than 5 μm and not more than 20 μm. The first semiconductor region 6 has a first conductivity type. The impurity concentration of the first semiconductor region 6 is, for example, 1.0×10 １０ cm －３ Above 1.0 x 10 １３ cm －３ In this embodiment, the first conductivity type is n-type.

[0013] The semiconductor device 1A includes a second semiconductor region 7 located in a lower region within the chip 2. The second semiconductor region 7 is a region that has a second conductivity type and is fixed to a predetermined potential, and has a layer shape extending along the second main surface 4. The second semiconductor region 7 is exposed from, for example, the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is fixed to a back gate potential. The back gate potential may be a reference potential that serves as a reference for circuit operation, or may be a ground potential. In this embodiment, the second conductivity type is p-type.

[0014] The second semiconductor region 7 is connected to the first semiconductor region 6. The thickness of the second semiconductor region 7 may be 50 μm or more and 400 μm or less. The second semiconductor region 7 is at least a part of a p-type semiconductor substrate. That is, the chip 2 has the first semiconductor region 6 included in the epitaxial semiconductor layer and the second semiconductor region 7 included in the semiconductor substrate. In other words, the chip 2 has a layered structure including a semiconductor substrate and an epitaxial semiconductor layer located on the semiconductor substrate.

[0015] At least one of the first semiconductor region 6 and the second semiconductor region 7 of the semiconductor device 1A has a plurality of device regions 8 defined on the first main surface 3 and spaced apart from one another. In the semiconductor device 1A, the number and arrangement of the plurality of device regions 8 are determined as appropriate. Each of the plurality of device regions 8 includes a functional device formed using regions inside and outside the chip 2. The functional device includes, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional device may also include a circuit network that combines at least two of the semiconductor switching device, the semiconductor rectifying device, and the passive device.

[0016] The semiconductor switching device may include at least one of a bipolar transistor, a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a JFET. The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0017] The multiple device regions 8 include at least one first transistor region 9A (first device region) and at least one second transistor region 9B (second device region). The first transistor region 9A includes a bipolar transistor structure. In this embodiment, the bipolar transistor structure is a so-called lateral PNP bipolar transistor (L-PNP transistor). In other words, an L-PNP transistor is provided in the first transistor region 9A of this embodiment. The bipolar transistor structure is, for example, a high-voltage device. The second transistor region 9B includes a FET structure. In this embodiment, the FET structure is a so-called LDMISFET (Lateral Double Diffused MISFET), which is a type of field-effect transistor. In other words, an LDMISFET, which is a transistor, is provided in the second transistor region 9B of this embodiment. The FET structure is, for example, a high-voltage device to which a drain voltage of 800 V or more can be applied in the off state. Below, the structure of the first transistor region 9A and the structure of the second transistor region 9B will be described in order.

[0018] 3, the first transistor region 9A is a region defined by an element isolation region DR. The element isolation region DR is a region set in at least one of a part of the first semiconductor region 6 and a part of the second semiconductor region 7, and surrounds the first transistor region 9A in a planar view. Therefore, the element isolation region DR is located between the first transistor region 9A and another device region 8 including the second transistor region 9B. The element isolation region DR has, for example, a first portion 25 located on the second semiconductor region 7 and a second portion 26 located on the first portion 25. In one example, each of the first portion 25 and the second portion 26 is p-type. In one example, the impurity concentration of the second portion 26 is 1.0×10 １４ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0019] As shown in FIG. 3 , the first transistor region 9A is provided with base regions 11 located in both the first semiconductor region 6 and the second semiconductor region 7, and emitter contact 12, collector contact 13, and base contact 14 located in the first semiconductor region 6. In addition, the first semiconductor region 6 has a first well region 15 located below the emitter contact 12, a second well region 16 located below the collector contact 13, and a third well region 17 located below the base contact 14. As shown in FIG. 2 , the first transistor region 9A is provided with a wiring W1 electrically connected to the emitter contact 12 via a contact C1, a wiring W2 electrically connected to the collector contact 13 via a contact C2, and a wiring W3 electrically connected to the base contact 14 via a contact C3. The wirings W1, W2, and W3 are spaced apart from one another. As a result, the wirings W1, W2, and W3 are electrically insulated from one another.

[0020] The base region 11 includes an n-type buried region 11a located in both the first semiconductor region 6 and the second semiconductor region 7, and an n-type region 11b located in the first semiconductor region 6 and covering the n-type buried region 11a. The impurity concentration of the n-type buried region 11a is higher than the impurity concentration of the n-type region 11b, and is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The impurity concentration of the n-type region 11b is, for example, 1.0×10 １０ cm －３ Above 1.0 x 10 １６ cm －３ The impurity concentration of the n-type region 11 b may be the same as the impurity concentration of the first semiconductor region 6 .

[0021] The emitter contact portion 12 is a p-type region that functions as a p-type emitter in a PNP bipolar transistor. In plan view, the emitter contact portion 12 is located closer to the center of the first transistor region 9A than the collector contact portion 13. For example, the emitter contact portion 12 is located in the center of the first transistor region 9A. The impurity concentration of the emitter contact portion 12 is, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The following is the result.

[0022] The collector contact portion 13 is a p-type region that functions as a p-type collector in a PNP bipolar transistor. In plan view, the collector contact portion 13 is located closer to the center of the first transistor region 9A than the base contact portion 14. The collector contact portion 13 has a frame shape that surrounds the emitter contact portion 12. The impurity concentration of the collector contact portion 13 is, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The following is the result.

[0023] The base contact portion 14 is an n-type region that functions as an n-type base in a PNP bipolar transistor. In plan view, the base contact portion 14 has a frame shape that surrounds the collector contact portion 13 and the emitter contact portion 12. The impurity concentration of the base contact portion 14 is, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The following is the result.

[0024] The first well region 15 is a p-type region in contact with the emitter contact portion 12, and is formed, for example, by diffusing p-type impurities contained in the emitter contact portion 12 into the first semiconductor region 6. The impurity concentration of the first well region 15 is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0025] The second well region 16 is a p-type region in contact with the collector contact portion 13, and is formed, for example, by diffusing p-type impurities contained in the collector contact portion 13 into the first semiconductor region 6. The impurity concentration of the second well region 16 is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0026] The third well region 17 is an n-type region in contact with the base contact portion 14, and is formed, for example, by diffusing n-type impurities contained in the base contact portion 14 into the first semiconductor region 6. In this embodiment, the third well region 17 reaches the n-type buried region 11a, but is not limited to this. The impurity concentration of the third well region 17 is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0027] As shown in FIG. 3, the first transistor region 9A includes a first insulating film 21 provided on a portion of the surface 6a of the first semiconductor region 6, and a second insulating film 22 located on the first insulating film 21 in the third direction Z.

[0028] The first insulating film 21 includes, for example, silicon oxide. In this embodiment, the first insulating film 21 is a local oxidation of silicon (LOCOS) film, which is a surface oxide film formed by selectively oxidizing the surface 6 a of the first semiconductor region 6, but is not limited to this. The first insulating film 21 may also be a shallow trench isolation (STI), which is a surface oxide film formed on the surface 6 a of the first semiconductor region 6. The shallow trench isolation (STI) may be formed below the LOCOS film. The STI includes, for example, an insulator (silicon oxide) buried in a trench formed by digging down a semiconductor layer. The first insulating film 21 may have a single-layer structure or a multilayer structure. The thickness of the first insulating film 21 is, for example, 100 nm to 1000 nm. The first insulating film 21 has a first insulating portion 21a located between the emitter contact portion 12 and the collector contact portion 13 in a planar view, a second insulating portion 21b located between the collector contact portion 13 and the base contact portion 14 in a planar view, and a third insulating portion 21c located outside the base contact portion 14 in a planar view. The first insulating portion 21a and the second insulating portion 21b each have a frame shape in a planar view. The first insulating portion 21a may overlap the first well region 15 in the third direction Z, or may overlap the second well region 16 in the third direction Z. The second insulating portion 21b may overlap the second well region 16 in the third direction Z, or may overlap the third well region 17 in the third direction Z. The third insulating portion 21c may overlap the element isolation region DR in the third direction Z.

[0029] The second insulating film 22 is a silicon nitride film that covers at least the first insulating film 21. As a result, the etching rate of the second insulating film 22 is different from the etching rate of a silicon oxide film. Therefore, for example, when a silicon oxide film is formed on the second insulating film 22, the second insulating film 22 can function as an etching stopper in etching the silicon oxide film. The second insulating film 22 is formed, for example, by CVD (Chemical Vapor Deposition). The thickness of the second insulating film 22 is, for example, 10 nm to 100 nm. The second insulating film 22 is provided with a first opening 22a located above the emitter contact portion 12, a second opening 22b located above the collector contact portion 13, and a third opening 22c located above the base contact portion 14. The first opening 22a is a region where a contact C1 is provided, the second opening 22b is a region where a contact C2 is provided, and the third opening 22c is a region where a contact C3 is provided. The first opening 22a, the second opening 22b, and the third opening 22c are each formed by, for example, etching.

[0030] As shown in FIG. 3 , the first transistor region 9A includes a spacer S located between the emitter contact 12 and the collector contact 13 in a plan view, and between the first insulating portion 21 a of the first insulating film 21 and the second insulating film 22 in the third direction Z. The spacer S is a member that increases the physical distance between the first semiconductor region 6 (particularly, the portion of the surface 6 a located between the emitter contact 12 and the collector contact 13) and the second insulating film 22, and has a frame shape that surrounds the emitter contact 12 in a plan view. Therefore, the emitter contact 12 is surrounded by the spacer S in a plan view. In this embodiment, the spacer S is conductive and electrically connected to the wiring W3 via the contact C4. Therefore, the spacer S in this embodiment is electrically connected to the base contact 14 via the wiring W3. The spacer S may be made of a metal such as aluminum, nickel, copper, or a known alloy, or may be made of polysilicon. In this embodiment, the spacer S includes polysilicon. In this case, the polysilicon may have either the first conductivity type or the second conductivity type. The thickness of the spacer S is not less than 0.1 nm and not more than 500 nm.

[0031] The second transistor region 9B includes a first potential region 111, a second potential region 112, and a drift region 113 located within the first semiconductor region 6. The first potential region 111 is a region to which a first potential is applied and is located in the center of the second transistor region 9B. The second potential region 112 is a region to which a second potential different from the first potential is applied and is separated from the first potential region 111 in a cross-sectional view. The second potential region 112 surrounds the first potential region 111 in a planar view. For example, the first potential region 111 is a high potential region to which a high potential (first potential) is applied, and the second potential region 112 is a low potential region to which a low potential (second potential) less than the high potential is applied. The drift region 113 is located between the first potential region 111 and the second potential region 112.

[0032] The first potential region 111 includes a well region 114 and a drain region 115. The well region 114 and the drain region 115 are each provided above the first semiconductor region 6. The well region 114 surrounds the drain region 115 in a plan view and is in contact with the drain region 115. Therefore, the potential of the well region 114 and the potential of the drain region 115 are fixed to the same potential (drain potential). In a plan view, the drain region 115 is separated from the periphery of the well region 114. In other words, in a plan view, the drain region 115 is located inside the periphery of the well region 114. The n-type impurity concentration of the well region 114 is higher than the n-type impurity concentration of the first semiconductor region 6. Furthermore, the n-type impurity concentration of the drain region 115 is higher than the n-type impurity concentration of the well region 114. The n-type impurity concentration of the well region 114 is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The n-type impurity concentration of the drain region 115 is, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The n-type impurity concentration of the drain region 115 may be the same as the impurity concentration of the base contact portion 14 in the first transistor region 9A.

[0033] In this embodiment, the well region 114 has an oval shape in a planar view, but is not limited to this. The well region 114 may have a circular, oval, or polygonal (e.g., rectangular) shape in a planar view. In this embodiment, the drain region 115 has an oval shape in a planar view, similar to the well region 114, but is not limited to this. The drain region 115 may have a circular, oval, or polygonal (e.g., rectangular) shape in a planar view.

[0034] The second potential region 112 includes a p-type body region 116. The body region 116 has, for example, an oval ring shape surrounding the drain region 115 in a plan view. The body region 116 extends in the third direction Z from the surface 6 a of the first semiconductor region 6 to the boundary between the first semiconductor region 6 and the second semiconductor region 7. Therefore, the body region 116 is electrically connected to the second semiconductor region 7 and is fixed to the potential of the second semiconductor region 7 (for example, the back gate potential). The body region 116 may be provided in both the first semiconductor region 6 and the second semiconductor region 7. The p-type impurity concentration of the body region 116 is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0035] The semiconductor device 1A includes a source region 117 provided in the body region 116. In this embodiment, the semiconductor device 1A includes multiple source regions 117, but is not limited to this. Each of the multiple source regions 117 is an n-type region and is fixed to a source potential. Specifically, a source potential is applied to each of the multiple source regions 117 from outside the chip 2. A p-type channel region 118 in the FET structure is formed in the first semiconductor region 6 between the source region 117 and the drift region 113 in the first direction X. Therefore, a current path extending in the first direction X is formed in the drift region 113 between the source region 117 and the drift region 113 in the first direction X. The source potential corresponds to the second potential. The n-type impurity concentration of the source region 117 is higher than the n-type impurity concentration of the well region 114. The n-type impurity concentration of the source region 117 may be the same as the n-type impurity concentration of the drain region 115. The n-type impurity concentration of the source region 117 is, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The channel region 118 controls whether the current path between the drain region 115 and the source region 117 is conductive or non-conductive.

[0036] The second potential region 112 includes a contact region 119 provided in the body region 116. In this embodiment, the semiconductor device 1A includes a plurality of contact regions 119, but is not limited to this. Each of the plurality of contact regions 119 is a p-type region. The p-type impurity concentration of each contact region 119 may be higher than the p-type impurity concentration of the body region 116. For example, the p-type impurity concentration of the contact region 119 may be, for example, 1.0×10 １８ cm －３ Above 1.0 x 10 ２１ cm －３ The following is an explanation. Each contact region 119 has a band shape in plan view, and is located within the body region 116 and inside the outer periphery of the body region 116. Furthermore, each contact region 119 is located closer to the outer periphery of the body region 116 than the source region 117. Each contact region 119 is in contact with the outer periphery of the body region 116, but this is not limited to this. Each of the multiple contact regions 119 is adjacent to the corresponding source region 117 in plan view. Therefore, in the surface layer portion of the body region 116, there coexist the source region 117, which is fixed to the source potential, and the contact region 119, which is fixed to a potential different from the source potential.

[0037] The semiconductor device 1A includes an n-type drift region 113 located between the drain region 115 and the source region 117 and in a surface layer portion of the first semiconductor region 6. The drift region 113 has, for example, an oval ring shape surrounding the drain region 115 in a plan view. The width of the drift region 113 is, for example, not less than 50 μm and not more than 200 μm. The width of the drift region 113 corresponds to the distance between the first potential region 111 and the second potential region 112 and is, for example, approximately constant along the oval ring shape.

[0038] The second transistor region 9B is provided with an insulating film 122 provided on a part of the surface 6a of the first semiconductor region 6. The insulating film 122 contains, for example, silicon oxide. In this embodiment, the insulating film 122 is formed simultaneously with the first insulating film 21 (see FIG. 3 ) of the first transistor region 9A. The insulating film 122 is located on the first semiconductor region 6 and covers the region between the drain region 115 and the source region 117 in the first semiconductor region 6.

[0039] The semiconductor device 1A includes a field electrode 125 (field plate) located on the insulating film 122. The field electrode 125 has functions such as suppressing electric field disturbances in the first semiconductor region 6, suppressing localized electric field concentration, and monitoring a high drain-gate voltage Vdg. The field electrode 125 is a high-resistance film connected to the first potential region 111 and the second potential region 112. The field electrode 125 overlaps the drift region 113 in the third direction Z. In this embodiment, the field electrode 125 does not overlap the channel region 118 in the third direction Z. The field electrode 125 includes, for example, polysilicon. In this case, the polysilicon included in the field electrode 125 may have the same or substantially the same crystallinity as the polysilicon included in the spacer S in the first transistor region 9A. The field electrode 125 is electrically connected to at least the drain region 115. In this embodiment, the field electrode 125 forms a potential gradient that gradually changes from the first potential region 111 toward the second potential region 112. The provision of such field electrode 125 suppresses bias in the electric field distribution in drift region 113. The thickness of field electrode 125 is, for example, not less than 50 nm and not more than 500 nm.

[0040] For example, the field electrode 125 concentrically surrounds the first potential region 111 including the drain region 115 multiple times in a planar view. In this embodiment, the field electrode 125 has a spiral shape surrounding the first potential region 111 in a planar view. The field electrode 125 may have a line width of 0.5 μm to 5 μm. The line width is defined by the width in a direction perpendicular to the extension direction (i.e., the spiral direction) of the field electrode 125. The field electrode 125 may have a resistance value of 10 MΩ to 100 MΩ. The pitch of the field electrode 125 may be 1 μm to 10 μm. The pitch of the field electrode 125 is defined by the distance between adjacent line portions. The number of turns of the field electrode 125 is, for example, 5 to 100. The number of turns may be 75 or less, or 50 or less.

[0041] The semiconductor device 1A includes an inner field electrode 129 located on the insulating film 122 and connected to the field electrode 125. The inner field electrode 129 is located closer to the drain region 115 than the field electrode 125 in a planar view. For example, the inner field electrode 129 is located in a region surrounded by the field electrode 125 in a planar view. The potential of the inner field electrode 129 is fixed to a first potential. The inner field electrode 129 may be part of the field electrode 125. In this case, the inner field electrode 129 functions as the innermost peripheral portion of the field electrode 125. The inner field electrode 129 includes, for example, the same material as the field electrode 125. The width of the inner field electrode 129 is, for example, 1 μm or more and 15 μm or less. The inner field electrode 129 may be formed wider than the field electrode 125. In this case, the width of the inner field electrode 129 is, for example, 1.5 to 5 times the width of the field electrode 125. The width of the inner field electrode 129 may be equal to or smaller than the line width of the field electrode 125 .

[0042] The semiconductor device 1A includes a gate insulating film 131 that contacts the first semiconductor region 6 and is located on the channel region 118. A portion of the gate insulating film 131 may overlap the insulating film 122. The thickness of the gate insulating film 131 is less than that of the insulating film 122, and is, for example, 10 nm to 200 nm. That is, the thickness of the gate insulating film 131 is different from the thickness of the first insulating film 21, which is a surface oxide film, and the thickness of the insulating film 122. The gate insulating film 131 has a single-layer structure or a multilayer structure and includes, for example, a silicon oxide film. In this embodiment, the gate insulating film 131 has an oval ring shape surrounding the insulating film 122 in a plan view. The gate insulating film 131 covers a portion of the drift region 113 and a portion of the body region 116.

[0043] The semiconductor device 1A includes a gate electrode 132 (gate) located on a gate insulating film 131. The gate electrode 132 includes, for example, a metal film, an alloy film, polysilicon, or the like. When the gate electrode 132 includes polysilicon, the polysilicon may have the same or substantially the same crystallinity as the polysilicon included in the spacer S in the first transistor region 9A. The gate electrode 132 overlaps not only the channel region 118 but also the drift region 113 in the third direction Z. The gate electrode 132 has an oval ring shape extending along the channel region 118 in a plan view, but is not limited to this. The gate electrode 132 has a lead portion 133 extending from the gate insulating film 131 onto the insulating film 122. The lead portion 133 has an oval ring shape surrounding a field electrode 125 (described later) in a plan view and is located above the drift region 113. The entire gate electrode 132 is located outside the field electrode 125 in a plan view.

[0044] The semiconductor device 1A includes an insulating layer 140 for protecting elements, wiring, and the like. The insulating layer 140 has a layered structure including multiple interlayer insulating films 141 stacked on top of each other. The number of stacked interlayer insulating films 141 is arbitrary and is not limited to a specific number. The insulating layer 140 may include three or more interlayer insulating films 141. FIG. 4 shows a first interlayer insulating film 141A, a second interlayer insulating film 141B, and a third interlayer insulating film 141C out of the multiple interlayer insulating films 141. Although not shown, multiple interlayer insulating films may also be provided in the first transistor region 9A.

[0045] The first interlayer insulating film 141A, the second interlayer insulating film 141B, and the third interlayer insulating film 141C are stacked in this order in the third direction Z. In the second transistor region 9B, the first interlayer insulating film 141A covers at least the insulating film 122, the gate insulating film 131, and the gate electrode 132. That is, the gate electrode 132 is located below the first interlayer insulating film 141A. In this embodiment, the first interlayer insulating film 141A is a silicon nitride film formed simultaneously with the second insulating film 22 in the first transistor region 9A. Therefore, the gate electrode 132 in the second transistor region 9B is located below the first interlayer insulating film 141A, which is a silicon nitride film. The second interlayer insulating film 141B is an insulating film covering the first interlayer insulating film 141A. The third interlayer insulating film 141C is an insulating film covering the second interlayer insulating film 141B. The thicknesses of first interlayer insulating film 141A, second interlayer insulating film 141B, and third interlayer insulating film 141C are each determined depending on, for example, the function required of field electrode 125, the thickness of insulating film 122, etc. Each of second interlayer insulating film 141B and third interlayer insulating film 141C includes at least one of a silicon oxide film and a silicon nitride film. Each of second interlayer insulating film 141B and third interlayer insulating film 141C may have a single-layer structure or a multilayer structure.

[0046] Multiple wiring films 142 are provided within the insulating layer 140. In this embodiment, multiple interlayer insulating films 141 and multiple wiring films 142 are alternately stacked, resulting in a multilayer wiring structure in the second transistor region 9B. The number of stacked wiring films 142 is arbitrary and is not limited to a specific number. FIG. 4 illustrates the multiple wiring films 142, with a first wiring film 142A located on the second interlayer insulating film 141B and a second wiring film 142B located on the third interlayer insulating film 141C. Each wiring film 142 includes, for example, at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film. Therefore, each of the first wiring film 142A and the second wiring film 142B may have a single-layer structure or a multilayer structure. Although not shown, a multilayer wiring structure may also be provided in the first transistor region 9A.

[0047] A plurality of first vias 143 and a plurality of second vias 149 are provided in the insulating layer 140. Each of the plurality of first vias 143 is a conductive portion that electrically connects conductive portions, such as the first potential region 111, the second potential region 112, and the field electrode 125, located below at least one of the first interlayer insulating film 141A and the second interlayer insulating film 141B, to the first wiring film 142A. Each of the plurality of first vias 143 penetrates at least one of the first interlayer insulating film 141A and the second interlayer insulating film 141B. Each of the plurality of second vias 149 is a conductive portion that electrically connects conductive portions, such as the first wiring film 142A located below the third interlayer insulating film 141C, to the second wiring film 142B, and penetrates the third interlayer insulating film 141C. Each of the plurality of first vias 143 and the plurality of second vias 149 is, for example, a tungsten plug.

[0048] The first wiring film 142A includes, for example, a first drain wiring 144, a first source wiring 145, a first gate wiring 146, a field wiring 147, and a field wiring 148. The first drain wiring 144 is electrically connected to the drain region 115 through one or more first vias 143. The first source wiring 145 is electrically connected to the source region 117 through one or more first vias 143. The first gate wiring 146 is electrically connected to the gate electrode 132 through one or more first vias 143. The field wiring 147 is electrically connected to one end of the field electrode 125 through one or more first vias 143. The field wiring 147 is electrically connected to, for example, the inner field electrode 129 through one or more first vias 143. The field wiring 147 may be part of the first drain wiring 144. The field wiring 148 is electrically connected to the other end of the field electrode 125 through one or more first vias 143. The field wiring 148 may be part of the first source wiring 145 .

[0049] The multiple second wiring films 142B include, for example, a second drain wiring 150, a second source wiring 151, and a second gate wiring (not shown). The second drain wiring 150 is electrically connected to the first drain wiring 144 and the field wiring 147 through multiple second vias 149. The second drain wiring 150 overlaps the drain region 115 and the field wiring 147. The second drain wiring 150 may overlap the entire drain region 115 and the entire field wiring 147. The second drain wiring 150 may overlap the inner field electrode 129. The second source wiring 151 is electrically connected to the first source wiring 145 and the field wiring 148 through multiple second vias 149. The second source wiring 151 has a ring shape extending along the body region 116 in a plan view. The second source wiring 151 may overlap the gate electrode 132 and the field wiring 148. The second source wiring 151 may overlap the entire body region 116 , the entire gate electrode 132 , and the entire field wiring 148 .

[0050] Next, an example of a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 5A to 5H. Each of Figures 5A to 5H is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to this embodiment. Each of Figures 5A to 5H shows a method for manufacturing a device region different from the first transistor region 9A and the second transistor region 9B. The L-PNP transistor provided in the first transistor region 9A and the LDMISFET provided in the second transistor region 9B can be formed simultaneously by the manufacturing method described below.

[0051] First, as a preparation step, as shown in FIG. 5A , a portion of the second semiconductor region 7, which is a semiconductor substrate, is doped with p-type impurities. This forms a p-type impurity region 31 for defining the first device region R1, a p-type impurity region 32 for defining the second device region R2, and a p-type impurity region 33 for defining the third device region R3. Next, another portion of the second semiconductor region 7 is doped with n-type impurities. This forms n-type impurity regions 34-36 in the first device region R1, the second device region R2, and the third device region R3, respectively. Each of the p-type impurity regions 31-33 will later function as part of an element isolation region. Each of the n-type impurity regions 34-36 will later function as part of an n-type buried region, for example. Note that the p-type impurity regions 31-33 may be formed after the formation of the n-type impurity regions 34-36.

[0052] In this embodiment, an L-PNP transistor is later formed in the first device region R1, a DMOS (Double-diffused MOS) transistor is later formed in the second device region R2, and a CMOS transistor is later formed in the third device region R3. Note that although the shape of the L-PNP transistor later formed in the first device region R1 is slightly different from the shape of the L-PNP transistor shown in FIG. 3, these L-PNP transistors can be formed simultaneously. Therefore, the description of the manufacturing method for the L-PNP transistor later formed in the first device region R1 can be used as a description of the manufacturing method for the L-PNP transistor provided in the first transistor region 9A.

[0053] 5B , a first semiconductor region 6, which is a semiconductor layer, is formed on the second semiconductor region 7 (first step). In the first step, for example, the first semiconductor region 6 is epitaxially grown on the second semiconductor region 7. In the first step, some of the p-type impurities contained in the p-type impurity regions 31 to 33 diffuse into the first semiconductor region 6. Similarly, some of the n-type impurities contained in the n-type impurity regions 34 to 36 diffuse into the first semiconductor region 6. As a result, a portion of each of the p-type impurity regions 31 to 33 expands into the first semiconductor region 6, and a portion of each of the n-type impurity regions 34 to 36 expands into the first semiconductor region 6.

[0054] 5C, a portion of the surface 6a of the first semiconductor region 6 is oxidized by a known method to form surface oxide films 41 to 43 (second step). In the second step, the surface oxide film 41 is formed in the first device region R1, the surface oxide film 42 is formed in the second device region R2, and the surface oxide film 43 is formed in the third device region R3. The surface oxide film 41 is formed simultaneously with the first insulating film 21 shown in FIG.

[0055] 5D , various doping processes are performed on the first semiconductor region 6 to form at least one of p-type impurity regions and n-type impurity regions in each of the first device region R1 to third device region R3 (step 3). In step 3, a p-type first well region 51, a p-type second well region 52 surrounding the first well region 51 as viewed from the third direction Z, and an n-type third well region 53 surrounding the second well region 52 as viewed from the third direction Z are formed in the first device region R1 of the first semiconductor region 6. A portion of the first well region 51 corresponds to the first well region 15 of the first transistor region 9A. A portion of the second well region 52 corresponds to the second well region 16 of the first transistor region 9A, and a portion of the third well region 53 corresponds to the third well region 17 of the first transistor region 9A.

[0056] In the third step, an n-type fourth well region 55 and a p-type fifth well region 56 are formed in the second device region R2 of the first semiconductor region 6, and an n-type impurity region 57 is formed in the third device region R3 of the first semiconductor region 6. In the third step, the first well region 51, the second well region 52, and the fifth well region 56 are formed simultaneously. Similarly, the third well region 53 and the fourth well region 55 are formed simultaneously. The n-type impurity region 57 may be formed simultaneously with the third well region 53, or may be formed at different times. The first well region 51, etc. may be formed before the formation of the second well region 52, etc., or may be formed after the formation of the second well region 52, etc.

[0057] In the third step, an element isolation region DR1 located between the first device region R1 and the second device region R2, an element isolation region DR2 located between the first device region R1 and the third device region R3, and the like are formed in the first semiconductor region 6.

[0058] 5E, gate insulating films 61 and 62 are formed in the second device region R2 and the third device region R3, respectively (fourth step). In the fourth step, the gate insulating film 61 is formed in the second device region R2 and the gate insulating film 62 is formed in the third device region R3 by a known method such as thermal oxidation.

[0059] Next, as shown in FIG. 5F , polysilicon 71 is formed on a portion of the surface oxide film 41, and gates 72 and 73 are simultaneously formed on the gate insulating films 61 and 62 (step 5). In step 5, polysilicon 71, which functions as a spacer, is formed on the insulating portion 41a of the surface oxide film 41. The insulating portion 41a is a portion of the surface oxide film 41 that surrounds the first well region 51 and is also surrounded by the second well region 52 when viewed from the third direction Z. Therefore, the insulating portion 41a is located between an emitter contact portion 81 and a collector contact portion 82 (see FIG. 5G ), which will be described later, in a plan view. The gate 72 is polysilicon formed on the gate insulating film 61 and functions as a gate for a DMOS to be formed later. A portion of the gate 72 may be formed on the surface oxide film 42, not on the gate insulating film 61. The gate 73 is polysilicon formed on the gate insulating film 62 and functions as a gate for a CMOS to be formed later. Therefore, the gates 72 and 73 contain polysilicon having the same or substantially the same crystallinity as the polysilicon 71 .

[0060] Next, as shown in FIG. 5G , various doping processes are performed on the first semiconductor region 6 (step 6). In step 6, in the first device region R1, a p-type emitter contact 81 is formed in the first well region 51, a p-type collector contact 82 is formed in the second well region 52, and an n-type base contact 83 is formed in the third well region 53. In the second device region R2, an n-type drain region 84 is formed in the fourth well region 55, and a p-type source region 85 is formed in the fifth well region 56. In addition, a p-type drain region 86 and a p-type source region 87 are formed in the third device region R3. In step 6, the emitter contact 81, the collector contact 82, the source region 85, the drain region 86, and the source region 87 are formed simultaneously. Similarly, the base contact 83 and the drain region 84 are formed simultaneously. The emitter contact 81 and the like may be formed before or after the base contact 83 and the like are formed.

[0061] 5H, a silicon nitride film 91 is formed to cover the polysilicon 71 and the gate 72 (seventh step). In the seventh step, the silicon nitride film 91 is formed by a known method such as CVD. The silicon nitride film 91 is formed simultaneously with the second insulating film 22 in the first transistor region 9A and the first interlayer insulating film 141A in the second transistor region 9B. Through the above steps, an L-PNP transistor is formed in the first device region R1, a DMOS (double-diffused MOS) transistor is formed in the second device region R2, and a CMOS transistor is formed in the third device region R3.

[0062] 4, an interlayer insulating film, a wiring film, a via, and the like are formed and patterned. As a result, for example, the polysilicon 71 is electrically connected to the base contact portion 83. Through the above steps, the semiconductor device 1A is manufactured.

[0063] Next, the effects achieved by the semiconductor device 1A manufactured by the manufacturing method according to this embodiment will be described with reference to the reference example described below and Figures 6 to 8. The semiconductor device according to the reference example described below has the same configuration as the semiconductor device 1A according to this embodiment, except that the L-PNP transistor does not have a spacer.

[0064] FIG. 6 is a diagram showing the base voltage-collector current characteristics of an L-PNP transistor according to a reference example. In FIG. 6, the horizontal axis represents base voltage, and the vertical axis represents collector current. In FIG. 6, plot 201 shows the base voltage-collector voltage waveform of an L-PNP transistor according to a reference example (hereinafter referred to as the "initial L-PNP transistor") that was not subjected to a voltage stress test at high temperatures (hereinafter simply referred to as a voltage stress test or voltage stress) described below. This waveform was obtained by varying the base voltage from 0 V to -1.2 V under the following conditions: device temperature: 25°C, collector voltage: -3 V, and emitter voltage: ground potential. Furthermore, plot 202 shows the base voltage-collector voltage waveform of an L-PNP transistor according to a reference example that was subjected to a voltage stress test described below for 250 hours (hereinafter referred to as the "L-PNP transistor after short-term stress test"). Plot 203 shows the waveform of the base voltage-collector voltage of an L-PNP transistor according to a reference example (hereinafter referred to as "L-PNP transistor after long-term stress test") that underwent a voltage stress test described below for 750 hours. In the voltage stress test described above, the collector potential of the L-PNP transistor was set to ground potential, and the emitter and base potentials were set to 7 V in an oven set to 150°C. After the voltage stress test was performed, the L-PNP transistor was removed from the oven and allowed to stand without any stress being applied. Then, after the temperature of the L-PNP transistor had dropped to 25°C, the waveform of the base voltage-collector voltage of the L-PNP transistor was measured.

[0065] As shown in plots 201 and 202 of Figure 6, the base voltage-collector voltage characteristics of the L-PNP transistor after the short-term stress test are almost unchanged from the base voltage-collector voltage characteristics of the initial L-PNP transistor. On the other hand, as shown in plots 201 and 203, the base voltage-collector voltage characteristics of the L-PNP transistor after the long-term stress test are significantly different from the base voltage-collector voltage characteristics of the initial L-PNP transistor. In particular, as shown in plot 203, the leakage current between the collector and emitter of the L-PNP transistor after the long-term stress test significantly increases when the base voltage is approximately 0V to -0.5V. From the above, it can be seen that the leakage current between the collector and emitter of the L-PNP transistor of the reference example tends to increase depending on the application time of voltage stress.

[0066] FIG. 7 is a diagram showing the base voltage-base current characteristics of the L-PNP transistor included in the semiconductor device 1A according to this embodiment. In FIG. 7, the horizontal axis represents base voltage, and the vertical axis represents base current. In FIG. 7, plot 301 shows the base voltage-base current waveform of the initial L-PNP transistor, plot 302 shows the base voltage-base current waveform of the L-PNP transistor after a short-term stress test, and plot 303 shows the base voltage-collector current waveform of the L-PNP transistor after a long-term stress test. The above-mentioned waveforms were obtained by varying the base voltage from 0 V to -1.2 V under the following conditions: device temperature: 25°C, collector voltage: -3 V, and emitter voltage: ground potential. As shown in FIG. 7, it can be seen that the base current leakage does not change depending on the application time of voltage stress.

[0067] The current gain of a bipolar transistor is expressed by IC (collector current) / IB (base current). Based on the results shown in Figures 6 and 7, the current gain of the L-PNP transistor of the reference example can fluctuate even at low collector currents depending on the application time of voltage stress. For this reason, it can be said that the current gain of the bipolar transistor of the reference example is unstable.

[0068] 8 is a diagram showing the Early voltages of the L-PNP transistors. In FIG. 8, graph 401 shows the Early voltages of the L-PNP transistors of the embodiment, and graph 402 shows the Early voltages of the L-PNP transistors of the reference example. As shown in FIG. 8, the Early voltage of the L-PNP transistor of the semiconductor device 1A of this embodiment is about 25% higher than the Early voltage of the L-PNP transistor of the semiconductor device of the reference example.

[0069] As described above, the semiconductor device 1A according to this embodiment differs from the semiconductor device according to the reference example in that it includes a spacer S. Therefore, it can be said that the inclusion of the spacer S in the L-PNP transistor reduces the leakage current between the emitter and collector and improves the Early voltage. These phenomena are presumed to be due to the position of the second insulating film 22, a silicon nitride film, located on the first insulating film 21. In the reference example, the second insulating film, a silicon nitride film, is located directly above the first insulating film. Here, the silicon nitride film contains a large number of dangling bonds. The intrinsic charge of these dangling bonds tends to become biased due to use of the semiconductor device at high temperatures, etc. Such changes in the charge state of the second insulating film tend to cause negative charges to become biased at the interface between the first insulating film and the second insulating film. As a result, when a voltage is applied to the L-PNP transistor according to the reference example for a long period of time at high temperatures, for example, holes gather at the interface between the first semiconductor region and the first insulating film. Therefore, when a voltage is applied to the L-PNP transistor according to the reference example for a long period of time at high temperatures, it is presumed that a leakage current occurs between the emitter and collector via the collected holes described above.

[0070] In contrast, in the L-PNP transistor of the semiconductor device 1A manufactured by the above-described manufacturing method, the spacer S is located between the emitter contact 12 and the collector contact 13, as viewed from the third direction Z, and between the first insulating film 21 and the second insulating film 22. This increases the physical distance between the first semiconductor region 6 and the second insulating film 22 between the emitter contact 12 and the collector contact 13. Therefore, even if a change in the charge state of the second insulating film 22 occurs as described above, holes are less likely to collect at the interface between the first semiconductor region 6 and the first insulating film 21. Therefore, even if a voltage is applied to the L-PNP transistor of the semiconductor device 1A for a long period of time at a high temperature, leakage current is less likely to occur between the emitter contact 12 and the collector contact 13. Therefore, according to this embodiment, the first transistor region 9A can be miniaturized, and leakage current between the emitter contact 12 and the collector contact 13 can be suppressed even if a voltage is applied to the semiconductor device 1A for a long period of time at a high temperature. Therefore, in this embodiment, it is estimated that even after the voltage stress test is performed for 2000 hours, the base voltage-collector voltage characteristics will remain almost unchanged from the base voltage-collector voltage characteristics before the voltage stress test.

[0071] In one example, the spacer S is conductive and electrically connected to the base contact portion 14. In this case, even if the spacer S is conductive, the charge state of the spacer S is less susceptible to the influence of the second insulating film 22. Therefore, even if a voltage is applied to the semiconductor device 1A for a long period of time at a high temperature, leakage current between the emitter contact portion 12 and the collector contact portion 13 can be effectively suppressed.

[0072] In one example, the spacer S includes polysilicon. Additionally, a second transistor region 9B separated from the first transistor region 9A is defined in the first semiconductor region 6, and a transistor (LDMISFET) having a source region 117, a drain region 115, and a gate electrode 132 located below a first interlayer insulating film 141A that is a silicon nitride film is located in the second transistor region 9B, and the gate electrode 132 includes polysilicon having the same or substantially the same crystallinity as the polysilicon included in the spacer S. This makes it possible to effectively suppress leakage current between the emitter contact portion 12 and the collector contact portion 13 in the L-PNP transistor without increasing the number of manufacturing steps of the semiconductor device 1A.

[0073] In one example, the transistor has a gate insulating film 131 located below a gate electrode 132, and the thickness of the gate insulating film 131 is different from the thickness of the insulating film 122, which is a surface oxide film. For example, by making the thickness of the gate insulating film 131 smaller than the thickness of the insulating film 122, the switching characteristics of the transistor can be improved.

[0074] In one example, an isolation region DR1 located between the first device region R1 and the second device region R2 is set in the first semiconductor region 6. This makes it possible to prevent a short circuit between the first device region R1 and the second device region R2.

[0075] In one example, the spacer S has a frame shape surrounding the emitter contact portion 12 when viewed from the third direction Z. In this case, leakage current between the emitter contact portion 12 and the collector contact portion 13 in the L-PNP transistor can be effectively suppressed.

[0076] Although the embodiments of the present disclosure have been described above, the present disclosure can also be embodied in other forms.

[0077] In the above embodiments, the conductivity types of the various semiconductor regions may be reversed, i.e., p-type regions may become n-type regions and n-type regions may become p-type regions.

[0078] In the above-described embodiments, a MISFET is formed in the second transistor region, but this is not limiting. For example, a JFET having a field plate and a trench as shown in the above-described embodiments may be formed in the transistor region. Even in this case, the same effects as those of the above-described embodiments can be achieved.

[0079] In the above embodiment, the element isolation region has a first portion and a second portion, but is not limited to this. For example, the element isolation region may further have a third portion located on the second portion in addition to the first portion and the second portion. In this case, the impurity concentration of the second portion is, for example, 1.0×10 １４ cm －３ Above 1.0 x 10 １８ cm －３ The impurity concentration of the third portion is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The following is the result.

[0080] In the above embodiment, the first semiconductor region may further include a fourth well region surrounding the first well region. The fourth well region is an n-type region in contact with the first well region and is located between the collector contact portion and the emitter contact portion in plan view. The fourth well region is provided, for example, so as not to overlap with the emitter contact portion and the collector contact portion in the third direction Z. Meanwhile, the spacer overlaps a portion of the fourth well region via the first insulating film. The impurity concentration of the fourth well region is, for example, 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ When the first semiconductor region further includes a fourth well region, malfunction of the L-PNP transistor caused by parasitic capacitance is suppressed.

[0081] In the above embodiment, the spacer is electrically connected to the base contact portion, but this is not limiting. The spacer may be conductive and grounded. Alternatively, the spacer may be insulating. In this case, in order to eliminate the influence of the above-mentioned dangling bonds, the spacer is formed from, for example, silicon oxide rather than silicon nitride. When the spacer includes silicon oxide, the thickness of the spacer is, for example, 50 nm to 500 nm.

[0082] In the above embodiment, the polysilicon and gate are formed after the gate insulating film is formed, but this is not limited to this. In other words, in the above embodiment, the fourth and fifth steps are performed in order, but this is not limited to this. The fourth and fifth steps may be completed simultaneously. For example, first, an insulating film is formed on the first semiconductor region and the surface oxide film, and then a polysilicon layer is formed on the insulating film. Subsequently, the insulating film and the polysilicon layer may be patterned to form gate insulating films 61 and 62, polysilicon 71, and gates 72 and 73. In this case, a portion of the remaining insulating film is provided between the polysilicon 71 and the surface oxide film 41. Completing the fourth and fifth steps simultaneously can simplify the manufacturing method of the semiconductor device.

[0083] In the above embodiments, the semiconductor device can be applied to a power module used in an inverter circuit that drives an electric motor used as a power source for, for example, automobiles (including electric vehicles), trains, industrial robots, air conditioners, air compressors, fans, vacuum cleaners, dryers, refrigerators, etc. The semiconductor device can also be applied to a power module used in an inverter circuit for a solar cell, a wind power generator, or other power generation device. Alternatively, the semiconductor device can be applied to a circuit module that constitutes an analog control power supply, a digital control power supply, etc.

[0084] Although an embodiment relating to one aspect of the present disclosure has been described in detail above, these are merely specific examples used to clarify the technical content of the present disclosure, and the present disclosure should not be interpreted as being limited to these specific examples, and the scope of the present disclosure is limited only by the appended claims.

[0085] Below, examples of features extracted from the description of this specification and the drawings are shown.

[0086] [A1] A semiconductor device comprising: a semiconductor substrate; a semiconductor layer located on the semiconductor substrate in a thickness direction of the semiconductor substrate, the semiconductor layer having a first device region; a surface oxide film provided on a part of a surface of the semiconductor layer; and a silicon nitride film located on the surface oxide film in the thickness direction, wherein a PNP transistor is located in the first device region, the PNP transistor having a p-type emitter, a p-type collector surrounding the emitter as viewed in the thickness direction, and an n-type base surrounding the collector as viewed in the thickness direction, and further comprising a spacer located between the emitter and the collector as viewed in the thickness direction, and between the surface oxide film and the silicon nitride film in the thickness direction.

[0087] [A2] The semiconductor device according to [A1], wherein the spacer is conductive and electrically connected to the base.

[0088] [A3] The semiconductor device according to claim 1, wherein the spacer is conductive and is grounded.

[0089] [A4] The semiconductor device according to [A2] or [A3], wherein the spacer includes polysilicon.

[0090] [A5] The semiconductor device according to [A4], wherein the semiconductor layer further defines a second device region separated from the first device region, the second device region includes a transistor having a source region, a drain region, and a gate located below the silicon nitride film, and the gate includes polysilicon having the same or substantially the same crystallinity as the polysilicon included in the spacer.

[0091] [A6] The semiconductor device according to [A5], wherein the transistor further includes a gate insulating film located below the gate, and the thickness of the gate insulating film is different from the thickness of the surface oxide film.

[0092] [A7] The semiconductor device according to [A5] or [A6], wherein an element isolation region is set in the semiconductor layer and is located between the first device region and the second device region.

[0093] [A8] The semiconductor device according to any one of [A2] to [A7], wherein the PNP transistor further has a p-type well region located below the emitter and an n-type well region surrounding the p-type well region as viewed in the thickness direction, and the spacer overlaps a portion of the n-type well region via the surface oxide film.

[0094] [A9] The semiconductor device according to [A1], wherein the spacer includes silicon oxide, and the spacer has a thickness of 50 nm or more and 500 nm or less.

[0095] [A10] The semiconductor device according to any one of [A1] to [A9], wherein the spacer has a frame shape surrounding the emitter when viewed in the thickness direction.

[0096] [A11] A semiconductor device comprising: a first step of forming a semiconductor layer on a semiconductor substrate; a second step of oxidizing a part of the surface of the semiconductor layer to form a surface oxide film; a third step of forming a p-type first well region in a first device region of the semiconductor layer, a p-type second well region surrounding the first well region as viewed in the thickness direction of the semiconductor substrate, and an n-type third well region surrounding the second well region as viewed in the thickness direction, and also forming a first conductivity type fourth well region and a second conductivity type fifth well region in a second device region of the semiconductor layer; a fourth step of forming a gate insulating film in the second device region; a fifth step of forming polysilicon on an insulating portion of the surface oxide film located in the first device region, and simultaneously forming a gate on the gate insulating film; a sixth step of forming a p-type emitter in the first well region, a p-type collector in the second well region, and an n-type base in the third well region, and also forming a source region in the fourth well region and a drain region in the fifth well region; and a seventh step of forming a silicon nitride film covering the polysilicon and the gate, In the fifth step, the insulating portion is located between the emitter and the collector when viewed in the thickness direction.

[0097] [A12] The method for manufacturing a semiconductor device according to [A11], wherein the polysilicon is electrically connected to the base.

[0098] [A13] The method for manufacturing a semiconductor device according to [A11], wherein the polysilicon is grounded.

[0099] [A14] The method for manufacturing a semiconductor device according to any one of [A11] to [A13], wherein the gate includes polysilicon having the same or substantially the same crystallinity as the polysilicon.

[0100] [A15] The method for manufacturing a semiconductor device according to any one of [A11] to [A14], wherein in the third step, an isolation region located between the first device region and the second device region is formed in the semiconductor layer.

[0101] [A16] The method for manufacturing a semiconductor device according to any one of [A11] to [A15], wherein the polysilicon has a frame shape surrounding the emitter when viewed in the thickness direction.

[0102] REFERENCE SIGNS LIST 1A...Semiconductor device 2...Chip 6...First semiconductor region (semiconductor layer) 6a...Surface 7...Second semiconductor region (semiconductor substrate) 9A...First transistor region 9B...Second transistor region 11...Base region 11a...n-type buried region 11b...n-type region 12...Emitter contact portion 13...Collector contact portion 14...Base contact portion 15, 51...First well region 16, 52...Second well region 17, 53...Third well region 21...First insulating film (surface oxide film) 21a...First insulating portion (insulating portion) 21b...Second insulating portion 21c...Third insulating portion 22...Second insulating film (surface oxide film) 22a...First opening 22b...Second opening 22c...Third opening 31-33...P-type impurity region 34-36...N-type impurity region 41-43...Surface oxide film 41a...insulating portion 55...fourth well region 61, 62, 131...gate insulating film 71...polysilicon 72, 73...gate 81...emitter contact portion 82...collector contact portion 83...base contact portion 84, 86, 115...drain region 85, 87, 117...source region 91...silicon nitride film 111...first potential region 112...second potential region 113...drift region 122...insulating film 125...field electrode 129...inner field electrode 132...gate electrode 140...insulating layer 141...interlayer insulating film 141A...first interlayer insulating film 141B...second interlayer insulating film 141C...third interlayer insulating film DR, DR1, DR2...element isolation region R1...first device region R2...second device region R3...third device region S...spacer.

Claims

1. A semiconductor device comprising: a semiconductor substrate; a semiconductor layer located on the semiconductor substrate in the thickness direction of the semiconductor substrate and having a first device region set therein; a surface oxide film provided on a part of the surface of the semiconductor layer; and a silicon nitride film located on the surface oxide film in the thickness direction, wherein in the first device region, a PNP transistor having a p-type emitter, a p-type collector surrounding the emitter as viewed from the thickness direction, and an n-type base surrounding the collector as viewed from the thickness direction is located, and further comprising a spacer located between the emitter and the collector as viewed from the thickness direction and located between the surface oxide film and the silicon nitride film in the thickness direction.

2. The semiconductor device according to claim 1, wherein the spacer has conductivity and is electrically connected to the base.

3. The semiconductor device according to claim 1, wherein the spacer has conductivity and is grounded.

4. The semiconductor device according to claim 2 or 3, wherein the spacer contains polysilicon.

5. In the semiconductor layer, a second device region separated from the first device region is further set, and in the second device region, a transistor having a source region, a drain region, and a gate located below the silicon nitride film is located, and the gate contains polysilicon having the same or substantially the same crystallinity as the polysilicon contained in the spacer. The semiconductor device according to claim 4.

6. The transistor according to claim 5 further has a gate insulating film located below the gate, and the thickness of the gate insulating film is different from the thickness of the surface oxide film. The semiconductor device according to claim 5.

7. The semiconductor device according to claim 5 or 6, wherein an element isolation region is set in the semiconductor layer between the first device region and the second device region.

8. The PNP transistor further has a p-type well region located below the emitter and an n-type well region surrounding the p-type well region as viewed from the thickness direction, and the spacer overlaps a part of the n-type well region through the surface oxide film. The semiconductor device according to any one of claims 2 to 7.

9. The semiconductor device according to claim 1, wherein the spacer contains silicon oxide, and the thickness of the spacer is 50 nm or more and 500 nm or less.

10. The semiconductor device according to any one of claims 1 to 9, wherein the spacer has a frame shape surrounding the emitter when viewed in the thickness direction.

11. A method of manufacturing a semiconductor device, comprising: a first step of forming a semiconductor layer on a semiconductor substrate; a second step of forming a surface oxide film on the surface of the semiconductor layer; a third step of forming a p-type first well region in a first device region of the semiconductor layer, a p-type second well region surrounding the first well region when viewed in the thickness direction of the semiconductor substrate, and an n-type third well region surrounding the second well region when viewed in the thickness direction, and forming a fourth well region of a first conductivity type and a fifth well region of a second conductivity type in a second device region of the semiconductor layer; a fourth step of forming a gate insulating film in the second device region; a fifth step of forming polysilicon on an insulating portion located in the first device region of the surface oxide film and simultaneously forming a gate on the gate insulating film; a sixth step of forming a p-type emitter in the first well region, a p-type collector in the second well region, and an n-type base in the third well region, and forming a source region in the fourth well region and a drain region in the fifth well region; and a seventh step of forming a silicon nitride film covering the polysilicon and the gate, wherein in the fifth step, the insulating portion is located between the emitter and the collector when viewed in the thickness direction.

12. The method of manufacturing a semiconductor device according to claim 11, wherein the polysilicon is electrically connected to the base.

13. The method of manufacturing a semiconductor device according to claim 11, wherein the polysilicon is grounded.

14. The method of manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the gate includes polysilicon having the same or substantially the same crystallinity as the polysilicon.

15. The method of manufacturing a semiconductor device according to any one of claims 11 to 14, wherein in the third step, an element isolation region located between the first device region and the second device region is formed in the semiconductor layer.

16. The method of manufacturing a semiconductor device according to any one of claims 11 to 15, wherein the polysilicon has a frame shape surrounding the emitter when viewed in the thickness direction.

Images