Semiconductor device, electronic apparatus, and method for producing semiconductor device

Abstract

This invention improves performance of a semiconductor device including a diamond device. In the present disclosure, a semiconductor device comprises: a non-doped layer; a surface conductive layer formed in the non-doped layer; a drain electrode electrically connected to the surface conductive layer; a source electrode electrically connected to the surface conductive layer; a gate electrode formed on the surface conductive layer and configured from a T-gate structure; a surface protective film in contact with the drain electrode, the source electrode, and the gate electrode; and a cavity portion formed between the gate electrode and the source electrode.

Description

Semiconductor device, electronic device, and method of manufacturing the semiconductor device

[0001] The present invention relates to a semiconductor device, an electronic device, and a method for manufacturing a semiconductor device, and relates to a technique that is effective when applied to a semiconductor device having, for example, a diamond layer.

[0002] Japanese Patent No. 5551648 (Patent Document 1) describes a technology relating to a diamond transistor in which the shape of the gate electrode is a so-called "T-shaped gate."

[0003] Patent No. 5551648

[0004] Diamond has overwhelming potential as a semiconductor device material compared to other materials. Therefore, diamond is a semiconductor material that is highly anticipated for application in high frequency and high power ranges. In this regard, for diamond devices used in high frequency and high power ranges, it is useful to configure the gate electrode with a "T-gate structure" to improve high frequency characteristics. However, the present inventors have newly discovered that adopting a "T-gate structure" may increase parasitic capacitance. An increase in parasitic capacitance leads to a decrease in cutoff frequency. A decrease in cutoff frequency is a factor that degrades high frequency characteristics. Therefore, there is a need for a method to reduce parasitic capacitance while adopting a "T-gate structure."

[0005] In one embodiment, the semiconductor device comprises a diamond layer, a surface conductive layer formed in the diamond layer, a drain electrode electrically connected to the surface conductive layer, a source electrode electrically connected to the surface conductive layer, a gate electrode formed on the surface conductive layer and having a T-gate structure, a surface protective film in contact with the drain electrode, the source electrode, and the gate electrode, and a cavity formed between the gate electrode and the source electrode.

[0006] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: (a) forming a field-effect transistor having a diamond layer with a surface conductive layer and including a gate electrode having a T-gate structure, a source electrode electrically connected to the surface conductive layer, and a drain electrode electrically connected to the surface conductive layer; and (b) forming a surface protection film in contact with the gate electrode, source electrode, and drain electrode after the step (a). In the step (a), a cavity is formed between the gate electrode and the source electrode. In the step (b), the cavity remains even after the surface protection film is formed.

[0007] According to one embodiment, the performance of a semiconductor device including a diamond device can be improved.

[0008] 9 is a diagram illustrating the configuration of a surface conduction FET investigated by the present inventors. FIG. 10 is a diagram illustrating the configuration of a surface conduction FET investigated by the present inventors. FIG. 11 is a diagram illustrating the configuration of a surface conduction FET investigated by the present inventors. FIG. 12 is a diagram illustrating the configuration of a surface conduction FET investigated by the present inventors. FIG. 13 is a diagram illustrating the parasitic capacitance of a surface conduction FET having a normal gate electrode. FIG. 14 is a diagram illustrating the connection relationship of the parasitic capacitance between the gate and the source. FIG. 15 is a diagram illustrating the connection relationship of the parasitic capacitance between the gate and the source. FIG. 16 is a diagram illustrating the configuration of a surface conduction FET investigated by the present inventors. FIG. 17 is a diagram illustrating the parasitic capacitance of a surface conduction FET having a T-gate structure. FIG. 18 is a diagram illustrating the connection relationship of the parasitic capacitance between the gate and the source. FIG. 19 is a diagram illustrating a planar arrangement of a source electrode, a drain electrode, and a gate electrode. FIG. 19 is a cross-sectional view taken along line A-A in FIG. 9. FIG. 10 is a diagram illustrating the parasitic capacitance existing between a gate electrode (gate) having a T-gate structure and a source electrode (source) in a semiconductor device in an embodied mode. FIG. 11 is a diagram illustrating a first capacitance. FIG. 12 is a diagram illustrating a second capacitance. FIG. 13 is a diagram illustrating a manufacturing process of a semiconductor device in an embodied mode. FIG. 14 is a diagram illustrating a manufacturing process of a semiconductor device subsequent to FIG. 14. FIG. 15 is a diagram illustrating a manufacturing process of a semiconductor device subsequent to FIG. 16. FIG. 17 is a diagram illustrating a manufacturing process of a semiconductor device subsequent to FIG. 18. FIG. 19 is a diagram illustrating a manufacturing process of a semiconductor device subsequent to FIG. 19.

[0009] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. In addition, hatching may be used even in plan views to make the drawings easier to understand.

[0010] <Usefulness of diamond as a semiconductor material> For example, in the fields of future mobile communications, satellite communications, or ultra-small radar, FETs (Field Effect Transistors) capable of high-power and high-frequency transmission are required. In this regard, semiconductor materials such as silicon (Si) and gallium arsenide (GaAs) reach their power density limits at frequencies above several GHz. For this reason, wide bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN) and diamond are being considered for use in FETs. In particular, diamond has the highest thermal conductivity of all materials (four times that of SiC, 16 times that of GaN) and the highest breakdown field strength of all semiconductor materials (three times that of SiC, 10 times that of GaN). Furthermore, the hole mobility and hole saturation velocity in diamond are equivalent to the electron mobility and electron saturation velocity in silicon.

[0011] Diamond has excellent heat dissipation properties due to its high thermal conductivity. Therefore, using diamond as a semiconductor material can suppress heat generation in semiconductor devices. Therefore, semiconductor devices using diamond can be expected to operate at high temperatures.

[0012] In addition, the high dielectric breakdown field strength of diamond makes it difficult for semiconductor devices to be destroyed even when high voltages are applied. For this reason, semiconductor devices using diamond are suitable for high-power applications. Furthermore, the high carrier mobility of diamond indicates that diamond has great potential as a semiconductor device for high-frequency applications.

[0013] For these reasons, diamond as a semiconductor material is considered to be promising for realizing next-generation semiconductor devices, including FETs capable of high-power and high-frequency operation.

[0014] <The difficulty of producing n-type diamond> As mentioned above, diamond is a wide band gap semiconductor material.Therefore, by introducing n-type impurities called donor into diamond, n-type diamond can be produced.Specifically, it is considered that by supplying electrons from the donor level of donor to the conduction band of diamond, n-type diamond can be realized.

[0015] Here, nitrogen can be mentioned as donor.However, in diamond, the donor level of nitrogen is not near the conduction band, but exists in the "deep level" away from the conduction band.Specifically, the donor level of nitrogen exists at the energy position 1.7 eV lower than the conduction band of diamond.As a result, in diamond, the activation energy for exciting electrons from the donor level of nitrogen to the conduction band of diamond is large.

[0016] For this reason, even if nitrogen, which acts as a donor, is introduced into diamond, it is difficult to increase the number of electrons supplied to the conduction band. As a result, it is difficult to make the nitrogen-introduced diamond function as an n-type diamond.

[0017] On the other hand, p-type diamond can be produced by introducing p-type impurities called acceptors into diamond. Specifically, it is thought that p-type diamond can be realized by exciting electrons from the valence band of diamond to the acceptor level of the acceptor, thereby generating holes in the valence band of diamond.

[0018] Here, boron can be mentioned as an acceptor. The acceptor level of this boron exists near the valence band of diamond. Specifically, boron, which is an acceptor, forms an acceptor level at an energy position 0.37 eV higher than the valence band of diamond. In other words, in diamond, the acceptor level of boron does not constitute a "deep level" like the donor level of nitrogen. For this reason, the activation energy for exciting electrons from the valence band of diamond to the acceptor level of boron is not so large. As a result, it is easier to produce p-type diamond in diamond than to produce n-type diamond.

[0019] Therefore, as the FET that uses diamond to manufacture, it is not the n-channel FET that generally requires n-type diamond, but the p-channel FET that uses p-type diamond, which is easier to manufacture than n-type diamond.In other words, the FET that uses diamond to manufacture is realized as the FET that uses hole as carrier, not the FET that uses electron as carrier.In particular, as the FET that uses diamond to manufacture, there is the p-channel FET that is called " surface conduction FET ".

[0020] This "surface conduction FET" will be described below.

[0021] <Surface-conduction FET> When diamond is hydrogen-terminated, there is a phenomenon in which holes (two-dimensional hole gas) are induced on the surface of the hydrogen-terminated diamond. A FET that utilizes this phenomenon is called a "surface-conduction FET." In other words, a "surface-conduction FET" is a FET that uses a surface-conduction layer consisting of two-dimensional hole gas induced on the surface of the hydrogen-terminated diamond as its channel. This "surface-conduction FET" is a FET that performs switching operations by controlling the conduction / non-conduction of the channel by changing the gate voltage applied to the gate electrode. A "surface-conduction FET" enables high-temperature operation with high breakdown voltage. This is because hydrogen-terminating diamond forms very strong "C-H" bonds.

[0022] The mechanism by which holes are induced on the surface of hydrogen-terminated diamond has not been fully elucidated. The following two theories are considered to be the most likely explanations.

[0023] First, one theory is the "transfer doping model." This theory states that electrons in the valence band of diamond move to a level determined by the chemical potential of the surface due to differences in chemical potential caused by adsorbates or changes in the pH of the surface, and holes are generated near the surface from which these electrons are removed.

[0024] On the other hand, there is another theory, the "negative ion model." This theory is as follows: In other words, in the "C-H" bond created by hydrogen-terminating diamond, hydrogen becomes positively charged while carbon becomes negatively charged due to the difference in electronegativity. As a result, negative ions in the atmosphere are adsorbed onto the positively charged hydrogen, and these adsorbed negative ions attract holes to the surface of the diamond.

[0025] As such, the mechanism has not been fully elucidated. Nevertheless, the phenomenon of holes being induced on the surface of hydrogen-terminated diamond does occur. Taking advantage of this phenomenon, a superior FET called a "surface conduction FET" has been realized, capable of high-voltage and high-temperature operation.

[0026] Examples of the excellent characteristics of the surface conduction FET are listed below.

[0027] Excellent properties for application to power devices: (1) High breakdown field strength of 10 (MV / cm) (2) High carrier density (10 １３ / cm ３ (above) Excellent characteristics for application to high frequency devices (1) A small relative dielectric constant of 5.7 (2) The channel formation region is located near the surface (10 nm or less from the surface) Excellent characteristics for high temperature operation (1) A large thermal conductivity of 22 W / cm·K (2) The cooling system can be eliminated or made smaller

[0028] <Background of Study on Surface-Conduction FET> FIG. 1 is a diagram showing the configuration of a surface-conduction FET 100A.

[0029] In FIG. 1 , a surface conduction FET 100A has a diamond substrate 101 into which nitrogen has been introduced. An undoped layer 102 is provided on the diamond substrate 101. A hydrogen termination region 103 and an oxygen termination region 104 are formed on the upper surface of the undoped layer 102. A channel formation region 105 containing a two-dimensional hole gas is formed below the hydrogen termination region 103. As shown in FIG. 1 , a source electrode 106 and a drain electrode 107 are disposed on the hydrogen termination region 103, spaced apart from each other. A gate electrode 109 is disposed on the hydrogen termination region 103 between the source electrode 106 and the drain electrode 107, with a gate insulating film 108 interposed therebetween. The gate electrode 109 is disposed apart from each of the source electrode 106 and the drain electrode 107.

[0030] 1, a portion of the hydrogen-termination region 103 formed on the channel-forming region 105 is exposed. As a result, the exposed hydrogen-termination region 103 is exposed to positive ions or negative ions (hereinafter, positive ions and negative ions are collectively referred to as ions) in the atmosphere.

[0031] Therefore, the ions may adversely affect the channel formation region 105 formed below the hydrogen-terminated region 103. This may cause fluctuations in the characteristics of the surface-conduction type FET 100A.

[0032] Note that substances that may adversely affect the channel formation region 105 may not be limited to ions. Therefore, ions in the atmosphere and neutral substances present in the atmosphere are considered to be substances that may adversely affect the channel formation region 105. In consideration of this, in this specification, substances that may adversely affect the channel formation region 105 are referred to as ions, etc.

[0033] Therefore, a surface conduction type FET 100B described below is being considered.

[0034] FIG. 2 is a diagram showing the configuration of the surface conduction type FET 100B.

[0035] As shown in FIG. 2 , a surface protective film 110 is formed to cover the source electrode 106, the drain electrode 107, and the gate electrode 109. The surface protective film 110 is also called a "passivation film." The surface protective film 110 covers the exposed hydrogen termination region 103. That is, the hydrogen termination region 103 is not exposed to ions in the atmosphere. In other words, the surface protective film 110 prevents ions in the atmosphere from contacting the hydrogen termination region 103. This prevents ions from adversely affecting the channel formation region 105 formed below the hydrogen termination region 103. Therefore, the surface conduction FET 100B is less likely to experience characteristic fluctuations due to ions in the atmosphere. Therefore, the surface conduction FET 100B can improve reliability.

[0036] From the above, the surface protection film 110 is effective in suppressing the characteristic fluctuation caused by ions in the atmosphere by covering the exposed hydrogen-terminated region 103 .

[0037] However, it is possible that the hydrogen termination region 103 is not exposed, for example, when the hydrogen termination region 103 is covered with the gate insulating film 108. Even in this case, it is effective to form the surface protective film 110. This is because covering the entire device with the surface protective film 110 can reduce the influence of ions and the like present outside the device on the device characteristics. In this way, regardless of whether the hydrogen termination region 103 is exposed, the surface protective film 110 is useful for improving the reliability of the device.

[0038] <T-gate structure> As mentioned above, a surface conduction FET is an example of a field effect transistor having a diamond layer. In the following, for example, a surface conduction FET that operates in a frequency range of GHz or more will be described. In this specification, an FET that operates in a frequency range of GHz or more will be called a "high frequency FET." In a high frequency FET, two mutually contradictory requirements must be satisfied in order to improve high frequency characteristics. The two mutually contradictory requirements are requirements regarding the configuration of the gate electrode of the high frequency FET.

[0039] Specifically, the two conflicting requirements are as follows:

[0040] (1) Shorten the gate length. This is because reducing the transit time of carriers (holes) controlled by the gate electrode contributes greatly to improving frequency characteristics. To shorten the transit time of carriers, it is important to shorten the gate length.

[0041] (2) Reducing gate resistance. Resistance is inversely proportional to the cross-sectional area. Considering this, increasing the cross-sectional area of ​​the gate electrode is effective in reducing gate resistance.

[0042] The above-mentioned requirement (1) is a requirement that provides an incentive to reduce the cross-sectional area of ​​the gate electrode. In contrast, the above-mentioned requirement (2) is a requirement that provides an incentive to increase the cross-sectional area of ​​the gate electrode. Therefore, requirements (1) and (2) are mutually contradictory. In this regard, in order to satisfy the two mutually contradictory requirements, it is effective to configure the gate electrode using a so-called "T-gate structure." The "T-gate structure" will be explained below.

[0043] In this specification, the term "T-gate structure" is used to broadly encompass a gate electrode structure having an "umbrella portion" and a "trunk portion," in which the horizontal width of the "umbrella portion" is greater than the horizontal width of the "trunk portion."

[0044] Therefore, the term "T-gate structure" as used in this specification also includes "distorted structures" such as a structure in which the "umbrella portion" is tilted, a structure in which the "umbrella portion" extends diagonally upward rather than horizontally (Y-gate), or a structure in which the "umbrella portion" extends to one side (Γ-gate).

[0045] FIG. 3 is a diagram showing the configuration of the surface conduction type FET 100C.

[0046] As shown in FIG. 3 , the surface conduction FET 100C has a gate electrode 130 configured with a T-gate structure. Specifically, the gate electrode 130 has a first width portion 120A ("trunk") and a second width portion 120B ("umbrella portion"). The width G1 of the first width portion 120A in the X direction is smaller than the width G2 of the second width portion 120B in the X direction. The first width portion 120A is formed on the gate insulating film 108. The second width portion 120B is formed on the first width portion 120A.

[0047] In the T-gate structure, the width G1 of the first width portion 120A close to the channel formation region 105 is small. Therefore, the transit time of carriers (holes) traveling directly below the first width portion 120A of the gate electrode 130 is short. Therefore, the surface conduction FET 100C improves frequency characteristics. Furthermore, in the T-gate structure, the width G2 of the second width portion 120B is large. Therefore, the gate resistance of the gate electrode 130 can be reduced.

[0048] From the above, the surface-conduction FET 100C having the gate electrode 130 with the T-gate structure can achieve both improved frequency characteristics and reduced gate resistance. In other words, the surface-conduction FET 100C can simultaneously satisfy two mutually contradictory requirements.

[0049] 3, even in the surface conduction FET 100C, a portion of the hydrogen termination region 103 formed on the channel formation region 105 is exposed. As a result, the exposed hydrogen termination region 103 is exposed to ions and the like in the atmosphere. Therefore, the ions and the like may adversely affect the channel formation region 105 formed below the hydrogen termination region 103. This raises concerns about fluctuations in the characteristics of the surface conduction FET 100C.

[0050] Therefore, it is conceivable to form a surface protective film on the surface conduction FET 100C so as to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. As a result, the exposed hydrogen termination region 103 is covered with the surface protective film. That is, the hydrogen termination region 103 is not exposed to ions in the atmosphere. In this way, by providing a surface protective film on the surface conduction FET 100C having a T-gate structure, it is possible to prevent ions in the atmosphere from adversely affecting the channel formation region 105 formed below the hydrogen termination region 103. Therefore, by providing a surface protective film on the surface conduction FET 100C, it is possible to reduce the occurrence of characteristic fluctuations caused by ions in the atmosphere.

[0051] In this specification, a diamond device in which a surface conduction FET 100C having a T-gate structure is provided with a surface protection film is referred to as a surface conduction FET 100. This surface conduction FET 100 is a novel diamond device that is of practical importance. The configuration of the surface conduction FET 100 having a T-gate structure and a surface protection film will be described below.

[0052] <Configuration of Surface Conduction Type FET 100> FIG. 4 is a diagram showing the configuration of the surface conduction type FET 100. As shown in FIG.

[0053] 4, a surface conduction FET 100 has a nitrogen-doped diamond substrate 101. An undoped layer 102 is provided on the diamond substrate 101. For example, the top surface of the undoped layer 102 is a (001) plane.

[0054] Here, the diamond substrate 101 into which nitrogen is introduced is used, but the present invention is not limited to this. For example, the surface conduction FET 100 may be fabricated on a free-standing film made of the non-doped layer 102.

[0055] The non-doped layer 102 may be configured to have an off-angle (for example, 3 degrees) in the <110> direction with respect to the (001) plane.

[0056] Here, the non-doped layer 102 referred to in this specification is a diamond layer in which the nitrogen impurity concentration is 10%, which is the lower limit of detection by a measuring device using SIMS (Secondary Ion Mass Spectrometry). １６ / cm ３ Diamond layer having a thickness of less than 100 nm.

[0057] A hydrogen termination region 103 and an oxygen termination region 104 are formed on the surface of the non-doped layer 102. As a result, a channel formation region 105 having a two-dimensional hole gas is formed in the hydrogen termination region 103 of the non-doped layer 102.

[0058] 4, a source electrode 106 and a drain electrode 107 are disposed apart from each other on the hydrogen-terminated region 103. That is, the source electrode 106 and the drain electrode 107, which are made of gold electrodes or the like, are formed directly on the hydrogen-terminated non-doped layer 102. The source electrode 106 and the drain electrode 107 are each in ohmic contact with the hydrogen-terminated non-doped layer 102.

[0059] A contact layer may be interposed between the hydrogen-terminated non-doped layer 102 and the source electrode 106, and between the hydrogen-terminated non-doped layer 102 and the drain electrode 107. The contact layer may be, for example, a p-type impurity layer having boron introduced therein at a high concentration. ＋ Specifically, a high concentration of boron is introduced into the contact layer so as to form an ohmic contact with the non-doped layer 102. The concentration of boron is, for example, 5×10 １９ / cm ３ That's it, 1 x 10 ２２ / cm ３ The thickness of the contact layer is, for example, about 20 nm to 300 nm.

[0060] A gate electrode 130 is disposed on the hydrogen-terminated region 103 between the source electrode 106 and the drain electrode 107, with a gate insulating film 108 interposed therebetween. The gate electrode 130 is disposed separately from each of the source electrode 106 and the drain electrode 107.

[0061] The gate electrode 130 has a T-gate structure. Specifically, the gate electrode 130 has a first width portion 120A and a second width portion 120B. The width G1 of the first width portion 120A in the X direction is smaller than the width G2 of the second width portion 120B in the X direction. The first width portion 120A is formed on the gate insulating film 108. The second width portion 120B is formed on the first width portion 120A. In this way, by configuring the gate electrode 130 with a T-gate structure, it is possible to achieve both improved frequency characteristics and reduced gate resistance.

[0062] The electrode materials of the source electrode 106, the drain electrode 107, and the gate electrode 130 are, for example, gold (Au), ruthenium (Ru), aluminum (Al), titanium (Ti), molybdenum (Mo), copper (Cu), chromium (Cr), lead (Pb), zinc (Zn), platinum (Pt), or a combination thereof (such as Ti / Mo / Au).

[0063] The thickness of each of the source electrode 106, the drain electrode 107, and the gate electrode 130 is, for example, about 10 nm or more and 500 nm or less.

[0064] The metal films constituting the source electrode 106, the drain electrode 107, and the gate electrode 130 can be formed by physical deposition methods such as sputtering and evaporation, or chemical deposition methods such as CVD and MOCVD.

[0065] 4 , a surface protective film 110 is formed so as to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. The surface protective film 110 is formed so as to be in contact with the source electrode 106, the drain electrode 107, and the gate electrode 130. The surface protective film 110 covers the exposed hydrogen-terminated region 103. In other words, the surface protective film 110 is in contact with the exposed hydrogen-terminated region 103.

[0066] As a result, the hydrogen-termination region 103 is not exposed to ions in the atmosphere. In other words, the surface protective film 110 prevents ions in the atmosphere from coming into contact with the hydrogen-termination region 103. This makes it possible to prevent ions in the atmosphere from adversely affecting the channel formation region 105 formed below the hydrogen-termination region 103.

[0067] The surface conduction FET 100 is configured as described above.

[0068] The surface-conduction FET 100 has a gate electrode 130 having a T-gate structure. Therefore, the surface-conduction FET 100 can achieve both improved frequency characteristics and reduced gate resistance. In particular, the improvement of frequency characteristics is due to the small width G1 in the X direction of the first width portion 120A of the gate electrode 130 having the T-gate structure. On the other hand, the reduction of gate resistance is due to the large width G2 in the X direction of the second width portion 120B of the gate electrode 130 having the T-gate structure.

[0069] The surface conduction FET 100 also has a surface protection film 110 that covers the exposed hydrogen termination region 103. This prevents the hydrogen termination region 103 from being exposed to ions in the atmosphere. As a result, the channel formation region 105 formed below the hydrogen termination region 103 can be prevented from being adversely affected by ions in the atmosphere. In other words, the surface conduction FET 100 can reduce the occurrence of characteristic fluctuations caused by ions in the atmosphere. Therefore, the surface conduction FET 100 can improve reliability.

[0070] In a surface conduction FET, a two-dimensional hole gas is induced in the hydrogen-terminated region of the diamond layer even when no gate voltage is applied to the gate electrode. That is, in a surface conduction FET, a channel made of a two-dimensional hole gas is formed in the hydrogen-terminated region even when no gate voltage is applied to the gate electrode. In other words, in a surface conduction FET, a channel made of a two-dimensional hole gas is formed in the hydrogen-terminated region even when a gate voltage of 0 V is applied to the gate electrode. For this reason, a surface conduction FET is usually a "normally-on FET." Therefore, in the embodied form, a "normally-on FET" is assumed. However, the technical idea of ​​this embodiment is not limited to a "normally-on FET." For example, the technical idea of ​​this embodiment can be widely applied to a "normally-off FET."

[0071] <Operation of Surface Conduction FET 100> Next, the operation of the surface conduction FET 100 will be described.

[0072] For example, when "+3 V" is applied to the gate electrode 130, the surface-conduction FET 100 is in an off state. That is, when "+3 V" is applied to the gate electrode 130, no channel is formed in the first region P1 of the channel formation region 105 even if a potential difference is applied between the source electrode 106 and the drain electrode 107. This is because when a positive potential of "+3 V" is applied to the gate electrode 130, a repulsive force is applied to the holes in the first region P1 of the channel formation region 105. As a result, the hole concentration in the first region P1 decreases. This causes the channel consisting of two-dimensional hole gas to disappear in the first region P1. Therefore, no hole current flows between the source electrode 106 and the drain electrode 107.

[0073] In contrast, when "0 V" is applied to the gate electrode 130, the repulsive force exerted by the gate electrode 130 on the holes in the first region P1 disappears. As a result, the hole concentration in the first region P1 located directly below the gate electrode 130 increases. As a result, a channel due to two-dimensional electron gas is formed not only in the second region P2 but also in the first region P1. That is, a channel is formed throughout the entire channel formation region 105, including the first region P1 and the second region P2. Therefore, with "0 V" applied to the gate electrode 130, for example, "0 V" is applied to the source electrode 106. Furthermore, "-100 V" is applied to the drain electrode 107. As a result, a hole current flows along the path from the source electrode 106 → the second region P2 of the channel formation region 105 → the first region P1 of the channel formation region 105 → the second region P2 of the channel formation region 105 → the drain electrode 107.

[0074] In this manner, by controlling the gate voltage applied to the gate electrode 130, it is possible to realize the switching operation (ON / OFF operation) of the surface conduction FET 100. For example, the surface conduction FET 100 operates as a "normally on FET."

[0075] <Consideration for Improvement> The present inventors have been studying room for improvement that becomes apparent in the surface-conduction FET 100 having the above-described T-gate structure and the surface protective film 110. As a result, the present inventors have newly found room for improvement that becomes apparent in the surface-conduction FET 100.

[0076] The following describes novel areas for improvement.

[0077] First, attention is focused on a surface conduction FET having a normal gate electrode.

[0078] 5 is a diagram illustrating the parasitic capacitance present in a surface conduction FET having a normal gate electrode. In FIG. 5, a gate insulating film 108 is formed between an undoped layer 102 and a gate electrode 109. Therefore, a capacitance Cox is formed between the undoped layer 102 and the gate electrode 109. Also, as shown in FIG. 5, a surface protective film 110 is formed between the gate electrode 109 and a source electrode 106. Therefore, a capacitance C1 is formed between the gate electrode 109 and the source electrode 106. As a result, in a surface conduction FET having a normal gate electrode, the capacitance Cox and the capacitance C1 are connected in parallel between the gate G and the source S, as shown in FIG. 6.

[0079] Using the capacitance Cox and the capacitance C1, the cutoff frequency fT is expressed by the following equation:

[0080] fT=gm / 2π(Cox+C1) where gm is the mutual conductance.

[0081] The cutoff frequency is one of the indicators that indicates the quality of high frequency characteristics. For example, current cannot be amplified at frequencies higher than the cutoff frequency. For this reason, a high cutoff frequency is desirable. In other words, as the cutoff frequency decreases, the high frequency characteristics deteriorate.

[0082] For example, the gate length is 0.1 μm, the gate width is 500 μm, the thickness of the gate insulating film 108 is 10 nm, and the gate insulating film 108 (CaF ２ ) has a relative dielectric constant of 6.8 and a mutual conductance gm of 150 mS / mm, the cutoff frequency is 40 GHz according to the above formula.

[0083] Next, attention will be focused on a surface conduction FET having a gate electrode with a T-gate structure.

[0084] 7 is a diagram illustrating the parasitic capacitance present in a surface conduction FET having a gate electrode with a T-gate structure. In FIG. 7, a gate insulating film 108 is formed between the non-doped layer 102 and the gate electrode 130. Therefore, a capacitance Cox is formed between the non-doped layer 102 and the gate electrode 130. Also, as shown in FIG. 7, a surface protective film 110 is formed between the gate electrode 130 and the source electrode 106. Therefore, a capacitance C1 is formed between the gate electrode 130 and the source electrode 106. Furthermore, as shown in FIG. 7, a capacitance C2 is also formed between the gate electrode 130 and the source electrode 106 due to the T-gate structure.

[0085] As a result, in a surface conduction FET having a gate electrode with a T-gate structure, the capacitances Cox, C1, and C2 are connected in parallel between the gate G and the source S, as shown in Fig. 8. In other words, when the T-gate structure is adopted, the parasitic capacitance increases.

[0086] In this case, the cutoff frequency fT is expressed by the following equation:

[0087] fT=gm / 2π(Cox+C1+C2) where gm is the mutual conductance.

[0088] Therefore, when the T-gate structure is adopted, it can be qualitatively understood from the above equation that the cutoff frequency fT is lowered by adding the capacitance C2. In other words, when the T-gate structure is adopted, the parasitic capacitance increases, and the high-frequency characteristics deteriorate.

[0089] For example, the gate length is 0.1 μm, the gate width is 500 μm, the thickness of the gate insulating film 108 is 10 nm, and the gate insulating film 108 (CaF ２ ) has a relative dielectric constant of 6.8, a mutual conductance gm of 150 mS / mm, and a surface protection film 110 (Al ２ O ３ ) is 10, X = 50 nm, and Y = 200 nm, the cutoff frequency is calculated to be 18 GHz from the above formula. In other words, by adopting the T-gate structure, the cutoff frequency is reduced by 54%.

[0090] The T-gate structure is a useful gate structure for high-frequency applications because it can satisfy two mutually contradictory requirements: a shorter gate length and a lower gate resistance. However, as mentioned above, the T-gate structure has the side effect of increasing parasitic capacitance in designs that take into account operation in the high-frequency range expected of diamond. As a result, the adoption of the T-gate structure leads to a decrease in the cutoff frequency fT. Therefore, in surface-conduction FETs that adopt the T-gate structure, a method for reducing parasitic capacitance is desired.

[0091] Therefore, in this embodiment, even when a T-gate structure is adopted, a device is devised to be able to reduce the parasitic capacitance. The technical idea of ​​this embodiment will be described below.

[0092] <Basic Concept of the Embodiment> The basic concept of the present embodiment is based on the premise that a surface protection film is formed between the gate electrode and the drain electrode and between the gate electrode and the source electrode. The basic concept also assumes that the gate electrode has a T-gate structure. The basic concept is to reduce the relative dielectric constant of the capacitive insulating film in order to reduce the parasitic capacitance caused by the surface protection film serving as the capacitive insulating film. That is, the parasitic capacitance is proportional to the relative dielectric constant of the capacitive insulating film. Therefore, the basic concept is to adopt an approach to reduce the parasitic capacitance by reducing the relative dielectric constant of the capacitive insulating film. For example, the basic concept is to realize a configuration in which the relative dielectric constant of the capacitive insulating film is reduced by forming a cavity within the parasitic capacitance. This is because the cavity has a low relative dielectric constant.

[0093] As a result, according to the basic concept, the relative dielectric constant of the surface protection film that functions as a capacitive insulating film can be reduced, thereby reducing parasitic capacitance. That is, according to the basic concept, even when a T-gate structure is adopted for the gate electrode of a surface conduction FET, the parasitic capacitance can be reduced. As a result, according to the basic concept, the decrease in cutoff frequency caused by the parasitic capacitance can be suppressed. As a result, according to the basic concept, high-frequency characteristics can be improved.

[0094] In particular, to improve high-frequency characteristics, it is effective to shorten the carrier transit time in the channel formation region. In other words, it is effective to reduce the distance between the source electrode and the drain electrode. In this case, if a T-gate structure is adopted for the gate electrode, the partial planar overlap between the gate electrode and the source electrode and the partial planar overlap between the gate electrode and the drain electrode will increase. This means that the parasitic capacitance will increase.

[0095] In this regard, adopting the basic concept allows for a reduction in parasitic capacitance even when the distance between the source and drain electrodes is reduced. In other words, while adopting the T-gate structure and a configuration that reduces the distance between the source and drain electrodes from the perspective of improving high-frequency characteristics, adopting the basic concept can also reduce the side effect of these configurations, namely, an increase in parasitic capacitance. Therefore, the basic concept is useful because the combination of adopting the T-gate structure, reducing the distance between the source and drain electrodes, and adopting the basic concept can significantly improve high-frequency characteristics while suppressing the side effects.

[0096] The following describes an embodiment that embodies the basic concept.

[0097] <Embodiments> <<Configuration of Semiconductor Device>> Figure 9 is a diagram showing the planar positional relationship between the source electrode 106, the drain electrode 107, and the gate electrode 130. As shown in Figure 9, the source electrode 106 has a portion that overlaps with the gate electrode 130 in plan view. Also, the drain electrode 107 has a portion that overlaps with the gate electrode 10 in plan view. As a result, parasitic capacitance increases. For this reason, it is important to reduce the parasitic capacitance. Below, using cross-sectional views, the configuration of a semiconductor device in an embodiment that has been devised to reduce parasitic capacitance will be described.

[0098] FIG. 10 is a cross-sectional view taken along line AA in FIG.

[0099] 10, the semiconductor device in the embodied embodiment has a non-doped layer 102, a hydrogen termination region 103, a channel formation region 105, a source electrode 106, a drain electrode 107, a gate insulating film 108, a gate electrode 130, a surface protective film 110A, and a cavity 200.

[0100] The non-doped layer 102 is a diamond layer. A hydrogen termination region 103 is formed on the upper surface of the non-doped layer 102. For example, a two-dimensional hole gas is induced in the non-doped layer 102 directly below the hydrogen termination region 103. As a result, a channel formation region 105 made of the two-dimensional hole gas is formed in the non-doped layer 102.

[0101] The source electrode 106 is electrically connected to the channel formation region 105. The drain electrode 107 is also electrically connected to the channel formation region 105. A gate electrode 130 is formed on a part of the hydrogen termination region 103 between the source electrode 106 and the drain electrode 107. The semiconductor device in this embodiment is intended for high frequency applications. Therefore, the gate electrode 130 has a T-gate structure with excellent high frequency characteristics.

[0102] Specifically, the gate electrode 130 has a first width portion 120A and a second width portion 120B. The width of the first width portion 120A in the X direction is smaller than the width of the second width portion 120B in the X direction. The first width portion 120A is formed on the gate insulating film 108. The second width portion 120B is formed on the first width portion 120A. By configuring the gate electrode 130 in this manner as a T-gate structure, it is possible to achieve both improved frequency characteristics and reduced gate resistance. Furthermore, from the perspective of improving high-frequency characteristics, it is desirable for the gate length Lg of the gate electrode 130 to be short. For example, the gate length Lg of the gate electrode 130 is desirably 500 nm or less in a frequency range exceeding several GHz, such as the so-called "Sub6" frequency range. Furthermore, the gate length Lg of the gate electrode 130 is desirably 150 nm or less in a frequency range of tens of GHz or more, such as ultra-high frequencies.

[0103] A gate insulating film 108 is interposed between the hydrogen termination region 103 and the gate electrode 130. The gate insulating film 108 is made of, for example, Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, Ta ２ O ５ , TiO ２ , W.O. ３ , LaF ３ , MgF ２ , Y.F. ３ , LiF or LiF ３ The present invention is configured to include any one of the following:

[0104] 10 , a surface protective film 110A is formed between the gate electrode 130 and the drain electrode 107 and between the gate electrode 130 and the source electrode 106. The surface protective film 110A is formed to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. Furthermore, the surface protective film 110A covers the exposed hydrogen-termination region 103. In other words, the surface protective film 110A is in contact with the hydrogen-termination region 103.

[0105] This prevents ions in the atmosphere from coming into contact with the hydrogen-termination region 103. Therefore, by forming the surface protective film 110A, it is possible to prevent ions in the atmosphere from adversely affecting the channel formation region 105 formed below the hydrogen-termination region 103. In other words, the surface protective film 110A has the function of protecting the hydrogen-termination region 103.

[0106] As a result, a semiconductor device having the surface protective film 110A has advantages such as improved long-term reliability, prevention of peeling of the electrodes (source electrode 106, drain electrode 107, and gate electrode 130), and suppression of deterioration of performance over time.

[0107] The surface protective film 110A is preferably made of a material with a small relative dielectric constant, for example. This is because a small relative dielectric constant of the surface protective film 110A can reduce the parasitic capacitance caused by the surface protective film 110A acting as a capacitive insulating film. Therefore, for example, the surface protective film 110A is preferably made of a material with a relative dielectric constant of less than 15. Specifically, the surface protective film 110A is made of Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, MgF ２ , Y.F. ３ It is preferable that the surface protective film 110A is configured to contain any of polyimide resin, epoxy resin, and acrylic resin. The surface protective film 110A may be configured from a film of a different type from that of the gate insulating film 108. This is because the characteristics required for the surface protective film 110A are different from the characteristics required for the gate insulating film 108.

[0108] 10, the surface protective film 110A has a cavity 200 that overlaps the gate electrode 130 in plan view. The cavity 200 is filled with, for example, air. However, the cavity 200 may also be filled with an insulating material having a smaller dielectric constant than the surface protective film 110A.

[0109] The embodiment is characterized in that a cavity 200 is formed so as to overlap the gate electrode 130 in plan view. The following describes the characteristics of the embodiment.

[0110] 10 , a surface protective film 110A is formed between the gate electrode 130 and the drain electrode 107, and between the gate electrode 130 and the source electrode 106, and a cavity 200 is formed to overlap the gate electrode in plan view. As a result, the cavity 200, which has a low relative dielectric constant, exists between the gate electrode 130 and the drain electrode 107 and between the gate electrode 130 and the source electrode 106. For example, the cavity 200 is filled with air, which has a relative dielectric constant of about 1. Alternatively, the cavity 200 is filled with an insulating material, which has a relative dielectric constant smaller than that of the surface protective film 110A. Therefore, the presence of the cavity 200, which has a low relative dielectric constant, can reduce parasitic capacitance. That is, according to the embodiment, the surface protective film 110A protects the hydrogen-terminated region 103, while the presence of the cavity 200 with a low dielectric constant can suppress an increase in parasitic capacitance caused by the surface protective film 110A. Therefore, according to the embodiment, the performance of a semiconductor device used in high-frequency applications can be improved.

[0111] Next, the cutoff frequency of the semiconductor device in the embodiment will be described.

[0112] FIG. 11 is a diagram illustrating the parasitic capacitance that exists between the gate electrode 130 having a T-gate structure and the source electrode 106 in the semiconductor device according to the embodiment.

[0113] 11 , the parasitic capacitance is composed of a parallel connection of capacitances Cox, C1A, and C2A. The capacitance Cox is a capacitance formed between the non-doped layer 102 and the gate electrode 130. The capacitance C1A is a capacitance formed between the first width portion 120A of the gate electrode 130 and the source electrode 106. The capacitance C2A is a capacitance formed between the second width portion 120B of the gate electrode 130 and the source electrode 106.

[0114] 12 is a diagram illustrating the capacitance C1A. As shown in FIG. 12, the surface protective film 110A, the cavity 200, and the surface protective film 110A are present between the source electrode 106 and the first width portion 120A. Therefore, the capacitance C1A between the source electrode 106 and the first width portion 120A is composed of a series connection of capacitances Ca, Cb, and Cc.

[0115] Therefore, the capacitance C1A is expressed by the following formula:

[0116] 1 / C1A=1 / Ca+1 / Cb+1 / Cc Solving this equation for capacitance C1A gives: C1A=Ca.Cb.Cc / (Cb.Cc+Ca.Cc+Ca.Cb) Here, capacitance Ca is the capacitance with the surface protective film 110A as the capacitive insulating film. Capacitance Cb is the capacitance with the cavity 200 as the capacitive insulating film. Capacitance Cc is the capacitance with the surface protective film 110A as the capacitive insulating film. Capacitance C1A is smaller than capacitance C1 due to the presence of capacitance Cb caused by the cavity 200, which has a small dielectric constant.

[0117] 13 is a diagram illustrating the capacitance C2A. As shown in FIG. 13, the surface protective film 110A, the cavity 200, and the surface protective film 110A are present between the source electrode 106 and the second width portion 120B. Therefore, the capacitance C2A between the source electrode 106 and the second width portion 120B is composed of a series connection of capacitances Cd, Ce, and Cf.

[0118] Therefore, the capacitance C2A is expressed by the following formula:

[0119] 1 / C2A=1 / Cd+1 / Ce+1 / Cf Solving this equation for capacitance C2A gives: C2A=Cd.Ce.Cf / (Cb.Cc+Ca.Cc+Ca.Cb) Here, capacitance Cd is the capacitance with the surface protective film 110A as the capacitive insulating film. Capacitance Ce is the capacitance with the cavity 200 as the capacitive insulating film. Capacitance Cf is the capacitance with the surface protective film 110A as the capacitive insulating film. Capacitance C2A is smaller than capacitance C2 due to the presence of capacitance Ce caused by the cavity 200, which has a small dielectric constant.

[0120] Based on the above, the cutoff frequency of the semiconductor device in the embodiment will be described.

[0121] The cutoff frequency fT is expressed by the following equation:

[0122] fT=gm / 2π(Cox+C1A+C2A) where gm is the mutual conductance.

[0123] The capacitance C1A is smaller than the capacitance C1. The capacitance C2A is smaller than the capacitance C2. Taking this into consideration, the following inequality holds:

[0124] gm / 2π(Cox+C1A+C2A)>gm / 2π(Cox+C1+C2). This means that the cutoff frequency of the structure shown in FIG. 10, which illustrates the embodiment, is higher than the cutoff frequency of the structure shown in FIG. 7. That is, according to the embodiment, the cutoff frequency can be increased. In this regard, current cannot be amplified at frequencies higher than the cutoff frequency. Taking this into consideration, in order to use higher frequency signals in the semiconductor device, it is desirable for the cutoff frequency of the semiconductor device to be high. In other words, an increase in the cutoff frequency means that the high-frequency characteristics can be improved. Therefore, in the embodiment, the cutoff frequency can be increased, thereby improving the high-frequency characteristics of the semiconductor device. That is, according to the embodiment, by covering the hydrogen-terminated region 103 with the surface protective film 110A, it is possible to suppress the decrease in cutoff frequency caused by the surface protective film 110A while suppressing the characteristic fluctuation of the semiconductor device. As such, the embodiment is useful in that it can improve the high-frequency characteristics of the semiconductor device.

[0125] For example, when the relative dielectric constant of cavity 200 is set to 1 and the cutoff frequency in the embodiment is calculated using the above formula, the cutoff frequency is estimated to be 31 GHz. In contrast, the cutoff frequency of the structure shown in Fig. 7 is estimated to be 18 GHz. This sufficiently supports the fact that the cutoff frequency can be increased according to the embodiment.

[0126] <<Method for Manufacturing a Semiconductor Device>> Next, a method for manufacturing a semiconductor device including a surface conduction FET will be described.

[0127] (1) Preparation of Diamond Substrate First, as shown in FIG. 14 , a diamond substrate 101 made of single-crystal diamond is prepared. Then, the top surface of the diamond substrate 101 is polished. For example, the top surface of the diamond substrate 101 is polished so that the surface roughness of the top surface of the diamond substrate 101 is less than 1 nm. This facilitates ensuring the flatness of the top surface of the non-doped layer 102 formed on the diamond substrate 101. As a result, the adhesion between the non-doped layer 102 and the electrodes formed on the non-doped layer 102 can be improved. Furthermore, it is desirable to eliminate polishing defects. Therefore, after polishing, it is desirable to remove polishing defects by ion beam etching (IBE). Furthermore, before forming the non-doped layer 102, it is desirable to remove organic and inorganic substances present on the top surface of the diamond substrate 101 by strong acid cleaning in a clean room. This facilitates ensuring the flatness of the top surface of the non-doped layer 102 formed on the diamond substrate 101. As a result, the adhesion between the non-doped layer 102 and the electrodes formed on the non-doped layer 102 can be improved.

[0128] (2) Formation of Non-Doped Layer Subsequently, as shown in FIG. 15, a non-doped layer 102 made of diamond is formed on the upper surface of the diamond substrate 101. The non-doped layer 102 can be formed by using, for example, the MPCVD method. The conditions for this are, for example, CH ４ The conditions were: / H=0.5%, no impurity added, total gas flow rate 500 sccm, chamber pressure 110 torr, synthesis temperature 900°C, and input power 1 kW. The thickness of the non-doped layer 102 was approximately 0.1 μm or more and 1 μm or less. A hydrogen termination region 103 was formed on the surface of the non-doped layer 102 thus formed. Due to the presence of this hydrogen termination region 103, a channel formation region 105 consisting of a two-dimensional hole gas (hole accumulation layer) was formed below the hydrogen termination region 103.

[0129] The thickness of the non-doped layer 102 is preferably small within a range that allows sufficient electrical properties to be obtained. This is because a thinner layer is more likely to have a flat upper surface. The surface resistance of the non-doped layer 102 is preferably, for example, 15 kΩ / □ or less. Furthermore, the surface roughness of the non-doped layer 102 is preferably small.

[0130] (3) Formation of Metal Film and Oxygen-Terminated Region As shown in Fig. 16, a metal film 140 is formed on the hydrogen-terminated region 103. The metal film 140 can be formed by, for example, electron beam evaporation or resistance heating evaporation. The material constituting the metal film 140 is, for example, gold (Au).

[0131] Next, photolithography and etching techniques are used to remove a portion of the metal film 140. Then, oxygen plasma treatment is used to selectively form the oxygen termination region 104 in the region from which the metal film 140 has been removed. The oxygen termination region 104 functions as an element isolation region. For example, a plasma generator is used to form the oxygen termination region 104. At this time, it is desirable to form the oxygen termination region 104 in an apparatus that can increase the degree of vacuum as much as possible, from the viewpoint of improving adhesion with the surface protection film formed on the oxygen termination region 104.

[0132] 17, the metal film 140 is patterned by photolithography and etching, thereby forming the source electrode 106 and the drain electrode 107 that are spaced apart from each other.

[0133] (5) Patterning of Resist Film Next, as shown in FIG. 17 , a resist film 150 is applied onto the non-doped layer 102 on which the source electrode 106 and the drain electrode 107 have been formed. Thereafter, the resist film 150 is patterned using photolithography. The resist film 150 is patterned to form a T-gate pattern for forming a T-gate structure. FIG. 11 schematically shows the T-gate pattern formed on the resist film 150. In practice, a plurality of resist films are stacked and patterned differently to form the T-gate pattern.

[0134] (6) Formation of Gate Insulating Film and Gate Electrode Next, as shown in FIG. 18 , a gate insulating film 108 is formed on the non-doped layer 102 exposed by the patterned resist film 150. The gate insulating film 108 is made of, for example, calcium fluoride. Then, a gate electrode 130 is formed on the gate insulating film 108. The gate electrode 130 is made of, for example, copper. By forming the gate electrode 130 using the resist film 150 with the T-gate pattern formed, the gate electrode 130 has a T-gate structure. Resistance heating deposition can be used for both the gate insulating film 108 and the gate electrode 130. In this case, forming the gate insulating film 108 and the gate electrode 130 in a continuous process can prevent contamination during the manufacturing process. As a result, adhesion between the gate insulating film 108 and the gate electrode 130 can be improved.

[0135] (7) Removal of Resist Film and Formation of Surface Protection Film Subsequently, as shown in FIG. 19 , the patterned resist film 150 is removed. Then, as shown in FIG. 20 , a surface protection film 110A is formed so as to cover the source electrode 106, the drain electrode 107, and the gate electrode 130. The material of the surface protection film 110A is, for example, aluminum oxide. The surface protection film 110A is formed by, for example, atomic layer deposition (ALD).

[0136] 20 , the surface protective film 110A is in contact with the hydrogen termination region 103. As a result, the exposed portion of the hydrogen termination region 103 is covered with the surface protective film 110A. As a result, the hydrogen termination region 103 is protected by the surface protective film 110A.

[0137] In this embodiment, the surface protection film 110A is formed by the ALD method. The ALD method has the property of forming a film even in a small gap. Therefore, as shown in FIG. 20 , the surface protection film 110A is formed in the gap between the T-gate structure and the source electrode 106 and in the gap between the T-gate structure and the drain electrode 107.

[0138] In this case, it is desirable to form the surface protective film 110A so that its thickness is smaller than 1 / 2 of "Z" shown in FIG. 20 . This is because, in this case, the surface protective film 110A is formed even inside the gap, so that the hydrogen termination region 103 can be covered with the surface protective film 110A, and even after the surface protective film 110A is formed, the cavity 200 that overlaps with the gate electrode 130 in plan view remains. That is, in order to form the cavity 200 that overlaps with the gate electrode 130 in plan view while protecting the hydrogen termination region 103 with the surface protective film 110A, it is necessary to make the film thickness of the surface protective film 110A smaller than Z / 2. Therefore, it is important to control the film thickness in the ALD method.

[0139] In this manner, a semiconductor device including a surface conduction FET can be manufactured.

[0140] (8) Summary A method for manufacturing a semiconductor device in an embodiment includes: (a) forming a field effect transistor having a diamond layer with a surface conductive layer and including a gate electrode having a T-gate structure, a source electrode electrically connected to the surface conductive layer, and a drain electrode electrically connected to the surface conductive layer; and (b) forming a surface protection film in contact with the gate electrode, source electrode, and drain electrode after the step (a). Here, in the step (a), a cavity is formed between the gate electrode and the source electrode. In the step (b), the cavity remains even after the surface protection film is formed.

[0141] <Modification 1> The surface conduction FET in the embodied form is an FET having a gate insulating film. However, the technical idea of ​​the present embodiment is not limited to this. The technical idea of ​​the present embodiment can be widely applied to, for example, surface conduction FETs that do not have a gate insulating film. In other words, the technical idea of ​​the present embodiment can be widely applied to surface conduction FETs in which a gate electrode and a non-doped layer form a Schottky junction.

[0142] <Modification 2> In the embodiment, for example, as shown in FIG. 9 , a surface-conduction FET is described in which each of the source electrode 106 and the drain electrode 107 has a portion that overlaps with a part of the gate electrode 130 in plan view. However, the technical idea of ​​this embodiment is not limited to this. The technical idea of ​​this embodiment can be widely applied to, for example, a surface-conduction FET in which each of the source electrode 106 and the drain electrode 107 does not have a portion that overlaps with a part of the gate electrode 130 in plan view. In this case, the cavity 200 may be formed between the source electrode 106 and the gate electrode 130 and between the drain electrode 107 and the gate electrode 130. That is, the cavity 200 may be formed not only in a portion that overlaps with the gate electrode 130 in plan view, but also in a portion that does not overlap with the gate electrode 130 in plan view.

[0143] <Variation 3> In a third embodiment, as shown in FIG. 10 or 20, a surface protective film 110A covers the hydrogen-termination region 103, and a cavity 200 is formed directly below the T-gate structure. According to this embodiment, covering the hydrogen-termination region 103 with the surface protective film 110A can suppress fluctuations in the characteristics of the semiconductor device. Furthermore, according to this embodiment, forming the cavity 200 reduces parasitic capacitance, thereby suppressing a decrease in cutoff frequency. In other words, this embodiment can simultaneously protect the hydrogen-termination region 103 and reduce parasitic capacitance.

[0144] However, the technical idea of ​​this embodiment is not limited to this. For example, as shown in Figure 21, a cavity 200 may be formed all the way below the T-gate structure. This configuration is particularly useful in that the cavity 200 can significantly reduce parasitic capacitance.

[0145] 21 does not need to be formed up to the gap immediately below the T-gate structure, so that the surface protection film 110B can be formed by a method such as CVD (Chemical Vapor Deposition) instead of ALD.

[0146] <Application Example to Electronic Device> An application example of the semiconductor device according to this embodiment to an electronic device will be described.

[0147] The semiconductor device according to the present embodiment has high potential as a semiconductor device and is expected to be applied to various electronic devices. An example of an electronic device to which the semiconductor device according to the present embodiment can be applied will be described below.

[0148] In recent years, the advancement of broadband information and communications has led to a demand for higher frequencies and higher output power in the high-frequency transistors that support communication systems. At the same time, from the perspective of energy conservation, there is also a demand for energy efficiency in high-frequency transistors. In this regard, diamond can be cited as a semiconductor material that meets the above requirements.

[0149] For example, the operating frequencies and output power of broadcasting terrestrial stations, communication satellites, and radar exceed the capabilities of current semiconductors, so vacuum tubes called traveling wave tubes are still in use, and there is a demand for improved reliability, efficiency, and miniaturization through the use of semiconductors.

[0150] Therefore, if high-frequency transistors using diamond as a semiconductor material are put into practical use, the high-frequency characteristics and high-output characteristics of communication systems including broadcasting terrestrial stations, communication satellites, radar, etc. can be dramatically improved. Therefore, using the semiconductor device of this embodiment as a high-frequency semiconductor device, which is a component of the above-mentioned communication system, is very useful from the perspective of improving the high-frequency characteristics and high-output characteristics of the communication system. In other words, the semiconductor device of this embodiment has excellent high-frequency characteristics, such as a high cutoff frequency. Therefore, by using an electronic device including the semiconductor device of this embodiment as a component of a communication system, the performance of the communication system can be improved.

[0151] Furthermore, the semiconductor device according to the present embodiment can be used in electronic devices such as sensors mounted on automobiles, thereby improving the performance of the electronic devices mounted on automobiles. As a result, the performance of the automobiles can be improved.

[0152] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0153] 100 Surface conduction type FET 100A Surface conduction type FET 100B Surface conduction type FET 100C Surface conduction type FET 101 Diamond substrate 102 Non-doped layer 103 Hydrogen termination region 104 Oxygen termination region 105 Channel formation region 106 Source electrode 107 Drain electrode 108 Gate insulating film 109 Gate electrode 110 Surface protective film 110A Surface protective film 110B Surface protective film 120A First width portion 120B Second width portion 130 Gate electrode 140 Metal film 150 Resist film Ca Capacitance Cb Capacitance Cc Capacitance Cd Capacitance Ce Capacitance Cf Capacitance Cox Capacitance C1 Capacitance C1A Capacitance C2 Capacitance C2A Capacitance

Claims

1. A semiconductor device comprising: a diamond layer; a surface conduction layer formed within the diamond layer; a drain electrode electrically connected to the surface conduction layer; a source electrode electrically connected to the surface conduction layer; a gate electrode formed on the surface conduction layer and composed of a T-gate structure; a surface protection film in contact with the drain electrode, the source electrode, and the gate electrode; and a cavity formed between the gate electrode and the source electrode. A semiconductor device.

2. In the semiconductor device according to claim 1, air is filled in the cavity.

3. In the semiconductor device according to claim 1, an insulating material is filled in the cavity, and the relative permittivity of the insulating material is smaller than the relative permittivity of the surface protection film.

4. In the semiconductor device according to claim 1, the surface protection film is in contact with the diamond layer.

5. In the semiconductor device according to claim 1, the relative permittivity of the surface protection film is smaller than 15.

6. In the semiconductor device according to claim 5, the surface protective film is Al ２ O ３ , SiO ２ , CaF ２ , HfO ２ , AlN, BN, Si ３ N ４ , SiON, MgF ２ , YF ３ , and contains any one of polyimide resin, epoxy resin, or acrylic resin.

7. In the semiconductor device according to claim 1, the gate electrode has a portion that overlaps either the source electrode or the drain electrode in a planar manner.

8. In the semiconductor device according to claim 1, a gate insulating film is interposed between the surface conduction layer and the gate electrode.

9. In the semiconductor device according to claim 8, the gate insulating film is a film of a type different from the surface protection film.

10. In the semiconductor device according to claim 1, the gate length of the gate electrode is 500 nm or less.

11. An electronic device including the semiconductor device according to claim 1.

12. A method for manufacturing a semiconductor device, comprising: (a) a step of forming a field effect transistor including a diamond layer having a surface conduction layer, and a gate electrode composed of a T-gate structure, a source electrode electrically connected to the surface conduction layer, and a drain electrode electrically connected to the surface conduction layer; (b) a step of forming a surface protection film in contact with the gate electrode, the source electrode, and the drain electrode after the step (a), wherein in the step (a), a cavity is formed between the gate electrode and the source electrode, and in the step (b), the cavity still exists after the surface protection film is formed.

13. In the method of manufacturing a semiconductor device according to claim 12, in the step (b), an ALD method is used.

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