Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a first metal plate; a first semiconductor chip; a second metal plate; a first main terminal; a second main terminal; a base member that is a resin material, that is not directly bonded to the first metal plate, and that is fixed to at least one of the first main terminal and the second main terminal; and a molding member that seals the first semiconductor chip, that is disposed so as to cover the first metal plate; and that is a resin material different from the base member. The melting point of the base member is higher than that of the molding member.

Description

Semiconductor Devices

[0001] This disclosure relates to a semiconductor device. This application claims priority to Japanese Application No. 2024-007537, filed on January 22, 2024, and incorporates by reference all of the contents of said Japanese application.

[0002] A technology relating to a semiconductor module including a semiconductor element has been disclosed (see, for example, Patent Document 1). The semiconductor module disclosed in Patent Document 1 includes a laminated substrate configured by arranging conductive patterns, a semiconductor element arranged on an upper surface of the conductive patterns, an integrated circuit that controls the drive of the semiconductor element, a control-side lead frame on which the integrated circuit is arranged, and a molded resin that packages the semiconductor element and the like.

[0003] Japanese Patent Application Laid-Open No. 2020-136369

[0004] A semiconductor device according to the present disclosure includes a first metal plate, a first semiconductor chip disposed on an upper surface of the first metal plate and electrically connected to the first metal plate, a second metal plate joined to the first semiconductor chip via a first conductive member, a first main terminal electrically connected to the first metal plate, a second main terminal electrically connected to the second metal plate, a base member made of a resin material that is not directly joined to the first metal plate and is fixed to the first main terminal or the second main terminal, and a molding member made of a resin material different from the base member, arranged to cover the first metal plate and seal the first semiconductor chip. The melting point of the base member is higher than the melting point of the molding member.

[0005] FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment. FIG. 2 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 3 is a schematic plan view of the semiconductor device shown in FIG. 2. FIG. 4 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 5 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 6 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 7 is a schematic plan view showing a state in which a first insulating substrate and a second insulating substrate are arranged. FIG. 8 is a schematic bottom view of the first insulating substrate and the second insulating substrate shown in FIG. 7. FIG. 9 is a schematic cross-sectional view showing an enlarged view cut along the plane indicated by arrows IX-IX in FIG. 7. FIG. 10 is a schematic plan view of the semiconductor device showing a state in which a first transistor chip and the like are arranged. FIG. 11 is a schematic cross-sectional view cut along the plane indicated by arrows XI-XI in FIG. 10. FIG. 12 is a schematic perspective view showing a case in which a base lead frame is formed by first punching a metal plate into a predetermined shape. FIG. 13 is a schematic perspective view showing a state in which a predetermined portion of the base lead frame shown in FIG. 12 is bent. Fig. 14 is a schematic perspective view showing a state in which the base member is attached to the base lead frame. Fig. 15 is a schematic perspective view showing a state in which molding is performed using a molding member. Fig. 16 is a schematic plan view showing an enlarged view of the exposed region. Fig. 17 is a schematic plan view showing an enlarged view of the region in which the positioning mechanism is provided.

[0006] [Problem to be Solved by the Present Disclosure] According to Patent Document 1, a control-side lead frame is provided on one side of a semiconductor module, and a main-circuit-side lead frame is provided on the other side. A plurality of terminals are also provided to connect to the control-side lead frame and the main-circuit-side lead frame. Since a certain insulation distance must be ensured between the terminals, there is a limit to how small the device itself can be.

[0007] Therefore, one object is to provide a semiconductor device that can easily ensure high insulation while achieving miniaturization of the device.

[0008] Effect of the Present Disclosure According to such a semiconductor device, high insulation properties can be easily ensured while miniaturizing the device.

[0009] [Description of Embodiments of the Present Disclosure] (1) A semiconductor device according to the present disclosure includes a first metal plate, a first semiconductor chip disposed on an upper surface of the first metal plate and electrically connected to the first metal plate, a second metal plate joined to the first semiconductor chip via a first conductive member, a first main terminal electrically connected to the first metal plate, a second main terminal electrically connected to the second metal plate, a base member made of a resin material that is not directly joined to the first metal plate and is fixed to at least one of the first main terminal and the second main terminal, and a molding member made of a resin material different from the base member that is arranged to cover the first metal plate and seal the first semiconductor chip. The melting point of the base member is higher than the melting point of the molding member.

[0010] According to the semiconductor device of the present disclosure, the base member is fixed to at least one of the first main terminal and the second main terminal, and the positional relationship of the second main terminal relative to the first main terminal can be adjusted via the base member, thereby easily ensuring insulation between the first main terminal and the second main terminal. Because the base member is not directly bonded to the first metal plate, it is easier to position the molding material that encapsulates the first semiconductor chip on the first metal plate, thereby improving the insulation of the first metal plate and the first semiconductor chip. In this case, because the melting point of the base member is higher than that of the molding material, the base member does not melt when the molding material is melted and then hardened to encapsulate the first semiconductor chip and cover the first metal plate. Therefore, the positioning of the components fixed to the base member can be reliably achieved. As described above, this semiconductor device can easily ensure high insulation while achieving a compact device.

[0011] (2) In the above (1), the base member may have a first intervening portion disposed between the first main terminal and the second main terminal in a region where the first main terminal and the second main terminal overlap when viewed in the thickness direction of the first semiconductor chip. This increases insulation due to the first intervening portion of the base member disposed between the first main terminal and the second main terminal, thereby reducing the risk of contact and short-circuiting between the first main terminal and the second main terminal.

[0012] (3) In the above (1) or (2), a region where a molding member is disposed may be provided between the base member and the first metal plate in the thickness direction of the first semiconductor chip. This allows the molding member disposed between the first metal plate and the base member to improve insulation with respect to the first metal plate. In this case, the base member and the molding member are both made of a resin material, which improves adhesion between the base member and the molding member.

[0013] (4) In any of (1) to (3) above, the semiconductor device may further include a third metal plate, a second semiconductor chip electrically connected to the second metal plate, a fourth metal plate connected to the second semiconductor chip via the second conductive member, and a third main terminal electrically connected to the fourth metal plate. The second main terminal may be electrically connected to the third metal plate. This allows a two-arm configuration to be adopted in the semiconductor device by utilizing the second semiconductor chip, the third metal plate, the fourth metal plate, and the third main terminal, thereby improving convenience.

[0014] (5) In the above (4), the base member may have a second intervening portion disposed between the first main terminal and the third main terminal in a region where the first main terminal and the third main terminal overlap when viewed in the thickness direction of the first semiconductor chip. This increases insulation by the second intervening portion of the base member disposed between the first main terminal and the third main terminal, thereby reducing the risk of contact and short-circuiting between the first main terminal and the third main terminal.

[0015] (6) In any of (1) to (5) above, the semiconductor device may further include a first control terminal that controls the operation of the first semiconductor chip and a first control reference terminal that serves as a reference for the potential of the first control terminal. The first control terminal and the first control reference terminal may each be held by a base member. The first control terminal and the first control reference terminal may each have an area that protrudes from the base member and the molding member. This allows the first control terminal and the first control reference terminal to be used to precisely control the operation of the first semiconductor chip. In this case, because the first control terminal and the first control reference terminal each have an area that protrudes from the molding member, it is easy to ensure electrical connection between the first control terminal and the first control reference terminal and the outside of the semiconductor device.

[0016] (7) In any of (4) to (6) above, the semiconductor device may further include a second control terminal that controls the operation of the second semiconductor chip and a second control reference terminal that serves as a reference for the potential of the second control terminal. The second control terminal and the second control reference terminal may each be held by a base member. The second control terminal and the second control reference terminal may each have an area that protrudes from the base member and the molding member. This allows the second control terminal and the second control reference terminal to be used to precisely control the operation of the second semiconductor chip. In this case, because the second control terminal and the second control reference terminal each have an area that protrudes from the molding member, it is easy to ensure electrical connection between the second control terminal and the second control reference terminal and the outside of the semiconductor device.

[0017] (8) In the above (7), any two or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal may have tie bar cut surfaces on their end surfaces. In the thickness direction of the first semiconductor chip, the tie bar cut surfaces of any two or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal may have the same height. This makes it easier to align the mating surfaces of the vertical molds when assembling them and injecting the molten molding material during manufacturing, thereby reducing the risk of the molten material leaking from the mold joints. This, in turn, improves productivity.

[0018] (9) In the above (8), the first semiconductor chip may be a transistor chip or a diode chip connected in anti-parallel to the transistor chip. Such a semiconductor chip is effectively used to control the operation of the semiconductor device.

[0019] (10) In the above (9), the semiconductor device may include one or more first semiconductor chips. The semiconductor device may further include a first lead frame (hereinafter, sometimes abbreviated as "first LF (Lead Frame)" or sometimes simply abbreviated as "LF") that is electrically connected to the first control terminal and electrically connects the gate electrodes of the one or more first semiconductor chips. This allows the first LF to efficiently control each gate electrode of the one or more first semiconductor chips.

[0020] (11) In the above (9) or (10), the semiconductor device may include one or more first semiconductor chips. The semiconductor device may further include a second lead frame (hereinafter sometimes abbreviated as "second LF") electrically connected to the first control reference terminal and electrically connecting source electrodes of each of the one or more first semiconductor chips. This allows the second LF to efficiently control the reference of each source electrode for the one or more first semiconductor chips.

[0021] (12) In the above (11), at least one of the first LF and the second LF may include an electronic component, thereby making it possible to suppress excessive load operation of a semiconductor chip electrically connected to at least one of the first LF and the second LF by the electronic component.

[0022] (13) In the above (11) or (12), at least one of the first LF and the second LF may be disposed on the upper surface of the first metal plate. This allows the size in at least one of the X direction and the Y direction, which will be described later, to be reduced. Furthermore, it also makes it easier to join at least one of the first LF and the second LF to the first metal plate. Therefore, productivity can be improved.

[0023] (14) In any of the above (11) to (13), the base member may include a positioning mechanism that regulates the position of at least one of the first main terminal, the second main terminal, the third main terminal, the first LF, and the second LF relative to the base member. This makes it possible to prevent misalignment relative to the base member during assembly using the positioning mechanism, thereby reliably ensuring insulation. Therefore, it is possible to improve assembly ease.

[0024] (15) In any of the above (11) to (14), the base member may include a fitting portion that fits with any one or more of the first main terminal, the second main terminal, the third main terminal, the first LF, and the second LF. This makes it possible to restrict movement of any one of the first main terminal, the second main terminal, the third main terminal, the first LF, and the second LF that are fitted to the base member by the fitting portion. Therefore, it is possible to reduce the risk of misalignment of the member fitted to the base member by the fitting portion during manufacturing, and to reliably ensure insulation.

[0025] (16) In the above (15), the fitting portion may include a fitting hole provided in one or more of the first main terminal, the second main terminal, the third main terminal, the first LF, and the second LF, and a fitting pin provided in the base member, protruding from the member in which the fitting hole is provided, and fitting into the fitting hole. This makes it possible to more easily achieve a mated state by fitting the fitting portion with the fitting pin fitting into the fitting hole.

[0026] (17) In any of (8) to (16) above, any one or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal may protrude from the molded member. A base member may be disposed at the base of any one or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal. This allows the members protruding from the molded member to easily ensure electrical connection to the outside. Furthermore, because the base member is disposed at the base of the members protruding from the molded member, even if stress is applied to the members protruding from the molded member in a direction such as bending, the stress can be absorbed by the base member disposed at the base, which has a high melting point and relatively high rigidity.

[0027] (18) In any of (8) to (17) above, the upper surfaces of one or more of the region where the first main terminal and the first metal plate are bonded, the region where the second main terminal and the second metal plate are bonded, the region where the first LF and the first control terminal are bonded, and the region where the second LF and the first control reference terminal are bonded may be covered only with a molding material. This allows the regions where the components overlap to be opened in the thickness direction of the first semiconductor chip before being covered with the molding material in the manufacturing process, making it easier to bond the components using techniques such as laser welding or ultrasonic bonding. This improves manufacturing efficiency.

[0028] (19) In any of (8) to (18) above, one or more of the region where the first main terminal and the first metal plate are joined, the region where the second main terminal and the second metal plate are joined, the region where the first LF and the first control terminal are joined, and the region where the second LF and the first control reference terminal are joined may be joined by adhesive or welding using a conductive member. This makes it possible to more reliably fix the overlapping regions of the members while ensuring conductivity. This therefore makes it possible to reliably operate the semiconductor device and improve reliability.

[0029] (20) In any one of (1) to (19) above, an insulating layer may be further included that is disposed on the lower surface side of the first metal plate, thereby improving the insulating properties of the semiconductor device.

[0030] (21) In any of the above (1) to (20), the material of the base member may be PPS resin or PBT resin. The material of the molding member may be epoxy resin. The epoxy resin used as the material of the molding member has high insulating properties. Furthermore, by using PPS resin or PBT resin as the base member, the difference in melting point between the base member and the molding member can be more reliably increased, thereby reducing the risk of the molding member melting when the molten, uncured epoxy resin is poured in. Therefore, deformation of the base member can be more reliably suppressed, ensuring high insulating properties.

[0031] [Details of the Embodiments of the Present Disclosure] Next, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters, and description thereof will not be repeated.

[0032] (Embodiment 1) A semiconductor device according to embodiment 1 of the present disclosure will be described. FIGS. 1 to 6 are schematic perspective views of the semiconductor device according to embodiment 1. FIG. 2 illustrates the semiconductor device shown in FIG. 1 with the molding material removed. FIG. 4 illustrates the semiconductor device shown in FIG. 2 with the N terminal removed. FIG. 5 illustrates the semiconductor device shown in FIG. 4 with the P terminal, O terminal, first gate terminal, first auxiliary source terminal, second gate terminal, second auxiliary source terminal, and part of the base member removed. FIG. 6 illustrates the semiconductor device shown in FIG. 5 with the electronic components, first LF, second LF, and base member removed. In FIG. 1 and subsequent drawings, the X direction indicates the direction in which the first insulating substrate and the second insulating substrate are arranged side by side, the Y direction indicates the direction perpendicular to the X direction, and the Z direction indicates the thickness direction of the first semiconductor chip. The X direction, Y direction, and Z direction are perpendicular to each other.

[0033] 1 to 6, a semiconductor device 10a in the first embodiment includes a first insulating substrate 11a as an insulating layer, a second insulating substrate 11b as an insulating layer, a first metal plate 12a, a second metal plate 12b, a third metal plate 12c, a fourth metal plate 12d, a first transistor chip (hereinafter sometimes abbreviated as "first TR chip"; or the transistor chip may be simply abbreviated as "TR chip") 13a, a first TR chip 13b, a first TR chip 13c, a first TR chip 13d as a first semiconductor chip, a first diode chip (hereinafter sometimes abbreviated as "first D chip"; or the diode chip may be simply abbreviated as "D chip") 14a, a first D chip 14b, a first D chip 14c, a first D chip 14d as a second semiconductor chip, and a second transistor chip (hereinafter sometimes abbreviated as "TR chip") 14b, a first D chip 14c, a first D chip 14d as a second semiconductor chip. The semiconductor device includes a second diode chip (hereinafter sometimes abbreviated as "second D chip") 15a, a second TR chip 15b, a second TR chip 15c, a second TR chip 15d, a second diode chip (hereinafter sometimes abbreviated as "second D chip") 16a, a second D chip 16b, a second D chip 16c, a second D chip 16d, a P terminal 17a as a first main terminal, an O terminal 17b as a second main terminal, an N terminal 17c as a third main terminal, a first gate terminal 21a as a first control terminal on the upper arm side, a first auxiliary source terminal (first Kelvin source terminal) 22a as a first control reference terminal on the upper arm side, a second gate terminal 21b as a second control terminal on the lower arm side, a second auxiliary source terminal (second Kelvin source terminal) 22b as a second control reference terminal on the lower arm side, a base member 23a, and a mold member 24a. The semiconductor device 10a also includes first LFs 26a and 26b and second LFs 27a and 27b. The semiconductor device 10a employs a 2-in-1 configuration and includes both an upper arm and a lower arm. When the upper arm is operating, a current flows through the P terminal 17a and the O terminal 17b, and when the lower arm is operating, a current flows through the O terminal 17b and the N terminal 17c.

[0034] The overall shape of the semiconductor device 10a is such that, with some exceptions, each component constituting the semiconductor device 10a is covered by a molding member 24a. The molding member 24a has insulating properties. Portions of the P terminal 17a, O terminal 17b, N terminal 17c, first gate terminal 21a, first auxiliary source terminal 22a, second gate terminal 21b, and second auxiliary source terminal 22b protrude from the molding member 24a. These protruding portions are used to ensure electrical continuity between the semiconductor device 10a and the outside.

[0035] The molding member 24a is made of, for example, a thermosetting resin, specifically, an epoxy resin. The molding member 24a is formed by combining an upper mold and a lower mold (not shown), injecting molten unhardened epoxy resin into the mold, and then heating the mold to harden it. A parting line 25a is provided around the entire periphery of the molding member 24a at a portion corresponding to the boundary between the upper and lower molds.

[0036] Next, the internal structure of the semiconductor device 10a will be described. Fig. 7 is a schematic plan view showing the state in which the first insulating substrate 11a and the second insulating substrate 11b are arranged. Fig. 8 is a schematic bottom view of the first insulating substrate 11a and the second insulating substrate 11b shown in Fig. 7. Fig. 9 is a schematic cross-sectional view showing an enlarged view taken along the plane indicated by arrow IX-IX in Fig. 7. Fig. 9 is a cross-sectional view showing the region including the first TR chip 13a and the first D chip 14a taken along the YZ plane.

[0037] 7 to 9, the first insulating substrate 11a has a rectangular shape in which the length in the Y direction is longer than the length in the X direction when viewed in the Z direction. The material of the first insulating substrate 11a is, for example, aluminum oxide (Al ２ O ３ The second insulating substrate 11b is made of one of silicon nitride (SiN) and aluminum nitride (AlN). The second insulating substrate 11b has the same shape and material as the first insulating substrate 11a, so a description thereof will be omitted. The first insulating substrate 11a and the second insulating substrate 11b are arranged side by side in the X direction.

[0038] In the Z direction, a first metal plate 12a and a second metal plate 12b are disposed on the first insulating substrate 11a. That is, the first metal plate 12a and the second metal plate 12b are disposed on one surface (front surface) of the first insulating substrate 11a. The first metal plate 12a and the second metal plate 12b are disposed with a gap between them. The first metal plate 12a is configured to be H-shaped when viewed in the Z direction. A pair of second metal plates 12b are provided with a gap in the Y direction. Each of the pair of second metal plates 12b is disposed between long strip-shaped portions of the first metal plate 12a that form the H shape, which are spaced apart in the X direction and extend in the Y direction. The first metal plate 12a and the second metal plate 12b are configured with a gap between them to form a shape that follows the overall rectangular outer shape of the first insulating substrate 11a. The first metal plate 12a and the second metal plate 12b are formed by etching a single metal plate disposed on the first insulating substrate 11a to form a pattern. A metal plate 18a, slightly smaller than the first insulating substrate 11a, is also disposed on the other surface (back surface) of the first insulating substrate 11a. That is, the first insulating substrate 11a has metal plates disposed on both sides in the thickness direction. The first insulating substrate 11a and the metal plates disposed on both sides thereof can be easily realized by using a direct bonded copper (DBC) substrate. A pair of metal first control plates 12e connected to the first gate terminal 21a and two pairs of metal first control reference plates 12f connected to the first auxiliary source terminal 22a are disposed on the first insulating substrate 11a.

[0039] Similar to the first insulating substrate 11a, a third metal plate 12c corresponding in shape and arrangement to the first metal plate 12a and a pair of fourth metal plates 12d corresponding in shape and arrangement to the second metal plate 12b are disposed on one surface of the second insulating substrate 11b. A metal plate 18b is also disposed on the other surface of the second insulating substrate 11b. Also provided on the second insulating substrate 11b are a pair of metal second control plates 12g connected to the second gate terminal 21b and two pairs of metal second control reference plates 12h connected to the second auxiliary source terminal 22b. The first insulating substrate 11a and the second insulating substrate 11b are point-symmetrical, and in this embodiment, the first insulating substrate 11a and the second insulating substrate 11b are formed from the same substrate.

[0040] In this embodiment, the semiconductor device 10a includes a plurality of, specifically a total of four, first TR chips 13a, 13b, 13c, and 13d, and a plurality of, specifically a total of four, first D chips 14a, 14b, 14c, and 14d. The four first TR chips 13a, 13b, 13c, and 13d are arranged on the first metal plate 12a in regions near the four corners of the rectangular first insulating substrate 11a.

[0041] In this embodiment, the first TR chip 13a is a vertical transistor chip, for example, a metal-oxide-semiconductor field effect transistor (MOSFET). The first TR chip 13a is a switching element. The first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are similar to the first TR chip 13a. The four first TR chips 13a, 13b, 13c, and 13d function as components of the upper arm.

[0042] FIG. 10 is a schematic plan view of a semiconductor device showing the arrangement of the first TR chip 13a and other components. FIG. 11 is a schematic cross-sectional view taken along the plane indicated by the arrows XI-XI in FIG. 10 . Referring to FIGS. 10 and 11 , the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are each electrically connected to the first metal plate 12a. Specifically, drain electrodes arranged on the backsides of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are joined and electrically connected to the first metal plate 12a using a conductive bonding material, such as solder or a sintered material. Gate electrodes and large-area source electrodes are arranged on the frontsides of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d. In this case, the first TR chip 13a and the first TR chip 13b are attached so that the gate electrodes of the two first TR chips 13a and 13b, which are spaced apart in the Y direction, face each other. Also, the first TR chip 13c and the first TR chip 13d are attached so that the gate electrodes of the two first TR chips 13c and 13d, which are spaced apart in the Y direction, face each other.

[0043] In this embodiment, the first D chip 14a is a Schottky barrier diode (SBD). The first D chip 14b, the first D chip 14c, and the first D chip 14d are similar to the first D chip 14a. The four first D chips 14a, 14b, 14c, and 14d are arranged on the first metal plate 12a. Specifically, they are arranged between the first TR chip 13a, the first TR chip 13b, and the first TR chip 13c, and the first TR chip 13d, which are arranged at intervals in the Y direction. The first D chip 14a, the first D chip 14b, the first D chip 14c, and the first D chip 14d are also electrically connected to the first metal plate 12a. Specifically, cathode electrodes arranged on the backside of first D chip 14a, first D chip 14b, first D chip 14c, and first D chip 14d are joined and electrically connected to first metal plate 12a with a conductive joining material, such as solder or a sintered material. Anode electrodes are arranged on the frontside of first D chip 14a, first D chip 14b, first D chip 14c, and first D chip 14d.

[0044] The first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are joined to the second metal plate 12b via first wires 31a serving as first conductive members. Specifically, the source electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are joined to the second metal plate 12b via the first wires 31a. The material of the first wires 31a may be aluminum (Al), copper (Cu), silver (Ag), gold (Au), or an alloy thereof. Alternatively, a copper clip may be used as the first conductive member. When a copper clip is used, it is connected via a bonding material. Furthermore, the gate electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are joined to the first control plate 12e via wires 32a. The source electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d are joined to the first control reference plate 12f via wires 33a.

[0045] The first D chip 14a, the first D chip 14b, the first D chip 14c, and the first D chip 14d are joined to the second metal plate 12b via a conductive member. Specifically, the anode electrodes of the first D chip 14a, the first D chip 14b, the first D chip 14c, and the first D chip 14d are joined to the second metal plate 12b via the conductive member, wire 34a. This electrically connects the source electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d to the anode electrodes of the first D chip 14a, the first D chip 14b, the first D chip 14c, and the first D chip 14d via the second metal plate 12b.

[0046] In this embodiment, the semiconductor device 10a includes a plurality of, specifically a total of four, second TR chips 15a, 15b, 15c, and 15d, and a plurality of, specifically a total of four, second D chips 16a, 16b, 16c, and 16d. The second TR chips 15a, 15b, 15c, and 15d are each electrically connected to the third metal plate 12c. The second TR chips 15a, 15b, 15c, and 15d are joined to the fourth metal plate 12d via second wires 31b serving as second conductive members. The gate electrodes of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d are joined to the second control plate 12g via wires 32b. The source electrodes of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d are joined to the second control reference plate 12h via wires 33b. The configuration, arrangement, and wiring of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, the second TR chip 15d and the second D chip 16a, the second D chip 16b, the second D chip 16c, the second D chip 16d are the same as those of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, the first TR chip 13d, the first D chip 14a, the first D chip 14b, the first D chip 14c, the first D chip 14d, and so a description thereof will be omitted. The four second TR chips 15a, the second TR chip 15b, the second TR chip 15c, the second TR chip 15d function as components of the lower arm.

[0047] The P terminal 17a, the O terminal 17b, and the N terminal 17c are each formed by bending a flat metal member. The P terminal 17a is electrically connected to the first metal plate 12a. Specifically, the P terminal 17a is bent toward the first metal plate 12a, and the portion of the P terminal 17a that overlaps with the first metal plate 12a is joined. The O terminal 17b is electrically connected to the second metal plate 12b. Specifically, the O terminal 17b is bent toward the second metal plate 12b, and the portion of the O terminal 17b that overlaps with the second metal plate 12b is joined. The O terminal 17b is also electrically connected to the third metal plate 12c. Specifically, the O terminal 17b is bent toward the third metal plate 12c, and the portion of the O terminal 17b that overlaps with the third metal plate 12c is joined. The N terminal 17c is electrically connected to the fourth metal plate 12d. Specifically, the N terminal 17c is bent toward the fourth metal plate 12d, and the portion overlapping the fourth metal plate 12d is joined. The P terminal 17a, the O terminal 17b, and the N terminal 17c each have a region that protrudes from the base member 23a and the molded member 24a. The P terminal 17a and the O terminal 17b each have a tie bar cut surface on their end surface. The O terminal 17b has an opening 19a penetrating through the thickness direction so that the region where the O terminal 17b and the third metal plate 12c overlap is exposed when viewed in the thickness direction of the first TR chip 13a. The N terminal 17c has an opening 19b penetrating through the thickness direction so that the region where the P terminal 17a and the first metal plate 12a overlap is exposed when viewed in the thickness direction of the first TR chip 13a. The P terminal 17a and the O terminal 17b are arranged to form parallel plates in the Z direction. Furthermore, the O terminal 17b and the N terminal 17c are arranged to form parallel plates in the Z direction, so that magnetic fluxes are cancelled out by the currents flowing in opposite directions, thereby reducing inductance.

[0048] The first gate terminal 21a controls the operation of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d. The first auxiliary source terminal 22a serves as a reference potential for the first gate terminal 21a. The second gate terminal 21b controls the operation of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d. The second auxiliary source terminal 22b serves as a reference potential for the second gate terminal 21b. The first gate terminal 21a, the first auxiliary source terminal 22a, the second gate terminal 21b, and the second auxiliary source terminal 22b are each held by the base member 23a. The first gate terminal 21a, the first auxiliary source terminal 22a, the second gate terminal 21b, and the second auxiliary source terminal 22b each have regions that protrude from the base member 23a and the mold member 24a. The first gate terminal 21 a, the first auxiliary source terminal 22 a, the second gate terminal 21 b, and the second auxiliary source terminal 22 b each have a tie-bar cut surface at an end face. Here, in the thickness direction of the first TR chip 13 a, the heights of the tie-bar cut surfaces of the P terminal 17 a, the O terminal 17 b, the first gate terminal 21 a, the first auxiliary source terminal 22 a, the second gate terminal 21 b, and the second auxiliary source terminal 22 b are the same.

[0049] The semiconductor device 10a includes a first LF 26a on the upper arm side. The first LF 26a is electrically connected to the first gate terminal 21a. The first LF 26a is electrically connected to the gate electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d. That is, the first gate terminal 21a is electrically connected to the gate electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d via the first LF 26a. The first LF 26a is disposed on the upper surface of the first metal plate 12a.

[0050] The first LF 26a includes a rectangular chip resistor 28a as an electronic component. The rectangular chip resistor 28a is disposed between the first gate terminal 21a and each gate electrode, i.e., in the middle of the first LF 26a. Such a rectangular chip resistor 28a can function as a so-called gate resistor. Note that the first LF 26a may include a chip resistor, a capacitor, or a thermistor as an electronic component instead of the rectangular chip resistor 28a. Of course, it may also include multiple electronic components of various types. The electronic component is disposed above the first TR chip 13a, etc. Therefore, thermal interference can be prevented even if the first TR chip 13a, etc. generates heat, and high reliability can be ensured even with electronic components with lower heat resistance than the first TR chip 13a, etc.

[0051] The semiconductor device 10a includes a second LF 27a on the upper arm side. The second LF 27a is electrically connected to the first auxiliary source terminal 22a. The second LF 27a is electrically connected to the source electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d. That is, the first auxiliary source terminal 22a is electrically connected to the source electrodes of the first TR chip 13a, the first TR chip 13b, the first TR chip 13c, and the first TR chip 13d via the second LF 27a. The second LF 27a is disposed on the upper surface of the first metal plate 12a. Like the first LF 26a, the second LF 27a may also include an electronic component such as a square chip resistor 28a.

[0052] The semiconductor device 10a includes a first LF 26b on the lower arm side. The first LF 26b is electrically connected to the second gate terminal 21b. The first LF 26b is electrically connected to the gate electrodes of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d. That is, the second gate terminal 21b is electrically connected to the gate electrodes of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d via the first LF 26b. The first LF 26b is disposed on the third metal plate 12c.

[0053] The first LF 26b includes a rectangular chip resistor 28b. The rectangular chip resistor 28b is provided between the second gate terminal 21b and each gate electrode, i.e., in the middle of the first LF 26b. Note that the first LF 26b may include a chip resistor, a capacitor, or a thermistor as an electronic component instead of the rectangular chip resistor 28b. Of course, the first LF 26b may include a plurality of various electronic components.

[0054] The semiconductor device 10a includes a second LF 27b on the lower arm side. The second LF 27b is electrically connected to the second auxiliary source terminal 22b. The second LF 27b is electrically connected to the source electrodes of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d. That is, the second auxiliary source terminal 22b is electrically connected to the source electrodes of the second TR chip 15a, the second TR chip 15b, the second TR chip 15c, and the second TR chip 15d via the second LF 27b. The second LF 27b is disposed on the third metal plate 12c. Like the first LF 26b, the second LF 27b may also include an electronic component such as a square chip resistor 28b.

[0055] The base member 23a is fixed to at least one of the P terminal 17a and the O terminal 17b. In this embodiment, the base member 23a is fixed to both the P terminal 17a and the O terminal 17b. The base member 23a also fixes the first gate terminal 21a, the first auxiliary source terminal 22a, the second gate terminal 21b, and the second auxiliary source terminal 22b. The region where the P terminal 17a and the first metal plate 12a are joined, the region where the O terminal 17b and the second metal plate 12b and the third metal plate 12c are joined, the region where the N terminal 17c and the fourth metal plate 12d are joined, the region where the first gate terminal 21a and the first LF 26a are joined, the region where the first auxiliary source terminal 22a and the second LF 27a are joined, the region where the second gate terminal 21b and the first LF 26b are joined, and the second auxiliary source terminal 22b and the second gate terminal 21b are joined. When molding member 24a is not disposed, the region where first LF 26a and first control plate 12e are bonded to second LF 27b, the region where first LF 26a and first control plate 12e are bonded to second LF 27a and first control reference plate 12f, the region where first LF 26b and second control plate 12g are bonded to second LF 27b and second control reference plate 12h are bonded to each other, and the region where first LF 26b and second control plate 12g are bonded to second LF 27b and second control reference plate 12h are exposed when viewed in the thickness direction of first TR chip 13a. In other words, the upper surface of the region where P terminal 17a and first metal plate 12a are bonded to each other is covered only by molding member 24a.

[0056] The base member 23a is made of a resin material, such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT). The melting point of the base member 23a is higher than the melting point of the mold member 24a.

[0057] Here, we will explain the case where the base member 23a is formed by hoop molding. A metal plate having portions corresponding to the P terminal 17a, the O terminal 17b, the first gate terminal 21a, the first auxiliary source terminal 22a, the second gate terminal 21b, and the second auxiliary source terminal 22b can be formed by punching a single base LF 29a into a predetermined shape and then bending the base LF 29a into a predetermined shape. FIG. 12 is a schematic perspective view showing a case where a single metal plate is first punched into a predetermined shape to form the base LF (base lead frame) 29a. FIG. 13 is a schematic perspective view showing the state in which the base LF 29a shown in FIG. 12 has been bent at predetermined locations. Then, hoop molding is performed to attach the base member 23a to the base LF 29a. FIG. 14 is a schematic perspective view showing the state in which the base member 23a is attached to the base LF 29a. After molding using a mold member 24a, the outer periphery is removed by tie bar cutting. FIG. 15 is a schematic perspective view showing the state after molding using the molding member 24a.

[0058] 14 , the P terminal 17a, the O terminal 17b, the first gate terminal 21a, the first auxiliary source terminal 22a, the second gate terminal 21b, the second auxiliary source terminal 22b, and the base member 23a are integrated into a single component, which significantly reduces the number of components required when assembling the semiconductor device 10a. Furthermore, because the base member 23a is pre-fixed to the base LF 29a, there is no need to fix the base member 23a when assembling the semiconductor device 10a. Because the P terminal 17a, the O terminal 17b, the first gate terminal 21a, the first auxiliary source terminal 22a, the second gate terminal 21b, and the second auxiliary source terminal 22b are formed from a single base LF 29a, the heights of the portions protruding from the mold member 24a are uniform. Therefore, when the molds are arranged and assembled in the vertical direction during manufacturing and the molten material of the molding member 24a is poured, the mating surfaces of the molds in the vertical direction can be easily aligned, reducing the risk of the molten material leaking out from the joints of the molds. Although the schematic perspective view shown in Fig. 14 illustrates only one LF configuration, a configuration in which multiple LFs are connected in series may also be employed.

[0059] In base member 23a formed by hoop molding, the region where first gate terminal 21a and first LF 26a are bonded, the region where first auxiliary source terminal 22a and second LF 27a are bonded, the region where second gate terminal 21b and first LF 26b are bonded, and the region where second auxiliary source terminal 22b and second LF 27b are bonded are exposed when viewed in the thickness direction of first TR chip 13a when mold member 24a is not arranged. Figure 16 is a schematic plan view showing an enlarged view of the exposed regions. Referring also to Figure 16, the upper surfaces of the region where the first gate terminal 21a and the first LF 26a are joined, the region where the first auxiliary source terminal 22a and the second LF 27a are joined, the region 39a where the second gate terminal 21b and the first LF 26b are joined, and the region 39b where the second auxiliary source terminal 22b and the second LF 27b are joined are covered only by the molding member 24a.

[0060] The base member 23a has a first intermediate portion 36a disposed between the O terminal 17b and the N terminal 17c in the region where the O terminal 17b and the N terminal 17c overlap when viewed in the thickness direction of the first TR chip 13a. The base member 23a also has a second intermediate portion 36b disposed between the P terminal 17a and the N terminal 17c in the region where the P terminal 17a and the N terminal 17c overlap when viewed in the thickness direction of the first TR chip 13a. The base member 23a includes a positioning mechanism 37a that regulates the positions of the first LF 26a, the first LF 26b, and the second LF 27a, the second LF 27b relative to the base member 23a. FIG. 17 is a schematic plan view showing an enlarged view of the region where the positioning mechanism 37a is provided. Referring also to FIG. 17, the positioning mechanism 37a is composed of a protrusion 38a that protrudes upward in the thickness direction of the first TR chip 13a. The positioning mechanism 37a allows the first LF 26a, the first LF 26b, the second LF 27a and the second LF 27b to be easily positioned on the base member 23a, and the necessary insulation distance can be reliably ensured.

[0061] The base member 23a also includes a fitting portion 41a that fits with the N terminal 17c. The fitting portion 41a includes a fitting hole 42a provided in the N terminal 17c and a fitting pin 43a that protrudes from the base member 23a and fits into the fitting hole 42a. Two fitting holes 42a are provided spaced apart in the X direction. Two fitting pins 43a are also provided spaced apart in the X direction at positions corresponding to the fitting holes 42a. The fitting portion 41a and the fitting hole 42a make it easy to position the N terminal 17c on the base member 23a, and the required insulation distance can be reliably ensured.

[0062] The molding member 24a seals the TR chips such as the first TR chip 13a and the D chips such as the first D chip. The molding member 24a is arranged to cover the first metal plate 12a, the second metal plate 12b, the third metal plate 12c, and the fourth metal plate 12d. The material of the molding member 24a is different from the material of the base member 23a.

[0063] P terminal 17a, O terminal 17b, N terminal 17c, first gate terminal 21a, first auxiliary source terminal 22a, second gate terminal 21b, and second auxiliary source terminal 22b protrude from mold member 24a. Base member 23a is disposed at the base of P terminal 17a, O terminal 17b, N terminal 17c, first gate terminal 21a, first auxiliary source terminal 22a, second gate terminal 21b, and second auxiliary source terminal 22b.

[0064] Next, a brief description will be given of an example of a method for manufacturing the semiconductor device 10a having the above configuration. First, the first insulating substrate 11a and the second insulating substrate 11b on which the first metal plate 12a and the like having the above configuration are arranged are prepared. Then, the first TR chip 13a and the like are bonded to the upper surfaces of the first metal plate 12a and the third metal plate 12c, respectively. Then, wiring is performed using the first wires 31a and the like.

[0065] As described above, the base LF 29a is punched into a predetermined shape, bent, and hoop-molded to form the base member 23a. Next, it is placed in a predetermined position on the first insulating substrate 11a and the second insulating substrate 11b. The first LF 26a, the second LF 27a, and other components are then positioned, and the terminals and metal plates are joined by laser welding. After joining, the upper and lower mold dies are attached, and molten uncured molding resin is injected and heated to harden. Because the base member 23a is fixed to the base LF 29a, it is not affected by the molten uncured molding resin, ensuring reliable insulation. The mold is then removed, and the outer periphery of the base LF 29a is removed to obtain the semiconductor device 10a configured as described above.

[0066] Next, a brief explanation of the current flow will be given. On the upper arm side, the first TR chip 13a, etc., is turned on by control via the first gate terminal 21a, and the second TR chip 15a, etc., is turned off by control via the second gate terminal 21b. This causes current to flow from the P terminal 17a through the first metal plate 12a, the first TR chip 13a, etc., the first wire 31a, the second metal plate 12b, and the O terminal 17b in this order. On the lower arm side, the second TR chip 15a, etc., is turned on by control via the second gate terminal 21b, and the first TR chip 13a, etc., is turned off by control via the first gate terminal 21a. This causes current to flow from the O terminal 17b through the third metal plate 12c, the second TR chip 15a, etc., the second wire 31b, the fourth metal plate 12d, and the N terminal 17c in this order.

[0067] According to the semiconductor device 10a of the present disclosure, the base member 23a is fixed to the P terminal 17a and the O terminal 17b. This allows the positional relationship of the O terminal 17b relative to the P terminal 17a to be adjusted via the base member 23a, thereby easily ensuring insulation between the P terminal 17a and the O terminal 17b. Because the base member 23a is not directly bonded to the first metal plate 12a, the molding member 24a that seals the first TR chip 13a and other components can be easily positioned on the first metal plate 12a, thereby improving insulation between the first metal plate 12a and the first TR chip 13a and other components. In this case, the melting point of the base member 23a is higher than that of the molding member 24a. Therefore, the base member 23a does not melt when the molding member 24a is melted and then hardened to seal the first TR chip 13a and other components and cover the first metal plate 12a. This ensures reliable positioning of components fixed to the base member 23a. As described above, with the semiconductor device 10a, high insulation properties can be easily ensured while miniaturizing the device.

[0068] In this embodiment, the base member has a first intervening portion disposed between the O terminal and the N terminal in a region where the O terminal and the N terminal overlap when viewed in the thickness direction of the first TR chip. Therefore, the first intervening portion of the base member disposed between the O terminal and the N terminal enhances insulation and reduces the risk of the O terminal and the N terminal coming into contact and causing a short circuit. While the first intervening portion is disposed between the O terminal and the N terminal in this embodiment, the first intervening portion may be disposed between the P terminal and the O terminal.

[0069] In this embodiment, the first TR chip has a region between the base member and the first metal plate in the thickness direction where the mold member is disposed. Therefore, the mold member disposed between the first metal plate and the base member can improve insulation from the first metal plate. In this case, the base member and the mold member are both made of a resin material, which can improve adhesion between the base member and the mold member.

[0070] In this embodiment, the semiconductor device includes a third metal plate, a second semiconductor chip electrically connected to the second metal plate, a fourth metal plate connected to the second semiconductor chip via a second conductive member, and a third main terminal electrically connected to the fourth metal plate. The second main terminal is electrically connected to the third metal plate. Therefore, by utilizing the second semiconductor chip, the third metal plate, the fourth metal plate, and the third main terminal, a two-arm configuration can be adopted in the semiconductor device, thereby improving convenience.

[0071] In this embodiment, the base member has a second intervening portion disposed between the P terminal and the N terminal in the region where the P terminal and the N terminal overlap when viewed in the thickness direction of the first TR chip 13a. Therefore, the second intervening portion of the base member disposed between the P terminal and the N terminal improves insulation, thereby reducing the risk of the P terminal and the N terminal coming into contact with each other and causing a short circuit.

[0072] In this embodiment, the semiconductor device includes a first gate terminal that controls the operation of the first TR chip and a first auxiliary source terminal that serves as a reference for the potential of the first gate terminal. The first gate terminal and the first auxiliary source terminal are each held by a base member. The first gate terminal and the first auxiliary source terminal each have regions that protrude from the base member and the molding member. Therefore, the operation of the first TR chip can be precisely controlled using the first gate terminal and the first auxiliary source terminal. In this case, because the first gate terminal and the first auxiliary source terminal each have regions that protrude from the molding member, it is easy to ensure electrical connection between the first gate terminal and the first auxiliary source terminal and the outside of the semiconductor device 10a.

[0073] In this embodiment, the semiconductor device includes a second gate terminal that controls the operation of the second TR chip and a second auxiliary source terminal that serves as a reference for the potential of the second gate terminal. The second gate terminal and the second auxiliary source terminal are each supported by a base member. The second gate terminal and the second auxiliary source terminal each have regions that protrude from the base member and the molding member. Therefore, the second gate terminal and the second auxiliary source terminal can be used to precisely control the operation of the second TR chip. In this case, because the second gate terminal and the second auxiliary source terminal each have regions that protrude from the molding member, it is easy to ensure electrical connection between the second gate terminal and the second auxiliary source terminal and the outside of the semiconductor device 10a.

[0074] In this embodiment, the P terminal, O terminal, first gate terminal, first auxiliary source terminal, second gate terminal, and second auxiliary source terminal each have a tie bar cut surface on its end face. In the thickness direction of the first TR chip, the tie bar cut surfaces of the P terminal, O terminal, first gate terminal, first auxiliary source terminal, second gate terminal, and second auxiliary source terminal are at the same height. Therefore, during manufacturing, when the molds are vertically arranged and assembled and the molten molding material is poured, the mating surfaces of the vertical molds are easily aligned, reducing the risk of the molten material spilling out from the mold joints. This improves productivity.

[0075] In this embodiment, one or more first TR chips are included. The semiconductor device 10a includes a first LF electrically connected to the first gate terminal and electrically connecting the gate electrodes of each of the one or more first TR chips. Therefore, for the one or more first TR chips, the first LF can efficiently control each gate electrode.

[0076] In this embodiment, the semiconductor device 10a includes one or more first TR chips. The semiconductor device 10a includes a second LF electrically connected to the first auxiliary source terminal and electrically connecting the source electrodes of each of the one or more first TR chips. Therefore, for the one or more first TR chips, the second LF can efficiently control the reference of each source electrode.

[0077] In this embodiment, the first LF includes an electronic component, so that the electronic component can suppress excessive load operation of the TR chip electrically connected to the first LF.

[0078] In this embodiment, the first LF and the second LF are disposed on the upper surface of the first metal plate. This allows the size to be reduced in at least one of the X direction and the Y direction. Furthermore, it is possible to easily join the first LF and the second LF to the first metal plate. This allows for improved productivity.

[0079] In this embodiment, the base member includes a positioning mechanism that regulates the positions of the first LF and the second LF relative to the base member. Therefore, by using the positioning mechanism, it is possible to prevent misalignment with the base member during assembly, and insulation can be reliably ensured. Therefore, it is possible to improve the ease of assembly.

[0080] In this embodiment, the base member includes a fitting portion that fits onto the N terminal. This restricts movement of the N terminal fitted to the fitting portion relative to the base member. This reduces the risk of misalignment of the component fitted to the fitting portion relative to the base member during manufacturing, ensuring reliable insulation.

[0081] In this embodiment, the mating portion includes a mating hole provided in the N terminal and a mating pin provided in the base member that protrudes into the member in which the mating hole is provided and fits into the mating hole. Therefore, by fitting the mating pin into the mating hole, the mating state by the mating portion can be more easily achieved.

[0082] In this embodiment, the P terminal, the O terminal, the N terminal, the first gate terminal, the first auxiliary source terminal, the second gate terminal, and the second auxiliary source terminal protrude from the molded member. A base member is disposed at the bases of the P terminal, the O terminal, the N terminal, the first gate terminal, the first auxiliary source terminal, the second gate terminal, and the second auxiliary source terminal. This allows the components protruding from the molded member to easily ensure electrical connection to the outside. Furthermore, because the base member is disposed at the bases of the components protruding from the molded member, even if stress is applied to the components protruding from the molded member in a direction such as bending, the stress can be absorbed by the base member disposed at the base, which has a high melting point and relatively high rigidity.

[0083] In this embodiment, the upper surfaces of the region where the P terminal and the first metal plate are bonded, the region where the O terminal and the second and third metal plates are bonded, the region where the N terminal and the fourth metal plate are bonded, the region where the first LF and the first and second control plates are bonded, the region where the second LF and the first and second control plates are bonded, the region where the first LF and the first and second gate terminals are bonded, and the region where the second LF and the first and second auxiliary source terminals are bonded are only covered with the molding material. With this configuration, the regions where the components overlap can be opened in the thickness direction of the first TR chip before being covered with the molding material during the manufacturing process, facilitating bonding of the components using techniques such as laser welding or ultrasonic bonding. This improves manufacturing efficiency.

[0084] In this embodiment, the following regions are joined by welding: the region where the P terminal and the first metal plate are joined; the region where the O terminal and the second and third metal plates are joined; the region where the N terminal and the fourth metal plate are joined; the region where the first LF and the first and second control plates are joined; the region where the second LF and the first and second control plates are joined; the region where the first LF and the first and second gate terminals are joined; and the region where the second LF and the first and second auxiliary source terminals are joined. This allows the overlapping regions of the components to be more securely fixed while ensuring conductivity. This ensures reliable operation of the semiconductor device and improves reliability.

[0085] In this embodiment, the semiconductor device 10a includes a first insulating substrate disposed on the underside of the first metal plate and the second metal plate, thereby improving the insulation of the semiconductor device 10a. The semiconductor device also includes a second insulating substrate disposed on the underside of the third metal plate and the fourth metal plate.

[0086] In this embodiment, the base member is made of PPS resin or PBT resin. The molding member is made of epoxy resin. The epoxy resin used as the molding member has high insulating properties. Furthermore, by using PPS resin or PBT resin as the base member, the difference in melting point between the base member and the molding member can be more reliably increased, thereby reducing the risk of the molding member melting when the molten, uncured epoxy resin is poured in. Therefore, deformation of the base member can be more reliably suppressed, ensuring high insulating properties. In this embodiment, the base member is made of a thermoplastic resin and the molding member is made of a thermosetting resin. However, this is not a limitation. Both may be made of thermoplastic resins as long as the melting point of the base member is higher than that of the molding member. Furthermore, if a thermosetting resin is used for the base member and is heated and cured once, it will not melt when the thermosetting resin of the molding member is poured in. Therefore, both may be made of thermosetting resins.

[0087] (Other Embodiments) In the above-described embodiments, the first TR chip and the second TR chip are not limited to MOSFETs, but may be IGBTs (Insulated Gate Bipolar Transistors). In this case, this can be achieved by replacing the above-described "source" with "emitter" and "drain" with "collector." The first D chip and the second D chip may be FWDs (Free Wheeling Diodes).

[0088] In the above-described embodiments, the first semiconductor chip may be a TR chip or a D chip connected in anti-parallel to the TR chip. Such a semiconductor chip is effectively used to control the operation of the semiconductor device.

[0089] In the above embodiment, the base member may include a fitting portion that fits with one or more of the P terminal, O terminal, N terminal, first LF, and second LF. This makes it possible to restrict movement of any one of the P terminal, O terminal, N terminal, first LF, and second LF that are fitted with the fitting portion relative to the base member. Therefore, it is possible to reduce the risk of misalignment of the member fitted with the fitting portion relative to the base member during manufacturing.

[0090] In the above-described embodiment, the fitting portion may include a fitting hole provided in one or more of the P terminal, the O terminal, the N terminal, the first LF, and the second LF, and a fitting pin provided in the base member, protruding from the member in which the fitting hole is provided, and fitting into the fitting hole. This makes it possible to more easily achieve a mating state using the fitting portion by fitting the fitting pin into the fitting hole.

[0091] In the above embodiment, the base member may include a positioning mechanism that regulates the position of at least one of the P terminal, the O terminal, the N terminal, the first LF, and the second LF relative to the base member. This makes it possible to suppress misalignment of the P terminal, the O terminal, the N terminal, the first LF, and the second LF relative to the base member during assembly, thereby improving ease of assembly.

[0092] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined not by the above description but by the claims, and it is intended to include all modifications within the meaning and scope of the claims.

[0093] 10a semiconductor device, 11a first insulating substrate, 11b second insulating substrate, 12a first metal plate, 12b second metal plate, 12c third metal plate, 12d fourth metal plate, 12e first control plate, 12f first control reference plate, 12g second control plate, 12h second control reference plate, 13a, 13b, 13c, 13d first transistor chip (first TR chip), 14a, 14b, 14c, 14d first diode chip (first D chip), 15a, 15b, 15c, 15d second transistor chip (second TR chip), 16a, 16b, 16c, 16d second diode chip (second D chip), 17a P terminal, 17b O terminal, 17c N terminal, 18a, 18b metal plates, 19a, 19b openings, 21a first gate terminal, 21b Second gate terminal, 22a: First auxiliary source terminal, 22b: Second auxiliary source terminal, 23a: Base member, 24a: Molding member, 25a: Parting line, 26a, 26b: First lead frame (first LF), 27a, 27b: Second lead frame (second LF), 28a, 28b: Square chip resistor, 29a: Base lead frame (base LF), 31a: First wire, 31b: Second wire, 32a, 32b, 33a, 33b, 34a: Wire, 36a: First interposing portion, 36b: Second interposing portion, 37a: Positioning mechanism, 38a: Protrusion, 39a, 39b: Region, 41a: Fitting portion, 42a: Fitting hole, 43a: Fitting pin.

Claims

1. A semiconductor device comprising: a first metal plate; a first semiconductor chip disposed on the upper surface of the first metal plate and electrically connected to the first metal plate; a second metal plate joined to the first semiconductor chip via a first conductive member; a first main terminal electrically connected to the first metal plate; a second main terminal electrically connected to the second metal plate; a base member made of a resin material, not directly joined to the first metal plate, and fixed to at least one of the first main terminal and the second main terminal; and a mold member made of a resin material different from the base member, disposed to seal the first semiconductor chip and cover the first metal plate, wherein the melting point of the base member is higher than the melting point of the mold member.

2. The semiconductor device according to claim 1, wherein the base member has a first intervening portion disposed between the first main terminal and the second main terminal in a region where the first main terminal and the second main terminal overlap when viewed in the thickness direction of the first semiconductor chip.

3. The semiconductor device according to claim 1 or 2, wherein there is a region where the mold member is disposed between the base member and the first metal plate in the thickness direction of the first semiconductor chip.

4. The semiconductor device according to any one of claims 1 to 3, further comprising: a third metal plate; a second semiconductor chip electrically connected to the second metal plate; a fourth metal plate connected to the second semiconductor chip via a second conductive member; and a third main terminal electrically connected to the fourth metal plate, wherein the second main terminal is electrically connected to the third metal plate.

5. The semiconductor device according to claim 4, wherein the base member has a second intervening portion disposed between the first main terminal and the third main terminal in a region where the first main terminal and the third main terminal overlap when viewed in the thickness direction of the first semiconductor chip.

6. The semiconductor device according to any one of claims 1 to 5, further comprising a first control terminal for controlling the operation of the first semiconductor chip and a first control reference terminal serving as a reference for the potential of the first control terminal, wherein the first control terminal and the first control reference terminal are each held by the base member, and the first control terminal and the first control reference terminal each have a region protruding from the base member and the mold member.

7. The semiconductor device according to claim 4, further comprising a second control terminal for controlling the operation of the second semiconductor chip and a second control reference terminal serving as a reference for the potential of the second control terminal, wherein the second control terminal and the second control reference terminal are each held by the base member, and the second control terminal and the second control reference terminal each have a region protruding from the base member and the mold member.

8. Any two or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal have a tapered cut surface on an end face, and in the thickness direction of the first semiconductor chip, the heights of the tapered cut surfaces of any two or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal are the same. The semiconductor device according to claim 7.

9. The semiconductor device according to any one of claims 1 to 8, wherein the first semiconductor chip is a transistor chip or a diode chip connected in anti-parallel to the transistor chip.

10. The semiconductor device according to claim 9, wherein one or more first semiconductor chips are included, and the semiconductor device further includes a first lead frame that is electrically connected to the first control terminal and electrically connects the gate electrodes of the one or more first semiconductor chips.

11. The semiconductor device according to claim 9, wherein one or more first semiconductor chips are included, and the semiconductor device further includes a second lead frame that is electrically connected to the first control reference terminal and electrically connects the source electrodes of the one or more first semiconductor chips.

12. The semiconductor device according to claim 11, wherein at least one of the first lead frame and the second lead frame includes an electronic component.

13. The semiconductor device according to claim 11, wherein at least one of the first lead frame and the second lead frame is disposed on the upper surface of the first metal plate.

14. The semiconductor device according to claim 11, wherein the base member includes a positioning mechanism that regulates the position of at least any one of the first main terminal, the second main terminal, the third main terminal, the first lead frame, and the second lead frame with respect to the base member.

15. The semiconductor device according to claim 11, wherein the base member includes a fitting portion that fits into any one or more of the first main terminal, the second main terminal, the third main terminal, the first lead frame, and the second lead frame.

16. The semiconductor device according to claim 15, wherein the fitting portion includes a fitting hole provided in any one or more of the first main terminal, the second main terminal, the third main terminal, the first lead frame, and the second lead frame, and a fitting pin provided on the base member and protruding with respect to the member provided with the fitting hole and fitting into the fitting hole.

17. Any one or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal protrude from the mold member, and the base member is disposed at the base of any one or more of the first main terminal, the second main terminal, the third main terminal, the first control terminal, the first control reference terminal, the second control terminal, and the second control reference terminal. The semiconductor device according to claim 8.

18. The upper surface of any one or more of the region where the first main terminal is joined to the first metal plate, the region where the second main terminal is joined to the second metal plate, the region where the first lead frame is joined to the first control terminal, and the region where the second lead frame is joined to the first control reference terminal is covered only by the mold member. The semiconductor device according to claim 11.

19. The semiconductor device according to claim 11, wherein any one or more of the region where the first main terminal is joined to the first metal plate, the region where the second main terminal is joined to the second metal plate, the region where the first lead frame is joined to the first control terminal, and the region where the second lead frame is joined to the first control reference terminal are joined by adhesion or welding with a conductive member.

20. The semiconductor device according to any one of claims 1 to 19, further including an insulating layer disposed on the lower surface side of the first metal plate.

21. The material of the base member is PPS resin or PBT resin, and the material of the mold member is epoxy resin. The semiconductor device according to any one of claims 1 to 20.

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