Semiconductor integrated circuit device

Abstract

An inverter cell (C1) having a logical function is provided with an active region (2P1), an active region (2N1) formed above the active region (2P1), and a power supply wiring (11) formed to a back surface wiring layer. A termination cell (C3) that is disposed on at least one of both ends of a cell row (CR) and that does not have a logical function is provided with an active region (2P3) and an active region (2N3) that is formed above the active region (2P3). In a second direction, ends of the active region (2P1) on a first side and a second side are arranged between ends of the active region (2P3) on the first side and the second side.

Description

semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells (hereinafter, also simply referred to as cells, as appropriate) that include CFETs (Complementary FETs).

[0002] The standard cell method is known as a method for forming a semiconductor integrated circuit on a semiconductor substrate. In this method, basic units (e.g., inverters, latches, flip-flops, full adders, etc.) having specific logic functions are prepared in advance as standard cells, and multiple standard cells are arranged on the semiconductor substrate and connected with wiring to design an LSI chip.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved improved integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched. Nanosheet FETs are one type of three-dimensional transistor that has attracted attention.

[0004] Standard cells include cells with logic functions such as NAND gates and NOR gates (hereinafter referred to as logic cells, as appropriate), as well as cells without logic functions. An example of a cell without logic functions is a "termination cell." A "termination cell" is a cell that does not contribute to the logic function of a circuit block and is used to terminate the circuit block. By placing a termination cell, it is possible to suppress variations in the finished shape of the layout pattern of cells located inside the termination cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0005] Patent Document 1 discloses a termination cell using a CFET (Complementary FET) in which a P-type nanosheet transistor and an N-type nanosheet transistor are stacked on a substrate in order to reduce the area of ​​a semiconductor integrated circuit device.

[0006] A standard cell using a CFET is disclosed in Patent Document 2. In Patent Document 2, wiring is provided on the back surface immediately below the transistor, and the source and drain of the transistor are connected to this wiring.

[0007] International Publication No. 2020 / 170715 U.S. Patent Application Publication No. 2022 / 0123023

[0008] However, regarding termination cells using CFETs, no specific study has yet been made on the layout structure of termination cells in which wiring is provided on the back surface immediately below the transistor.

[0009] The present disclosure aims to provide a layout for a semiconductor integrated circuit device including a termination cell using a CFET, in which wiring is provided on the back side of the transistor.

[0010] In a first aspect of the present disclosure, there is provided a semiconductor device comprising a plurality of cell rows each including a plurality of standard cells arranged side by side in a first direction, wherein a first cell row being one of the plurality of cell rows comprises a first standard cell having a logic function and a second standard cell arranged on at least one of both ends of the first cell row and not having a logic function, wherein the first standard cell comprises: a first active region constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel including a first nanosheet extending in the first direction; a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view, the second active region constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the second nanosheet extending in the first direction as the channel; a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; a second power supply wiring extending in the first direction, and supplying a second power supply voltage different from the first power supply voltage; the second standard cell is formed in a region where a region serving as a source of the first transistor in a first active region overlaps with the first power wiring, and comprises a first via connecting the source of the first transistor in the first active region with the first power wiring, and the second power wiring is connected to the source of the second transistor in the second active region; the second standard cell comprises: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the channel including a third nanosheet extending in the first direction; and a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the channel including a fourth nanosheet extending in the first direction; and in a second direction perpendicular to the first direction and the depth direction, a first end of the third active region which is one side in the second direction perpendicular to the first direction and the depth direction;The first side end and the second side end of the first active region are arranged between the second side end, which is the other side in the second direction.

[0011] According to the present disclosure, the first and second ends of the first active region of the first standard cell having a logic function are arranged between the first and second ends of the third active region of the second standard cell not having a logic function. By arranging the second standard cell at at least one of the two ends of the first cell row, the third active region of the second standard cell can be arranged along the entire side surface in the first direction of the first active region of the first standard cell. Therefore, the distance from the first active region of the first standard cell to the third active region of the second standard cell is set to a predetermined value. This improves the accuracy of estimating the transistor performance of standard cells having a logic function.

[0012] In a second aspect of the present disclosure, a semiconductor device includes a plurality of standard cells arranged side by side in a first direction, and a plurality of cell rows arranged side by side in a second direction perpendicular to the first direction, the plurality of cell rows including a first cell row including first and third standard cells having a logic function, and a second cell row arranged at either end of the plurality of cell rows in the second direction and including a second standard cell having no logic function, the first standard cell constituting a channel, a source, and a drain of a first transistor of a first conductivity type, the channel being formed by a first active region including a first nanosheet extending in the first direction, the first active region being formed above the first active region in a depth direction and overlapping with the first active region in a plan view, the second standard cell constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel being including a second nanosheet extending in the first direction, and a second active region being formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage. a power supply wiring; a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage; and a first via formed in a region in the first active region where a region serving as a source of the first transistor overlaps with the first power supply wiring, connecting the source of the first transistor in the first active region to the first power supply wiring, wherein the second power supply wiring is connected to the source of the first transistor in the first active region; the second standard cell comprising: a third active region formed in the same layer as the first active region in the depth direction, constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the channel including a third nanosheet extending in the first direction; and a fourth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the channel including a fourth nanosheet extending in the first direction; and the third standard cell comprising:a fifth active region formed in the same layer as the first active region, constituting a channel, a source, and a drain of a third transistor of the first conductivity type, the fifth active region including a fifth nanosheet extending in the first direction as the channel; a sixth active region formed in the same layer as the second active region in the depth direction, constituting a channel, a source, and a drain of a fourth transistor of the second conductivity type, the sixth nanosheet extending in the first direction as the channel; and a sixth active region formed in the same layer as the first power supply wiring in the depth direction, extending in the first direction, and connected to the first power supply wiring. a fifth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring; a sixth power supply wiring formed in the same layer as the second power supply wiring in the depth direction, extending in the first direction, and connected to the second power supply wiring; and a third via formed in a region where a region serving as a source of the third transistor in the fifth active region overlaps with the fifth power supply wiring, and connecting the source of the third transistor in the third active region to the fifth power supply wiring, wherein in a plan view, the width of the first active region in the second direction is the same as the width of the third active region in the second direction and is larger than the width of the fifth active region in the second direction.

[0013] According to the present disclosure, in a layout of a semiconductor integrated circuit device including a termination cell using a CFET in which wiring is provided on the back side of the transistor, it is possible to improve the accuracy of estimating the transistor performance of a standard cell having a logic function.

[0014] 10 is a plan view showing an example layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment. 11 is a plan view of portion A1 in FIG. 1. 12 is a cross-sectional view of FIG. 2. 13 is a circuit diagram of an inverter cell. 14 is a plan view of portion A2 in FIG. 1. 15 is a plan view of portion A3 in FIG. 1. 16 is another example configuration of a semiconductor integrated circuit device according to the first embodiment. 17 is a plan view showing another example layout structure of a termination cell C4 according to the first embodiment. 18 is a plan view showing another example layout structure of inverter cells C1, C2 according to the first embodiment. 19 is a plan view showing an example layout of a circuit block included in a semiconductor integrated circuit device according to the second embodiment. 19 is a plan view of portion A4 in FIG. 20. 21 is a plan view of portion A5 in FIG. 21. 22 is a plan view of portion A6 in FIG. 22.

[0015] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells. At least some of the plurality of standard cells include nanosheet FETs, and further include a CFET structure in which transistors of different conductivity types (in the embodiment, the lower part of the cell is P conductivity type and the upper part of the cell is N conductivity type) are stacked.

[0016] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0017] 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a first embodiment. Note that in FIG. 1, only power supply wiring formed in a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed is shown, and other components are omitted.

[0018] 1 is configured by arranging standard cells. In this embodiment, power supply wiring is formed in a BM0 (Backside Metal 0) wiring layer, which is a backside wiring layer provided on the backside of a semiconductor chip on which transistors are formed, and in an M0 wiring layer, which is a metal wiring layer above the transistors.

[0019] In the following description, in plan views such as Figure 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). In the following description, the same symbols refer to the same things, and their explanations may be omitted.

[0020] 1 and other plan views, the solid lines surrounding the cells indicate the cell frames (outer edges of the standard cells). The standard cells are arranged so that the cell frames are in contact with the cell frames of adjacent cells in the X or Y direction.

[0021] 1, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The plurality of cells includes standard cells having logic functions such as NAND gates and NOR gates, and termination cells having no logic functions.

[0022] Here, a "terminal cell" refers to a cell that does not contribute to the logical function of the circuit block and is arranged at the end of the circuit block. Here, the "end of the circuit block" refers to both ends of the cell row that constitutes the circuit block (here, both ends in the X direction), as well as the top and bottom rows of the circuit block (here, both end cell rows in the Y direction). In other words, a "terminal cell" is arranged at the end of the cell row, which is the end of the circuit block, such as both ends in the X direction or both end cell rows in the Y direction. By arranging the terminal cell, it is possible to suppress variation in the finished shape of the layout pattern of the cells located inside the terminal cell, thereby suppressing manufacturing variation in semiconductor integrated circuit devices and improving yield and reliability.

[0023] In the layout of FIG. 1 , a rectangular logic unit LC, which includes logic cells having logic functions and realizes the circuit functions, is arranged in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C1 and C2 are arranged in the logic unit LC. Termination cells C3 and C4 are arranged in the termination cell unit. Specifically, termination cells C3 are arranged on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C4 are arranged in the cell rows CR arranged in the top and bottom rows of the circuit block in the Y direction.

[0024] In each cell, power supply wiring is formed in the center in the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, power supply wiring (power supply wiring 11 described later) that supplies power supply voltage VDD is formed in the BM0 wiring layer, and power supply wiring (power supply wiring 51 described later) that supplies power supply voltage VSS is formed in the M0 wiring layer. Each cell receives the power supply voltages VDD and VSS from the outside via these power supply wirings. That is, in the block layout of FIG. 1, power supply wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of the cell column CR.

[0025] (Configuration of inverter cell C1) Fig. 2 is a plan view of portion A1 in Fig. 1, Fig. 3 is a cross-sectional view in Fig. 2, and Fig. 4 is a circuit diagram configured in the inverter cell. Specifically, Fig. 2(a) shows the lower part of the cell, Fig. 2(b) shows the upper part of the cell, Fig. 3(a) is a cross-section taken along line X1-X1' in Fig. 2, Fig. 3(b) is a cross-section taken along line Y1-Y1' in Fig. 2, and Fig. 3(c) is a cross-section taken along line Y2-Y2' in Fig. 2.

[0026] As shown in FIG. 4, the inverter cell C1 has transistors P1 and N1, and an inverter circuit with an input A and an output Y is configured.

[0027] As shown in FIGS. 1 and 2, the inverter cell C1 is arranged at the left end of the logic section LC in the drawing, and the termination cell C3 is arranged adjacent to it on the left side.

[0028] In the following description, the dashed lines running vertically and horizontally in plan views such as FIG. 2 and the dashed lines running vertically in cross-sectional views such as FIG. 3 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid.

[0029] 2A, a BM0 wiring layer is formed on the back surface of a semiconductor chip on which transistors are formed. In the BM0 wiring layer, a power supply wiring 11 extending in the X direction is formed at the center of the cell in the Y direction of the drawing. The power supply wiring 11 supplies a power supply voltage VDD.

[0030] An active region that forms the channel, source, and drain of the P-type transistor is formed in the P-type transistor region at the bottom of the cell. Specifically, an active region 2P1 is formed in the P-type transistor region. The active region 2P1 overlaps with the power supply wiring 11 in plan view.

[0031] A P-type transistor P1 is formed in the P-type transistor region. The transistor P1 has a channel made of a nanosheet 21 that is made of three overlapping sheets in a planar view and extends in the X direction. In the active region 2P1, the portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in the region where the power supply wiring 11 and the active region 2P1 overlap in a planar view.

[0032] As shown in FIG. 2B, an active region that forms the channel, source, and drain of the N-type transistor is formed in the N-type transistor region in the upper part of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. The active region 2N1 is disposed above the active region 2P1 in the Z direction. The active region 2N1 overlaps with the active region 2P1 in a plan view.

[0033] An N-type transistor N1 is formed in the N-type transistor region. The transistor N1 has, as a channel, a nanosheet 22 having a structure of three overlapping sheets in a plan view and extending in the X direction.

[0034] In the active region, the portions that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0035] A gate wiring 31 is formed in the center of the cell in the X direction of the drawing, extending in the Y direction and extending in the Z direction from the top of the cell to the bottom of the cell. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0036] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0037] 2A, local interconnects (LI) 41 and 42 extending in the Y direction are formed below the cell. The local interconnect 41 is connected to a portion of the active region 2P1 that serves as the source of the transistor P1. The local interconnect 42 is connected to a portion of the active region 2P1 that serves as the drain of the transistor P1.

[0038] 2B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N1 that will become the source of the transistor N1. The local wiring 44 is connected to a portion of the active region 2N1 that will become the drain of the transistor N1.

[0039] In the M0 wiring layer, which is a metal wiring layer above the active region 2N1, a power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. The power supply wiring 51 supplies a power supply voltage VSS. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0040] The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing. The power supply wiring 51 overlaps with the active region 2N1 in plan view. The power supply wiring 51 is connected to a portion of the active region 2N1 that serves as the source of the transistor N1 through a via 62 and a local wiring 43. The via 62 is formed in the region where the power supply wiring 51 and the active region 2N1 overlap in plan view.

[0041] The wiring 52 is disposed on the lower side of the cell in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the gate wiring 31 overlap in a plan view.

[0042] The wiring 53 is arranged on the upper side of the cell in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64 and 65 and local wirings 42 and 44.

[0043] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C1 is a standard cell having a logic function.

[0044] As shown in FIGS. 2A and 2B, the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction in plan view.

[0045] (Configuration of inverter cell C2) Fig. 5 is a plan view of portion A2 in Fig. 1. Specifically, Fig. 5(a) shows the lower part of the cell, and Fig. 5(b) shows the upper part of the cell.

[0046] As shown in FIGS. 1 and 5, the inverter cell C2 is arranged at the left end of the logic section LC in the drawing, and the termination cell C3 is arranged adjacent to it on the left side.

[0047] The inverter cell C2 has a configuration similar to that of the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C2 is a standard cell having a logic function.

[0048] As shown in FIG. 5, the inverter cell C2 is different from the inverter cell C1 shown in FIG. 2 in that active regions 2P2 and 2N2 having different widths in the Y direction are arranged in place of the active regions 2P1 and 2N1.

[0049] Specifically, the active regions 2P2 and 2N2 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C1 is greater than the drive capability of the inverter cell C2.

[0050] 2 and 5, the upper end of the active region 2P2 (2N2) in the Y direction on the drawing is located at the same position in the Y direction as the upper end of the active region 2P1 (2N1) in the Y direction on the drawing. That is, the upper end of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction on the drawing and the upper end of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction on the drawing are aligned in the Y direction.

[0051] (Configuration of Terminating Cell C3) As shown in FIG. 1, the terminating cells C3 are arranged on both the left and right ends of the cell row CR in the X direction.

[0052] 2A and 5A, the BM0 wiring layer is formed with a power supply wiring 11 extending in the X direction and wirings 111 and 112. The power supply wiring 11 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The wirings 111 and 112 are formed at the top and bottom of the power supply wiring 11 in the Y direction in the drawing, respectively.

[0053] An active region 2P3 is formed in the P-type transistor region below the cell. The active region 2P3 overlaps with the power supply wiring 11 in plan view.

[0054] P-type dummy transistors DP1 to DP3 are formed in the active region 2P3. The dummy transistors DP1 to DP3 each have a channel made of three overlapping sheets in a plan view, and have nanosheets 121 to 123 extending in the X direction.

[0055] 2B and 5B, an active region 2N3 is formed in the N-type transistor region in the upper part of the cell. The active region 2N3 overlaps with the active region 2P3 in plan view.

[0056] N-type dummy transistors DN1 to DN3 are formed in the active region 2N3. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 as channels, each of which has a three-sheet structure overlapping in a plan view and extends in the X direction.

[0057] Dummy gate wirings 131 to 133 are formed extending in the Y and Z directions. Nanosheets 121 and 124 overlap with dummy gate wiring 131 in a planar view. Nanosheets 122 and 125 overlap with dummy gate wiring 132 in a planar view. Nanosheets 123 and 126 overlap with dummy gate wiring 133 in a planar view. Dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 132 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 133 corresponds to the gates of dummy transistors DP3 and DN3.

[0058] Dummy gate wirings 134 and 135 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 135 is shared with another cell (inverter cell C1 in FIG. 2 and inverter cell C2 in FIG. 5) arranged on the right side of the drawing.

[0059] As shown in FIGS. 2A and 5A, local interconnections 141 to 144 extending in the Y direction are formed below the cell. Local interconnection 141 is connected to a portion in active region 2P3 that will become the source of dummy transistor DP1. Local interconnection 142 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP1 and a portion in active region 2P3 that will become the source of dummy transistor DP2. Local interconnection 143 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP2 and a portion in active region 2P3 that will become the source of dummy transistor DP3. Local interconnection 144 is connected to a portion in active region 2P3 that will become the drain of dummy transistor DP3.

[0060] As shown in FIGS. 2B and 5B, local interconnections 145 to 148 extending in the Y direction are formed above the cell. Local interconnection 145 is connected to a portion of active region 2N3 that will become the source of dummy transistor DN1. Local interconnection 146 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN1 and a portion of active region 2N3 that will become the source of dummy transistor DN2. Local interconnection 147 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN2 and a portion of active region 2N3 that will become the source of dummy transistor DN3. Local interconnection 148 is connected to a portion of active region 2N3 that will become the drain of dummy transistor DN3.

[0061] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction and wirings 151 and 152. The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The wirings 151 and 152 are formed at the top and bottom of the power supply wiring 51 in the Y direction in the drawing, respectively.

[0062] 2 and 5, unlike the inverter cells C1 and C2, the dummy gate wirings 131 to 135 and the local wirings 141 to 148 are not connected to other wirings. In other words, the termination cell C3 is a standard cell that does not have a logic function.

[0063] 2 and 5, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0064] The local wirings 41, 42, and 141 to 144 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction. The local wirings 43, 44, and 145 to 148 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction.

[0065] The local wirings 41 to 44 and 141 to 148 are arranged so that their upper ends in the Y direction are at the same position on the drawing. The local wirings 41 to 44 and 141 to 148 are arranged so that their lower ends in the Y direction are at the same position on the drawing.

[0066] 2 and 5, inverter cells C1 and C2 having a logic function and a terminal cell C3 having no logic function are arranged in a cell row CR. The terminal cell C3 is arranged at the left end of the cell row CR in the X direction of the drawing. Dummy gate wirings 131-135 of the terminal cell C3 are arranged in the same layer in the Z direction as the gate wiring 31 of the inverter cells C1 and C2. Local wirings 141-144 of the terminal cell C3 are arranged in the same layer in the Z direction as the local wirings 41 and 42 of the inverter cells C1 and C2. Local wirings 145-148 of the terminal cell C3 are arranged in the same layer in the Z direction as the local wirings 43 and 44 of the inverter cells C1 and C2. In other words, by providing dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings including the dummy gate wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the circuit block from the terminal cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0067] Furthermore, the dummy gate wirings 131 to 135 of the terminal cell C3 are formed with the same length Lg in the Y direction as the gate wiring 31 and dummy gate wirings 32 and 33 of the inverter cells C1 and C2, thereby suppressing variations in the finished shape of the layout pattern and suppressing manufacturing variations in the semiconductor integrated circuit device.

[0068] Furthermore, the local wirings 141 to 148 of the terminal cell C3 are arranged so that their upper ends in the Y direction are at the same position as the upper ends in the Y direction of the local wirings 41 to 44 of the inverter cells C1 and C2. The local wirings 141 to 148 of the terminal cell C3 are arranged so that their lower ends in the Y direction are at the same position as the lower ends in the Y direction of the local wirings 41 to 44 of the inverter cells C1 and C2. In other words, the upper and lower ends in the Y direction of the local wirings arranged in the terminal cells are aligned with the upper and lower ends in the Y direction of the local wirings arranged in the cells that constitute the logic unit LC, respectively. This makes it possible to constant the distance from the logic unit LC to the nearest local wiring, thereby improving the performance predictability of the cells arranged in the logic unit LC.

[0069] In addition, the active region 2P3 (2N3) of the termination cell C3 is arranged in the same layer as the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2 in the Z direction, which makes it possible to uniformize the layout pattern of the active regions where the transistors are configured, and suppress manufacturing variations.

[0070] Furthermore, the active regions 2P3 and 2N3 of the termination cell C3 are located close to the dummy gate wiring 32 (135) located at the boundary between the termination cell C3 and the inverter cells C1 and C2. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0071] The Y-direction width of the active region 2P1 (2N1) in the inverter cell C1 and the Y-direction width of the active region 2P3 (2N3) in the termination cell C3 are w1. The Y-direction width of the active region 2P2 (2N2) in the inverter cell C2 is w2, which is smaller than w1. The Y-direction top ends of the active region 2P1 (2N1), the active region 2P2 (2N2), and the active region 2P3 (2N3) are all located at the same position in the Y direction. That is, the Y-direction top ends of the active region 2P1 (2N1) in the inverter cell C1, the active region 2P2 (2N2) in the inverter cell C2, and the active region 2P3 (2N3) in the termination cell C3 are all aligned in the Y direction. By arranging the termination cell C3 adjacent to the inverter cells C1 and C2, each having an active area with a different width in the Y direction, the active area of ​​the termination cell C3 can be positioned along the entire left side of the active area of ​​the inverter cell C1 and the entire left side of the active area of ​​the inverter cell C2. Therefore, the distances from the active area 2P1 (2N1) of the inverter cell C1 and the active area 2P2 (2N2) of the inverter cell C2 to the active area 2P3 (2N3) of the termination cell C3 are set to predetermined values. This improves the accuracy of estimating the transistor performance of the logic cells.

[0072] Although five dummy gate wirings (dummy gate wirings 131 to 135) and eight local wirings (local wirings 141 to 148) are arranged in the termination cell C3, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C3 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C3 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C3 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C3.

[0073] In this embodiment, the active regions of the inverter cells C1, C2, and the termination cell C3 have the same Y-direction width at the top and bottom of the cells, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P3 of the termination cell C3 is the same as the Y-direction width of the active region 2P1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2P2 of the inverter cell C2. Similarly, it is sufficient that the Y-direction width of the active region 2N3 of the termination cell C3 is the same as the Y-direction width of the active region 2N1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2N2 of the inverter cell C2.

[0074] Although the present embodiment has been described with reference to an example in which two inverter cells with different widths of active regions are arranged in a circuit block, three or more inverter cells with different widths of active regions may be arranged in a circuit block. In this case, the width of the active region of the termination cell C3 in the Y direction may be adjusted to the width of the active region with the largest width in the Y direction among the active regions included in the three or more inverter cells.

[0075] (Configuration of Termination Cell C4) Figure 6 is a plan view of portion A3 in Figure 1. Specifically, Figure 6(a) shows the lower part of the cell, and Figure 6(b) shows the upper part of the cell.

[0076] 1, the terminal cell C4 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C1 and C2 arranged at the top end of the logic unit LC in the drawing.

[0077] 6A, the BM0 wiring layer is formed with a power supply wiring 11 and wirings 211 and 212 extending in the X direction. The power supply wiring 11 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The wirings 211 and 212 are formed at the top and bottom of the power supply wiring 11 in the Y direction in the drawing, respectively.

[0078] An active region 2P4 is formed in the P-type transistor region below the cell. The active region 2P4 overlaps with the power supply wiring 11 in plan view.

[0079] P-type dummy transistors DP4 to DP6 are formed in the active region 2P4. The dummy transistors DP4 to DP6 have nanosheets 221 to 223 extending in the X direction.

[0080] 6B, an active region 2N4 is formed in the N-type transistor region in the upper part of the cell. The active region 2N4 overlaps with the active region 2P4 in plan view.

[0081] N-type dummy transistors DN4 to DN6 are formed in the active region 2N4. The dummy transistors DN4 to DN6 have nanosheets 224 to 226 extending in the X direction.

[0082] Dummy gate wirings 231 to 233 are formed extending in the Y and Z directions. Nanosheets 221 and 224 overlap with dummy gate wiring 231 in a planar view. Nanosheets 222 and 225 overlap with dummy gate wiring 232 in a planar view. Nanosheets 223 and 226 overlap with dummy gate wiring 233 in a planar view. Dummy gate wiring 231 corresponds to the gates of dummy transistors DP4 and DN4. Dummy gate wiring 232 corresponds to the gates of dummy transistors DP5 and DN5. Dummy gate wiring 233 corresponds to the gates of dummy transistors DP6 and DN6.

[0083] Dummy gate wiring 234, 235 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 234 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 235 is shared with other cells arranged on the right side of the drawing.

[0084] As shown in FIG. 6A, local wirings 241 to 244 extending in the Y direction are formed below the cell. Local wiring 241 is connected to a portion in the active region 2P4 that will become the source of dummy transistor DP4. Local wiring 242 is connected to a portion in the active region 2P4 that will become the drain of dummy transistor DP4 and a portion in the active region 2P4 that will become the source of dummy transistor DP5. Local wiring 243 is connected to a portion in the active region 2P4 that will become the drain of dummy transistor DP5 and a portion in the active region 2P4 that will become the source of dummy transistor DP6. Local wiring 244 is connected to a portion in the active region 2P4 that will become the drain of dummy transistor DP6.

[0085] As shown in FIG. 6B, local interconnections 245 to 248 extending in the Y direction are formed above the cell. Local interconnection 245 is connected to a portion of active region 2N4 that will become the source of dummy transistor DN4. Local interconnection 246 is connected to a portion of active region 2N4 that will become the drain of dummy transistor DN4 and a portion of active region 2N4 that will become the source of dummy transistor DN5. Local interconnection 247 is connected to a portion of active region 2N4 that will become the drain of dummy transistor DN5 and a portion of active region 2N4 that will become the source of dummy transistor DN6. Local interconnection 248 is connected to a portion of active region 2N4 that will become the drain of dummy transistor DN6.

[0086] The M0 wiring layer is formed with a power supply wiring 51 extending in the X direction and wirings 251 and 252. The power supply wiring 51 is formed in the center of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS. The wirings 251 and 252 are formed at the top and bottom of the power supply wiring 51 in the Y direction in the drawing, respectively.

[0087] 6, unlike the inverter cells C1 and C2, the dummy gate wirings 231 to 235 and the local wirings 241 to 248 are not connected to any other wirings. In other words, the terminal cell C4 is a standard cell that does not have a logic function.

[0088] 6, nanosheets 221 and 224 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C1, respectively, and are arranged in the same layer in the Z direction. Nanosheets 223 and 226 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C2, respectively, and are arranged in the same layer in the Z direction.

[0089] The gate wiring 31 and the dummy gate wirings 32, 33, 231 to 235 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. The dummy gate wirings 231 to 235 are also arranged at the same pitch Pg in the X direction and in the same layer in the Z direction.

[0090] The local wirings 241 to 244 are arranged at the same pitch P1 in the X direction. The local wirings 41, 42, and 241 to 244 are arranged in the same layer in the Z direction. The local wirings 245 to 248 are arranged at the same pitch P1 in the X direction. The local wirings 43, 44, and 245 to 248 are arranged in the same layer in the Z direction.

[0091] The local wirings 241 to 248 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 241 to 248 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0092] In FIG. 6 , a termination cell C4 having no logic function is arranged adjacent to inverter cells C1 and C2 having logic functions in the cell column CR at the top row in the Y direction of the circuit block. The active region 2P4 (2N4) of the termination cell C4 is arranged in the same layer as the active region 2P1 (2N1) of the inverter cell C1 and the active region 2P2 (2N2) of the inverter cell C2. The local wirings 241-244 of the termination cell C4 are arranged in the same layer as the local wirings 41 and 42 of the inverter cells C1 and C2. The local wirings 245-248 of the termination cell C4 are arranged in the same layer as the local wirings 43 and 44 of the inverter cells C1 and C2. In other words, by providing dummy transistors, dummy gate wiring, and local wiring in the termination cell, transistors including dummy transistors, gate wiring including dummy gate wiring, and local wiring are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0093] Furthermore, nanosheets 221 and 224 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C1. Nanosheets 223 and 226 of terminal cell C4 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C2. Dummy gate wirings 231 to 235 of terminal cell C3 are arranged in the same positions in the X direction as gate wiring 31 of inverter cell C1, dummy gate wiring 33 of inverter cell C1 (dummy gate wiring 32 of inverter cell C2), gate wiring 31 of inverter cell C2, dummy gate wiring 32 of inverter cell C1, and dummy gate wiring 33 of inverter cell C2. Local wirings 241, 242, 245, and 246 of terminal cell C4 are arranged in the same positions in the X direction as local wirings 41 to 44 of inverter cell C1. The local interconnects 243, 244, 247, and 248 of the terminal cell C4 are arranged in the same positions in the X direction as the local interconnects 41 to 44 of the inverter cell C2. That is, the terminal cell C4 has dummy transistors, dummy gate interconnects, and local interconnects formed across the entire cell width. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0094] Although five dummy gate wirings (dummy gate wirings 231 to 235) and eight local wirings (local wirings 241 to 248) are arranged in the termination cell C4, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C4 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C4 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C4 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C4.

[0095] In this embodiment, the active regions of the inverter cells C1, C2, and the termination cell C4 have the same Y-direction width at the top and bottom of the cells, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P4 of the termination cell C4 is the same as the Y-direction width of the active region 2P1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2P2 of the inverter cell C2. Similarly, it is sufficient that the Y-direction width of the active region 2N4 of the termination cell C4 is the same as the Y-direction width of the active region 2N1 of the inverter cell C1 and is larger than the Y-direction width of the active region 2N2 of the inverter cell C2.

[0096] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C4 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0097] (Other Configuration Examples) The power supply wiring formed on the back surface side of the transistor described above may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.

[0098] 7A shows another example of the configuration of the semiconductor integrated circuit device according to the first embodiment. The semiconductor integrated circuit device 100 shown in FIG. 7A is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Standard cells including the inverter cells described above are arranged on chip A. Power supply wiring is formed in a wiring layer provided on the surface of chip B. Chip B is attached to the back side of chip A using bumps or the like.

[0099] 7B shows a cross section of this configuration example taken along line Y1-Y1' in FIG. 2. As shown in FIG. 7B, a power supply wiring 11 that supplies VDD is formed in a wiring layer provided on the surface of chip B. Although not shown, in inverter cell C1 (C2), power supply wiring 11 is connected to active region 2P1 (2P2) of chip A through via 61.

[0100] This configuration example also provides the same effects as those of FIG.

[0101] (Modification of Termination Cell C4) Figure 8 is a plan view showing another example of the layout structure of termination cell C4 according to the first embodiment. Specifically, Figure 8(a) shows the lower part of termination cell C4, and Figure 8(b) shows the upper part of termination cell C4. In termination cell C4 of Figure 8, the cell height (width in the Y direction) is twice as large as that of termination cell C4 of Figure 4, and dummy gate wiring, local wiring, wiring, etc. are formed in the upper part of the drawing in the Y direction.

[0102] 8A, the BM0 wiring layer is formed with a power supply wiring 311 extending in the X direction and wirings 312 and 313. The power supply wiring 311 supplies a power supply voltage VDD. The power supply wiring 311 and the wirings 312 and 313 are formed above the power supply wiring 11 and the wirings 211 and 212 in the Y direction in the drawing.

[0103] Dummy gate wirings 331 to 335 are formed extending in the Y and Z directions. The dummy gate wirings 331 to 335 are formed above the dummy gate wirings 231 to 235 in the Y direction in the drawing.

[0104] Local wirings 341 to 344 extending in the Y direction are formed below the cells. The local wirings 341 to 344 are formed above the local wirings 241 to 244 in the Y direction in the drawing.

[0105] 8B, local wirings 345 to 348 extending in the Y direction are formed above the cells. The local wirings 345 to 348 are formed above the local wirings 245 to 248 in the Y direction in the drawing.

[0106] The M0 wiring layer is formed with a power supply wiring 351 extending in the X direction and wirings 352 and 353. The power supply wiring 351 supplies a power supply voltage VSS. The power supply wiring 351 and the wirings 352 and 353 are formed above the power supply wiring 51 and the wirings 251 and 252 in the Y direction in the drawing.

[0107] The termination cell C4 in FIG. 8 is a standard cell that does not have a logic function, similar to the termination cell C4 in FIG.

[0108] 8, the dummy gate wirings 331 to 335 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the dummy gate wirings 331 to 335 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0109] Furthermore, the local wirings 341 to 344 are arranged at the same pitch P1 in the X direction. The local wirings 241 to 244 and 341 to 344 are arranged in the same layer in the Z direction. The local wirings 345 to 348 are arranged at the same pitch P1 in the X direction. The local wirings 245 to 248 and 345 to 348 are arranged in the same layer in the Z direction.

[0110] The local wirings 341 to 348 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 341 to 348 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0111] 8, power supply wiring 311, wiring 312, 313, dummy gate wiring 331 to 335, local wiring 341 to 348, power supply wiring 351, and wiring 352, 353 are formed at the top of the cell in the Y direction in the drawing. That is, power supply wiring 311, wiring 312, 313, dummy gate wiring 331 to 335, local wiring 341 to 348, power supply wiring 351, and wiring 352, 353 are regularly arranged outside the circuit block. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0112] In the terminal cell C4 of FIG. 8 , two power supply wirings (power supply wirings 311 and 351), four wirings (wirings 312, 313, 352, and 353), five dummy gate wirings (dummy gate wirings 331 to 335), and eight local wirings (local wirings 341 to 348) are arranged at the top of the cell in the Y direction of the drawing. However, the number of power supply wirings, wirings, dummy gate wirings, and local wirings is not limited to this. However, the terminal cell C4 is arranged with the number of power supply wirings, wirings, dummy gate wirings, and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the top and bottom of the cell of the terminal cell C4 may differ. Furthermore, the cell width (dimension in the X direction) of the terminal cell C3 may be changed depending on the number of dummy gate wirings and local wirings arranged in the terminal cell C4.

[0113] In addition, in the terminal cell C4 of Figure 8, the power supply wiring (power supply wiring 311, 351), wiring (wiring 312, 313, 352, 353), dummy gate wiring (dummy gate wiring 331 to 335), and local wiring (local wiring 341 to 348) arranged at the top of the cell in the Y direction on the drawing are the same length as the power supply wiring (power supply wiring 11, 51), wiring (wiring 211, 212, 251, 252), dummy gate wiring (dummy gate wiring 231 to 235), and local wiring (local wiring 241 to 248) arranged at the bottom of the cell in the Y direction on the drawing, but this is not limited to this, and the power supply wiring, wiring, dummy gate wiring, and local wiring arranged at the top of the cell in the Y direction on the drawing may be shorter.

[0114] (Modification of Inverter Cell C2) Figure 9 is a plan view showing another example of the layout structure of the inverter cells C1 and C2 according to the first embodiment. Specifically, Figure 9(a) shows the lower part of the inverter cell C1, Figure 9(b) shows the upper part of the inverter cell C1, Figure 9(c) shows the lower part of the inverter cell C2, and Figure 9(d) shows the upper part of the inverter cell C2. In Figure 9, the positions of the active regions 2P2 and 2N2 of the inverter cell C2 in the Y direction are different from those of the inverter cell C1 in Figure 2 and the inverter cell C2 in Figure 5.

[0115] 9, the center of the active region 2P2 (2N2) in the Y direction is located at the same position in the Y direction as the center of the active region 2P1 (2N1) in the Y direction. That is, the center of the active region 2P1 (2N1) of the inverter cell C1 in the Y direction and the center of the active region 2P2 (2N2) of the inverter cell C2 in the Y direction are aligned in the Y direction. This provides the same effects as those in FIGS. 2 and 5.

[0116] In addition, without being limited to the first embodiment and its modified examples, the same effects as those shown in Figures 2 and 5 can be obtained as long as the upper and lower ends of the active region 2P2 (2N2) in the Y direction are positioned between the upper and lower ends of the active region 2P1 (2N1) in the Y direction.

[0117] Second Embodiment (Circuit Block Configuration) Fig. 10 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to a second embodiment. Specifically, Fig. 10 shows the lower part of the cell. Note that Fig. 10 only shows the power supply wiring arranged in the standard cell, and other parts are omitted.

[0118] 10 is configured by arranging standard cells. In this embodiment, the power supply wiring is formed in a BM0 wiring layer, which is a backside wiring layer provided on the backside of the semiconductor chip on which the transistors are formed.

[0119] In the layout of Fig. 10, a plurality of cells arranged in the X direction constitute a cell column CR (six columns in this example). The plurality of cells includes inverter cells C5 and C6 having logic functions and terminal cells C7 and C8. The inverter cells C5 and C6 constitute the inverter circuit of Fig. 4.

[0120] Power supply wiring is formed in the BM0 wiring layer at both ends of each cell in the Y direction, and each cell receives power supply voltages VDD and VSS from the outside via this power supply wiring. Every other cell row CR is arranged inverted in the Y direction. At the boundary between adjacent cell rows CR, the power supply wiring (power supply wiring 11 described later) that supplies the power supply voltage VDD is continuous in the X direction, and the power supply wiring (power supply wiring 12 described later) that supplies the power supply voltage VSS is continuous in the X direction. That is, in the BM0 wiring layer, power supply wiring extending in the X direction is formed, and the power supply wiring that supplies the power supply voltage VDD and the power supply wiring that supplies the power supply voltage VSS are alternately arranged in the Y direction.

[0121] In the layout of Figure 10, similar to the layout of Figure 1, a rectangular logic unit LC that includes logic cells having logic functions and realizes the circuit function is placed in the center of the circuit block. Termination cell units are formed along the outer edges of the circuit block, surrounding this logic unit LC. Inverter cells C5 and C6 are placed in the logic unit LC. Termination cells C7 and C8 are placed in the termination cell unit. Specifically, termination cells C7 are placed on both the left and right ends of each cell row CR in the X direction of the drawing. Termination cells C8 are placed in the cell rows CR placed in the top and bottom rows of the circuit block in the Y direction.

[0122] (Configuration of inverter cell C5) Figure 11 is a plan view of portion A4 in Figure 10. Specifically, Figure 11(a) shows the lower part of the cell, and Figure 11(b) shows the upper part of the cell. Note that inverter cells C5 and C6 each have the inverter circuit of Figure 4 configured therein.

[0123] As shown in FIGS. 10 and 11, the inverter cell C5 is arranged at the left end of the logic section LC in the drawing, and the termination cell C7 is arranged adjacent to it on the left side.

[0124] 11A, the BM0 wiring layer is formed with power supply wirings 11 and 12 extending in the X direction. The power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the lower end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0125] An active region 2P5 is formed in the P-type transistor region at the bottom of the cell. A transistor P1 is formed in the active region 2P5. The transistor P1 has a nanosheet 21. In the active region 2P5, a portion that serves as the source of the transistor P1 is connected to the power supply wiring 11 via a via 61. The via 61 is formed in a region where the power supply wiring 11 and the active region 2P5 overlap in a planar view.

[0126] 11B, an active region 2N5 is formed in the N-type transistor region in the upper part of the cell. The active region 2N5 is arranged higher in the Z direction than the active region 2P5. The active region 2N5 overlaps with the active region 2P5 in plan view.

[0127] The active region 2N5 includes a transistor N1. The transistor N1 includes a nanosheet 22.

[0128] A gate wiring 31 extending in the Y direction is formed in the center of the cell in the X direction in the drawing. The nanosheets 21 and 22 overlap the gate wiring 31 in plan view. The gate wiring 31 corresponds to the gates of the transistors P1 and N1.

[0129] Dummy gate wirings 32 and 33 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 32 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 33 is shared with other cells arranged on the right side of the drawing.

[0130] 11A, local wirings 41 and 42 extending in the Y direction are formed below the cell. The local wiring 41 is connected to a portion of the active region 2P5 that will become the source of the transistor P1. The local wiring 42 is connected to a portion of the active region 2P5 that will become the drain of the transistor P1.

[0131] 11B, local wirings 43 and 44 extending in the Y direction are formed above the cell. The local wiring 43 is connected to a portion of the active region 2N5 that will become the source of the transistor N1. The local wiring 43 is connected to the power supply wiring 12 via a via 62. The via 62 is formed in a region where the power supply wiring 12 and the local wiring 43 overlap in a planar view. That is, the power supply wiring 12 is connected to a portion of the active region 2N5 that will become the source of the transistor N1 via the via 62 and the local wiring 43. The local wiring 44 is connected to a portion of the active region 2N5 that will become the drain of the transistor N1.

[0132] In the M0 wiring layer, wirings 52 and 53 extending in the X direction are formed. The wiring 52 corresponds to the input A, and the wiring 53 corresponds to the output Y.

[0133] The wiring 52 is disposed in the center of the cell in the Y direction in the drawing. The wiring 52 is connected to the gate wiring 31 through a via 63. The via 63 is formed in a region where the wiring 52 and the gate wiring 31 overlap in a plan view.

[0134] The wiring 53 is arranged on the upper side of the cell in the Y direction in the drawing. The wiring 53 is connected to the portion that becomes the drain of the transistor P1 and the portion that becomes the drain of the transistor N1 through vias 64 and 65 and local wirings 42 and 44.

[0135] As described above, the inverter cell C5 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C5 is a standard cell having a logic function.

[0136] As shown in FIGS. 11A and 11B, the active regions 2P5 and 2N5 in the inverter cell C5 have a width of w1 in the Y direction in plan view.

[0137] (Configuration of inverter cell C6) Figure 12 is a plan view of portion A5 in Figure 10. Specifically, Figure 12(a) shows the lower part of the cell, and Figure 12(b) shows the upper part of the cell.

[0138] As shown in FIGS. 10 and 12, the inverter cell C6 is arranged at the left end of the logic section LC in the drawing, and the termination cell C7 is arranged adjacent to it on the left side.

[0139] The inverter cell C6 has a configuration similar to that of the inverter cell C5. Specifically, the inverter cell C6 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with an input A and an output Y. In other words, the inverter cell C6 is a standard cell having a logic function.

[0140] As shown in FIG. 12, the inverter cell C6 is different from the inverter cell C5 shown in FIG. 10 in that active regions 2P6 and 2N6 having different widths in the Y direction are arranged in place of the active regions 2P5 and 2N5.

[0141] Specifically, the active regions 2P6 and 2N6 have a width w2 in the Y direction, which is smaller than w1. That is, the drive capability of the inverter cell C5 is greater than the drive capability of the inverter cell C6.

[0142] 11 and 12, the upper end of the active region 2P5 (2N5) in the Y direction on the drawing is located at the same position in the Y direction as the upper end of the active region 2P6 (2N6) in the Y direction on the drawing. That is, the upper end of the active region 2P5 (2N5) in the Y direction on the drawing of the inverter cell C5 and the upper end of the active region 2P6 (2N6) in the Y direction on the drawing of the inverter cell C6 are aligned in the Y direction.

[0143] (Configuration of Terminating Cell C7) As shown in FIG. 10, the terminating cells C7 are arranged on both the left and right ends of the cell row CR in the X direction.

[0144] 11A and 12A, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. Power supply wiring 11 is formed at the upper end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. Power supply wiring 12 is formed at the lower end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0145] An active region 2P7 is formed in the P-type transistor region below the cell. The active region 2P7 overlaps with the power supply wirings 11 and 12 in plan view.

[0146] Dummy transistors DP1 to DP3 are formed in the active region 2P7. The dummy transistors DP1 to DP3 have nanosheets 121 to 123 extending in the X direction as channels.

[0147] 11B and 12B, an active region 2N7 is formed in the N-type transistor region in the upper part of the cell. The active region 2N7 overlaps with the active region 2P7 in plan view.

[0148] Dummy transistors DN1 to DN3 are formed in the active region 2N7. The dummy transistors DN1 to DN3 have nanosheets 124 to 126 extending in the X direction as channels.

[0149] Dummy gate wirings 131 to 133 are formed extending in the Y and Z directions. Nanosheets 121 and 124 overlap with dummy gate wiring 131 in a planar view. Nanosheets 122 and 125 overlap with dummy gate wiring 132 in a planar view. Nanosheets 123 and 126 overlap with dummy gate wiring 133 in a planar view. Dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1. Dummy gate wiring 132 corresponds to the gates of dummy transistors DP2 and DN2. Dummy gate wiring 133 corresponds to the gates of dummy transistors DP3 and DN3.

[0150] Dummy gate wirings 134 and 135 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 135 is shared with another cell (inverter cell C5 in FIG. 11 and inverter cell C6 in FIG. 12) arranged on the right side of the drawing.

[0151] As shown in FIGS. 11A and 12A, local interconnections 141 to 144 extending in the Y direction are formed below the cell. Local interconnection 141 is connected to a portion in active region 2P7 that will become the source of dummy transistor DP1. Local interconnection 142 is connected to a portion in active region 2P7 that will become the drain of dummy transistor DP1 and a portion in active region 2P7 that will become the source of dummy transistor DP2. Local interconnection 143 is connected to a portion in active region 2P7 that will become the drain of dummy transistor DP2 and a portion in active region 2P7 that will become the source of dummy transistor DP3. Local interconnection 144 is connected to a portion in active region 2P7 that will become the drain of dummy transistor DP3.

[0152] As shown in FIGS. 11B and 12B, local interconnections 145 to 148 extending in the Y direction are formed above the cell. Local interconnection 145 is connected to a portion of active region 2N7 that will become the source of dummy transistor DN1. Local interconnection 146 is connected to a portion of active region 2N7 that will become the drain of dummy transistor DN1 and a portion of active region 2N7 that will become the source of dummy transistor DN2. Local interconnection 147 is connected to a portion of active region 2N7 that will become the drain of dummy transistor DN2 and a portion of active region 2N7 that will become the source of dummy transistor DN3. Local interconnection 148 is connected to a portion of active region 2N7 that will become the drain of dummy transistor DN3.

[0153] The M0 wiring layer is formed with wirings 153 to 156 extending in the X direction. The wirings 153 to 156 are arranged at the same pitch in the Y direction.

[0154] 11 and 12, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. Furthermore, the gate wiring 31 and the dummy gate wirings 32 (135), 131 to 134 are arranged at the same pitch Pg in the X direction and are arranged in the same layer in the Z direction.

[0155] The local wirings 41, 42, and 141 to 144 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction. The local wirings 43, 44, and 145 to 148 are arranged at the same pitch P1 in the X direction and are arranged in the same layer in the Z direction.

[0156] The local wirings 41 to 44 and 141 to 148 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 42 to 44 and 141 to 148 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0157] 11 and 12, inverter cells C5 and C6 having a logic function and a terminal cell C7 having no logic function are arranged in a cell column CR. The terminal cell C7 is arranged at the left end of the cell column CR in the X direction of the drawing. Dummy gate wirings 131-135 of the terminal cell C7 are arranged in the same layer in the Z direction as the gate wiring 31 of the inverter cells C5 and C6. Local wirings 141-144 of the terminal cell C7 are arranged in the same layer in the Z direction as the local wirings 41 and 42 of the inverter cells C5 and C6. Local wirings 145-148 of the terminal cell C7 are arranged in the same layer in the Z direction as the local wirings 43 and 44 of the inverter cells C5 and C6. In other words, by providing dummy gate wirings and local wirings in the terminal cells, the gate wirings and local wirings including the dummy gate wirings are arranged regularly. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the circuit block from the terminal cell, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0158] Furthermore, the dummy gate wirings 131 to 135 of the terminal cell C7 are formed to have the same length Lg in the Y direction as the gate wiring 31 and dummy gate wirings 32 and 33 of the inverter cells C5 and C6, thereby suppressing variations in the finished shape of the layout pattern and suppressing manufacturing variations in the semiconductor integrated circuit device.

[0159] Furthermore, the local wirings 141 to 148 of the terminal cell C7 are arranged so that their upper ends in the Y direction are at the same position as the upper ends in the Y direction of the local wirings 41 to 44 of the inverter cells C5 and C6. The local wirings 141 to 148 of the terminal cell C7 are arranged so that their lower ends in the Y direction are at the same position as the lower ends in the Y direction of the local wirings 42 to 44 of the inverter cells C5 and C6. In other words, the upper and lower ends in the Y direction of the local wirings arranged in the terminal cells are aligned with the upper and lower ends in the Y direction of the local wirings arranged in the cells that constitute the logic unit LC, respectively. This makes it possible to constant the distance from the logic unit LC to the nearest local wiring, thereby improving the performance predictability of the cells arranged in the logic unit LC.

[0160] In addition, the active region 2P7 (2N7) of the termination cell C7 is arranged in the same layer as the active region 2P5 (2N5) of the inverter cell C5 and the active region 2P6 (2N6) of the inverter cell C6 in the Z direction, which makes it possible to standardize the layout pattern of the active regions where the transistors are configured, and suppress manufacturing variations.

[0161] Furthermore, the active regions 2P7 and 2N7 of the termination cell C7 are located close to the dummy gate wiring 32 (135) located at the boundary between the termination cell C7 and the inverter cells C5 and C6. In other words, by providing an active region in the termination cell, the distance from the cell located at the end of the logic unit to the nearest active region can be made constant, thereby improving the performance predictability of the logic unit.

[0162] The Y-direction width of the active region 2P5 (2N5) in the inverter cell C5 and the Y-direction width of the active region 2P7 (2N7) in the termination cell C7 are w1. The Y-direction width of the active region 2P6 (2N6) in the inverter cell C6 is w2, which is smaller than w1. The Y-direction top ends of the active regions 2P5 (2N5), 2P6 (2N6), and 2P7 (2N7) are all located at the same position in the Y-direction. That is, the Y-direction top ends of the active region 2P5 (2N5) in the inverter cell C5, the Y-direction top ends of the active region 2P6 (2N6) in the inverter cell C6, and the Y-direction top ends of the active region 2P7 (2N7) in the termination cell C7 are all aligned in the Y-direction. By arranging the termination cell C7 adjacent to the inverter cells C5 and C6, each having an active area with a different width in the Y direction, the active area of ​​the termination cell C7 can be positioned along the entire left side of the active area of ​​the inverter cell C5 and the entire left side of the active area of ​​the inverter cell C6. Therefore, the distances from the active area 2P5 (2N5) of the inverter cell C5 and the active area 2P6 (2N6) of the inverter cell C6 to the active area 2P7 (2N7) of the termination cell C7 are set to predetermined values. This improves the accuracy of estimating the transistor performance of the logic cells.

[0163] Although five dummy gate wirings (dummy gate wirings 131 to 135) and eight local wirings (local wirings 141 to 148) are arranged in the termination cell C7, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C7 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C7 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C7 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C7.

[0164] In this embodiment, the active regions of the upper and lower parts of the inverter cells C5 and C6 and the termination cell C7 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P7 of the termination cell C7 is the same as the Y-direction width of the active region 2P5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2P6 of the inverter cell C6. Similarly, it is sufficient that the Y-direction width of the active region 2N7 of the termination cell C7 is the same as the Y-direction width of the active region 2N5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2N6 of the inverter cell C6.

[0165] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C7 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0166] (Configuration of Termination Cell C8) Figure 13 is a plan view of portion A6 in Figure 10. Specifically, Figure 13(a) shows the lower part of the cell, and Figure 13(b) shows the upper part of the cell.

[0167] 10, the terminal cell C8 is arranged in the topmost cell row CR in the Y direction of the circuit block, and is arranged adjacent to the upper side of the inverter cells C5 and C6 arranged at the top end of the logic unit LC in the drawing.

[0168] 13A, power supply wirings 11 and 12 extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 11 is formed at the bottom end of the cell in the Y direction in the drawing, and supplies a power supply voltage VDD. The power supply wiring 12 is formed at the top end of the cell in the Y direction in the drawing, and supplies a power supply voltage VSS.

[0169] An active region 2P8 is formed in the P-type transistor region below the cell. The active region 2P8 overlaps with the power supply wirings 11 and 12 in plan view.

[0170] P-type dummy transistors DP4 to DP6 are formed in the active region 2P8. The dummy transistors DP4 to DP6 have nanosheets 221 to 223 extending in the X direction.

[0171] 13B, an active region 2N8 is formed in the N-type transistor region in the upper part of the cell. The active region 2N8 overlaps with the active region 2P8 in plan view.

[0172] N-type dummy transistors DN4 to DN6 are formed in the active region 2N8. The dummy transistors DN4 to DN6 have nanosheets 224 to 226 extending in the X direction.

[0173] Dummy gate wirings 231 to 233 are formed extending in the Y and Z directions. Nanosheets 221 and 224 overlap with dummy gate wiring 231 in a planar view. Nanosheets 222 and 225 overlap with dummy gate wiring 232 in a planar view. Nanosheets 223 and 226 overlap with dummy gate wiring 233 in a planar view. Dummy gate wiring 231 corresponds to the gates of dummy transistors DP4 and DN4. Dummy gate wiring 232 corresponds to the gates of dummy transistors DP5 and DN5. Dummy gate wiring 233 corresponds to the gates of dummy transistors DP6 and DN6.

[0174] Dummy gate wiring 234, 235 extending in the Y and Z directions are formed on both sides of the cell frame in the X direction. The dummy gate wiring 234 is shared with other cells arranged on the left side of the drawing. The dummy gate wiring 235 is shared with other cells arranged on the right side of the drawing.

[0175] As shown in FIG. 13A, local interconnections 241 to 244 extending in the Y direction are formed below the cell. Local interconnection 241 is connected to the portion of active region 2P8 that will become the source of dummy transistor DP4. Local interconnection 242 is connected to the portion of active region 2P8 that will become the drain of dummy transistor DP4 and the portion of active region 2P8 that will become the source of dummy transistor DP5. Local interconnection 243 is connected to the portion of active region 2P8 that will become the drain of dummy transistor DP5 and the portion of active region 2P8 that will become the source of dummy transistor DP6. Local interconnection 244 is connected to the portion of active region 2P8 that will become the drain of dummy transistor DP6.

[0176] As shown in FIG. 13B, local interconnections 245 to 248 extending in the Y direction are formed above the cell. Local interconnection 245 is connected to a portion of active region 2N8 that will become the source of dummy transistor DN4. Local interconnection 246 is connected to a portion of active region 2N8 that will become the drain of dummy transistor DN4 and a portion of active region 2N8 that will become the source of dummy transistor DN5. Local interconnection 247 is connected to a portion of active region 2N8 that will become the drain of dummy transistor DN5 and a portion of active region 2N8 that will become the source of dummy transistor DN6. Local interconnection 248 is connected to a portion of active region 2N8 that will become the drain of dummy transistor DN6.

[0177] The M0 wiring layer is formed with wirings 253 to 256 extending in the X direction. The wirings 253 to 256 are arranged at the same pitch in the Y direction.

[0178] 13, unlike the inverter cells C5 and C6, the dummy gate wirings 231 to 235 and the local wirings 241 to 248 are not connected to any other wirings. In other words, the termination cell C8 is a standard cell that does not have a logic function.

[0179] 13, nanosheets 221 and 224 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C5, respectively, and are arranged in the same layer in the Z direction. Nanosheets 223 and 226 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C6, respectively, and are arranged in the same layer in the Z direction.

[0180] The gate wiring 31 and the dummy gate wirings 32, 33, 231 to 235 are each formed to have the same length Lg in the Y direction and the same width Wg in the X direction. The dummy gate wirings 231 to 235 are also arranged at the same pitch Pg in the X direction and in the same layer in the Z direction.

[0181] The local wirings 241 to 244 are arranged at the same pitch P1 in the X direction. The local wirings 41, 42, and 241 to 244 are arranged in the same layer in the Z direction. The local wirings 245 to 248 are arranged at the same pitch P1 in the X direction. The local wirings 43, 44, and 245 to 248 are arranged in the same layer in the Z direction.

[0182] The local wirings 241 to 248 are arranged so that their upper ends in the Y direction are at the same position in the drawing, and the local wirings 241 to 248 are arranged so that their lower ends in the Y direction are at the same position in the drawing.

[0183] 13, a termination cell C8 having no logic function is arranged adjacent to inverter cells C5 and C6 having logic functions in the cell column CR at the top row in the Y direction of the circuit block. The active region 2P8 (2N8) of the termination cell C8 is arranged in the same layer as the active region 2P5 (2N5) of the inverter cell C5 and the active region 2P6 (2N6) of the inverter cell C6. The local wirings 241-244 of the termination cell C8 are arranged in the same layer as the local wirings 41 and 42 of the inverter cells C5 and C6. The local wirings 245-248 of the termination cell C8 are arranged in the same layer as the local wirings 43 and 44 of the inverter cells C5 and C6. In other words, by providing dummy transistors, dummy gate wiring, and local wiring in the termination cell, transistors including dummy transistors, gate wiring including dummy gate wiring, and local wiring are arranged in a regular pattern. This makes it possible to suppress variations in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices, improving yield and reliability.

[0184] Furthermore, nanosheets 221 and 224 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C5, respectively. Nanosheets 223 and 226 of terminal cell C8 are arranged in the same positions in the X direction as nanosheets 21 and 22 of inverter cell C6, respectively. Dummy gate wirings 231 to 235 of terminal cell C8 are arranged in the same positions in the X direction as gate wiring 31 of inverter cell C5, dummy gate wiring 33 of inverter cell C5 (dummy gate wiring 32 of inverter cell C6), gate wiring 31 of inverter cell C6, dummy gate wiring 32 of inverter cell C5, and dummy gate wiring 33 of inverter cell C6, respectively. Local wirings 241, 242, 245, and 246 of terminal cell C8 are arranged in the same positions in the X direction as local wirings 41 to 44 of inverter cell C5, respectively. The local interconnects 243, 244, 247, and 248 of the terminal cell C8 are arranged in the same positions in the X direction as the local interconnects 41 to 44 of the inverter cell C6. That is, the terminal cell C8 has dummy transistors, dummy gate interconnects, and local interconnects formed across the entire cell width. This makes it possible to suppress variations in the finished shape of the layout patterns of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variations in semiconductor integrated circuit devices and improving yield and reliability.

[0185] Although five dummy gate wirings (dummy gate wirings 231 to 235) and eight local wirings (local wirings 241 to 248) are arranged in the termination cell C8, the number of dummy gate wirings and local wirings is not limited to this. However, the termination cell C8 is arranged with the number of dummy gate wirings and local wirings required to suppress variations in the finished dimensions of the end of the logic unit. Furthermore, the number of local wirings arranged at the cell top and cell bottom of the termination cell C8 may differ. Furthermore, the cell width (dimension in the X direction) of the termination cell C8 may be changed depending on the number of dummy gate wirings and local wirings arranged in the termination cell C8.

[0186] In this embodiment, the active regions of the upper and lower parts of the inverter cells C5 and C6 and the termination cell C8 have the same Y-direction width, but this is not limited to this. In this case, it is sufficient that the Y-direction width of the active region 2P8 of the termination cell C8 is the same as the Y-direction width of the active region 2P5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2P6 of the inverter cell C6. Similarly, it is sufficient that the Y-direction width of the active region 2N8 of the termination cell C8 is the same as the Y-direction width of the active region 2N5 of the inverter cell C5 and is larger than the Y-direction width of the active region 2N6 of the inverter cell C6.

[0187] Although the present embodiment has been described with reference to an example in which two inverter cells with different active region widths are arranged in a circuit block, three or more inverter cells with different active region widths may be arranged in a circuit block. In this case, the width of the active region of the termination cell C8 in the Y direction may be adjusted to the active region with the largest Y direction width among the active regions included in the three or more inverter cells.

[0188] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0189] In addition, in the above-described embodiments and modifications, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0190] Furthermore, in each of the above-described embodiments and variants, a P-type transistor is formed at the bottom of the cell and an N-type transistor is formed at the top of the cell, but this is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor may be formed at the bottom of the cell.

[0191] Furthermore, in each of the above-described embodiments and variants, the standard cells having logic functions are described as inverter cells, but the standard cells having logic functions may also be other cells (NAND, NOR, flip-flops, etc.).

[0192] Furthermore, in each of the above-described embodiments and variants, the power supply wiring 11 formed in the BM0 wiring layer and the power supply wiring 51 formed in the M0 wiring layer are illustrated as having the same wiring width, but the wiring widths of the power supply wiring 11 and 51 may be different.

[0193] In addition, in the above-described embodiments and modifications, the size of the terminal cells C3, C4, C7, and C8 in the X direction is set to four grids, but this is not limitative.

[0194] In the present disclosure, with respect to termination cells using CFETs, it is possible to improve the accuracy of estimating the transistor performance of standard cells having logic functions in the layout of a semiconductor integrated circuit device including termination cells in which wiring is provided on the back side of the transistor.

[0195] 11, 12, 51, 311, 351 Power supply wiring 21, 22, 121 to 126 Nanosheet 31 Gate wiring 32, 33, 131 to 135, 231 to 235, 331 to 335 Dummy gate wiring 111, 112, 151 to 156, 211, 212, 251 to 256, 312, 313, 352, 353 Wiring 41 to 44, 141 to 148, 241 to 248, 341 to 348 Local wiring 61 to 65 Vias 2P1 to 2P6, 2N1 to 2N6 Active area P1, N1 Transistor DP1 to DP3, DN1 to DN3 Dummy transistor C1, C2, C5, C6 Inverter cell C4, C8 Termination cell

Claims

1. A semiconductor device includes a plurality of cell columns each including a plurality of standard cells arranged in a first direction. A first cell column, which is one of the plurality of cell columns, includes a first standard cell having a logic function and a second standard cell arranged at at least one of both ends of the first cell column and having no logic function. The first standard cell includes: a first active region including a first nanosheet extending in the first direction and constituting a channel, a source, and a drain of a first transistor of a first conductivity type; a second active region formed above the first active region in a depth direction, overlapping the first active region in a plan view, and constituting a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type, the channel including a second nanosheet extending in the first direction; a first power supply wiring formed on a back side of the first transistor, extending in the first direction, and supplying a first power supply voltage; a second power supply wiring extending in the first direction and supplying a second power supply voltage different from the first power supply voltage; and a first via formed in a region where a region serving as the source of the first transistor in the first active region overlaps the first power supply wiring and connecting the source of the first transistor in the first active region and the first power supply wiring. The second power supply wiring is connected to the source of the second transistor in the second active region. The second standard cell includes: a third active region formed in the same layer as the first active region in the depth direction and constituting a channel, a source, and a drain of a first dummy transistor of the first conductivity type, the channel including a third nanosheet extending in the first direction; and a fourth active region formed in the same layer as the second active region in the depth direction and constituting a channel, a source, and a drain of a second dummy transistor of the second conductivity type, the channel including a fourth nanosheet extending in the first direction.In a second direction perpendicular to the first direction and the depth direction, between an end portion on a first side, which is one side in the second direction of the third active region, and an end portion on a second side, which is the other side in the second direction, the end portion on the first side and the end portion on the second side of the first active region are arranged in a semiconductor integrated circuit device.

2. The semiconductor integrated circuit device according to claim 1, wherein in the second direction, between the end on the first side and the end on the second side of the fourth active region, the end on the first side and the end on the second side of the second active region are arranged. Semiconductor integrated circuit device.

3. The semiconductor integrated circuit device according to claim 1, wherein the first standard cell further includes a gate wiring that extends in the second direction and the depth direction and serves as the gates of the first and second transistors. The second standard cell further includes a first dummy gate wiring that extends in the second direction and the depth direction and serves as the gates of the first and second dummy transistors. At the boundary between the first standard cell and the second standard cell, a second dummy gate wiring extending in the second direction and the depth direction is provided. The gate wiring, the first dummy gate wiring, and the second dummy gate wiring are arranged at the same pitch in the first direction. Semiconductor integrated circuit device.

4. In the semiconductor integrated circuit device according to claim 1, the first standard cell further includes: a first local wiring extending in the second direction and connected to the source of the first transistor in the first active region; a second local wiring extending in the second direction and connected to the drain of the first transistor in the first active region; a third local wiring extending in the second direction and connected to the source of the second transistor in the second active region; and a fourth local wiring extending in the second direction and connected to the drain of the second transistor in the second active region. The second standard cell further includes: a fifth local wiring extending in the second direction and connected to the source of the first dummy transistor in the third active region; a sixth local wiring extending in the second direction and connected to the drain of the first dummy transistor in the third active region; a seventh local wiring extending in the second direction and connected to the source of the second dummy transistor in the fourth active region; and an eighth local wiring extending in the second direction and connected to the drain of the second dummy transistor in the fourth active region. The first, second, fifth, and sixth local wirings are arranged in the same layer in the depth direction and at the same pitch in the first direction. The third, fourth, seventh, and eighth local wirings are arranged in the same layer in the depth direction and at the same pitch in the first direction. A semiconductor integrated circuit device.

5. In the semiconductor integrated circuit device according to claim 1, the second power supply wiring is formed above the second active region in the depth direction. A semiconductor integrated circuit device.

6. In the semiconductor integrated circuit device according to claim 5, the second standard cell extends in the first direction, is formed in the same layer as the first power supply wiring in the depth direction, and includes a third power supply wiring connected to the first power supply wiring, and further includes a fourth power supply wiring that extends in the first direction, is formed in the same layer as the second power supply wiring in the depth direction, and is connected to the second power supply wiring. Semiconductor integrated circuit device.

7. In the semiconductor integrated circuit device according to claim 1, the second cell row, which is one of the plurality of cell rows, includes a third standard cell having a logic function and the second standard cell disposed at at least one of both ends of the second cell row. The third standard cell is formed in the same layer as the first active region in the depth direction, and constitutes a channel, a source, and a drain of the third transistor of the first conductivity type. As the channel, it includes a fifth active region including a fifth nanosheet extending in the first direction, is formed in the same layer as the second active region in the depth direction, and constitutes a channel, a source, and a drain of the fourth transistor of the second conductivity type. As the channel, it includes a sixth active region including a sixth nanosheet extending in the first direction, includes a fifth power supply wiring that is formed in the same layer as the first power supply wiring in the depth direction and extends in the first direction, and includes a sixth power supply wiring that is formed in the same layer as the second power supply wiring in the depth direction and extends in the first direction. A third via is formed in a region where a region serving as a source of the third transistor in the fifth active region overlaps with the fifth power supply wiring, and connects the source of the third transistor in the third active region to the fifth power supply wiring. In a plan view, the width of the fifth active region in the second direction is smaller than the width of the first active region in the second direction. Semiconductor integrated circuit device.

8. The semiconductor integrated circuit device according to claim 7, wherein in the first cell row, in a plan view, an end portion on the first side of the first active region and an end portion on the first side of the third active region are arranged at the same position in the second direction; and in the second cell row, in a plan view, an end portion on the first side of the third active region and an end portion on the first side of the fifth active region are arranged at the same position in the second direction.

9. The semiconductor integrated circuit device according to claim 7, wherein in the first cell row, in a plan view, a central portion in the second direction of the first active region and a central portion in the second direction of the third active region are arranged at the same position in the second direction; and in the second cell row, in a plan view, a central portion in the second direction of the third active region and a central portion in the second direction of the fifth active region are arranged at the same position in the second direction.

10. The semiconductor integrated circuit device according to claim 1, wherein the first power supply wiring is arranged at an end portion on the first side of the first standard cell; and the second power supply wiring is formed in the same layer as the first power supply wiring in the depth direction and is arranged at an end portion on the second side of the first standard cell.

11. The semiconductor integrated circuit device according to claim 10, wherein the second standard cell further includes a third power supply wiring that extends in the first direction, is formed in the same layer as the first power supply wiring in the depth direction, is arranged at an end portion on the first side of the second standard cell, and is connected to the first power supply wiring; and a fourth power supply wiring that extends in the first direction, is formed in the same layer as the second power supply wiring in the depth direction, is arranged at an end portion on the second side of the second standard cell, and is connected to the second power supply wiring.

12. In the semiconductor integrated circuit device according to claim 10, a second cell row, which is one of the plurality of cell rows, includes a third standard cell having a logic function and the second standard cell disposed at at least one of both ends of the second cell row. The third standard cell is formed in the same layer as the first active region in the depth direction, and constitutes a channel, a source, and a drain of a third transistor of the first conductivity type. As the channel, it includes a fifth active region including a fifth nanosheet extending in the first direction. The third standard cell is formed in the same layer as the second active region in the depth direction, and constitutes a channel, a source, and a drain of a fourth transistor of the second conductivity type. As the channel, it includes a sixth active region including a sixth nanosheet extending in the first direction. The third standard cell is formed in the same layer as the first power supply wiring in the depth direction, and includes a fifth power supply wiring extending in the first direction. The third standard cell is formed in the same layer as the second power supply wiring in the depth direction, and includes a sixth power supply wiring extending in the first direction. A third via that connects a region that becomes a source of the third transistor in the fifth active region and the fifth power supply wiring is formed in a region where the region that becomes the source of the third transistor in the fifth active region and the fifth power supply wiring overlap. In a plan view, a width of the fifth active region in the second direction is smaller than a width of the first active region in the second direction. A semiconductor integrated circuit device.

13. In the semiconductor integrated circuit device according to claim 12, in the first cell row, in a plan view, a central portion of the first active region in the second direction and a central portion of the third active region in the second direction are disposed at the same position in the second direction. In the second cell row, in a plan view, a central portion of the third active region in the second direction and a central portion of the fifth active region in the second direction are disposed at the same position in the second direction. A semiconductor integrated circuit device.

14. Each includes a plurality of standard cells arranged side by side in a first direction, and includes a plurality of cell columns arranged side by side in a second direction perpendicular to the first direction. The plurality of cell columns include a first cell column including first and third standard cells having a logic function, and a second cell column including a second standard cell that is arranged at either one of both ends in the second direction in the plurality of cell columns and does not have a logic function. The first standard cell constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, and as the channel, includes a first active region including a first nanosheet extending in the first direction, is formed above the first active region in the depth direction, has an overlap with the first active region in a plan view, and constitutes a channel, a source, and a drain of a second transistor of a second conductivity type different from the first conductivity type. As the channel, it includes a second active region including a second nanosheet extending in the first direction, is formed on the back side of the first transistor, extends in the first direction, and is a first power supply wiring for supplying a first power supply voltage, extends in the first direction, and is a second power supply wiring for supplying a second power supply voltage different from the first power supply voltage, and is formed in a region where a region serving as a source of the first transistor in the first active region overlaps with the first power supply wiring, and includes a first via for connecting the source of the first transistor in the first active region and the first power supply wiring. The second power supply wiring is connected to the source of the first transistor in the first active region. The second standard cell includes a third active region including a third nanosheet extending in the first direction, which constitutes a channel, a source, and a drain of a first dummy transistor of the first conductivity type and is formed in the same layer as the first active region in the depth direction, and a fourth active region including a fourth nanosheet extending in the first direction, which constitutes a channel, a source, and a drain of a second dummy transistor of the second conductivity type and is formed in the same layer as the second active region in the depth direction.The third standard cell is formed in the same layer as the first active region in the depth direction, and constitutes the channel, source, and drain of the third transistor of the first conductivity type. As the channel, it includes a fifth active region including a fifth nanosheet extending in the first direction. The third standard cell is formed in the same layer as the second active region in the depth direction, and constitutes the channel, source, and drain of the fourth transistor of the second conductivity type. As the channel, it includes a sixth active region including a sixth nanosheet extending in the first direction. The third standard cell is formed in the same layer as the first power supply wiring in the depth direction, extends in the first direction, and is a fifth power supply wiring connected to the first power supply wiring. The third standard cell is formed in the same layer as the second power supply wiring in the depth direction, extends in the first direction, and is a sixth power supply wiring connected to the second power supply wiring. The third standard cell is formed in a region where a region serving as the source of the third transistor in the fifth active region overlaps with the fifth power supply wiring, and includes a third via connecting the source of the third transistor in the third active region and the fifth power supply wiring. In a plan view, a width of the first active region in the second direction is the same as a width of the third active region in the second direction, and is larger than a width of the fifth active region in the second direction. A semiconductor integrated circuit device.

15. The semiconductor integrated circuit device according to claim 14, wherein in a plan view, the width of the second active region in the second direction is the same as the width of the fourth active region in the second direction and is larger than the width of the sixth active region in the second direction.

16. The semiconductor integrated circuit device according to claim 14, wherein the second power supply wiring is formed above the second active region in the depth direction.

17. The semiconductor integrated circuit device according to claim 14, wherein the second standard cell further includes: a first dummy gate wiring extending in the second direction and the depth direction and serving as a gate of the first and second dummy transistors; and a third dummy gate wiring extending in the second direction and the depth direction and disposed on a first side which is one side of the first dummy gate wiring in the second direction.

18. The semiconductor integrated circuit device according to claim 14, wherein the first power supply wiring is disposed at an end portion on a first side which is one side of the first standard cell in the second direction, the second power supply wiring is formed in the same layer as the first power supply wiring in the depth direction, and is disposed at an end portion on a second side which is the other side of the first standard cell in the second direction.

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