Semiconductor device

Abstract

This semiconductor device includes: a first conductivity-type semiconductor layer having a first main surface and a second main surface; a first conductivity-type first pillar region extending in the depth direction of the semiconductor layer from the first main surface to the second main surface in the semiconductor layer; and a second conductivity-type second pillar region adjacent to the first pillar region in the semiconductor layer and extending in the depth direction. In the depth direction, the maximum value of a profile of a first conductivity-type background impurity concentration of the second pillar region is 1 / 2 or less of the maximum value of a profile of a first conductivity-type first impurity concentration of the first pillar region.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-009955 filed with the Japan Patent Office on January 26, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] US Patent Application Publication No. 2015 / 0028351

[0005] [Summary] A semiconductor device according to an embodiment of the present disclosure includes a semiconductor layer of a first conductivity type having a first main surface and a second main surface, a first pillar region of the first conductivity type extending in a depth direction of the semiconductor layer from the first main surface toward the second main surface within the semiconductor layer, and a second pillar region of a second conductivity type adjacent to the first pillar region within the semiconductor layer and extending in the depth direction, wherein, in the depth direction, a maximum value of a profile of a background impurity concentration of the first conductivity type in the second pillar region is equal to or less than half of a maximum value of a profile of a first impurity concentration of the first conductivity type in the first pillar region.

[0006] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example of a chip layout. FIG. 4 is a perspective view showing an example of a chip layout. FIG. 5 is a cross-sectional perspective view showing a main portion of a chip together with a basic configuration of pillar regions. FIG. 6 is a profile showing an example of a concentration gradient in a drift region, a first pillar region, and a second pillar region. FIG. 7 is a profile showing a reference example of a concentration gradient in a drift region, a first pillar region, and a second pillar region. FIG. 8 is a diagram showing a charge balance distribution in the depth direction of a superjunction structure. FIG. 9 is a cross-sectional perspective view showing a pillar region according to a first embodiment. FIG. 10 is a cross-sectional perspective view showing a pillar region according to a second embodiment. FIG. 11 is a cross-sectional perspective view showing a pillar region according to a third embodiment. FIG. 12 is a cross-sectional perspective view showing a pillar region according to a fourth embodiment. FIG. 13 is a cross-sectional perspective view showing a pillar region according to a fifth embodiment. FIG. 14 is a cross-sectional perspective view showing a pillar region according to a sixth embodiment. FIG. 15 is a cross-sectional perspective view showing a pillar region according to a seventh embodiment. FIG. 16 is a cross-sectional perspective view showing a pillar region according to an eighth embodiment. FIG. 17 is a cross-sectional perspective view showing a pillar region according to a ninth embodiment. FIG. 18 is a cross-sectional perspective view showing a pillar region according to a tenth embodiment. FIG. 19 is a cross-sectional perspective view showing a pillar region according to an eleventh embodiment. FIG. 20 is a plan view showing a main part of an active region. FIG. 21 is a cross-sectional perspective view showing a gate structure according to the first embodiment. FIG. 22 is a cross-sectional view showing a main part of a peripheral region. FIG. 23 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 24 is a flowchart showing an example of a method for manufacturing a semiconductor device. FIG. 25A is a cross-sectional perspective view showing an example of a method for manufacturing a semiconductor device. FIG. 25B is a cross-sectional perspective view showing a step after FIG. 25A. FIG. 25C is a cross-sectional perspective view showing a step after FIG. 25B. FIG. 25D is a cross-sectional perspective view showing a step after FIG. 25C. FIG. 26 is a plan view showing a semiconductor device according to a second embodiment. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 26. Fig. 28 is a plan view showing an example of a chip layout. Fig. 29 is a perspective view showing an example of a chip layout. Fig. 30 is a plan view showing a main part of an active region.FIG. 31 is a sectional perspective view showing a gate structure according to a first embodiment. FIG. 32 is a sectional view showing a main part of the peripheral region. FIG. 33 is a sectional perspective view showing a gate structure according to a second embodiment. FIG. 34 is a sectional perspective view showing a gate structure according to a third embodiment. FIG. 35 is a sectional perspective view showing a gate structure according to a fourth embodiment. FIG. 36 is a plan view showing a semiconductor device according to the third embodiment. FIG. 37 is a sectional view taken along line XXXVII-XXXVII shown in FIG. 36. FIG. 38 is a plan view showing an example of a chip layout. FIG. 39 is a perspective view showing an example of a chip layout. FIG. 40 is a sectional perspective view showing a diode structure according to the basic embodiment.

[0007] [Detailed Description] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic views and are not strictly illustrative, and the scale, ratio, angle, etc. are not necessarily the same. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0008] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] FIG. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a chip 2. FIG. 4 is a perspective view showing an example layout of the chip 2. FIG. 5 is a cross-sectional perspective view showing a main portion of the chip 2 together with the basic form of a second pillar region 12.

[0011] 1 to 5, semiconductor device 1A is a SiC semiconductor device in this embodiment. Semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may also be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0013] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0014] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0015] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0017] 5, the chip 2 (first main surface 3 and second main surface 4) has an off angle θoff inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Doff by the off angle θoff. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θoff.

[0018] The off-direction Doff is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0019] The off angle θ is preferably 5° or less. The off angle θ is particularly preferably 2° or more and 4.5° or less. The off angle θ is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θ is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0020] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Doff and off angle θoff described above.

[0021] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0022] The base layer 6 has a base thickness TB. The base thickness TB may be 5 μm or more and 300 μm or less. The base thickness TB may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The base thickness TB is preferably 50 μm or more and 250 μm or less.

[0023] The chip 2 includes a stacked layer 7 stacked on a base layer 6. The stacked layer 7 may be referred to as a "semiconductor layer," "SiC layer," "SiC stacked layer," "semiconductor stacked layer," or the like. In this embodiment, the stacked layer 7 is provided as a layer for forming a superjunction structure SJ. In this embodiment, the stacked layer 7 is formed of a single semiconductor layer, but may be formed of multiple semiconductor layers. When the stacked layer 7 is formed of multiple semiconductor layers, the number of layers is arbitrary and is adjusted appropriately depending on the electrical characteristics to be achieved. Examples of electrical characteristics include a breakdown voltage and a resistance value.

[0024] The stacked portion 7 extends in layers in the horizontal direction and forms part of the first to fourth side surfaces 5A to 5D of the chip 2. The stacked portion 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) grown from the base layer 6 as a starting point.

[0025] The laminate 7 has a lower end and an upper end. The lower end of the laminate 7 is the starting point of crystal growth, and the upper end of the laminate 7 is the end point of crystal growth. Because the laminate 7 is grown continuously from the base layer 6, the lower end of the laminate 7 coincides with the upper end of the base layer 6. The boundary between the base layer 6 and the laminate 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The laminate 7 has an off-direction Doff and an off-angle θoff that are approximately the same as the off-direction Doff and off-angle θoff of the base layer 6.

[0026] The entire stacked layer 7 may be referred to as the drift region 8. The drift region 8 is a region that serves as the base of impurity regions (such as the first pillar region 13, the second pillar region 12, the body region 32, the source region 33, and the contact region 34, which will be described later) that are selectively formed by implanting impurity ions into the stacked layer 7. By implanting n-type impurity ions or p-type impurity ions into the stacked layer 7 to a concentration that exceeds the impurity concentration of the drift region 8, various n-type or p-type impurity regions having characteristics according to the respective concentrations are formed.

[0027] Although the drift region 8 is replaced by various impurity regions in the target region of the stacked layer 7 by ion implantation, the n-type impurity ions added during epitaxial growth of the stacked layer 7 remain at the concentration at the time of growth. As a result, the drift region 8 provides an n-type background concentration within a range that does not impair the characteristics (electrical behavior) of the various impurity regions. On the other hand, even if only a small amount of n-type or p-type impurity ions are implanted into the stacked layer 7, the characteristics of the drift region 8 are maintained in the region, and the drift region 8 remains.

[0028] The n-type impurity concentration of the stacked layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6. １５ cm －３ 1x10 or more １６ cm －３The n-type impurity concentration of the multilayer portion 7 may have the following peak value: The n-type impurity concentration of the multilayer portion 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the multilayer portion 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0029] The stacked layer 7 (drift region 8) has an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the stacked layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. The stacked layer 7 preferably contains a pentavalent element other than phosphorus.

[0030] The n-type impurity concentration of the stacked layer 7 (drift region 8) is preferably adjusted by at least nitrogen. When the stacked layer 7 contains two or more pentavalent elements, the stacked layer 7 preferably contains nitrogen and a pentavalent element other than nitrogen. In this case, the stacked layer 7 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen. In this embodiment, the stacked layer 7 (drift region 8) does not contain phosphorus, but contains nitrogen as a pentavalent element.

[0031] The stacked portion 7 has an epitaxial thickness TE. The epitaxial thickness TE is preferably less than the base thickness TB. The epitaxial thickness TE is preferably 1 μm or more. The epitaxial thickness TE is preferably 5 μm or less. The epitaxial thickness TE may have a value belonging to any one of the following ranges: 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, and 4.5 μm or more to 5 μm or less.

[0032] The semiconductor device 1A includes an active region 10 set in a chip 2. The active region 10 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 10 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 10 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0033] The semiconductor device 1A includes a peripheral region 11 set outside the active region 10 in the chip 2. The peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a plan view. The peripheral region 11 extends in a band shape along the active region 10 in a plan view, and is set in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 10.

[0034] The semiconductor device 1A includes a plurality of p-type second pillar regions 12 formed in the stacked layer 7 in the active region 10. The second pillar regions 12 may also be referred to as "pillar layers," "column layers (regions)," "p-type layers (regions)," "p-type zones," etc. The plurality of second pillar regions 12 are formed at intervals in the horizontal direction within the stacked layer 7, and define a plurality of n-type first pillar regions 13, each of which is made up of a part of the stacked layer 7.

[0035] The multiple second pillar regions 12 are formed by part of the stacked layer 7. The multiple second pillar regions 12 form multiple pn junctions having charge balance together with the multiple first pillar regions 13. As a result, the multiple second pillar regions 12 form a super junction structure SJ together with the multiple first pillar regions 13 within the stacked layer 7. The state of having charge balance means that, with respect to multiple adjacent second pillar regions 12, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the multiple first pillar regions 13.

[0036] The multiple second pillar regions 12 are arranged at intervals in the first direction X within the stack unit 7, and are each formed in a strip shape extending in the second direction Y. That is, the multiple second pillar regions 12 are formed in a stripe shape extending in the second direction Y, and the multiple first pillar regions 13 are formed in a stripe shape extending in the second direction Y. Furthermore, the multiple second pillar regions 12 are arranged at intervals in the m-axis direction of the SiC single crystal, and extend in the a-axis direction of the SiC single crystal. In other words, the extending direction of the multiple second pillar regions 12 coincides with the off-direction Doff of the stack unit 7.

[0037] 5 , the plurality of second pillar regions 12 each have a second lower end 12a on the lower end side of the laminated portion 7 and a second upper end 12b on the upper end side of the laminated portion 7. The second lower end 12a is located in a region on the lower end side of the laminated portion 7 relative to the intermediate portion of the thickness range of the laminated portion 7, and the second upper end 12b is located in a region on the upper end side of the laminated portion 7 relative to the intermediate portion of the thickness range of the laminated portion 7.

[0038] The second lower end 12a may be formed at a distance from the lower end of the laminate 7 toward the upper end, and may face the base layer 6 across a part (lower end) of the laminate 7. The second lower end 12a may be substantially coincident with the lower end of the laminate 7 and connected to the base layer 6.

[0039] The distance between the lower end of laminated portion 7 and second lower end 12a may be 0 μm or more and 2 μm or less. The distance between the lower end of laminated portion 7 and second lower end 12a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0040] The second lower end 12a may have an extension that crosses the boundary between the base layer 6 and the laminated portion 7 and is located within the base layer 6. In this case, the thickness of the extension of the second lower end 12a, based on the upper end of the base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of the extension of the second lower end 12a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0041] The second upper end 12b may be formed at a distance from the upper end of the laminated portion 7 toward the lower end thereof, and may face the upper end of the laminated portion 7 across a part (upper end) of the laminated portion 7. The second upper end 12b may be substantially coincident with the upper end of the laminated portion 7.

[0042] The distance between the upper end of the laminated portion 7 and the second upper end 12b may be 0 μm or more and 1 μm or less. The distance between the upper end of the laminated portion 7 and the second upper end 12b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0043] The plurality of second pillar regions 12 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the second pillar region 12 may have the following peak value. The p-type impurity concentration of the second pillar region 12 is preferably adjusted with at least one trivalent element. In this embodiment, the p-type impurity concentration of the second pillar region 12 is adjusted with aluminum.

[0044] Each of the multiple second pillar regions 12 has a second width W2. The second width W2 is the width in a direction perpendicular to the extension direction of the second pillar regions 12. The second width W2 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the second width W2 may be equal to or greater than the epitaxial thickness TE.

[0045] The second width W2 may be 0.1 μm or more and 10 μm or less. The second width W2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or less The second width W2 may have a value belonging to any one of the following ranges: 5 μm or less, 5 μm or more and 5.5 μm or less, 5.5 μm or more and 6 μm or less, 6 μm or more and 6.5 μm or less, 6.5 μm or more and 7 μm or less, 7 μm or more and 7.5 μm or less, 7.5 μm or more and 8 μm or less, 8 μm or more and 8.5 μm or less, 8.5 μm or more and 9 μm or less, 9 μm or more and 9.5 μm or more and 10 μm or less. The second width W2 is preferably 0.5 μm or more and 1.5 μm or less.

[0046] Each of the second pillar regions 12 has a second thickness T2. The second thickness T2 may also be referred to as the depth of the second pillar regions 12. The second thickness T2 may be less than the epitaxial thickness TE of the stack 7. The second thickness T2 may also be greater than the epitaxial thickness TE. The second thickness T2 may also be approximately equal to the epitaxial thickness TE.

[0047] The second thickness T2 is preferably 1 μm or more. The second thickness T2 is preferably 30 μm or less. The second thickness T2 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, 4.5 μm or more to 5 μm or less, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, and 25 μm or more to 30 μm or less.

[0048] It is preferable that the second width W2 is less than the epitaxial thickness TE of the laminated portion 7, and that the second thickness T2 is greater than the second width W2. In other words, it is preferable that the multiple second pillar regions 12 each have a second aspect ratio T2 / W2 such that they extend in a vertically elongated columnar shape along the thickness direction of the laminated portion 7. The second aspect ratio T2 / W2 is the ratio of the second thickness T2 to the second width W2. In this case, it is particularly preferable that the second thickness T2 is greater than the epitaxial thickness TE. For example, the second aspect ratio T2 / W2 may be greater than 1 and not greater than 100.

[0049] The multiple second pillar regions 12 are formed at intervals of a second pitch P2 in the first direction X. The second pitch P2 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the second pitch P2 may be equal to or greater than the epitaxial thickness TE.

[0050] The second pitch P2 may be 0.1 μm or more and 10 μm or less. The second pitch P2 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more The second pitch P2 may have a value belonging to any one of the ranges of 0.5 μm to 1.5 μm, 5 μm to 5.5 μm, 5.5 μm to 6 μm, 6 μm to 6.5 μm, 6.5 μm to 7 μm, 7 μm to 7.5 μm, 7.5 μm to 8 μm, 8 μm to 8.5 μm, 8.5 μm to 9 μm, 9 μm to 9.5 μm, and 9.5 μm to 10 μm.

[0051] 5 , the plurality of first pillar regions 13 each have a first lower end 13a on the lower end side of the laminated portion 7 and a first upper end 13b on the upper end side of the laminated portion 7. The first lower end 13a is located in a region on the lower end side of the laminated portion 7 relative to the intermediate portion of the thickness range of the laminated portion 7, and the first upper end 13b is located in a region on the upper end side of the laminated portion 7 relative to the intermediate portion of the thickness range of the laminated portion 7.

[0052] The first lower end 13a may be formed at a distance from the lower end of the laminate 7 toward the upper end, and may face the base layer 6 across a part (lower end) of the laminate 7. The first lower end 13a may be substantially coincident with the lower end of the laminate 7 and connected to the base layer 6.

[0053] The distance between the lower end of laminated portion 7 and first lower end 13a may be 0 μm or more and 2 μm or less. The distance between the lower end of laminated portion 7 and first lower end 13a may have a value belonging to any one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0054] First lower end 13a may have an extension that crosses the boundary between base layer 6 and stacked portion 7 and is located within base layer 6. In this case, the thickness of the extension of first lower end 13a, based on the upper end of base layer 6, may be greater than 0 μm and less than 2 μm. The thickness of the extension of first lower end 13a may have a value that belongs to any one of the ranges of greater than 0 μm and less than 0.5 μm, 0.5 μm or more to 1 μm or less, 1 μm or more to 1.5 μm or less, and 1.5 μm or more to 2 μm or less.

[0055] The first upper end 13b may be formed at a distance from the upper end of the laminated portion 7 toward the lower end thereof, and may face the upper end of the laminated portion 7 across a part (upper end) of the laminated portion 7. The first upper end 13b may be substantially coincident with the upper end of the laminated portion 7.

[0056] The distance between the upper end of the laminated portion 7 and the first upper end 13b may be 0 μm or more and 1 μm or less. The distance between the upper end of the laminated portion 7 and the first upper end 13b may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0057] The plurality of first pillar regions 13 are 1×10 １５ cm －３ 1x10 or more １８ cm －３The first pillar region 13 may have the following n-type impurity concentration as a peak value. The n-type impurity concentration is adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the first pillar region 13 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. In this embodiment, the n-type impurity concentration of the first pillar region 13 is adjusted by phosphorus.

[0058] Each of the multiple first pillar regions 13 has a first width W1. The first width W1 is the width in a direction perpendicular to the extension direction of the first pillar regions 13. The first width W1 is preferably the same as the second width W2. Of course, the first width W1 may be wider or narrower than the second width W2. The first width W1 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the first width W1 may be equal to or greater than the epitaxial thickness TE.

[0059] The first width W1 may be 0.1 μm or more and 10 μm or less. The first width W1 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or less The first width W1 may have a value belonging to any one of the following ranges: 5 μm or less, 5 μm or more and 5.5 μm or less, 5.5 μm or more and 6 μm or less, 6 μm or more and 6.5 μm or less, 6.5 μm or more and 7 μm or less, 7 μm or more and 7.5 μm or less, 7.5 μm or more and 8 μm or less, 8 μm or more and 8.5 μm or less, 8.5 μm or more and 9 μm or less, 9 μm or more and 9.5 μm or more and 10 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0060] Each of the first pillar regions 13 has a first thickness T1. The first thickness T1 may also be referred to as the depth of the first pillar regions 13. The first thickness T1 may be less than the epitaxial thickness TE of the stack 7. The first thickness T1 may also be greater than the epitaxial thickness TE. The first thickness T1 may also be approximately equal to the epitaxial thickness TE.

[0061] The first thickness T1 is preferably 1 μm or more. The first thickness T1 is preferably 30 μm or less. The first thickness T1 may have a value belonging to any one of the ranges of 1 μm or more to 1.5 μm or less, 1.5 μm or more to 2 μm or less, 2 μm or more to 2.5 μm or less, 2.5 μm or more to 3 μm or less, 3 μm or more to 3.5 μm or less, 3.5 μm or more to 4 μm or less, 4 μm or more to 4.5 μm or less, 4.5 μm or more to 5 μm or less, 5 μm or more to 10 μm or less, 10 μm or more to 15 μm or less, 15 μm or more to 20 μm or less, 20 μm or more to 25 μm or less, and 25 μm or more to 30 μm or less.

[0062] It is preferable that the first width W1 is less than the epitaxial thickness TE of the stacked portion 7, and that the first thickness T1 is greater than the first width W1. In other words, it is preferable that the multiple first pillar regions 13 each have a first aspect ratio T1 / W1 such that they extend in a vertically elongated columnar shape along the thickness direction of the stacked portion 7. The first aspect ratio T1 / W1 is the ratio of the first thickness T1 to the first width W1. In this case, it is particularly preferable that the first thickness T1 be greater than the epitaxial thickness TE. For example, the first aspect ratio T1 / W1 may be greater than 1 and not greater than 100.

[0063] The multiple first pillar regions 13 are formed at intervals of a first pitch P1 in the first direction X. The first pitch P1 is preferably less than the epitaxial thickness TE of the stacked portion 7. Of course, the first pitch P1 may be equal to or greater than the epitaxial thickness TE.

[0064] The first pitch P1 may be 0.1 μm or more and 10 μm or less. The first pitch P1 may be 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, 4.5 μm or more The first pitch P1 may have a value belonging to any one of the ranges of 0.5 μm to 1.5 μm, 5 μm to 5.5 μm, 5.5 μm to 6 μm, 6 μm to 6.5 μm, 6.5 μm to 7 μm, 7 μm to 7.5 μm, 7.5 μm to 8 μm, 8 μm to 8.5 μm, 8.5 μm to 9 μm, 9 μm to 9.5 μm, and 9.5 μm to 10 μm.

[0065] In this embodiment, the drift region 8 in the active region 10 is wholly or partially replaced by the first pillar region 13 and the second pillar region 12. The drift region 8 may be formed (remain) outside the formation region of the first pillar region 13 and the second pillar region 12 in the active region 10. In order to clarify the basic form of the first pillar region 13 and the second pillar region 12, Figure 5 shows an embodiment in which the drift region 8 is not formed in the active region 10, but is formed only in the peripheral region 11. Although not shown in Figure 5, the drift region 8 may remain in the active region 10.

[0066] Note that the first pillar region 13 may be simply referred to as a drift region because it is an impurity region that maintains the conductivity type of the drift region 8. Considering the concentration difference between the first pillar region 13 and the drift region 8 (the concentration of the first pillar region 13 > the concentration of the drift region 8), the first pillar region 13 may be referred to as a "high-concentration drift region" and the drift region 8 may be referred to as a "low-concentration drift region." Furthermore, considering that the first pillar region 13 is formed in the drift region 8 after the formation of the drift region 8, the drift region 8 may be referred to as a "base drift region" and the first pillar region 13 may be referred to as a "second drift region."

[0067] Hereinafter, the concentration gradient of the impurity concentration in the drift region 8, the first pillar region 13, and the second pillar region 12, as well as the charge balance CB of the superjunction structure SJ will be specifically described with reference to FIGS.

[0068] Fig. 6 is a profile showing an example of the concentration gradient in the drift region 8, the first pillar region 13, and the second pillar region 12. Fig. 7 is a profile showing a reference example of the concentration gradient in the drift region 8 (same concentration as the first pillar region 13) and the second pillar region 12. Fig. 8 is a diagram showing the distribution of charge balance CB in the depth direction of the superjunction structure SJ.

[0069] 6 and 7 , the vertical axis represents the depth of the drift region 8, the first pillar region 13, and the second pillar region 12, with the first main surface 3, the first upper end 13b, and the second upper end 12b as the reference (zero point). In this embodiment, the depth of the first pillar region 13 and the second pillar region 12 are the same as the thickness of the first pillar region 13 and the second pillar region 12, respectively. The horizontal axis represents the n-type impurity concentration of the drift region 8, the n-type impurity concentration of the first pillar region 13, and the p-type impurity concentration of the second pillar region 12.

[0070] 6 and 7 , the concentration profiles of the drift region 8 and the second pillar region 12 are concentration profiles at a central position C2 in the width direction of the second pillar region 12. In other words, the n-type impurity concentration of the drift region 8 here indicates the background concentration (Ndb) of the second pillar region 12 that has replaced the drift region 8. The concentration profile of the first pillar region 13 is a concentration profile at a central position C1 in the width direction of the first pillar region 13.

[0071] 6 , first profiles 20 and 21 indicated by dashed lines are examples of profiles of the n-type impurity concentration in the first pillar region 13. The profile of the n-type impurity concentration in the first pillar region 13 can take various shapes based on the method of adding n-type impurity ions (ion addition during epitaxial growth, ion implantation such as random implantation or channeling implantation), addition conditions (implantation conditions such as dose, implantation temperature, and implantation energy), the relationship between the incident angle (implantation direction) of the n-type impurity ions and the crystal axis of the stacked portion 7, and the like.

[0072] For example, the n-type impurity concentration of the first pillar region 13 may be formed in a generally mountain-like shape having a first peak Pd at a certain depth, as shown in the first profile 20. In this case, the first profile 20 may have a portion (gradual increase portion) in which the n-type impurity concentration gradually increases from the first upper end 13b to the first lower end 13a at a relatively steep increase rate to the first peak Pd, and a portion (gradual decrease portion) in which the impurity concentration gradually decreases at a relatively slow decrease rate, which is formed in a region closer to the first lower end 13a than the first peak Pd.

[0073] The first peak portion Pd is a portion having a peak value (maximum value) of the n-type impurity concentration. The first peak portion Pd is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the n-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).

[0074] Furthermore, the n-type impurity concentration of the first pillar region 13 may not have a specific peak value and may exhibit a first profile 21 that is substantially flat in the depth direction. In this case, the first pillar region 13 may have a constant n-type impurity concentration in the depth direction. Therefore, in the first profile 21, the n-type impurity concentration at an arbitrary depth position may be the maximum value (peak value) of the n-type impurity concentration of the first pillar region 13.

[0075] In this embodiment, the first pillar region 13 is formed by ion implantation into the stacked portion 7 (see FIG. 25C ), and therefore exhibits a concentration gradient depicted by a substantially mountain-shaped first profile 20. Note that the profile of the n-type impurity concentration in the first pillar region 13 may have a shape other than the shapes of the first profiles 20 and 21.

[0076] The first pillar region 13 may have a maximum value (peak value) of n-type impurity concentration higher than the peak value (maximum value) of the n-type impurity concentration of the drift region 8. More specifically, the first pillar region 13 may have a maximum value (peak value) of n-type impurity concentration higher than the peak value (maximum value) of the n-type impurity concentration of the drift region 8. １５ cm －３ 1x10 or more １８ cm －３ When the n-type impurity concentration of the first pillar region 13 exhibits a first profile 20 having a substantially mountain shape, the value of the first peak Pd may be 1×10 １５ cm －３ 1x10 or more １８ cm －３ On the other hand, when the n-type impurity concentration of the first pillar region 13 exhibits a flat first profile 21, the value of the n-type impurity concentration at an arbitrary depth position may be 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following maximum value (peak value).

[0077] 6 , drift profiles 22 and 23 indicated by two-dot chain lines are examples of profiles of n-type impurity concentration in drift region 8. The profile of n-type impurity concentration in drift region 8 can take various shapes based on the method of adding n-type impurity ions (ion addition during epitaxial growth, ion implantation such as random implantation or channeling implantation), addition conditions (implantation conditions such as dose, implantation temperature, and implantation energy), the relationship between the incident angle (implantation direction) of the n-type impurity ions and the crystal axis of stacked portion 7, and the like.

[0078] For example, the n-type impurity concentration of drift region 8 may not have a specific peak value and may exhibit a drift profile 22 that is approximately flat in the depth direction. In this case, drift region 8 may have a constant n-type impurity concentration in the depth direction. Therefore, in drift profile 22, the n-type impurity concentration at any depth position may be the maximum value of the n-type impurity concentration of drift region 8. In this embodiment, drift region 8 is a region that maintains the impurity concentration of stacked portion 7 formed by epitaxial growth (see FIG. 25B ). Therefore, drift region 8 exhibits a concentration gradient depicted by flat drift profile 22.

[0079] Alternatively, drift region 8 may be formed by ion implantation after epitaxial growth of stacked portion 7. In this case, the n-type impurity concentration of drift region 8 may be formed in a generally mountain-like shape having a drift peak Pdb at a certain depth, as shown by drift profile 23. In this case, drift profile 23 may have a portion (gradual increase portion) in which the n-type impurity concentration gradually increases at a relatively steep rate from second upper end 12b to second lower end 12a up to drift peak Pdb, and a portion (gradual decrease portion) in which the impurity concentration gradually decreases at a relatively slower rate in a region closer to second lower end 12a than drift peak Pdb. Note that the profile of the n-type impurity concentration of drift region 8 may have a shape other than the shapes of drift profiles 22 and 23.

[0080] The drift peak portion Pdb is a portion having a peak value (maximum value) of the n-type impurity concentration. The drift peak portion Pdb is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the n-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).

[0081] The drift region 8 may have a maximum value (peak value) of n-type impurity concentration that is lower than the maximum value (peak value) of the n-type impurity concentration of the first pillar region 13. More specifically, the drift region 8 may have a maximum value (peak value) of n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １７ cm －３When the n-type impurity concentration of the drift region 8 exhibits a flat drift profile 22, the value of the n-type impurity concentration at any depth position may be 1×10 １５ cm －３ 1x10 or more １７ cm －３ On the other hand, when the n-type impurity concentration in the drift region 8 shows a drift profile 23 having a substantially mountain shape, the value of the drift peak portion Pdb may be 1×10 １５ cm －３ 1x10 or more １７ cm －３ It may be the following maximum value (peak value).

[0082] The maximum values ​​(peak values) of the drift profiles 22, 23 are equal to or less than half the maximum value (peak value) of the first profile 21 of the first pillar region 13. More preferably, the maximum values ​​(peak values) of the drift profiles 22, 23 are equal to or less than one order of magnitude smaller than the maximum value (peak value) of the first profile 21 of the first pillar region 13. In other words, the maximum values ​​(peak values) of the drift profiles 22, 23 are equal to or less than one tenth the maximum value (peak value) of the first profile 21 of the first pillar region 13.

[0083] 6 , a second profile 24 indicated by a solid line is an example of a profile of the p-type impurity concentration in the second pillar region 12. The profile of the p-type impurity concentration in the second pillar region 12 can take various shapes based on the method of adding p-type impurity ions (ion implantation such as random implantation or channeling implantation), the addition conditions (implantation conditions such as dose, implantation temperature, and implantation energy), the relationship between the incident angle (implantation direction) of the p-type impurity ions and the crystal axis of the stacked portion 7, and the like.

[0084] For example, the p-type impurity concentration of the second pillar region 12 may be formed in a generally mountain-shaped configuration with a second peak Pa at a certain depth, as shown by the second profile 24. In this case, the second profile 24 may have a portion (gradual increase portion) in which the n-type impurity concentration gradually increases from the second upper end 12b to the second lower end 12a at a relatively steep rate of increase up to the second peak Pa, and a portion (gradual decrease portion) formed in a region closer to the second lower end 12a than the second peak Pa, in which the impurity concentration gradually decreases at a relatively slower rate of decrease. In this embodiment, the second pillar region 12 is a region formed by ion implantation into the stack portion 7 after the formation of the stack portion 7 having the opposite conductivity type (n-type in this embodiment) to the second pillar region 12 (see FIG. 25D ). Therefore, the second pillar region 12 exhibits the concentration gradient depicted by the generally mountain-shaped second profile 24.

[0085] The second peak portion Pa is a portion having a peak value (maximum value) of the p-type impurity concentration. The second peak portion Pa is also a main convex concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).

[0086] The maximum value (peak value) of the p-type impurity concentration in the second pillar region 12 is ideally a value calculated based on the dose of p-type impurity ions implanted into the stacked portion 7. More specifically, the second pillar region 12 has a p-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ When the p-type impurity concentration of the second pillar region 12 exhibits a second profile 24 having a substantially mountain shape, the value of the second peak Pa may be 1×10 １５ cm －３ 1x10 or more １８ cm －３ It may be the following maximum value (peak value).

[0087] On the other hand, the second pillar region 12 is formed inside the drift region 8, which is a base region of the opposite conductivity type to the second pillar region 12, and replaces the drift region 8. Therefore, the effective p-type impurity concentration (effective acceptor concentration) of the second pillar region 12 is a value (Na-Ndb) obtained by subtracting the concentration in the drift region 8 as the background concentration Ndb of the second pillar region 12 from the ideal p-type impurity concentration (ideal value Na) of the second pillar region 12.

[0088] 6 , the background concentration Ndb in the second pillar region 12 is a concentration in the drift region 8 that is lower than the concentration Nd in the first pillar region 13. Therefore, the effective p-type impurity concentration (Na−Ndb) in the second pillar region 12 can be made closer to the ideal p-type impurity concentration Na in the second pillar region 12. In other words, since (Na−Ndb)≈Na holds, the profile (effective profile 15) of the effective p-type impurity concentration (Na−Ndb) in the second pillar region 12 can be expressed by a second profile 24 that indicates the ideal p-type impurity concentration Na in the second pillar region 12. As a result, the effective profile 15 (effective p-type profile) of the second pillar region 12 and the first profile 20 (n-type profile) of the first pillar region 13 can be made equal to or closer to each other.

[0089] In the superjunction structure SJ, the closeness of the effective acceptor concentration (Na-Ndb) of the second pillar region 12 and the donor concentration Nd of the first pillar region 13 contributes to stabilizing the charge balance of the superjunction structure SJ. When the donor concentration Nd of the first pillar region 13 is Nd, the width of the first pillar region 13 is W1, the acceptor concentration Na of the second pillar region 12 is Na, and the width of the second pillar region 12 is W2, the charge balance CB between the first pillar region 13 and the second pillar region 12 is expressed by the following formula (1): CB=(Nd×W1) / (Na×W2) (1)

[0090] According to this embodiment, the maximum value of the background concentration Ndb in the second pillar region 12 is the concentration in the drift region 8, which is small. As a result, even if the background concentration Ndb varies in the depth direction of the stacked portion 7, the effect of this variation on the effective acceptor concentration (Na-Ndb) in the second pillar region 12 can be reduced. Therefore, the effective acceptor concentration (Na-Ndb) in the second pillar region 12 can be stabilized to be approximately equal to the acceptor concentration Na in the second pillar region 12. As a result, the effect on the charge balance CB between the first pillar region 13 and the second pillar region 12 can be reduced, thereby suppressing fluctuations in the withstand voltage due to a breakdown in the charge balance CB (charge imbalance). Therefore, the superjunction structure SJ can further improve the withstand voltage performance of the semiconductor device 1A.

[0091] Furthermore, since the effective acceptor concentration (Na−Ndb) of the second pillar region 12 and the donor concentration Nd of the first pillar region 13 are similar to each other, the charge balance CB can be made close to 1. This makes it possible to stabilize the charge balance CB. For example, the effective acceptor concentration (Na−Ndb) of the second pillar region 12 can be set to be 90% or more and 110% or less of the donor concentration Nd of the first pillar region 13.

[0092] Furthermore, the background concentration Ndb in the second pillar region 12 is the concentration in the drift region 8. For example, when the drift region 8 is formed by epitaxial growth, a raw material gas for the drift region 8 is supplied while adding n-type impurity ions during the crystal growth process. Because the impurity distribution in the epitaxial layer (drift region 8) can be easily controlled, for example, the drift impurity concentration (background concentration Ndb) can be made constant or approximately constant in the depth direction of the epitaxial layer.

[0093] This similarly makes the background concentration Ndb constant or nearly constant, effectively reducing the variation in the effective acceptor concentration (Na-Ndb) in the depth direction in the second pillar region 12. As a result, it is possible to further suppress fluctuations in the breakdown voltage due to charge imbalance in the superjunction structure SJ. For example, as shown in FIG. 8 , in the section from the top (first upper end 13b, second upper end 12b) to the bottom (first lower end 13a, second lower end 12a) in the depth direction of the superjunction structure SJ, the charge balance CB can be kept within a range of 0.9 to 1.1, as indicated by the solid line 16.

[0094] Because the charge balance CB is stable, the width W1 of the first pillar region 13 and the width W2 of the second pillar region 12 can be made the same width. As a result, there is no need to narrow or widen only one of the widths of the first pillar region 13 and the second pillar region 12. This allows the superjunction structure SJ to be formed at a high density, further improving the breakdown voltage.

[0095] In contrast, as shown in FIG. 7 , when the background concentration Ndb in the second pillar region 12 is the same or approximately the same as the concentration Nd in the first pillar region 13, the n-type impurities that cancel out the p-type impurities in the second pillar region 12 are greater than in the case of FIG. 6 . For example, this is the case when the profile of the background concentration Ndb is represented by the first profile 20 or the first profile 21 in FIG. 6 . In this case, the p-type impurities in the second pillar region 12 are largely canceled out by the background n-type impurities. As a result, as shown in FIG. 7 , the effective profile 15 shifts to the lower concentration side, and the effective acceptor concentration (Na-Ndb) in the second pillar region 12 and the donor concentration Nd (first profile 20) in the first pillar region 13 diverge. This makes it difficult to ensure charge balance CB.

[0096] Furthermore, if the background concentration Ndb of the second pillar region 12 is provided by an impurity region formed by ion implantation into the stacked layer 7, the background concentration Ndb may vary in the depth direction depending on the ion implantation environment, etc. For example, after epitaxial growth of the stacked layer 7, n-type impurity ions are implanted throughout the stacked layer 7 to replace the drift region 8 with the donor concentration Nd of the first pillar region 13. With ion implantation, it is difficult to achieve a constant impurity concentration in the depth direction of the stacked layer 7. Therefore, even if the second pillar region 12 is formed by implanting p-type impurity ions that exceed the concentration in the first pillar region 13, it is difficult to avoid the effects of variations in the donor concentration Nd. As a result, charge imbalance occurs, and the charge balance CB may vary significantly in the depth direction, as shown by the two-dot chain line 17 in FIG. 8 . The semiconductor device 1A of this embodiment can suppress variations in breakdown voltage due to such charge imbalance.

[0097] 8 to 19, first to eleventh embodiments of the second pillar region 12 will be described below. The second pillar regions 12 may have at least one of the features shown in the first to eleventh embodiments. The second pillar regions 12 may have a feature that combines a plurality (two or more) of the features shown in the first to eleventh embodiments.

[0098] 9 is a cross-sectional perspective view showing the second pillar region 12 according to the first embodiment. Referring to Fig. 9, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the stacked portion 7, and is formed in the stacked portion 7 (drift region 8) at a distance from the upper end of the stacked portion 7. Specifically, the second upper end 12b of the second pillar region 12 is formed at a distance from the upper end (first main surface 3) of the stacked portion 7 toward the lower end, and faces the first main surface 3 with a part (upper end) of the stacked portion 7 in between.

[0099] 10 is a cross-sectional perspective view showing a second pillar region 12 according to the second embodiment. Referring to Fig. 10, the second pillar region 12 has a thickness less than the epitaxial thickness TE of the stacked layer 7, and is formed in the stacked layer 7 (drift region 8) at a distance from the lower end of the stacked layer 7. Specifically, a second lower end 12a of the second pillar region 12 is formed at a distance from the lower end (base layer 6) of the stacked layer 7 toward the upper end, and faces the base layer 6 with a part (lower end) of the stacked layer 7 in between.

[0100] 11 is a cross-sectional perspective view showing a second pillar region 12 according to a third embodiment. Referring to FIG. 11 , the second pillar region 12 has a thickness less than the epitaxial thickness TE of the stacked portion 7 and is formed in the stacked portion 7 (drift region 8) at a distance from both the lower and upper ends of the stacked portion 7. Specifically, the second upper end 12b of the second pillar region 12 is formed at a distance from the upper end (first main surface 3) of the stacked portion 7 toward the lower end and faces the first main surface 3 across a portion (upper end) of the stacked portion 7. Meanwhile, the second lower end 12a of the second pillar region 12 is formed at a distance from the lower end (base layer 6) of the stacked portion 7 toward the upper end and faces the base layer 6 across a portion (lower end) of the stacked portion 7.

[0101] 12 is a cross-sectional perspective view showing a second pillar region 12 according to a fourth embodiment. Referring to Fig. 12, the plurality of second pillar regions 12 each have a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked layer 7. In this embodiment, the first region 18 and the second region 19 are spaced apart from each other in the thickness direction of the stacked layer 7. The first region 18 and the second region 19 may each independently have a concentration gradient of the p-type impurity concentration indicated by the second profile 24 (effective profile 15) shown in Fig. 6 .

[0102] A part of the stacked layer 7 (drift region 8) is interposed between the first region 18 and the second region 19. The part of the drift region 8 provides an n-type intermediate region 25 that physically separates the first region 18 and the second region 19. The intermediate region 25 may be located at the center of the stacked layer 7 in the thickness direction, or at the upper or lower end side relative to the center position.

[0103] 13 is a cross-sectional perspective view showing a second pillar region 12 according to a fifth embodiment. Referring to FIG. 13, each of the multiple second pillar regions 12 has a stacked structure including a first region 18 and a second region 19 in the thickness direction of the stacked layer 7. In this embodiment, the first region 18 and the second region 19 are connected to each other in the thickness direction of the stacked layer 7. The first region 18 and the second region 19 may each independently have a concentration gradient of p-type impurity concentration indicated by the second profile 24 (effective profile 15) shown in FIG. 6. The boundary 26 between the first region 18 and the second region 19 may be located at the center of the thickness direction of the stacked layer 7, or may be located on the upper or lower end side of the center position.

[0104] Fig. 14 is a cross-sectional perspective view showing a second pillar region 12 according to a sixth embodiment. Fig. 15 is a cross-sectional perspective view showing a second pillar region 12 according to a seventh embodiment. With reference to Figs. 14 and 15 , the second pillar region 12 having a second upper end 12b at a position spaced apart from the upper end of the laminated portion 7 may have a laminated structure including a first region 18 and a second region 19.

[0105] Fig. 16 is a cross-sectional perspective view showing a second pillar region 12 according to an eighth embodiment. Fig. 17 is a cross-sectional perspective view showing a second pillar region 12 according to a ninth embodiment. With reference to Figs. 16 and 17 , the second pillar region 12 having a second lower end 12a at a position spaced apart from the lower end of the laminated portion 7 may have a laminated structure including a first region 18 and a second region 19.

[0106] Fig. 18 is a cross-sectional perspective view showing a second pillar region 12 according to a tenth embodiment. Fig. 19 is a cross-sectional perspective view showing a second pillar region 12 according to an eleventh embodiment. With reference to Figs. 18 and 19 , the second pillar region 12 having a second upper end 12b and a second lower end 12a at positions spaced apart from the upper and lower ends of the laminated portion 7, respectively, may have a laminated structure including a first region 18 and a second region 19.

[0107] Below, examples of device structures formed in the active region 10 are shown. FIG. 20 is a plan view showing a main portion of the active region 10. FIG. 21 is a cross-sectional perspective view showing a gate structure 35 according to a first embodiment. FIG. 21 illustrates a second pillar region 12 according to a third embodiment. Of course, FIG. 21 may also apply a configuration in which any one or more of the second pillar regions 12 according to the basic embodiment and the first to eleventh embodiments are applied.

[0108] 20 and 21 , in this embodiment, the semiconductor device 1A includes a metal insulator semiconductor (MIS) structure 31 as an example of a device structure formed in the active region 10. The MIS structure 31 may also be referred to as a "field effect transistor structure."

[0109] The semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10. In this embodiment, the plurality of body regions 32 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the plurality of body regions 32 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. In other words, the extension direction of the plurality of body regions 32 coincides with the off-direction Doff of the SiC single crystal. Furthermore, the extension direction of the plurality of body regions 32 coincides with the extension direction of the plurality of second pillar regions 12.

[0110] The body regions 32 are formed in the surface layer portion of the first main surface 3 so as to overlap the second pillar regions 12 corresponding to them in the stacking direction. Specifically, the body regions 32 overlap the second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0111] When the multiple second pillar regions 12 are formed at intervals from the first main surface 3, the multiple body regions 32 are each formed in a region between the first main surface 3 and the second upper ends 12b (see FIG. 11) of the multiple second pillar regions 12. The multiple body regions 32 are preferably formed on the first main surface 3 side of the intermediate thickness range of the stacked unit 7, and are exposed from the first main surface 3. The multiple body regions 32 are preferably connected to the corresponding second pillar regions 12 (second upper ends 12b).

[0112] The plurality of body regions 32 are each formed wider than the second pillar region 12 directly below them, and are formed at intervals from the adjacent plurality of second pillar regions 12 toward the second pillar region 12 directly below them. The plurality of body regions 32 expose a portion of the first pillar region 13 from a region of the first main surface 3 between the adjacent plurality of second pillar regions 12.

[0113] The plurality of body regions 32 may be, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0114] The p-type impurity concentrations of the plurality of body regions 32 are preferably adjusted by at least one trivalent element. The trivalent element of the body region 32 may be the same as or different from the trivalent element of the second pillar region 12, etc. The trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.

[0115] The semiconductor device 1A includes one or more n-type source regions 33 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. In this embodiment, a plurality of (two in this embodiment) source regions 33 are formed at intervals in the surface layer portion of each body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the first pillar region 13 and the drift region 8 of the stacked portion 7. The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more２１ cm －３ The n-type impurity concentration may have the following peak value:

[0116] The multiple source regions 33 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the multiple source regions 33 may be formed at intervals along the extension direction of the corresponding body region 32. The multiple source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32. The multiple source regions 33, together with the multiple first pillar regions 13, define a channel (current path) along the first main surface 3 at the periphery of the body region 32.

[0117] The semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer portions of the plurality of body regions 32 in the active region 10. The contact regions 34 may also be referred to as "back gate regions." In this embodiment, one contact region 34 is formed in a region between the plurality of adjacent source regions 33 in the surface layer portion of each body region 32.

[0118] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0119] The plurality of contact regions 34 may each extend in a strip shape along the extension direction of the corresponding body region 32. Of course, the plurality of contact regions 34 may also be formed at intervals along the extension direction of the corresponding body region 32. The plurality of contact regions 34 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the peripheral edge of the corresponding body region 32.

[0120] The semiconductor device 1A includes a plurality of planar electrode type gate structures 35 arranged on the first main surface 3 in the active region 10. The gate structures 35 may also be referred to as "planar gate structures." The plurality of gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction. A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.

[0121] In this embodiment, the multiple gate structures 35 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple gate structures 35 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. In other words, the extension direction of the multiple gate structures 35 coincides with the off-direction Doff of the SiC single crystal. Furthermore, the extension direction of the multiple gate structures 35 coincides with the extension direction of the multiple second pillar regions 12.

[0122] The plurality of gate structures 35 are arranged shifted from the plurality of second pillar regions 12 toward the plurality of first pillar regions 13, and overlap the plurality of first pillar regions 13 in a one-to-one correspondence in the stacking direction. In this embodiment, the plurality of gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the plurality of source regions 33 located in one and the other body regions 32.

[0123] Each of the plurality of gate structures 35 has a stacked structure including a gate insulating film 36 disposed on the first main surface 3 and a gate electrode 37 disposed on the gate insulating film 36. The gate insulating film 36 may include a silicon oxide film. The gate electrode 37 may include conductive polysilicon.

[0124] Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the second pillar region 12 in the stacking direction. Of course, either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the second pillar region 12 in the stacking direction.

[0125] The configuration on the peripheral region 11 side will be described below. Fig. 22 is a cross-sectional view showing a main portion of the peripheral region 11. The semiconductor device 1A includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer portion of the first main surface 3 in the peripheral region 11.

[0126] The number of field regions 38 is typically 4 to 8. The field regions 38 are formed in an electrically floating state and relieve the electric field within chip 2 at the periphery of first main surface 3. The number, width, depth, p-type impurity concentration, etc. of field regions 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0127] The multiple field regions 38 are formed at intervals in a region between the periphery of the chip 2 and the active region 10. The multiple field regions 38 are formed in strip shapes extending along the active region 10 in a plan view. Each of the multiple field regions 38 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, the multiple field regions 38 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active region 10 (i.e., the multiple second pillar regions 12) in a plan view.

[0128] The multiple field regions 38 are formed in the stack 7 at intervals from the lower end of the stack 7 (drift region 8) toward the first main surface 3, and each form a p-n junction with the drift region 8. The multiple field regions 38 preferably have bottoms located on the first main surface 3 side of the intermediate portion of the thickness range of the stack 7. In this embodiment, the multiple field regions 38 are formed at intervals from the multiple second pillar regions 12 toward the periphery of the chip 2. Therefore, the multiple field regions 38 do not face the multiple second pillar regions 12 in the stacking direction.

[0129] The bottoms of the plurality of field regions 38 may be located closer to the first main surface 3 than the depth position of the second upper end 12b of the second pillar region 12. Of course, the bottoms of the plurality of field regions 38 may be located closer to the second lower end 12a of the second pillar region 12 than the depth position of the second upper end 12b of the second pillar region 12. In this case, the bottoms of the plurality of field regions 38 are preferably located closer to the first main surface 3 than the intermediate portion of the thickness range of the second pillar region 12.

[0130] The field regions 38 may have a thickness approximately equal to that of the body regions 32. In this case, the field regions 38 may be formed simultaneously with the body regions 32. Of course, the field regions 38 may have a thickness greater than that of the body regions 32. Alternatively, the field regions 38 may have a thickness less than that of the body regions 32.

[0131] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0132] The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentrations of the plurality of body regions 32. Furthermore, the p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentrations of the plurality of body regions 32.

[0133] The p-type impurity concentrations of the multiple field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as the trivalent element in the second pillar regions 12, etc., or may be a different species from the trivalent element in the second pillar regions 12, etc. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0134] The plurality of field regions 38 preferably have a width different from the second width W2 of the second pillar region 12. In other words, the electric field relaxation effect of the plurality of field regions 38 is preferably adjusted separately from the plurality of second pillar regions 12.

[0135] It is particularly preferable that the width of the plurality of field regions 38 be greater than the second width W2 of the second pillar region 12. Of course, the width of the plurality of field regions 38 may be smaller than the second width W2. Alternatively, the width of the plurality of field regions 38 may be approximately equal to the second width W2.

[0136] The field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second pillar regions 12. It is particularly preferable that the pitch of the field regions 38 be larger than the second pitch P2. Of course, the pitch of the field regions 38 may be smaller than the second pitch P2. Alternatively, the pitch of the field regions 38 may be approximately equal to the second pitch P2.

[0137] The semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3. The interlayer insulating film 40 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 40 has a stacked structure including a first insulating film 41 and a second insulating film 42 (see FIG. 22). The first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 include a silicon oxide film made of an oxide of the chip 2 (stacked portion 7).

[0138] The first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11. The first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36. The first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11. In this embodiment, the first insulating film 41 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Of course, the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, with the stacked portion 7 exposed from the periphery of the first main surface 3.

[0139] The second insulating film 42 is stacked on the first insulating film 41. The second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 40 preferably includes a silicon oxide film. The second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11, sandwiching the first insulating film 41 therebetween.

[0140] The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 in the peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the periphery of the first main surface 3. Of course, the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the periphery of the first main surface 3 together with the first insulating film 41.

[0141] The semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (gate electrodes 37) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0142] 1 , the semiconductor device 1A includes a gate pad 45 disposed on an interlayer insulating film 40. The gate pad 45 is an electrode to which a gate potential is applied from the outside. The gate pad 45 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. The gate pad 45 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0143] In this embodiment, the gate pad 45 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The gate pad 45 may be disposed at an interval from the outer periphery region 11 toward the active region 10. In this embodiment, the gate pad 45 is disposed on the periphery of the active region 10 in plan view.

[0144] 1 shows an example in which the gate pad 45 is arranged in a region along the center of the second side surface 5B on the periphery of the active region 10. Of course, the gate pad 45 may also be arranged in a region along the center of any of the first to fourth side surfaces 5A to 5D. Of course, the gate pad 45 may also be arranged at any corner of the active region 10 in a plan view. Also, the gate pad 45 may be arranged in the center of the active region 10 in a plan view. In this embodiment, the gate pad 45 is formed in a quadrangular shape in a plan view.

[0145] The semiconductor device 1A includes at least one gate wiring 46 (multiple in this embodiment) extending from the gate pad 45 onto the interlayer insulating film 40. The gate wiring 46 may also be referred to as a "wiring" or "wiring electrode." The multiple gate wirings 46 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 40 side. In this embodiment, the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0146] The first gate wiring 46A is drawn out from the gate pad 45 toward the first side surface 5A and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35.

[0147] The second gate wiring 46B is drawn out from the gate pad 45 toward the third side surface 5C and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) part (specifically, the other end portions) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end portions of the multiple gate structures 35.

[0148] The semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and the gate wiring 46. The source pad 47 is an electrode to which a source potential is applied from the outside. The source pad 47 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.

[0149] The source pad 47 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10. The source pad 47 may be disposed at an interval from the peripheral region 11 toward the active region 10. In this embodiment, the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view. Of course, the source pad 47 may also be formed in a quadrangular shape in a plan view.

[0150] The source pad 47 penetrates the interlayer insulating film 40 via the plurality of contact openings 43, and is electrically connected to the plurality of body regions 32, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the plurality of second pillar regions 12 via the plurality of body regions 32.

[0151] 2 , the semiconductor device 1A includes a drain pad 48 covering the second main surface 4. The drain pad 48 is an electrode to which a drain potential is applied from the outside. The drain pad 48 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 48 forms an ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the drain pad 48 is electrically connected to the stacked portion 7 (the drift region 8 and the plurality of first pillar regions 13) via the base layer 6.

[0152] The drain pad 48 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 48 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0153] The breakdown voltage that can be applied between source pad 47 and drain pad 48 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0154] 23 is a schematic diagram showing a wafer 50 used in the manufacture of the semiconductor device 1A. The wafer 50 is a substrate of the base layer 6 and contains SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0155] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Doff and the off-angle θoff described above.

[0156] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0157] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 23 shows an orientation flat extending in the m-axis direction in a plan view.

[0158] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a semiconductor device 1A. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0159] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0160] Fig. 24 is a flowchart showing an example of a method for manufacturing the semiconductor device 1A. Fig. 25A to Fig. 25D are cross-sectional perspective views showing an example of a method for manufacturing the semiconductor device 1A. Fig. 25A to Fig. 25D show cross-sectional perspective views of a part of the active region 10 of one device region 55.

[0161] First, referring to FIG. 25A, the above-described wafer 50 preparation step is carried out (step S1 in FIG. 24).

[0162] Next, referring to FIG. 25B , the step of forming the n-type stacked layer 7 is performed (step S2 in FIG. 24 ). The stacked layer 7 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth while adding n-type impurity ions. The impurity ions used are at least one pentavalent element, preferably nitrogen. At this point, the entire stacked layer 7 (active region 10 and peripheral region 11) is formed as the drift region 8. Therefore, the stacked layer 7 may have a concentration gradient of the n-type impurity concentration indicated by the drift profile 22 or drift profile 23 shown in FIG. 6 .

[0163] Next, referring to FIG. 25C , a step of forming a first mask 60 having a predetermined pattern is performed (step S3 in FIG. 24 ). The first mask 60 is preferably an organic mask (resist mask). The first mask 60 is disposed on the first main surface 3 of the stacked layer 7 and has a plurality of first openings 61 that expose regions of the stacked layer 7 where a plurality of first pillar regions 13 are to be formed. The plurality of first openings 61 are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y. In other words, the plurality of first openings 61 have an extension direction that extends along the off-direction Doff in a plan view.

[0164] Next, referring to FIG. 25C , a step of forming a plurality of first pillar regions 13 is performed (step S4 in FIG. 24 ). The step of forming the plurality of first pillar regions 13 includes a step of ion implantation of a pentavalent element (n-type impurity) into the stacked layer 7. The impurity ions used are at least one type of pentavalent element, preferably phosphorus. The ion implantation step can be performed by, for example, random implantation or channeling implantation. At this point, the region of the stacked layer 7 that was covered with the first mask 60 (for example, the region where the second pillar region 12 is to be formed) remains as the drift region 8.

[0165] Next, referring to FIG. 25D , a step of forming a second mask 62 having a predetermined pattern is performed (step S5 in FIG. 24 ). The second mask 62 is preferably an organic mask (resist mask). The second mask 62 is disposed on the first main surface 3 of the stacked layer 7 and has a plurality of second openings 63 that expose regions of the stacked layer 7 where a plurality of second pillar regions 12 are to be formed. The second openings 63 are formed at intervals in the first direction X and are each partitioned into strips extending in the second direction Y. In other words, the second openings 63 have an extension direction that extends along the off direction Doff in a plan view.

[0166] Next, referring to FIG. 25D , a step of forming a plurality of second pillar regions 12 is performed (step S6 in FIG. 24 ). The step of forming the plurality of second pillar regions 12 includes a step of ion implantation of a trivalent element (p-type impurity) into the stacked layer 7. The impurity ions used are at least one type of trivalent element, preferably aluminum. The ion implantation step can be performed by, for example, random implantation, channeling implantation, or the like. As a result, the second pillar regions 12 are formed in the drift region 8 exposed from the second openings 63.

[0167] Thereafter, the MIS structure 31, a plurality of field regions 38, the interlayer insulating film 40, the gate pad 45, the gate wiring 46, the source pad 47, the drain pad 48, etc. are formed (step S7 in FIG. 24). Then, the wafer 50 is cut along a plurality of cutting lines 56. In this way, a plurality of semiconductor devices 1A are manufactured from one wafer 50.

[0168] 25C , the portion of the drift region 8 where the second pillar region 12 is to be formed is covered with the first mask 60. This prevents new n-type impurity ions from being implanted into the drift region 8, thereby maintaining the drift concentration of the drift region 8.

[0169] Furthermore, because the drift region 8 can be protected from irradiation with n-type impurity ions by the first mask 60, it is possible to prevent crystal defects 64 (damage) generated in the first pillar region 13 from being formed in the region where the second pillar region 12 is to be formed. As a result, the second pillar region 12 can be formed by implanting p-type impurity ions into the drift region 8, which is relatively less damaged, and the depth of the second pillar region 12 can be easily controlled.

[0170] Fig. 26 is a plan view showing a semiconductor device 1B according to a second embodiment. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII shown in Fig. 26. Fig. 28 is a plan view showing an example layout of a chip 2. Fig. 29 is a perspective view showing an example layout of a chip 2.

[0171] 26 to 29, semiconductor device 1B includes chip 2, base layer 6, stacked portion 7, active region 10 and peripheral region 11, similar to semiconductor device 1A.

[0172] In this embodiment, the semiconductor device 1B includes an active surface 71, an outer surface 72, and first to fourth connecting surfaces 73A to 73D formed on the first main surface 3. The active surface 71, the outer surface 72, and the first to fourth connecting surfaces 73A to 73D define an active plateau 74 on the first main surface 3.

[0173] The active surface 71 may be referred to as a “first surface portion,” the outer peripheral surface 72 may be referred to as a “second surface portion,” the first to fourth connecting surfaces 73A to 73D may be referred to as “connecting surface portions,” and the active plateau 74 may be referred to as a “mesa portion.” The active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D (i.e., the active plateau 74) may be considered to be components of the chip 2 (first main surface 3).

[0174] The active surface 71 is formed in the active region 10. That is, the active surface 71 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 71 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 71 is formed by the c-plane (Si-plane). In this embodiment, the active surface 71 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0175] The outer peripheral surface 72 is formed in the outer peripheral region 11. In other words, the outer peripheral surface 72 is formed outside the active surface 71. The outer peripheral surface 72 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 71. The outer peripheral surface 72 extends in a band shape along the active surface 71 in a plan view, and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 71.

[0176] The outer peripheral surface 72 has a flat surface extending in the first direction X and the second direction Y, and is formed substantially parallel to the active surface 71. In this embodiment, the outer peripheral surface 72 is formed by the c-plane (Si-plane). The outer peripheral surface 72 is continuous with the first to fourth side surfaces 5A to 5D. The outer peripheral surface 72 has a circumferential depth DO.

[0177] The peripheral depth DO may be 0.1 μm or more and 2 μm or less. The peripheral depth DO may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The peripheral depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0178] The first to fourth connection surfaces 73A to 73D extend in the vertical direction Z and connect the active surface 71 and the outer peripheral surface 72. The first connection surface 73A is located on the first side surface 5A side, the second connection surface 73B is located on the second side surface 5B side, the third connection surface 73C is located on the third side surface 5C side, and the fourth connection surface 73D is located on the fourth side surface 5D side. The first connection surface 73A and the third connection surface 73C extend in the first direction X and face the second direction Y. The second connection surface 73B and the fourth connection surface 73D extend in the second direction Y and face the first direction X.

[0179] The first to fourth connection surfaces 73A to 73D may extend substantially perpendicularly between the active surface 71 and the outer peripheral surface 72 so as to define a quadrangular pillar-shaped active plateau 74. The first to fourth connection surfaces 73A to 73D may be inclined obliquely downward from the active surface 71 toward the outer peripheral surface 72 so as to define a quadrangular pyramidal-shaped active plateau 74. In this way, the active plateau 74 is defined in a protruding shape on the first main surface 3 of the stack portion 7.

[0180] The semiconductor device 1B includes a plurality of p-type second pillar regions 12 formed in the stacked portion 7 in the active region 10. The plurality of second pillar regions 12 are formed in the same layout as in the semiconductor device 1A.

[0181] The second pillar regions 12 may have at least one of the features shown in the basic form and the first to eleventh embodiments. The second pillar regions 12 may have a feature that combines two or more of the features shown in the basic form and the first to eleventh embodiments.

[0182] Fig. 30 is a plan view showing a main part of the active region 10. Fig. 31 is a cross-sectional perspective view showing a gate structure 35 according to the first embodiment. With reference to Figs. 30 and 31, a semiconductor device 1B includes an MIS structure 31 formed in the active region 10. The following configurations will be described as components of the semiconductor device 1B, but they are also components of the MIS structure 31.

[0183] The semiconductor device 1B includes a p-type body region 32 formed in a surface layer portion of the first main surface 3 (active surface 71). In this embodiment, the body region 32 is formed in a layer shape extending along the active surface 71. The body region 32 may be formed over the entire active surface 71 and exposed from the first to fourth connection surfaces 73A to 73D.

[0184] The body region 32 is formed at an interval from the lower end of the stacked portion 7 toward the active surface 71, and overlaps with a plurality of second pillar regions 12 in the stacking direction. The body region 32 preferably overlaps with all of the second pillar regions 12 in the stacking direction. The body region 32 is preferably formed at an interval from the depth position of the outer circumferential surface 72 toward the active surface 71, and is preferably exposed from the first main surface 3.

[0185] When the second pillar regions 12 are formed at intervals from the first main surface 3, the body region 32 is formed in a region between the active surface 71 and the second upper ends 12b (see FIG. 11 ) of the second pillar regions 12. The body region 32 is preferably connected to the second pillar regions 12 (second upper ends 12b).

[0186] The body region 32 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0187] The p-type impurity concentration of the body region 32 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 32 may be the same as or different from the trivalent element of the second pillar region 12, etc. The trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.

[0188] The semiconductor device 1B includes a plurality of trench electrode-type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10. The gate structures 35 may also be referred to as "trench gate structures." A gate potential is applied to the plurality of gate structures 35 as a control potential. The plurality of gate structures 35 control inversion and non-inversion of a channel (current path) in the body region 32 in response to the gate potential.

[0189] The multiple gate structures 35 are arranged at intervals inward from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 in the active region 10. In this embodiment, the multiple gate structures 35 are arranged in stripes extending in the extension direction of the multiple second pillar regions 12. Specifically, in this embodiment, the multiple gate structures 35 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0190] That is, the multiple gate structures 35 are arranged at intervals in the m-axis direction of the SiC single crystal and extend in the a-axis direction of the SiC single crystal. In other words, the extending direction of the multiple gate structures 35 coincides with the off-direction Doff of the SiC single crystal. Furthermore, the extending direction of the multiple gate structures 35 coincides with the extending direction of the multiple second pillar regions 12.

[0191] In this embodiment, the multiple gate structures 35 are arranged shifted from the multiple second pillar regions 12 toward the multiple first pillar regions 13. Specifically, the multiple gate structures 35 penetrate the body region 32 at intervals from the multiple second pillar regions 12, and are arranged in a one-to-one correspondence within the multiple first pillar regions 13. In other words, the multiple gate structures 35 face the multiple second pillar regions 12 in the horizontal direction.

[0192] The multiple gate structures 35 are formed at intervals from the lower ends of the multiple first pillar regions 13 toward the active surface 71, and face the multiple base layers 6 across parts of the multiple first pillar regions 13. The multiple gate structures 35 are preferably formed at intervals from intermediate portions of the thickness ranges of the multiple second pillar regions 12 toward the active surface 71. Of course, the multiple gate structures 35 may also be formed at depth positions that cross the intermediate portions of the thickness ranges of the multiple second pillar regions 12.

[0193] Each gate structure 35 has a trench width WT in the first direction X and a trench depth DT in the vertical direction Z. The trench width WT is less than the second pitch P2. The trench depth DT is less than the second thickness T2 of the second pillar region 12. The trench depth DT is preferably approximately equal to the aforementioned periphery depth DO. Of course, the trench depth DT may be equal to or greater than the periphery depth DO, or may be less than the periphery depth DO.

[0194] The trench width WT may be 0.1 μm or more and 5 μm or less. The trench width WT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0195] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less.

[0196] Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77. The trench 75 is formed in the active surface 71 and defines the wall surface of the gate structure 35. The insulating film 76 covers the wall surface of the trench 75. The insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0197] In this embodiment, the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2. The buried electrode 77 is buried in the trench 75 with the insulating film 76 therebetween and faces the channel with the insulating film 76 therebetween. The buried electrode 77 may include p-type or n-type conductive polysilicon.

[0198] The semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71). The plurality of source regions 33 are formed in a surface layer portion of the body region 32. The plurality of source regions 33 have an n-type impurity concentration higher than the n-type impurity concentrations of the first pillar regions 13 and the drift region 8 of the stacked portion 7. The plurality of source regions 33 have an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0199] The multiple source regions 33 extend in a strip shape along the corresponding gate structures 35 in a plan view. The multiple source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the first pillar regions 13 in the stacking direction, sandwiching a part of the body region 32 therebetween. The multiple source regions 33, together with the multiple first pillar regions 13 located directly below them, define channels (current paths) that extend along the wall surfaces of the corresponding gate structures 35.

[0200] The multiple source regions 33 may face the second pillar region 12 across a part of the body region 32 in the stacking direction. Of course, the multiple source regions 33 may be formed at intervals from the second pillar region 12 to the first pillar region 13 side (gate structure 35 side) so as not to face the second pillar region 12 in the stacking direction.

[0201] The semiconductor device 1B includes a plurality of contact regions 34 formed in regions between the plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71). The plurality of contact regions 34 are formed in a surface layer portion of the body region 32.

[0202] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of second pillar regions 12. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0203] The plurality of contact regions 34 are interposed in regions between the plurality of adjacent source regions 33 and extend in strip shapes along the plurality of gate structures 35. The plurality of contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the plurality of second pillar regions 12 with a part of the body region 32 sandwiched therebetween in the stacking direction.

[0204] The multiple contact regions 34 may face the first pillar region 13 across a part of the body region 32 in the stacking direction. Of course, the multiple contact regions 34 may be formed at intervals from the first pillar region 13 toward the second pillar region 12 so as not to face the first pillar region 13 in the stacking direction.

[0205] The configuration on the side of peripheral region 11 will be described below. Fig. 32 is a cross-sectional view showing a main portion of peripheral region 11. Referring to Fig. 32, semiconductor device 1B includes a p-type well region 78 formed in a surface layer portion of peripheral surface 72. Well region 78 is formed at an interval from the periphery of peripheral surface 72 (first to fourth side surfaces 5A to 5D) toward active surface 71 in a plan view, and extends in a band shape along active surface 71.

[0206] In this embodiment, the well region 78 is formed in a ring shape (specifically, a rectangular ring shape) surrounding the active surface 71 in a plan view. The well region 78 is drawn out from the surface layer portion of the outer circumferential surface 72 toward the first to fourth connection surfaces 73A to 73D, and extends along the surface layer portions of the first to fourth connection surfaces 73A to 73D. The well region 78 is electrically connected to the body region 32 in the surface layer portion of the active surface 71. The well region 78 is formed at a distance from the lower end of the stacked portion 7 toward the outer circumferential surface 72, and faces the base layer 6 with a portion of the drift region 8 sandwiched therebetween.

[0207] The bottom of the well region 78 is located closer to the lower end of the stacked portion 7 than the bottom wall of the gate structure 35. The bottom of the well region 78 is preferably located closer to the outer circumferential surface 72 than the second lower ends 12a of the multiple second pillar regions 12. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the intermediate portions of the thickness ranges of the multiple second pillar regions 12.

[0208] The well region 78 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0209] The well region 78 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 34. The p-type impurity concentration of the well region 78 is higher than the p-type impurity concentration of the body region 32. Of course, the p-type impurity concentration of the well region 78 may be lower than that of the body region 32. The well region 78 forms a pn junction with the drift region 8.

[0210] The p-type impurity concentration of the well region 78 is preferably adjusted by at least one trivalent element. The trivalent element of the well region 78 may be the same as the trivalent element of the second pillar region 12, etc., or may be a different species from the trivalent element of the second pillar region 12, etc. The trivalent element of the well region 78 may be at least one of boron, aluminum, gallium, and indium.

[0211] Semiconductor device 1B includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer portion of outer peripheral surface 72 in outer peripheral region 11. The multiple field regions 38 are formed in the surface layer portion of outer peripheral surface 72 in the same manner as in semiconductor device 1A.

[0212] In this embodiment, the field regions 38 are arranged at intervals from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 and the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Specifically, the field regions 38 are arranged at intervals from the well region 78 toward the periphery of the outer circumferential surface 72.

[0213] The field regions 38 extend in a strip shape along the active surface 71 in a plan view and are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 71. The field regions 38 are formed at intervals from the bottom of the stacked portion 7 (drift region 8) toward the outer peripheral surface 72, and face the base layer 6 with part of the drift region 8 in between. The field regions 38 are located closer to the lower end of the drift region 8 than the bottom of the gate structure 35.

[0214] The semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3. The interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42. In this embodiment, the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D. The first insulating film 41 is connected to an insulating film 76 on the active surface 71, exposing the buried electrode 77.

[0215] The first insulating film 41 covers the well region 78 and the plurality of field regions 38 on the outer peripheral surface 72. In this embodiment, the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 41 may be formed at an interval inward from the periphery of the outer peripheral surface 72, with the second layer 9 exposed from the periphery of the outer peripheral surface 72. The first insulating film 41 covers the well region 78 on the first to fourth connection surfaces 73A to 73D.

[0216] In this embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D, sandwiching the first insulating film 41 therebetween. The second insulating film 42 covers the plurality of gate structures 35 in the active region 10. The second insulating film 42 covers the plurality of field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41 therebetween. In this embodiment, the second insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 42 may be formed spaced inward from the periphery of the outer peripheral surface 72, exposing the stacked portion 7, together with the first insulating film 41, from the periphery of the outer peripheral surface 72.

[0217] The semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40. The plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (buried electrodes 77) and a plurality of contact openings 43 that expose a plurality of source regions 33. The plurality of contact openings 43 for the source regions 33 are formed in regions between adjacent plurality of gate structures 35, and expose a plurality of source regions 33 and a plurality of contact regions 34.

[0218] The semiconductor device 1B includes a sidewall structure 79 disposed in the interlayer insulating film 40 so as to cover at least one of the first to fourth connecting surfaces 73A to 73D. The sidewall structure 79 is disposed on the first insulating film 41 and is covered by the second insulating film 42. The sidewall structure 79 reduces a step formed between the active surface 71 and the outer peripheral surface 72.

[0219] The sidewall structure 79 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 73A to 73D so as to surround the active surface 71 in a plan view.

[0220] The sidewall structure 79 may have a portion extending in a film-like manner along the outer peripheral surface 72 and a portion extending in a film-like manner along the first to fourth connecting surfaces 73A to 73D. In this embodiment, the sidewall structure 79 is formed at a distance from the innermost field region 38 toward the active surface 71, and faces the well region 78 in the horizontal direction and the stacking direction, with the first insulating film 41 sandwiched therebetween. The sidewall structure 79 may face the body region 32, with the first insulating film 41 sandwiched therebetween.

[0221] Similar to the semiconductor device 1A, the semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48. The drain pad 48 is formed in the same form as in the first embodiment.

[0222] In this embodiment, the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view. The gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view. Of course, the gate pad 45 may also be disposed in a corner of the active surface 71 or in the center of the active surface 71 in a plan view.

[0223] In this embodiment, the plurality of gate wirings 46 are arranged on the active surface 71 at intervals from the outer peripheral surface 72 in a plan view. The plurality of gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.

[0224] The first gate wiring 46A is drawn out from the gate pad 45 toward the first connection surface 73A, and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, orthogonal to) some (specifically, one end) of the multiple gate structures 35. The first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43, and is electrically connected to one end of the multiple gate structures 35 (buried electrodes 77).

[0225] The second gate wiring 46B is drawn out from the gate pad 45 toward the third connection surface 73C and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, orthogonal to) some (specifically, the other ends) of the multiple gate structures 35. The second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other ends of the multiple gate structures 35 (buried electrodes 77).

[0226] In this embodiment, source pad 47 is disposed on active surface 71 at a distance from outer peripheral surface 72 in a plan view. Source pad 47 penetrates interlayer insulating film 40 via multiple contact openings 43 and is electrically connected to body region 32, multiple source regions 33, and multiple contact regions 34. In other words, source pad 47 is electrically connected to multiple second pillar regions 12 via body region 32.

[0227] Fig. 33 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment. The plurality of gate structures 35 according to the first embodiment described above were arranged shifted from the plurality of second pillar regions 12 toward the plurality of first pillar regions 13. In contrast, referring to Fig. 33, the plurality of gate structures 35 according to the second embodiment are arranged so as to overlap the plurality of second pillar regions 12 in the stacking direction. The plurality of gate structures 35 overlap the plurality of second pillar regions 12 in a one-to-one correspondence in the stacking direction.

[0228] The plurality of gate structures 35 each have a bottom wall connected to the corresponding second pillar region 12. Specifically, the plurality of gate structures 35 are formed wider than the corresponding second pillar region 12, and each have a bottom wall connected to the corresponding second pillar region 12 and a sidewall connected to the corresponding first pillar region 13.

[0229] That is, the buried electrodes 77 face the corresponding second pillar regions 12 across the insulating film 76 in the stacking direction, and face the corresponding first pillar regions 13 across the insulating film 76 in the horizontal direction. The aforementioned multiple source regions 33 and multiple contact regions 34 face the corresponding first pillar regions 13 across a part of the body region 32 in the stacking direction, respectively.

[0230] Fig. 34 is a cross-sectional perspective view showing a gate structure 35 according to the third embodiment. Referring to Fig. 34, the plurality of gate structures 35 according to the third embodiment each have a configuration that contributes to narrowing the pitch. The plurality of gate structures 35 according to the third embodiment are particularly effective in realizing a narrower pitch in the second pillar regions 12. Fig. 34 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the third embodiment, but the configuration of the gate structure 35 according to the third embodiment is also applicable to the configuration of the gate structure 35 according to the second embodiment.

[0231] Each of the multiple gate structures 35 includes a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80. The trench 75 has the same configuration as in the first embodiment. In this configuration, the insulating film 76 is formed at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, exposing a surface portion of the first main surface 3 (active surface 71) at the opening end of the trench 75. The upper end of the insulating film 76 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 75.

[0232] In this embodiment, the buried electrode 77 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the open end of the trench 75. The buried electrode 77 exposes a surface portion of the first main surface 3 (active surface 71) and an upper end of the insulating film 76 at the open end of the trench 75. The upper end of the buried electrode 77 is preferably located on the first main surface 3 side relative to the intermediate depth range of the trench 75.

[0233] The buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first main surface 3 (active surface 71), and covers the insulating film 76 and the buried electrode 77 within the trench 75. The buried insulator 80 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the buried electrode 77, and exposes a surface portion of the first main surface 3 (active surface 71) at the open end of the trench 75.

[0234] The upper end of the buried insulator 80 is preferably located closer to the first main surface 3 than the intermediate depth of the trench 75. The buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The buried insulator 80 preferably includes a silicon oxide film.

[0235] In this embodiment, the aforementioned plurality of source regions 33 are respectively formed in regions between the plurality of adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71). The plurality of source regions 33 are arranged at intervals along the plurality of gate structures 35 so as to be connected to the plurality of gate structures 35 located on both sides thereof.

[0236] Specifically, the plurality of source regions 33 arranged along one sidewall of the gate structure 35 face in one-to-one correspondence with the plurality of source regions 33 arranged along the other sidewall of the gate structure 35. In other words, the plurality of source regions 33 are arranged in a matrix in plan view.

[0237] Of course, the plurality of source regions 33 on one side may face the regions between the plurality of source regions 33 on the other side in a one-to-one correspondence. That is, the plurality of source regions 33 may be arranged in a staggered pattern in a plan view. The plurality of source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 interposed therebetween.

[0238] In this embodiment, the aforementioned plurality of contact regions 34 are formed in regions between adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71). The plurality of contact regions 34 are arranged at intervals along the plurality of gate structures 35 so as to be connected to the plurality of gate structures 35 located on both sides.

[0239] Specifically, the plurality of contact regions 34 are arranged alternately with the plurality of source regions 33 along the plurality of gate structures 35. More specifically, the plurality of contact regions 34 arranged along one sidewall of the gate structure 35 face in one-to-one correspondence with the plurality of contact regions 34 arranged along the other sidewall of the gate structure 35. Furthermore, the plurality of source regions 33 are arranged in a matrix in plan view.

[0240] Of course, the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence. That is, the multiple contact regions 34 may be arranged in a staggered pattern in a plan view. The multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 sandwiched therebetween.

[0241] Although specific illustration is omitted, the interlayer insulating film 40 has a laminated structure including a first insulating film 41 and a second insulating film 42. As in the first embodiment, the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D.

[0242] In this embodiment, the first insulating film 41 covers the peripheral edge of the active surface 71 and exposes the plurality of gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the plurality of gate structures 35, exposing the buried electrodes 77. The first insulating film 41 also covers the outer peripheral surface 72 and the first to fourth connecting surfaces 73A to 73D in the same manner as in the first embodiment.

[0243] As in the first embodiment, the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connecting surfaces 73A to 73D, sandwiching the first insulating film 41. In this embodiment, the second insulating film 42 covers the peripheral portion of the active surface 71 and exposes the plurality of gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the second insulating film 42 extends from above the first main surface 3 (active surface 71) into the trench 75 at both ends of the plurality of gate structures 35 and is connected to the buried insulator 80 within the trench 75.

[0244] In this form, the interlayer insulating film 40 includes a plurality of contact openings 43 (not shown) that expose both ends (buried electrodes 77) of the plurality of gate structures 35, and a single contact opening 43 that collectively exposes the inner portions (buried insulator 80) of the plurality of gate structures 35, the plurality of source regions 33, and the plurality of contact regions 34.

[0245] The gate pad 45, the gate wirings 46, and the drain pad 48 have the same configurations as those in the first embodiment. The source pad 47 extends from above the interlayer insulating film 40 into the single contact opening 43, and collectively covers the inner portions (buried insulator 80) of the gate structures 35, the source regions 33, and the contact regions 34 within the single contact opening 43.

[0246] The source pad 47 is electrically insulated from the plurality of gate structures 35 (buried electrodes 77) by the buried insulator 80, and is electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 on the first main surface 3 (active surface 71). The source pad 47 has a buried portion buried in the trench 75. The buried portion of the source pad 47 faces the buried electrode 77 within the trench 75 with the buried insulator 80 sandwiched therebetween, and is electrically connected to the plurality of source regions 33 and the plurality of contact regions 34 at the open end of the trench 75.

[0247] 35 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment. Referring to Fig. 35, the plurality of gate structures 35 according to the fourth embodiment each have a configuration obtained by modifying the plurality of gate structures 35 according to the third embodiment. The configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the first to third embodiments.

[0248] Each of the gate structures 35 includes a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80. The trench 75 has the same configuration as in the first embodiment. In this configuration, the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.

[0249] The upper insulating film 81 is formed as an insulating film for channel control, and covers the wall surface on the opening side of the trench 75 relative to the bottom of the body region 32. The upper insulating film 81 has a portion that covers the first pillar region 13 across the boundary between the first pillar region 13 and the body region 32. In this case, the coverage area of ​​the upper insulating film 81 with respect to the body region 32 is preferably larger than the coverage area of ​​the upper insulating film 81 with respect to the first pillar region 13.

[0250] The upper insulating film 81 may include a silicon oxide film. The upper insulating film 81 preferably includes a silicon oxide film made of an oxide of the chip 2. The upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value belonging to any one of the ranges of 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0251] The lower insulating film 82 covers the wall surface of the trench 75 on the bottom wall side of the bottom of the body region 32. The lower insulating film 82 covers the first pillar region 13. The coverage area of ​​the first pillar region 13 by the lower insulating film 82 is larger than the coverage area of ​​the body region 32 by the upper insulating film 81.

[0252] The lower insulating film 82 may include a silicon oxide film. The lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method. The lower insulating film 82 has a thickness greater than that of the upper insulating film 81. The thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.

[0253] The lower insulating film 82 may have a thickness of 100 nm to 500 nm. The thickness of the lower insulating film 82 may have a value belonging to any one of the ranges of 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0254] In this embodiment, the buried electrode 77 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85. The upper electrode 83 is buried in the opening side of the trench 75 with an insulating film 76 sandwiched therebetween. Specifically, the upper electrode 83 is buried in the opening side of the trench 75 with an upper insulating film 81 sandwiched therebetween, and faces the body region 32 with the upper insulating film 81 sandwiched therebetween.

[0255] The area of ​​the upper electrode 83 facing the body region 32 is larger than the area of ​​the upper electrode 83 facing the first pillar region 13. In this embodiment, the upper electrode 83 is embedded in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75. The upper electrode 83 exposes a surface portion of the first main surface 3 (active surface 71) and an upper end of the upper insulating film 81 at the opening end of the trench 75.

[0256] A gate potential as a control potential is applied to the upper electrode 83. In response to the gate potential, the upper electrode 83 controls the inversion and non-inversion of a channel (current path) in the body region 32. The upper electrode 83 may include p-type or n-type conductive polysilicon.

[0257] The lower electrode 84 is embedded in the bottom wall side of the trench 75 with the insulating film 76 sandwiched therebetween. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the lower insulating film 82 sandwiched therebetween, and faces the first pillar region 13 with the lower insulating film 82 sandwiched therebetween. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with respect to the bottom of the body region 32. Although specific illustration is omitted, the lower electrode 84 is extended to the opening side of the trench 75 in parts of the trench 75 (both ends in this embodiment).

[0258] The facing area of ​​the lower electrode 84 with respect to the first pillar region 13 is larger than the facing area of ​​the upper electrode 83 with respect to the body region 32. The lower electrode 84 extends in a wall shape along the depth direction of the trench 75. The lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83 and engages with the lower end of the upper electrode 83. The upper end of the lower electrode 84 faces the upper insulating film 81 (body region 32) with the lower end of the upper electrode 83 sandwiched in the horizontal direction.

[0259] A gate potential or a source potential may be applied to the lower electrode 84. When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the gate structure 35.

[0260] On the other hand, when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the first pillar region 13 is reduced. This suppresses a decrease in switching speed due to the parasitic capacitance. The lower electrode 84 may include p-type or n-type conductive polysilicon.

[0261] The intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 75. The intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82. The intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82. The thickness of the intermediate insulating film 85 is preferably greater than that of the upper insulating film 81. The intermediate insulating film 85 may include a silicon oxide film. The intermediate insulating film 85 preferably includes a silicon oxide film made of an oxide of the lower electrode 84.

[0262] The buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first main surface 3 (active surface 71), and covers the upper insulating film 81 and the upper electrode 83 within the recess. The buried insulator 80 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the upper electrode 83, and exposes a surface portion of the first main surface 3 (active surface 71) at the open end of the trench 75.

[0263] In this embodiment, the plurality of source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the upper electrode 83 and the buried insulator 80 with the upper insulating film 81 interposed therebetween. In this embodiment, the plurality of contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the upper electrode 83 and the buried insulator 80 with the upper insulating film 81 interposed therebetween.

[0264] The plurality of field regions 38, the interlayer insulating film 40, the gate pad 45, the plurality of gate wirings 46, the source pad 47, and the drain pad 48 have the same configurations as those in the second embodiment. In this configuration, the plurality of gate wirings 46 penetrate the interlayer insulating film 40 via the plurality of contact openings 43 and are electrically connected to the plurality of upper electrodes 83. When a gate potential is applied to the lower electrode 84, the plurality of gate wirings 46 penetrate the interlayer insulating film 40 via the plurality of contact openings 43 and are electrically connected to the plurality of upper electrodes 83 and the plurality of lower electrodes 84.

[0265] When a source potential is applied to the lower electrode 84, the source pad 47 is electrically connected to the plurality of lower electrodes 84. In this case, the semiconductor device 1B may include a source wiring extending from the source pad 47 onto the interlayer insulating film 40. In this case, the source wiring is formed in a line shape extending along the periphery of the active surface 71 so as to intersect (specifically, orthogonally intersect) with a portion (one end or both ends) of the plurality of gate structures 35 in a region outside the plurality of gate wirings 46. The source wiring penetrates the interlayer insulating film 40 via the plurality of contact openings 43 and is electrically connected to the plurality of lower electrodes 84.

[0266] Fig. 36 is a plan view showing a semiconductor device 1C according to a third embodiment. Fig. 37 is a cross-sectional view taken along line XXXVII-XXXVII shown in Fig. 36. Fig. 38 is a plan view showing an example layout of a chip 2. Fig. 39 is a perspective view showing an example layout of a chip 2.

[0267] 36 to 39 , similar to the semiconductor device 1A, the semiconductor device 1C includes a chip 2, a base layer 6, a stacked portion 7, an active region 10, a peripheral region 11, a plurality of second pillar regions 12, a plurality of first pillar regions 13, and a plurality of field regions 38. The plurality of second pillar regions 12 may have at least one of the plurality of features shown in the basic form and the first to eleventh embodiment examples described above. The plurality of second pillar regions 12 may have a feature that combines a plurality (two or more) of the features shown in the basic form and the first to eleventh embodiment examples described above.

[0268] The semiconductor device 1C includes an interlayer insulating film 90 that selectively covers the first main surface 3. The interlayer insulating film 90 may have a single layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 90 has a single layer structure including a silicon oxide film.

[0269] The interlayer insulating film 90 covers the plurality of field regions 38 in the peripheral region 11. In this embodiment, the interlayer insulating film 90 is continuous with the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. Of course, the interlayer insulating film 90 may be formed at a distance inward from the periphery of the first main surface 3, with the stacked portion 7 exposed from the periphery of the first main surface 3.

[0270] The interlayer insulating film 90 has a contact opening 91 that exposes the active region 10. In this form, the contact opening 91 has an opening wall surface positioned above the innermost field region 38, exposing the entire active region 10 and the inner edge of the innermost field region 38.

[0271] The semiconductor device 1C includes a first pad electrode 92 covering the first main surface 3 in the active region 10. The first pad electrode 92 is formed as an anode pad. The first pad electrode 92 is disposed inward from the periphery of the chip 2 at a distance. The first pad electrode 92 is formed in a polygonal shape (a quadrangular shape in this embodiment) that follows the periphery of the chip 2 in a plan view.

[0272] The first pad electrode 92 extends from above the interlayer insulating film 90 into the contact opening 91 and is electrically connected to the first main surface 3 and the innermost field region 38 within the contact opening 91. The first pad electrode 92 forms a Schottky junction with the first main surface 3 (first pillar region 13). As a result, an SBD structure 93 (Schottky Barrier Diode structure) serving as a diode structure (device structure) is formed in the active region 10.

[0273] The semiconductor device 1C includes a second pad electrode 94 covering the second main surface 4. The second pad electrode 94 is formed as a cathode pad. The second pad electrode 94 forms ohmic contact with the base layer 6 exposed from the second main surface 4. In other words, the second pad electrode 94 is electrically connected to the first pillar region 13 via the base layer 6.

[0274] The second pad electrode 94 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The second pad electrode 94 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0275] The breakdown voltage that can be applied between the first pad electrode 92 and the second pad electrode 94 (between the first main surface 3 and the second main surface 4) may be 500 V to 3000 V or less. The breakdown voltage may have a value that belongs to any one of the following ranges: 500 V to 1000 V or less, 1000 V to 1500 V, 1500 V to 2000 V, 2000 V to 2500 V, and 2500 V to 3000 V.

[0276] A basic form of an SBD structure 93 will be shown below with reference to FIG. 40 . FIG. 40 is a cross-sectional perspective view showing an SBD structure 93 according to the basic form. Referring to FIG. 40 , when the plurality of second pillar regions 12 and the plurality of first pillar regions 13 are exposed from the first main surface 3, the first pad electrode 92 is mechanically and electrically connected to the plurality of second pillar regions 12 and the plurality of first pillar regions 13 at the first main surface 3. In this case, the first pad electrode 92 forms a JBS structure (Junction Barrier Controlled Schottky structure) with the plurality of second pillar regions 12 and forms a Schottky junction with the plurality of first pillar regions 13.

[0277] The above-described embodiments can be implemented in other forms. For example, in each of the above-described embodiments, the base layer 6 and the stacked portion 7 each include a SiC single crystal. However, at least one of the base layer 6 and the stacked portion 7 or all of the base layer 6 and the stacked portion 7 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0278] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３The base layer 6 and the laminated portion 7 may be made of the same type of single crystal, or may be made of different types of single crystal.

[0279] In the above-described embodiments, examples have been shown in which the MIS structure 31 and the SBD structure 93 are individually formed on different chips 2. However, the MIS structure 31 and the SBD structure 93 may be formed on one chip 2. In this case, the SBD structure 93 may be electrically interposed between the source pad 47 (anode pad) and the drain pad 48 (cathode pad) as a freewheeling diode for the MIS structure 31.

[0280] In the above-described embodiments, an n-type base layer 6 has been described. However, a p-type base layer 6 may be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

[0281] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0282] [Supplementary Note 1-1] A semiconductor device (1A, 1B, 1C) comprising: a first conductivity type semiconductor layer (7) having a first main surface (3) and a second main surface (4); a first conductivity type first pillar region (13) extending in the semiconductor layer (7) in a depth direction (Z) of the semiconductor layer (7) from the first main surface (3) toward the second main surface (4); and a second conductivity type second pillar region (12) adjacent to the first pillar region (13) in the semiconductor layer (7) and extending in the depth direction (Z), wherein in the depth direction (Z), a maximum value of a first conductivity type background impurity concentration profile (22, 23) of the second pillar region (12) is equal to or less than half of a maximum value of a first conductivity type first impurity concentration profile (20, 21) of the first conductivity type of the first pillar region (13).

[0283] According to this configuration, the maximum value of the background impurity concentration of the first conductivity type in the second pillar region (12) is small. As a result, even if the background impurity concentration varies in the depth direction (Z) of the semiconductor layer (7), the influence of the variation on the effective impurity concentration of the second conductivity type in the second pillar region (12) can be reduced. Therefore, the effective impurity concentration of the second conductivity type in the second pillar region (12) can be stabilized. As a result, the influence on the charge balance between the first pillar region (13) and the second pillar region (12) can be reduced, thereby suppressing fluctuations in the breakdown voltage due to a charge imbalance.

[0284] [Supplementary Note 1-2] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-1, wherein the maximum value of the background impurity concentration profile (22, 23) is smaller than the maximum value of the first impurity concentration profile (20, 21) by one or more orders of magnitude.

[0285] [Appendix 1-3] The semiconductor device (1A, 1B, 1C) according to Appendix 1-1 or 1-2, wherein the first impurity concentration is adjusted by a first element, the second pillar region (12) does not contain the first element, and the background impurity concentration is adjusted by a second element different from the first element.

[0286] [Supplementary Note 1-4] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-3, wherein the first element and the second element are trivalent elements different from each other.

[0287] [Supplementary Note 1-5] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-4, wherein the first element is phosphorus (P) and the second element is nitrogen (N).

[0288] [Supplementary Note 1-6] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-1 or 1-2, wherein the background impurity concentration profile (22, 23) is a profile at a central position in the width direction of the second pillar region (12).

[0289] [Appendix 1-7] The semiconductor device (1A, 1B, 1C) according to appendix 1-1 or 1-2, wherein the second pillar region (12) has a thickness (T2) of 1 μm or more and 30 μm or less.

[0290] According to this configuration, the second pillar region (12) is formed to a relatively deep position in the semiconductor layer (7), thereby improving the breakdown voltage.

[0291] [Supplementary Note 1-8] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-1 or 1-2, wherein the first pillar region (13) and the second pillar region (12) have the same width (W1, W2).

[0292] [Appendix 1-9] The semiconductor device (1A, 1B, 1C) according to appendix 1-1 or 2, wherein the semiconductor layer (7) is a SiC semiconductor layer (7).

[0293] According to this configuration, the features of the first pillar region (13) and the second pillar region (12) described above can be applied to the power semiconductor device (1A, 1B, 1C) having the SiC semiconductor layer (7).

[0294] [Supplementary Note 1-10] A SiC chip (2) having a first main surface (3) and a second main surface (4), a drift region (8) of a first conductivity type formed in a surface layer portion of the first main surface (3) of the SiC chip (2), a superjunction structure (SJ) including first pillar regions (13) of the first conductivity type and second pillar regions (12) of a second conductivity type arranged adjacent to each other and alternately repeated in a direction along the first main surface (3) in the drift region (8), and a device structure (31, 93) formed between the superjunction structure (SJ) and the first main surface (3), In the depth direction (Z) of the SiC chip (2), a maximum value of a profile (22, 23) of a background impurity concentration of the first conductivity type in the second pillar region (12) is equal to or less than half of a maximum value of a profile (20, 21) of a first impurity concentration of the first conductivity type in the first pillar region (13).

[0295] According to this configuration, the maximum value of the background impurity concentration of the first conductivity type in the second pillar region (12) is small. As a result, even if the background impurity concentration varies in the depth direction (Z) of the SiC chip (2), the influence of the variation on the effective impurity concentration of the second conductivity type in the second pillar region (12) can be reduced. Therefore, the effective impurity concentration of the second conductivity type in the second pillar region (12) can be stabilized. As a result, the influence on the charge balance between the first pillar region (13) and the second pillar region (12) can be reduced, thereby suppressing fluctuations in the breakdown voltage due to a charge imbalance. Therefore, the superjunction structure (SJ) can further improve the breakdown voltage performance of the SiC semiconductor device (1A, 1B, 1C).

[0296] [Appendix 1-11] The semiconductor device (1A, 1B, 1C) according to Appendix 1-10, wherein the drift region (8) has a first conductivity type drift impurity concentration, the maximum value of the drift impurity concentration profile (22, 23) in the depth direction (Z) is smaller by one or more orders of magnitude than the maximum value of the first impurity concentration profile (20, 21), and the background impurity concentration profile (22, 23) and the drift impurity concentration profile (22, 23) are equal to or similar to each other.

[0297] For example, when the drift region (8) is formed by epitaxial growth, the source gas for the drift region (8) is supplied while doping with impurity ions during the crystal growth process. Because the impurity distribution in the epitaxial layer (drift region (8)) can be easily controlled, for example, the drift impurity concentration can be made constant or nearly constant in the depth direction (Z) of the epitaxial layer. This similarly makes the background impurity concentration constant or nearly constant, effectively reducing the variation in the effective impurity concentration of the second conductivity type in the second pillar region (12) in the depth direction (Z). As a result, fluctuations in breakdown voltage due to charge imbalance in the superjunction structure (SJ) can be further suppressed.

[0298] [Supplementary Note 1-12] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 1-11, wherein when a first impurity concentration N1 of the first pillar region (13) is defined as N1, a width W1 of the first pillar region (13) is defined as N2, a second conductivity type impurity concentration N2 of the second pillar region (12) is defined as N2, and a width W2 of the second pillar region (12) is defined as W2, a charge balance CB between the first pillar region (13) and the second pillar region (12) is expressed by the following formula (1): The charge balance CB is in the range of 0.9 to 1.1 in the section from the top to the bottom in the depth direction (Z) of the superjunction structure (SJ). CB=(N1×W1) / (N2×W2) (1)

[0299] With this configuration, the charge balance of the superjunction structure (SJ) is within the range of 0.9 to 1.1 in the section from the top to the bottom in the depth direction (Z). Because the charge balance variation range is narrow, the withstand voltage of the superjunction structure (SJ) can be stably ensured.

[0300] [Appendix 1-13] The semiconductor device (1A, 1B, 1C) according to appendix 1-12, wherein the width W1 of the first pillar region (13) and the width W2 of the second pillar region (12) are the same width.

[0301] As described above, the charge balance of the superjunction structure (SJ) is within the range of 0.9 to 1.1 in the section from the top to the bottom in the depth direction (Z). This allows the width W1 of the first pillar region (13) and the width W2 of the second pillar region (12) to be the same width. As a result, it is not necessary to narrow or widen only one of the widths of the first pillar region (13) and the second pillar region (12). This allows the superjunction structure (SJ) to be formed with high density, further improving the breakdown voltage.

[0302] [Appendix 1-14] The semiconductor device (1A, 1B, 1C) according to Appendix 1-12, wherein the second pillar region (12) has a thickness (T2) of 1 μm or more and 30 μm or less.

[0303] According to this configuration, the super junction structure (SJ) is formed to a relatively deep position in the SiC chip (2), thereby improving the breakdown voltage.

[0304] [Appendix 1-15] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-11 to 1-14, wherein the first impurity concentration is adjusted by phosphorus (P), the second pillar region (12) does not contain phosphorus (P), and the drift impurity concentration is adjusted by nitrogen (N).

[0305] [Appendix 1-16] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-11 to 1-15, wherein the SiC chip (2) includes a base SiC layer (6) and a SiC layer stacked on the base SiC layer (6), and the second pillar region (12) includes a lower end (12a) that coincides with a lower end of the SiC layer and is connected to the base SiC layer (6), and an upper end (12b) that coincides with an upper end of the SiC layer.

[0306] [Appendix 1-17] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-11 to 1-15, wherein the SiC chip (2) includes a base SiC layer (6) and a SiC layer (7) stacked on the base SiC layer (6), and the second pillar region (12) includes a lower end (12a) that coincides with a lower end of the SiC layer (7) and is connected to the base SiC layer (6), and an upper end (12b) that is formed at a distance from an upper end of the SiC layer toward the lower end and faces the first main surface (3) across a part of the SiC layer (7).

[0307] [Appendix 1-18] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-11 to 1-15, wherein the SiC chip (2) includes a base SiC layer (6) and a SiC layer (7) stacked on the base SiC layer (6), and the second pillar region (12) is formed at an interval from a lower end to an upper end of the SiC layer (7), and includes a lower end (12a) facing the base SiC layer (6) across a part of the SiC layer (7), and an upper end (12b) coinciding with an upper end of the SiC layer (7).

[0308] [Appendix 1-19] The semiconductor device (1A, 1B, 1C) according to any one of Appendices 1-11 to 1-15, wherein the SiC chip (2) includes a base SiC layer (6) and a SiC layer (7) stacked on the base SiC layer (6), and the second pillar region (12) includes a lower end (12a) formed at a distance from a lower end of the SiC layer to an upper end thereof and facing the base SiC layer (6) with a portion of the SiC layer (7) interposed therebetween, and an upper end (12b) formed at a distance from an upper end of the SiC layer to a lower end thereof and facing the first main surface (3) with a portion of the SiC layer (7) interposed therebetween.

[0309] [Supplementary Note 1-20] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-16 to Supplementary Note 1-19, wherein the second pillar region (12) has a stacked structure including a first region (18) and a second region (19) in a thickness direction (Z) of the SiC layer (7), and the first region (18) and the second region (19) are arranged at an interval from each other in the thickness direction (Z) of the SiC layer (7) and face each other with a part (25) of the SiC layer (7) sandwiched therebetween.

[0310] [Supplementary Note 1-21] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 1-16 to Supplementary Note 1-19, wherein the second pillar region (12) has a stacked structure including a first region (18) and a second region (19) in a thickness direction (Z) of the SiC layer (7), and the first region (18) and the second region (19) are connected to each other in the thickness direction (Z) of the SiC layer (7).

[0311] [Supplementary Note 1-22] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-16 to Supplementary Note 1-21, wherein the device structure (31, 93) includes a field-effect transistor structure (31) having a body region (32) of a second conductivity type formed in a surface layer portion of the first main surface (3) and overlapping the second pillar region (12) in a thickness direction (Z) of the SiC layer (7), a source region (33) of a first conductivity type formed in a surface layer portion of the body region (32), and a gate structure (35) overlapping the body region (32).

[0312] [Supplementary Note 1-23] The semiconductor device (1A, 1B) according to Supplementary Note 1-22, wherein the gate structure (35) includes a planar gate structure.

[0313] [Supplementary Note 1-24] The semiconductor device (1A, 1B) according to Supplementary Note 1-22, wherein the gate structure (35) includes a trench gate structure.

[0314] [Appendix 1-25] The semiconductor device (1C) according to any one of Appendices 1-16 to 1-21, wherein the device structure (31, 93) includes a first electrode (92) formed on the first main surface (3) and electrically connected to the first pillar region (13), and a diode structure (93) formed by the first pillar region (13).

[0315] [Supplementary Note 2-1] A semiconductor device (1A, 1B, 1C) includes: a chip (2) having a first main surface (3) and a second main surface (4); an n-type drift region (8) formed in a surface layer portion of the first main surface (3) of the chip (2); a plurality of p-type pillar regions (12) arranged in the drift region (8) and extending in a thickness direction (Z) of the chip (2); and an n-type second drift region (13) sandwiched between the plurality of pillar regions (12) and having a higher impurity concentration than the drift region (8), wherein the drift region (8) has a concentration adjusted with nitrogen (N), and the second drift region (13) has a concentration adjusted with phosphorus (P), and an n-type background concentration in the pillar regions (12) is lower than the n-type impurity concentration of the second drift region (13).

[0316] [Supplementary Note 2-2] The semiconductor device (1A, 1B, 1C) according to Supplementary Note 2-1, wherein when a donor concentration in the second drift region (13) is Nd, an acceptor concentration in the pillar region (12) is Na, and a background donor concentration in the pillar region (12) is Ndb, an effective acceptor concentration (Na-Ndb) in the pillar region (12) expressed as a difference between the acceptor concentration Na and the background donor concentration Ndb is 90% or more and 110% or more of the donor concentration Nd.

[0317] [Supplementary Note 2-3] The maximum value of the donor concentration Nd in the thickness direction (Z) of the chip (2) is 1×10 １６ cm －３ 1x10 or more １８ cm －３ the maximum value of the effective acceptor concentration (Na-Ndb) in the thickness direction (Z) of the chip (2) is 1×10 or less; １６ cm －３ 1x10 or more１８ cm －３ The semiconductor device (1A, 1B, 1C) described in Appendix 2-2 below.

[0318] [Supplementary Note 2-4] The background donor concentration in the thickness direction (Z) of the chip (2) is 1×10 １５ cm －３ 1x10 or more １６ cm －３ The semiconductor device (1A, 1B, 1C) according to Supplementary Note 2-2 or Supplementary Note 2-3 is as follows:

[0319] [Supplementary Note 2-5] The semiconductor device (1A, 1B, 1C) according to any one of Supplementary Note 2-2 to Supplementary Note 2-4, wherein when the width of the second drift region (13) is W1 and the width of the pillar region (12) is W2, a charge balance CB between the second drift region (13) and the pillar region (12) is expressed by the following formula (1): The charge balance CB is in the range of 0.9 to 1.1 in a section from a top to a bottom in a depth direction (Z) of the pillar region (12). CB=(Nd×W1) / (Na×W2) (1)

[0320] 1A: Semiconductor device 1B: Semiconductor device 1C: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: Base layer 7: Stacked portion 8: Drift region 9: Second layer 10: Active region 11: Peripheral region 12: Second pillar region 12a: Second bottom end 12b: Second top end 13: First pillar region 13a: First bottom end 13b: First top end 15: Effective profile 16: Solid line 17: Two-dot chain line 18: First region 19: Second region 20: First profile 21: First profile 22: Drift profile 23: Drift profile 24 : Second profile 25 : Intermediate region 26 : Boundary portion 31 : MIS structure 32 : Body region 33 : Source region 34 : Contact region 35 : Gate structure 36 : Gate insulating film 37 : Gate electrode 38 : Field region 40 : Interlayer insulating film 41 : First insulating film 42 : Second insulating film 43 : Contact opening 45 : Gate pad 46 : Gate wiring 46A : First gate wiring 46B : Second gate wiring 47 : Source pad 48 : Drain pad 50 : Wafer 51 : First wafer main surface 52 : Second wafer main surface 53 : Wafer side surface 54 : Mark 55 : Device region 56 : Planned cutting line 60 : First mask 61 : First opening 62 : Second mask 63 : Second opening 64 : Crystal defect 71 : Active surface 72 : Outer peripheral surface 73A : First connection surface 73B : Second connection surface 73C : Third connection surface 73D : Fourth connection surface 74 : Active plateau 75 : Trench 76 : Insulating film 77 : Buried electrode 78 : Well region 79 : Sidewall structure 80 : Buried insulator 81 : Upper insulating film 82 : Lower insulating film 83 : Upper electrode 84 : Lower electrode 85 : Intermediate insulating film90: Interlayer insulating film 91: Contact opening 92: First pad electrode 93: SBD structure 94: Second pad electrode

Claims

1. A semiconductor device comprising a first-conductivity-type semiconductor layer having a first main surface and a second main surface, a first-pillar region of the first conductivity type extending in the depth direction of the semiconductor layer from the first main surface toward the second main surface within the semiconductor layer, and a second-pillar region of the second conductivity type adjacent to the first-pillar region within the semiconductor layer and extending in the depth direction, wherein in the depth direction, the maximum value of the profile of the background impurity concentration of the first conductivity type in the second-pillar region is 1 / 2 or less of the maximum value of the profile of the first impurity concentration of the first conductivity type in the first-pillar region.

2. The semiconductor device according to claim 1, wherein the maximum value of the profile of the background impurity concentration is at least one order of magnitude smaller than the maximum value of the profile of the first impurity concentration.

3. The semiconductor device according to claim 1 or 2, wherein the first impurity concentration is adjusted in concentration by a first element, the second-pillar region does not contain the first element, and the background impurity concentration is adjusted in concentration by a second element different from the first element.

4. The semiconductor device according to claim 3, wherein the first element and the second element are composed of different trivalent elements.

5. The semiconductor device according to claim 4, wherein the first element is phosphorus (P) and the second element is nitrogen (N).

6. The semiconductor device according to any one of claims 1 to 5, wherein the profile of the background impurity concentration is the profile at the central position in the width direction of the second-pillar region.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second-pillar region has a thickness of 1 µm or more and 30 µm or less.

8. The semiconductor device according to any one of claims 1 to 7, wherein the first-pillar region and the second-pillar region have the same width.

9. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor layer is a SiC semiconductor layer.

10. An SiC chip having a first main surface and a second main surface, a drift region of a first conductivity type formed in a surface layer portion of the first main surface of the SiC chip, and a first conductivity type first pillar region and a second conductivity type second pillar region that are alternately and repeatedly arranged adjacent to each other in a direction along the first main surface within the drift region, and a superjunction structure including a device structure formed between the superjunction structure and the first main surface, wherein in a depth direction of the SiC chip, a maximum value of a profile of a background impurity concentration of the first conductivity type of the second pillar region is 1 / 2 or less of a maximum value of a profile of a first impurity concentration of the first conductivity type of the first pillar region. A semiconductor device.

11. The drift region has a drift impurity concentration of a first conductivity type, a maximum value of a profile of the drift impurity concentration in the depth direction is at least one order of magnitude smaller than a maximum value of a profile of the first impurity concentration, and the profile of the background impurity concentration and the profile of the drift impurity concentration are equal to or approximate to each other. The semiconductor device according to claim 10.

12. When a first impurity concentration N1 of the first pillar region, a width W1 of the first pillar region, a second impurity concentration N2 of the second conductivity type of the second pillar region, and a width W2 of the second pillar region are defined, a charge balance CB between the first pillar region and the second pillar region is represented by the following formula (1), and the charge balance CB is in a range of 0.9 or more and 1.1 or less in a section from the top to the bottom in the depth direction of the superjunction structure. The semiconductor device according to claim 11. CB = (N1 × W1) / (N2 × W2) ··· (1) 13. The width W1 of the first pillar region and the width W2 of the second pillar region are the same width as each other. The semiconductor device according to claim 12.

14. The second pillar region has a thickness of 1 μm or more and 30 μm or less. The semiconductor device according to claim 12 or 13.

15. The first impurity concentration is adjusted in concentration by phosphorus (P), the second pillar region does not contain phosphorus (P), and the drift impurity concentration is adjusted in concentration by nitrogen (N). The semiconductor device according to any one of claims 11 to 14.

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