Display driving board, display module, and display apparatus

Abstract

Disclosed are a display driving board, a display module, and a display apparatus. The display driving board (10) comprises: a printed circuit board (100); and a display interface (110), a timing controller (130), and a common mode inductor (120) which are provided on the printed circuit board (100). The printed circuit board (100) comprises at least one group of differential signal lines, and each group of differential signal lines comprises a first differential signal line (S1) and a second differential signal line (S2). Differential signal receiving pads of the display interface (110) are electrically connected to input terminal pads of the common mode inductor (120) by means of the first differential signal line (S1). Output terminal pads of the common mode inductor (120) are electrically connected to differential signal transmission pads of the timing controller (130) by means of the second differential signal line (S2).

Description

Display driver board, display module and display device Technical Field

[0001] The present disclosure belongs to the field of display technology and relates to a display driver board, a display module and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, relatively low manufacturing cost and no radiation, and occupies an important position in the current flat panel display market.

[0003] However, TFT-LCDs are susceptible to electrostatic discharge (ESD). While installing an ESD protection unit on a TFT-LCD can, to a certain extent, prevent static damage to the electronic components and circuits within the TFT-LCD, it can still easily cause display issues such as screen flickering, hindering image quality.

[0004] Summary of the Invention

[0005] In a first aspect of the present disclosure, a display driver board is provided, comprising: a printed circuit board and a display interface, a timing controller and a common-mode inductor arranged on the printed circuit board, the common-mode inductor being located between the display interface and the timing controller, the printed circuit board comprising a first conductive layer, the first conductive layer being provided with a display interface pad, a timing controller pad and at least one group of common-mode inductor pads, the display interface, the timing controller and the common-mode inductor being arranged at their respective corresponding pads on the first conductive layer. The display interface pad includes at least one group of differential signal receiving pads to receive the display differential signal transmitted by the mainboard. The common mode inductor pad includes an input end pad and an output end pad. The timing controller pad includes: a differential signal transmission pad corresponding to each group of the differential signal receiving pads; the printed circuit board also includes: at least one group of differential signal lines to transmit differential signals; each group of the differential signal lines includes: a first differential signal line and a second differential signal line. The differential signal receiving pad is electrically connected to the input end pad through the first differential signal line, and the output end pad is electrically connected to the differential signal transmission pad through the second differential signal line.

[0006] In combination with the first aspect of the present disclosure, in some embodiments, the printed circuit board further includes: a second conductive layer and a third conductive layer serving as signal routing layers, the third conductive layer being located between the first conductive layer and the second conductive layer; wherein at least the second differential signal line is located in the third conductive layer; the output end pad is electrically connected to one end of the second differential signal line through a first via, and the differential signal transmission pad is electrically connected to the other end of the second differential signal line through a second via.

[0007] In combination with the first aspect of the present disclosure, in some embodiments, the printed circuit board further includes: a fourth conductive layer and a fifth conductive layer, the fourth conductive layer is located on the side of the third conductive layer close to the first conductive layer, and the fifth conductive layer is located on the side of the third conductive layer close to the second conductive layer, and the fourth conductive layer and the fifth conductive layer are the ground layers of the printed circuit board.

[0008] In combination with the first aspect of the present disclosure, in some embodiments, the printed circuit board further includes a sixth conductive layer, and the sixth conductive layer is a power supply layer of the printed circuit board.

[0009] In combination with the first aspect of the present disclosure, in some embodiments, the sixth conductive layer is located between the fifth conductive layer and the third conductive layer, and the printed circuit board further includes a first insulating layer and multiple second insulating layers, the first insulating layer is located between the sixth conductive layer and the third conductive layer, and the multiple second insulating layers are insulating layers other than the first insulating layer between adjacent conductive layers of the printed circuit board, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer; and / or the thickness of the first insulating layer is greater than or equal to half the thickness of the printed circuit board.

[0010] In combination with the first aspect of the present disclosure, in some embodiments, the thickness of the first insulating layer is greater than or equal to 15 mil.

[0011] In combination with the first aspect of the present disclosure, in some embodiments, the printed circuit board further includes a sixth conductive layer, located on a side of the second conductive layer away from the fifth conductive layer, and the sixth conductive layer serves as a ground layer of the printed circuit board; and / or, the power line of the printed circuit board is located on the third conductive layer.

[0012] In combination with the first aspect of the present disclosure, in some embodiments, the diameter of the first via hole and the second via hole is less than or equal to 2.5 mm.

[0013] In combination with the first aspect of the present disclosure, in some embodiments, the printed circuit board further includes: a common voltage signal line, a pulse width modulation signal line, a backlight enable signal line, a latch signal line, a communication bus, and a reset signal line, and at least one of the common voltage signal line, the pulse width modulation signal line, the backlight enable signal line, the latch signal line, the communication bus, and the reset signal line is located in a conductive layer between the first conductive layer and the second conductive layer.

[0014] In combination with the first aspect of the present disclosure, in some embodiments, at least one of the common voltage signal line, the pulse width modulation signal line, the backlight enable signal line, the latch signal line, the communication bus, and the reset signal line is located in the third conductive layer.

[0015] In combination with the first aspect of the present disclosure, in some embodiments, the display driver board further includes: a binding area, the binding area includes a binding pin, and the printed circuit board further includes: a third differential signal line, one end of the third differential signal line is electrically connected to the signal transmission pin of the timing controller, and the other end of the third differential signal line is electrically connected to the binding pin, and the third differential signal line is located in the third conductive layer.

[0016] In combination with the first aspect of the present disclosure, in some embodiments, the printed circuit board includes multiple groups of differential signal lines, and the length difference between different groups of differential signal lines is less than or equal to 20 mil; and / or, for the same group of differential signal lines, the first differential signal line includes a first sub-signal line and a second sub-signal line, the second differential signal line includes a third sub-signal line and a fourth sub-signal line, the sum of the lengths of the first sub-signal line and the third sub-signal line is a first length value, the sum of the lengths of the second sub-signal line and the fourth sub-signal line is a second length value, and the difference between the first length value and the second length value is less than or equal to 10 mil.

[0017] In combination with the first aspect of the present disclosure, in some embodiments, the orthographic projection of the timing controller on the surface of the printed circuit board is a polygon; the timing controller pads include K groups of pads, each group of pads is arranged along the extension direction of one side of the polygon, and there is a corner area between each two adjacent groups of pads, and K is an integer greater than or equal to 3; the printed circuit board includes a plurality of first conductive areas as the first grounding end, and the plurality of first conductive areas include: a first conductive area and a second conductive area, the first conductive area is the first conductive area with the largest outer area of ​​the timing controller, and the second conductive area is the first conductive area corresponding to the area enclosed by the timing controller pads, and the second conductive area is connected to the first conductive area at least from two corner areas.

[0018] In conjunction with the first aspect of the present disclosure, in some embodiments, the polygon is a quadrilateral, and the K group of pads includes: a first group of pads, a second group of pads, a third group of pads, and a fourth group of pads, wherein the first group of pads is arranged opposite to the third group of pads, and the second group of pads is arranged opposite to the fourth group of pads; a first corner region is defined between the first group of pads and the second group of pads, a second corner region is defined between the second group of pads and the third group of pads, a third corner region is defined between the third group of pads and the fourth group of pads, and a fourth corner region is defined between the fourth group of pads and the first group of pads. The second conductive region is connected to the first conductive region at the first corner region, the third corner region, and the fourth corner region.

[0019] In combination with the first aspect of the present disclosure, in some embodiments, the timing controller includes: N groups of signal transmission pins, the N groups of signal transmission pins include M groups of vacant pins, the vacant pins are grounded, wherein M and N are integers greater than or equal to 2.

[0020] In combination with the first aspect of the present disclosure, in some embodiments, the number of the vacant pins is m, and the number of the signal transmission pins is n, wherein the ratio of m to n is greater than or equal to 0.25.

[0021] In combination with the first aspect of the present disclosure, in some embodiments, the timing controller is configured to detect whether the data enable signal from the differential signal receiving pin of the display interface is abnormal; if abnormal, determine whether the duration of the abnormality exceeds a preset time value; if exceeded, control the display panel to display a pre-stored picture, wherein the preset time value is T, the duration of one line cycle of the data enable signal is H, and the ratio of T to H is greater than 2.

[0022] In combination with the first aspect of the present disclosure, in some embodiments, the ratio of T to H is 3-10.

[0023] In combination with the first aspect of the present disclosure, in some embodiments, each conductive layer of the printed circuit board is provided with a first conductive area serving as a first grounding terminal and a second conductive area serving as a second grounding terminal, the first conductive areas of each conductive layer of the printed circuit board are electrically connected, and the second conductive areas of each conductive layer of the printed circuit board are electrically connected; the second conductive area is configured to be electrically connected to the backplane of the backlight module; and the spacing distance between the first conductive area and the second conductive area is greater than 0.2 mm.

[0024] In combination with the first aspect of the present disclosure, in some embodiments, the spacing distance between the first conductive region and the second conductive region is 3 to 5 mm.

[0025] In combination with the first aspect of the present disclosure, in some embodiments, the first conductive layer is further provided with a first resistance pad corresponding to each group of the common-mode inductor pads, and the first resistance pad includes: a first connection end pad and a second connection end pad; the input end pad and the first connection end pad are electrically connected to the differential signal receiving pad through the first differential signal line, and the output end pad and the second connection end pad are electrically connected to the differential signal transmission pad through the second differential signal line.

[0026] In combination with the first aspect of the present disclosure, in some embodiments, the input-end pad at least partially overlaps with the first connection-end pad, and the output-end pad at least partially overlaps with the second connection-end pad.

[0027] In combination with the first aspect of the present disclosure, in some embodiments, the first conductive layer is further provided with a first conductive region serving as a first ground terminal and a second conductive region serving as a second ground terminal; the second conductive region is configured to be grounded; the display driving board further includes: an electrostatic attenuation device, the electrostatic attenuation device being electrically connected between the first conductive region and the second conductive region, the electrostatic attenuation device including at least one of a magnetic bead, a jumper resistor, and a capacitor.

[0028] In combination with the first aspect of the present disclosure, in some embodiments, the first conductive layer is further provided with a magnetic bead pad, a capacitor pad, and a second resistor pad. The magnetic bead pad includes a first magnetic bead pad and a second magnetic bead pad; the second resistor pad includes a first resistor pad and a second resistor pad; the capacitor pad includes a first capacitor pad and a second capacitor pad; the first magnetic bead pad, the first resistor pad, and the first capacitor pad at least partially overlap with the first conductive region; the second magnetic bead pad is electrically connected to the second conductive region via a first connecting line; the second resistor pad is electrically connected to the second conductive region via a second connecting line; and the second capacitor pad is electrically connected to the second conductive region via a third connecting line.

[0029] In combination with the first aspect of the present disclosure, in some embodiments, an opening is provided on one side of the first conductive region close to the second conductive region, and the magnetic bead pad, the capacitor pad and the second resistor pad are arranged in the opening; and the spacing between adjacent pads among the magnetic bead pad, the capacitor pad and the second resistor pad is 0.5 to 3 mm.

[0030] In a second aspect of the present disclosure, a display module is provided, comprising: a display panel and the display driver board provided in the first aspect of the present disclosure, wherein the display driver board is electrically connected to the display panel.

[0031] In combination with the second aspect of the present disclosure, in some embodiments, the display module further includes a backplane; an insulating coating layer disposed on a surface of the display driving board close to the backplane; and an insulating gasket disposed between the insulating coating layer and the backplane.

[0032] In combination with the second aspect of the present disclosure, in some embodiments, the display module further includes: a back panel; a packaging cover plate, the display driver board is arranged in a accommodating space formed between the packaging cover plate and the back panel; and a packaging tape, attached to a side of the packaging cover plate away from the display driver board, and a portion of the packaging tape that exceeds the packaging cover plate is attached to the back panel.

[0033] In a third aspect of the present disclosure, a display device is provided, comprising: the display module provided in the second aspect of the present disclosure.

[0034] The above description is only an overview of the technical solutions provided by some embodiments of the present disclosure. In order to more clearly understand the technical means of the embodiments of the present disclosure, they can be implemented in accordance with the contents of the specification. In order to make the embodiments of the present disclosure more obvious and easy to understand, the specific implementation methods of the embodiments of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] FIG1 shows a graph showing a current variation of ESD;

[0037] FIG2 shows a rear view of a display module according to some embodiments of the present disclosure;

[0038] FIG3 shows a circuit block diagram of a display driver board according to some embodiments of the present disclosure;

[0039] FIG4 shows a connection diagram of a common-mode inductor according to some embodiments of the present disclosure;

[0040] FIG5 shows a pin diagram of a common-mode inductor according to some embodiments of the present disclosure;

[0041] FIG6 shows a schematic structural diagram of a display driver board according to some embodiments of the present disclosure;

[0042] 7A to 7D illustrate layouts of printed circuit boards according to some embodiments of the present disclosure;

[0043] FIG8 shows a connection diagram of an electrostatic attenuation device according to some embodiments of the present disclosure;

[0044] FIG9 shows a waveform diagram of a signal subjected to ESD interference during an ESD test;

[0045] FIG10 shows a timing diagram of signal transmission between the mainboard and the display module;

[0046] FIG11 shows a waveform diagram of a DE signal according to some embodiments of the present disclosure;

[0047] FIG12 shows a product driving timing diagram according to some embodiments of the present disclosure;

[0048] FIG13 shows a partial schematic diagram of a first conductive layer according to some embodiments of the present disclosure;

[0049] FIG14 shows a partial enlarged view of the dotted line box area in FIG13 ;

[0050] FIG15A shows a schematic diagram of a stack of printed circuit boards according to some embodiments of the present disclosure;

[0051] FIG15B shows a partial schematic diagram of a first conductive layer according to some other embodiments of the present disclosure;

[0052] FIG15C shows a partial schematic diagram of a third conductive layer according to some embodiments of the present disclosure;

[0053] FIG15D shows a schematic diagram of stacking of printed circuit boards according to other embodiments of the present disclosure;

[0054] FIG15E shows a schematic diagram of stacking of printed circuit boards according to still other embodiments of the present disclosure;

[0055] FIG15F shows a schematic diagram of stacking of printed circuit boards according to some other embodiments of the present disclosure;

[0056] FIG16 shows another partial schematic diagram of the first conductive layer according to some embodiments of the present disclosure;

[0057] FIG17A shows another partial schematic diagram of the first conductive layer according to some embodiments of the present disclosure;

[0058] FIG17B shows another partial schematic diagram of the first conductive layer according to other embodiments of the present disclosure;

[0059] FIG18 shows a cross-sectional schematic diagram of a display module according to some embodiments of the present disclosure;

[0060] FIG19 shows a schematic plan view of an insulating spacer according to some embodiments of the present disclosure;

[0061] FIG20 shows a schematic plan view of an insulating coating layer according to some embodiments of the present disclosure;

[0062] FIG21 shows a schematic cross-sectional view of a display module according to some other embodiments of the present disclosure; and

[0063] FIG22 shows a schematic structural diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0064] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0065] It should be noted that the term "and / or" appearing in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. "At least one" includes one or more situations, and "at least two" and "a plurality" include two or more situations. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0066] As used herein, "about" and "slightly greater than" include the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] The terms "equal" and "same" as used herein include the stated conditions and conditions similar to the stated conditions, where the range of the similar conditions is within an acceptable range of deviation, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "equal" includes absolute equality and approximate equality, where the acceptable range of deviation for approximate equality can include, for example, a difference between two conditions that is less than or equal to 5% of either condition.

[0068] It should be understood that in the exemplary embodiments of the present disclosure, when a layer or element is referred to as being on another layer or substrate, the layer or element may be directly on the other layer or substrate, or an intervening layer may exist between the layer or element and the other layer or substrate. "The orthographic projection of B is within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0069] Figure 1 shows the current variation curve of ESD, with the horizontal axis being time and the vertical axis being current. ESD is a process characterized by high potential, strong electric field, and instantaneous high current. As shown in Figure 1, at t s In less than 1ns (approximately 0.7 to 1ns), the voltage is instantly boosted to several kV. The instantaneous pulse current generated during the discharge process can reach tens or even hundreds of amperes, which can be fatal to semiconductor process devices. If this discharge current enters the input terminal of the integrated circuit, it can seriously burn the chip, or at least interfere with the normal operation of the chip, causing voltage misidentification or logic circuit lockup.

[0070] TFT-LCDs are semiconductor devices with thin-film transistors (TFTs) installed in the pixel areas of the display panel and the gate driver on array (GOA) area on the array substrate. The routing and patterning of the TFTs' insulating, semiconductor, and conductive layers, such as metal or transparent conductive layers, are also susceptible to ESD interference. LCDs use progressive scanning, achieving normal display according to pre-set timing. ESD interference can cause momentary signal timing disruptions, resulting in momentary display flickering. These abnormalities will automatically return to normal after the discharge is complete.

[0071] In this regard, some embodiments of the present disclosure attempt to design a series of ESD protection measures in the display module. For example, a transient voltage suppression device such as a transient voltage suppression diode (TVS) is set in the display driver board, such as adding a TVS tube connected to the ground at the power output position; and adding ESD energy absorption devices such as TVS tubes at the input signal position of the display interface such as the Low-Voltage Differential Signaling (LVDS) interface or the embedded display interface (eDP). For another example, a 100Ω~1K resistor is connected in series with the relevant signal connected to the motherboard, as well as a resistor and capacitor network to the ground, to limit current and absorb ESD transient high current interference. For another example, conductive foam or conductive tape can be used to establish additional conductive pathways. For example, conductive tape can be used to connect the exposed copper area of ​​the display driver board and the backplane of the backlight module, thereby establishing more connections between the display driver board and other devices and the module backplane, and establishing more conductive paths for ESD transient interference, which can be discharged to the backlight backplane, reducing interference with electronic devices and signals in the display panel and display driver board.

[0072] However, these ESD protection measures are primarily designed to prevent burnout of electrical components within display modules, but ESD interference with display signals can still occur. With the advancement of display technology, many application areas, such as rail transit and medical equipment, are placing higher demands on display modules' ESD resistance.

[0073] Based on this, in order to further improve the display module's ability to resist ESD interference and reduce the problem of display flickering caused by ESD interference, some embodiments of the present disclosure provide a display driver board, display module, and display device. Below, with reference to the accompanying drawings, the display driver board, display module, and display device provided by some embodiments of the present disclosure are described in detail.

[0074] Some embodiments of the present disclosure provide a display module, which may include: a display panel, a backlight module, and a display driver board. The display panel is disposed on the light-emitting side of the backlight module. In some embodiments, the display panel is a liquid crystal display panel.

[0075] The backlight module includes a back plate and a backlight source, which provides backlight for the display panel. In some embodiments, the backlight module is an edge-lit backlight module, in which case the backlight source can be a light bar.

[0076] FIG2 shows a back view of the display module 1 according to some embodiments of the present disclosure. As shown in FIG2 , the display driver board 10 is arranged on the side of the back plate 310 away from the display panel, that is, on the backlight side of the backlight module. The backlight side and the light-emitting side of the backlight module are opposite sides. In some embodiments, the display driver board 10 can be connected to the back plate 310 by screws; in other embodiments, the display driver board 10 can also be bonded to the back plate 310 by conductive adhesive; this embodiment does not limit this.

[0077] In some embodiments, the display module 1 may further include: a flexible printed circuit 200 (FPC) and a source driver chip 220 (Source IC). Each source driver chip 220 is disposed on a flexible printed circuit 200, one end of the flexible printed circuit 200 is bound and connected to a binding area on the display driver board 10, and the other end is bound and connected to the display panel, so that each source driver chip 220 is electrically connected to multiple data lines in the display panel. Through the binding connection between the flexible printed circuit 200, the display driver board 10, and the display panel, the display control signal output by the display driver board 10 can be transmitted to the gate driver circuit 210 of the display panel, the data signal output by the display driver board 10 can be transmitted to the source driver chip 220, and the data voltage signal output by the source driver chip 220 can be transmitted to the data line in the display panel, thereby driving the display panel to display an image.

[0078] The number of source driver chips 220 in the display module 1 can be one or more (e.g., 4, 6, or 8, etc.), depending on the actual product needs, and this embodiment does not impose any restrictions on this. In some embodiments, for a 15.8-inch display panel, the source driver can use four source driver chips 220, and the gate driver can use a GOA circuit integrated in the border area of ​​the display panel. Accordingly, four flexible circuit boards 200 and one display driver board 10 can be used.

[0079] Some embodiments of the present disclosure provide a display driver board 10, which includes: a printed circuit board 100 (PCB) and a display interface 110, a timing controller IC 130 (TCON IC), and a common-mode inductor 120 arranged on the PCB 100. The display interface 110 is a signal input interface of the display driver board 10 and is configured to receive signals transmitted by the mainboard. The display interface 110 includes at least one group of differential signal receiving pins to receive display differential signals transmitted by the mainboard. The timing controller 130 includes: differential signal transmission pins corresponding to each group of differential signal receiving pins. The PCB 100 includes: at least one group of differential signal lines to transmit differential signals; each group of differential signal lines includes: a first differential signal line and a second differential signal line, the first differential signal line electrically connecting the differential signal receiving pin and the input end of the common-mode inductor 120, and the second differential signal line electrically connecting the output end of the common-mode inductor 120 and the differential signal transmission pin of the timing controller 130.

[0080] In some embodiments, the display driving board 10 may be a circuit board (PCB+Assembly, PCBA for short) assembled with various electronic components through a surface mounting process.

[0081] In some embodiments, the display interface 110 may be an LVDS interface or an eDP interface, etc. Each group of differential signal receiving pins of the display interface 110 corresponds to a group of differential signal channels (Lane). For example, the display interface 110 may be 1Lane, 2Lane or 4Lane, etc. Taking the liquid crystal display module 1 with a resolution of 2560×600 and a refresh rate of 60Hz as an example, the total bandwidth needs to adopt a 4Lane display interface 110. At this time, the display interface 110 can receive and transmit four pairs of display differential signals to the timing controller 130 through four groups of differential signal receiving pins, and each pair of display differential signals includes: a positive (Positive) signal and a negative (Negative) signal. Accordingly, each group of differential signal channels includes a first sub-channel and a second sub-channel, which output a positive (Positive) signal and a negative (Negative) signal, respectively.

[0082] FIG3 shows a circuit block diagram of a display driver board 10 according to some embodiments of the present disclosure. As shown in FIG2 and FIG3 , the display driver board 10 may include a printed circuit board 100 and a display interface 110, a timing controller 130, and a common-mode inductor 120 disposed on the printed circuit board 100. In some embodiments, the display interface 110, the timing controller 130, and the common-mode inductor 120 may be soldered to corresponding pads disposed on the printed circuit board 100. In some embodiments, the common-mode inductor 120 may be disposed on the printed circuit board 100 between the display interface 110 and the timing controller 130 to minimize the wiring length and reduce interference to the display differential signal during transmission.

[0083] After research, the inventors found that ESD interference with the differential signal input to the timing controller 130 is one of the main reasons for screen flicker during ESD testing. When performing an ESD test on the display module 1, the test is usually performed in the BIST (Built in Self Test) display mode to confirm whether the direct cause of the module screen flicker is external or internal to the module. The BIST display mode can be set to display five solid color images of black, white, red, green and blue in a loop, for example, it can be set to display in a loop at intervals of 1s or 2s. These images are stored in the timing controller 130 and belong to the built-in test images of the timing controller 130. Usually, when the input signal of the timing controller 130 is abnormal, the timing controller 130 will be triggered to enter the BIST display mode.

[0084] Experiments have shown that the degree of screen flickering tested in BIST display mode is significantly lower than that tested in normal display mode. This is because the display differential signals from the entire system motherboard are more susceptible to ESD interference. The entire system ESD test points are the entire system frame and backplane 310. ESD interferes with the display differential signals and transmission cables through direct coupling between the motherboard and the display driver board 10 (also known as the TCON board), as well as indirect coupling through the backplane 310. This causes the differential signals to experience timing disruption due to ESD interference. Introducing a common-mode inductor 120 between the display interface 110 and the timing controller 130 can effectively reduce the impact of ESD interference on the differential signals.

[0085] Common-mode inductor 120, also known as a common-mode choke, suppresses common-mode signals and prevents them from transmitting through it. However, differential-mode signals are not suppressed and can be transmitted normally. Common-mode inductor 120 is used in switching power supplies to filter common-mode electromagnetic interference (EMI) and to suppress electromagnetic interference (EMI) on high-speed signal lines. It offers low impedance for differential-mode signals and high impedance for common-mode signals.

[0086] By connecting common-mode inductor 120 in series between timing controller 130 and display interface 110, the aforementioned characteristics of common-mode inductor 120 can be leveraged to significantly improve ESD interference filtering in display differential signals. ESD interference appears as a common-mode signal to common-mode inductor 120 and is effectively filtered out by it, while differential signals can still be transmitted normally. This reduces ESD interference on differential signals and mitigates display flickering caused by ESD interference.

[0087] In some embodiments, the display driver board 10 may further include: an electrostatic protection device 111, the input end of the electrostatic protection device 111 is electrically connected to the display interface 110, and the output end of the electrostatic protection device 111 is connected to the input end of the common-mode inductor 120. At this time, the display differential signal input from the outside of the display driver board 10 passes through the display interface 110 and the electrostatic protection device 111, enters the common-mode inductor 120, and then enters the timing controller 130 after passing through the common-mode inductor 120. By superimposing the common-mode inductor 120 and the electrostatic protection device 111 between the timing controller 130 and the display interface 110, it is beneficial to further suppress ESD interference in the display differential signal. In some embodiments, the electrostatic protection device 111 can be a TVS tube or other applicable transient voltage suppression device.

[0088] It should be noted that conventional TVS tubes are parallel devices connected to the ground for transmitting signals. If a TVS tube is simply set between the timing controller 130 and the display interface 110, while the TVS tube absorbs electrostatic energy, the timing controller 130 will still be affected by instantaneous ESD interference and affect the display effect. The common-mode inductor 120 is a series device for transmitting signals. For the common-mode inductor 120, ESD interference has been greatly suppressed after passing through the common-mode inductor 120. The display differential signal transmitted to the timing controller 130 is a signal with greatly suppressed ESD interference. Therefore, compared with the conventional design with only TVS tubes, setting the common-mode inductor 120 in the display driver board 10 is conducive to significantly improving the anti-ESD interference capability of the display module 1.

[0089] In some embodiments, the display interface 110 is an eDP interface, and the display differential signal is an eDP signal. The eDP signal is a differential signal with a relatively high transmission rate, for example, it can reach above 100 MHz. In this case, the display driver board 10 may further include: a coupling capacitor connected in series between the common-mode inductor 120 and the timing controller 130. After passing through the coupling capacitor, the DC component in the eDP signal can be filtered out, leaving only the AC component. The timing controller 130 receives the AC component of the eDP signal for data processing.

[0090] In some embodiments, the display interface 110 includes multiple groups of differential signal receiving pins. Accordingly, multiple common-mode inductors 120 are provided. The timing controller 130 also includes multiple groups of differential signal transmission pins. The display differential signal is transmitted between each group of differential signal receiving pins and the corresponding differential signal transmission pins through the above-mentioned group of differential signal lines.

[0091] In some embodiments, the printed circuit board 100 includes multiple groups of differential signal lines, and the length difference between different groups of differential signal lines is less than or equal to 20 mils, for example, 1 mil, 3 mils, 5 mils, 7 mils, 10 mils, 15 mils, or 20 mils. The term "mil" herein refers to a unit of length or thickness, where 1 mil = 1 / 1000 inch = 0.0254 millimeter. In some embodiments, the length of a group of differential signal lines can be the sum of the lengths of a first differential signal line and a second differential signal line.

[0092] It should be noted that the first differential signal line further includes a first sub-signal line and a second sub-signal line, and the second differential signal line further includes a third sub-signal line and a fourth sub-signal line. The sum of the lengths of the first sub-signal line and the third sub-signal line is a first length value, and the sum of the lengths of the second sub-signal line and the fourth sub-signal line is a second length value. The sum of the lengths of the first differential signal line and the second differential signal line can be: the average of the first length value and the second length value, or the cumulative sum of the first length value and the second length value, or the maximum or minimum value of the first length value and the second length value, determined according to actual needs, and this disclosure does not impose any restrictions on this.

[0093] In some embodiments, for the same group of differential signal lines, the difference between the first length value and the second length value is less than or equal to 10 mil, for example, it can be 1 mil, 2 mil, 3 mil, 4 mil, 5 mil, 8 mil or 10 mil.

[0094] By reducing the length difference between pairs of differential signal lines in different groups, and / or reducing the length difference within the same group of differential signal lines, the consistency of signal arrival time can be improved, thereby reducing the risk of abnormalities such as screen flickering and line flickering caused by ESD interference in the back-end timing controller 130.

[0095] FIG4 shows a connection diagram of a common-mode inductor 120 according to some embodiments of the present disclosure. As shown in FIG4 , taking a 4-Lane display interface as an example, namely Lane0, Lane1, Lane2, and Lane3, it is necessary to set up four TVS tubes, respectively represented as TVS0, TVS1, TVS2, and TVS3, and set up four common-mode inductors 120, respectively represented as 120a, 120b, 120c, and 120d. For each pair of differential signals output by the differential signal channel, a common-mode inductor 120 is used for ESD interference filtering. Accordingly, the timing controller 130 includes four groups of differential signal input terminals, namely P0, P1, P2, and P3. Lane0 is electrically connected to P0 through TVS0, 120a, Lane1 is electrically connected to P1 through TVS1, 120b, Lane2 is electrically connected to P2 through TVS2, 120c, and Lane3 is electrically connected to P3 through TVS3, 120d.

[0096] Figure 5 shows a pinout diagram of a common-mode inductor according to some embodiments of the present disclosure. As shown in Figure 5, each common-mode inductor 120 includes two input pins, pin1 and pin3, and two output pins, pin2 and pin4. P and N represent the positive and negative signal lines of a differential signal pair, respectively. Pin1 and pin2 are electrically connected to the positive signal line P, and pin3 and pin4 are electrically connected to the negative signal line.

[0097] As shown in Figure 3, in some embodiments, the display driver board 10 may further include a power management chip (Power Management IC, referred to as PMIC) 150 and a voltage conversion chip (Level Shifter) 140. The power management chip 150 and the voltage conversion chip 140 are also provided on the printed circuit board 100. The timing controller 130 is also electrically connected to the power management chip 150, the voltage conversion chip 140 and the source driver chip 220, respectively. The power management chip 150 is electrically connected to the voltage conversion chip 140 and the source driver chip 220, respectively. The voltage conversion chip 140 is electrically connected to the gate drive circuit 210, and transmits a frame start signal STV and a clock control signal CLK to the gate drive circuit 210. In some embodiments, the gate drive circuit 210 may be a GOA circuit provided in the border area of ​​the display panel. In some embodiments, the power management chip 150 and the voltage conversion chip 140 can use chips with an ESD human body model (HBM) greater than or equal to 3 kilovolts, and the timing controller 130 and the source driver chip 220 can use chips with an ESD HBM greater than or equal to 5 kilovolts to improve the product's anti-ESD interference capability.

[0098] In some embodiments, the display driver board 10 may further include: a backlight driver chip 170 and a power interface 160, and the backlight driver chip 170 and the power interface 160 are also provided on the printed circuit board 100. The power management chip 150 and the backlight driver chip 170 are electrically connected to the power interface 160, respectively. The backlight driver chip 170 is electrically connected to the backlight source 300, and provides a backlight drive signal to the backlight source 300, such as an LED light source, to drive the backlight source 300 to emit light. In other embodiments, the backlight driver chip 170 may also be provided on other circuit boards other than the display driver board 10, and may be provided according to the needs of the actual product, which is not limited in this embodiment.

[0099] In some embodiments, the printed circuit board 100 may include a plurality of conductive layers stacked together, with an insulating layer between adjacent conductive layers, and each conductive layer is provided with a first conductive region serving as a first ground terminal GND and a second conductive region serving as a second ground terminal Ground. The first conductive regions of the conductive layers of the printed circuit board 100 are electrically connected, and the second conductive regions of the conductive layers of the printed circuit board 100 are electrically connected. The first ground terminal GND is the signal ground (also referred to as a reference ground) in the printed circuit board 100. The second ground terminal Ground is grounded, that is, it is configured to be electrically connected to the back panel 310 of the backlight module, and can be referred to as a "shell ground". The back panel 310 can be made of a conductive material such as a metal material. The second ground terminal Ground is electrically connected to the back panel 310 through a conductive structure such as a screw or a conductive tape.

[0100] In some embodiments, the second conductive region is provided with screw holes 1002 that penetrate the printed circuit board 100. This allows the display driver board 10 to be secured to the back plate 310 using conductive screws while simultaneously electrically connecting the second ground terminal Ground to the back plate 310. In other embodiments, the electrical connection between the second ground terminal Ground and the back plate 310 can also be achieved using conductive adhesive, or a combination of conductive adhesive and conductive fabric. This configuration is determined based on actual product needs and is not limited in this disclosure.

[0101] In each conductive layer of the printed circuit board 100, the first conductive area and the second conductive area are spaced apart, that is, a safe distance is left. In some embodiments, the spacing between the first conductive area and the second conductive area can be greater than 0.2 mm. When performing an ESD test on the display module 1, sparks caused by power outages can usually be seen. By increasing the spacing between the first conductive area and the second conductive area, that is, increasing the safe distance between the first ground terminal GND and the second ground terminal Ground, the impact of power outage interference on the signal ground can be effectively reduced, thereby reducing the screen flickering problem caused by significant interference to the signal ground.

[0102] It should be noted that the spacing between the first conductive region and the second conductive region can be set according to the tripping distance. In some embodiments, the spacing between the first conductive region and the second conductive region can be 3 to 5 mm, for example, 3 mm, 4 mm, or 5 mm, etc. This can meet the layout requirements of the printed circuit board 100 while minimizing tripping and reducing the impact of tripping interference on the signal ground of the display driver board 10.

[0103] In some embodiments, the printed circuit board 100 used by the display driver board 10 can be a multi-layer board, that is, it includes multiple conductive layers, and each conductive layer is provided with the above-mentioned first conductive area and second conductive area. Correspondingly, the spacing between the first conductive area and the second conductive area of ​​each conductive layer can be 3 to 5 mm. In some embodiments, the display driver board 10 can use a four-layer board, from the top to the bottom, respectively, the device layer (Top layer), the power layer (Layer 2), the ground layer (Layer 3) and the signal layer (BOT layer); each layer is provided with a first conductive area, and a second conductive area is provided at the corresponding position, and the second conductive area of ​​each layer overlaps the orthographic projection boundary on the printed circuit board 100 substrate 101.

[0104] It is understood that the display module 1 has an ESD discharge path from the inside out and an ESD interference path from the outside in. The ESD discharge path is as follows: ESD within the display panel passes through → the first ground terminal GND on the printed circuit board 100 → the second ground terminal Ground on the printed circuit board 100 → the backplane 310. The ESD interference path is as follows: the frame of the display module 1 → the backplane 310 → the printed circuit board 100, thereby affecting the integrated circuit devices (ICs) installed on the printed circuit board 100.

[0105] In some embodiments, to provide more ESD discharge paths, the printed circuit board 100 includes multiple, independently configured second ground terminals, Ground. ESD within the display module 1 can be transferred to the backplane 310 through these second ground terminals for discharge. The first ground terminal GND in the printed circuit board 100 can be a sheet-shaped conductive area, and the second ground terminal Ground can be a relatively smaller conductive area spaced apart from the first ground terminal GND. The second ground terminals Ground can be located at the edge of the printed circuit board 100.

[0106] FIG6 shows a schematic diagram of the structure of the display driver board according to some embodiments of the present disclosure. As shown in FIG6 , the printed circuit board 100 of the display driver board 10 can be in the shape of a bar, which includes two long sides arranged opposite to each other and two short sides arranged in two pairs. A binding area 1001 is provided on one of the long sides to bind with the flexible circuit board 200. In some embodiments, the display interface 110 can be provided on one of the short sides of the printed circuit board 100; along the long side direction, the distance between the timing controller 130 and the display interface 110 can be less than one-third of the length of the long side of the printed circuit board 100; the common-mode inductor 120 can be provided between the display interface 110 and the timing controller 130, close to the display interface 110, so as to absorb ESD interference in a timely manner. The spacing between the common-mode inductor 120 and the timing controller 130 is combined with the actual layout space so that the timing controller 130 is as close to the common-mode inductor as possible to minimize the transmission distance of the display differential signal and reduce the probability of the display differential signal being interfered with by ESD. For example, according to the shortest design principle, the distance between the common mode inductor 120 and the timing controller 130 may be 14-16 mm, such as 14 mm, 15 mm, or 16 mm.

[0107] A second conductive area (i.e., the second ground terminal Ground) is provided in the middle position of the long side with the binding area 1001, two second conductive areas are provided on the other long side, and a second conductive area is provided at each of the four corners of the strip, for a total of seven independent second conductive areas. The distance d marked in FIG6 represents the spacing distance between the first conductive area serving as the first ground terminal GND and the second conductive area serving as the second ground terminal Ground. Each second conductive area is provided with a screw hole 1002 to assemble the display driver board 10 to the back plate 310 by screws. In addition, in addition to setting the screw hole 1002, positioning holes can also be provided in some second conductive areas. As shown in FIG6, positioning holes can also be provided in the two second conductive areas on the long side where the binding area 1001 is not provided to facilitate positioning. Of course, in addition to the arrangement of the second conductive areas shown in FIG6, other methods can also be used to arrange more or fewer second conductive areas, which can be arranged according to actual needs, and this embodiment does not limit this.

[0108] Taking the four-layer printed circuit board 100 described above as an example, Figures 7A to 7D illustrate the layout of the printed circuit board according to some embodiments of the present disclosure. Figure 7A shows the layout of the device layer; Figure 7B shows the layout of the power layer; Figure 7C shows the layout of the ground layer; and Figure 7D shows the layout of the signal layer. As can be seen from Figures 7A to 7D, each conductive layer of the printed circuit board 100 is provided with a sheet-shaped first conductive region (i.e., the first ground terminal GND) and seven independent second conductive regions (i.e., the second ground terminals Ground) disposed at the edge. The second conductive regions of each layer are disposed at the same planar location and have the same size. The spacing between the second conductive regions and the first conductive regions of each conductive layer can be 3 to 5 mm. It should be noted that, in some conductive layers of the printed circuit board 100, to avoid signal lines, the spacing between one or more second conductive regions and the first conductive region can be appropriately reduced compared to the spacing between other second conductive regions. For example, it can be reduced to 1 to 3 mm, such as 1 mm, 2 mm, or 3 mm. For example, the spacing distance between the second conductive region and the first conductive region located in the middle position of FIG. 7B and FIG. 7D is smaller than the spacing distance between other second conductive regions and the first conductive region in the same layer.

[0109] In some embodiments, the display driver board 10 may further include: an electrostatic attenuation device 180. FIG8 shows a connection diagram of the electrostatic attenuation device 180 according to some embodiments of the present disclosure. As shown in FIG8 , the first ground terminal GND and the second ground terminal Ground can be electrically connected through the electrostatic attenuation device 180 and the routing. By increasing the safety distance between the first ground terminal GND and the second ground terminal Ground, and realizing the electrical connection between the first ground terminal GND and the second ground terminal Ground through the routing of the electrostatic attenuation device 180, the ESD interference source can be controlled to be transmitted to the first ground terminal GND along the routing path of the electrostatic attenuation device 180, rather than the two grounds being electrically coupled through any path and affecting each other, which is beneficial to reducing the impact of ESD interference on the display screen. Moreover, since the second ground terminal Ground is electrically connected to the back plate 310, when ESD is coupled from the back plate 310 to the printed circuit board 100 of the display driver board 10, it needs to pass through the electrostatic attenuation device 180 and then reach the first ground terminal GND. This can suppress and attenuate the ESD interference, which is beneficial to improving the anti-ESD interference capability of the display driver board 10, thereby improving the anti-ESD interference capability of the display module 1.

[0110] In some embodiments, the ESD attenuation device 180 may include at least one of a ferrite bead, a jumper resistor (also known as a 0-ohm resistor), and a capacitor. The configuration can be tailored to the needs of the product and ESD test results. In some embodiments, a ferrite bead connection circuit, a jumper resistor connection circuit, and a capacitor connection circuit may be provided between the first ground terminal GND and the second ground terminal Ground on the printed circuit board 100. During use, the ESD attenuation device 180 can be flexibly selected for placement based on actual needs to expand the applicability of the printed circuit board 100.

[0111] It should be noted that ESD testing refers to electrostatic discharge testing, which is a test of the anti-static ability of electronic products. In actual implementation, static electricity can be released from electronic products through an electrostatic discharge gun tip to obtain an ESD test structure. In some application scenarios, ESD test results can be divided into four levels: Class A: No functional defects during the test (especially no screen flicker); Class B: Functional defects during the test are automatically recovered; Class C: Functional defects during the test are recoverable after restart; Class D: Functional defects during the test are not recoverable even after restart.

[0112] For example, for a 15.8-inch QHD (Quarter High Definition) strip screen, if the electrostatic attenuation device 180 selects a 0-ohm resistor, the client ESD test result is: Class A; if the electrostatic attenuation device 180 selects a magnetic bead, the client ESD test is: Class B, and the probability of screen flickering compared to a 0-ohm resistor increases by about 2%. Therefore, in some embodiments, in the display driver board 10 applied to a 15.8-inch QHD strip screen, the electrostatic attenuation device 180 can use a 0-ohm resistor. For another example, for an 86-inch strip screen, the electrostatic attenuation device 180 selects a capacitor, and the client ESD test result is: class B, but compared to selecting a 0-ohm resistor, the probability of screen flickering can be reduced by about 2%. Therefore, in some embodiments, in the display driver board 10 applied to an 86-inch strip screen, the electrostatic attenuation device 180 can use a capacitor.

[0113] The inventors have discovered that during actual use of a display product, ESD interference is coupled through the entire housing to the bezel and backplane 310 of the display module 1, and then to the internal circuit boards, including the entire mainboard and display driver board 10. Therefore, the display differential signal input from the display driver board 10 to the timing controller 130 is subject to ESD interference, resulting in short-term signal anomalies in the timing controller 130. However, since the duration of ESD is typically short, on the order of nanoseconds, the duration of the abnormality caused by ESD interference in the timing controller 130 signal is also relatively short.

[0114] However, when the display module 1 is subjected to an ESD test, the display differential signal transmitted from the entire mainboard to the timing controller 130 in the display driver board 10 is subject to ESD interference. After the display differential signal input to the timing controller 130 is subject to ESD interference, the display control signal output by the timing controller 130, such as the frame start signal STV and the GOA drive signal such as the clock control signal CLK, will also be deformed following the interference jitter of the input signal, causing the display panel to malfunction and the screen to flicker. Figure 9 shows a signal waveform diagram subject to ESD interference during the ESD test. The display differential signal may include: a data signal, a line synchronization signal, a field synchronization signal, a data enable (Data Enable, referred to as DE) signal, and a pixel clock signal. As shown in Figure 9, the pixel clock signal (such as LVDS_CLK in Figure 9) and the clock control signal CLK and the frame start signal STV output by the timing controller 130 will jitter due to ESD interference.

[0115] The signal timing anomaly caused by the transient interference of ESD will trigger the BIST and other protection functions of the timing controller 130, causing the display panel to stop displaying the current frame data during the timing anomaly and instead display a preset test screen (usually a black screen). After the signal returns to normal, it will display the received display data again. This will cause the display screen to flash black and then recover instantly.

[0116] Considering that the duration of ESD interference is very short, viewers who are actually watching the display screen will basically not be able to detect the abnormality of the screen. Instead, triggering the BIST mode will cause unnecessary screen flickering. Therefore, in order to reduce the screen flickering caused by BIST malfunction due to ESD interference and further improve the screen flickering problem of the display module 1, in some embodiments, the timing controller 130 detects whether the DE signal from the differential signal receiving pin of the display interface 110 is abnormal. If it is abnormal, it determines whether the duration of the abnormality exceeds a preset time value. If it exceeds, the display panel is controlled to display a pre-stored screen. The preset time value is T, and the duration of one line cycle of the DE signal is H. The ratio of T to H can be greater than 2, that is, T can be set to more than twice H. If the duration of the abnormality exceeds the preset time value, it means that the current abnormality is not caused by ESD interference, and the BIST display mode is triggered, and the display panel is controlled to display the test screen pre-stored in the memory until the DE signal returns to normal.

[0117] In some embodiments, the display differential signal includes a data signal, a horizontal synchronization signal, a vertical synchronization signal, a DE signal, and a pixel clock signal. The data signal is the current frame display screen signal transmitted from the mainboard. The test screen is a BIST screen pre-stored in the memory of the timing controller 130. In some embodiments, the test screen may include five solid color screens: black, white, red, green, and blue. After triggering the BIST display mode, the timing controller 130 stops display control of the current frame display screen and controls the display panel to display the five solid color screens in a loop until the DE signal returns to normal. It then controls the display panel to display the received display screen frame by frame.

[0118] By modifying the preset time value T configured in the timing controller 130 and delaying the BIST triggering time, the influence of ESD interference can be effectively filtered out, which is beneficial to reducing the screen flickering problem of the display screen.

[0119] Figure 10 shows a timing diagram for signal transmission between the motherboard and the display module. In Figure 10(a), H-Sync represents the horizontal synchronization signal, H_DE represents the horizontal DE signal, and in Figure 10(b), V-Sync represents the vertical synchronization signal, V_DE represents the vertical DE signal. H_DE represents the waveform of one horizontal cycle of V_DE. The timing controller 130 receives signals and data from the motherboard by identifying the DE signal and generates the waveforms required for the display panel drive timing, such as the frame start signal STV and the clock control signal CLK, based on the DE signal.

[0120] Therefore, to prevent display anomalies caused by DE signal anomalies, the timing controller 130 detects DE signal anomalies. When a DE signal anomaly is detected and persists for a certain period of time, a protection function such as the BIST is triggered. There are various ways to detect DE signal anomalies. For example, the DE signal frequency and / or pulse width can be compared with a preset DE signal frequency and / or pulse width. If they differ, the DE signal is determined to be abnormal. This embodiment does not limit this.

[0121] In related technologies, a BIST screen is triggered when an abnormality is detected in the DE signal, specifically when the waveform of one row period of the DE signal is abnormal. For example, for a display product with a 60Hz refresh rate and 1125 pixel rows, the length of one row period of the DE signal (i.e., the charging time for one row of pixels, expressed as 1 hour) is: 1 / 60 / 1125, where " / " represents a division sign.

[0122] The preset time value T can be determined based on the duration of the ESD interference and the duration of one line cycle of the DE signal, and can be pre-configured in the timing controller 130, for example, it can be configured in a register within the timing controller 130. For example, when ESD interference is coupled to a signal, the signal is interfered with for a period of approximately 150μs to 400μs, and gradually decreases over time (as shown in FIG9 ). Taking a 15.8-inch strip screen with a refresh rate of 60Hz and a resolution of 2560×600 as an example, the strip screen includes: 19 empty pixel rows and 600 pixel rows in the display area, for a total of 619 pixel rows. In this case, 1H=1 / 60 / 619=26.9μs.

[0123] In some embodiments, the upper and lower limits of the ESD interference duration can be divided by the timing time of one line cycle, and the calculated results can be rounded. The upper and lower limits of the preset time value can be determined based on the rounded results. 150μs / 26.9μs is approximately equal to 5.6 line cycles, and 400μs / 26.9μs is approximately equal to 14.9 line cycles. Therefore, based on the time length of the signal being affected by ESD interference being 150μs to 400μs, 1H=26.9μs, in some embodiments, the ratio of the preset time value T to the line cycle H can be: 5 to 15, that is, the preset time value can be set to 5 to 15 line cycles, such as 5, 8, 10, 12, or 15 line cycles.

[0124] Considering that the interference of ESD on the signal will gradually decrease over time, when the interference is reduced to an acceptable error range, it will not be determined as an abnormality by the timing controller 130. The ESD interference duration can be divided by the timing time of one line cycle and rounded up. The rounded value is configured as the reference time value in the timing controller 130, and an ESD test is performed. Then, based on the ESD test results, the reference time value is adjusted. For example, when the actual expected ESD test requirements, such as Class A mentioned above, are met, the reference time value can be lowered according to a preset step size, so that the minimum reference time value that can meet the expected ESD test requirements is used as the preset time value. The downward adjustment step size can be set according to actual needs, for example, it can be set to 1 line cycle.

[0125] Therefore, in some embodiments, the ratio of the preset time value T to the row period H can be 3 to 10, that is, the preset time value can be set to 3 to 10 row periods, such as 3, 4, 5, 6, 7, 8, 9, or 10 row periods. This can not only mask the transient abnormal time period of the differential signal caused by ESD interference, preventing the timing controller 130 from triggering the display of the BIST screen when such transient abnormalities occur, filtering out the screen flicker caused by BIST malfunction due to ESD interference, but also reduce the risk of missing detection of other signal abnormalities.

[0126] It should be noted that, in actual implementation, the preset time value may be set based on the above preset time value range, combined with actual test conditions and the actual capabilities of the timing controller 130 .

[0127] Figure 11 shows a waveform diagram of a DE signal according to some embodiments of the present disclosure. In Figure 11, DE0 represents a normal DE signal, DE1 represents a DE signal with an abnormality during one line cycle, and DE2 represents a DE signal with an abnormality during four line cycles. Taking the preset time value as three line cycles as an example, for the DE signals DE0 and DE1 in Figure 11, the timing controller 130 determines that the DE signals are normal and does not trigger the display of the BIST screen. Instead, it receives the current frame display data from the motherboard by identifying the DE signal and generates the waveform required for the display panel drive timing based on the DE signal. However, for DE2 in Figure 11, the timing controller 130 triggers the display of the BIST screen upon detecting an abnormality during three line cycles. This means that the timing controller 130 no longer receives the current frame display data from the motherboard by identifying the DE signal, but instead controls the display panel to display a pre-stored BIST screen. Display of the display data transmitted from the motherboard resumes after detecting that the DE signal has returned to normal.

[0128] Figure 12 shows a product drive timing diagram according to some embodiments of the present disclosure. Figure 12 uses a linear display with a resolution of 2560×600 and six clock signal lines as an example. STV0 is the reset signal (Total Reset), used to reset and reduce noise in the GOA circuit during the blank time between the Nth and N+1th frames, thereby extending product life. STV is the frame start signal; CLK1-6 are clock control signals; VGL is a low-level voltage; and Source Out is the charging voltage signal output by the source driver chip 220. 1 hour is the charging time for a row of pixels, e.g., 1 hour = 1 / 60 / 619 = 26.9 μs. The STV signal is active high, and the high-level width can be 4 hours. The interval between the falling edge of STV0 and the rising edge of STV can be 1 hour. The high-level width of CLK1-6 is 3 hours. During the last 1 hour of each CLK interval, the pixels in the corresponding row of the display panel are charged by the Source Out signal, and this cycle repeats, achieving a refresh of 600 rows of pixels. When the DE signal is abnormal, the STV and CLK1-6 signals generated based on the DE signal (Figure 12) will also be abnormal. The data displayed in the current frame read based on the DE signal will also be abnormal. This indicates that Source Out is abnormal. If the abnormality persists for too long, it will cause an abnormal display. Therefore, setting the preset time value is necessary to promptly trigger the BIST function when the DE signal is abnormal, preventing display abnormalities. It also reduces screen flicker caused by BIST malfunctions due to brief ESD interference.

[0129] In some embodiments, the printed circuit board 100 may include at least a first conductive layer 101. FIG13 illustrates a partial schematic diagram of the first conductive layer according to some embodiments of the present disclosure, and FIG14 illustrates an enlarged partial view of the dashed-line area in FIG13. Referring to FIG13 and FIG14, the first conductive layer 101, serving as a device layer, may be provided with a display interface pad 110P, a timing controller pad 130P, and at least one set of common-mode inductor pads 120P. The display interface 110, the timing controller 130, and the common-mode inductor 120 are provided on corresponding pads on the first conductive layer 101. Specifically, the display interface 110 is soldered to the display interface pad 110P, the timing controller 130 is soldered to the timing controller pad 130P, and the common-mode inductor 120 is soldered to the common-mode inductor pad 120P. In some embodiments, the at least one set of common-mode inductor pads 120P may be located between the display interface pad 110P and the timing controller pad 130P.

[0130] In some embodiments, the first differential signal line and the second differential signal line may be located on the first conductive layer 101. The display interface pads 110P may include: differential signal receiving pads soldered to each set of differential signal receiving pins. Each set of common mode inductor pads 120P includes an input pad and an output pad. The timing controller pads 130P may include: differential signal transmission pads soldered to each set of differential signal transmission pins. The first differential signal line electrically connects the differential signal receiving pad to the input pad, and the second differential signal line electrically connects the output pad to the differential signal transmission pad.

[0131] In some embodiments, the first conductive layer 101 is further provided with first resistor pads corresponding to each group of common-mode inductor pads 120P. The first resistor pads include a first connection pad and a second connection pad. The input pad and the first connection pad are electrically connected to the differential signal receiving pad via a first differential signal line, and the output pad and the second connection pad are electrically connected to the differential signal transmitting pad via a second differential signal line.

[0132] Since soldering a common-mode inductor requires four pads, while soldering a resistor only requires two pads, each set of common-mode inductor pads 120P corresponds to two first resistor pads. It should be noted that the first resistor pads are reserved pads. This allows for flexible selection of whether to connect one common-mode inductor 120 or two jumper resistors to each set of differential signal transmission lines between the display interface 110 and the timing controller 130, depending on the needs of the actual product, when manufacturing the display driver board 10. This helps expand the range of display products for which the printed circuit board 100 is applicable.

[0133] In some embodiments, for each set of common-mode inductor pads 120P and its corresponding first resistor pad, the input pad at least partially overlaps with the first connection pad, and the output pad at least partially overlaps with the second connection pad. This can save space for device and circuit layout on the first conductive layer 101.

[0134] In some embodiments, each set of differential signal receiving pads may include a first sub-channel pad K1 and a second sub-channel pad K2. Common-mode inductor pads 120P may include a first sub-pad P1, a second sub-pad P2, a third sub-pad P3, and a fourth sub-pad P4. First sub-pad P1 and third sub-pad P3 are used to solder the two input pins, pin1 and pin3, of the common-mode inductor 120, and serve as input pads. Second sub-pad P2 and fourth sub-pad P4 are used to solder the two output pins, pin2 and pin4, of the common-mode inductor 120, and serve as output pads. Each set of differential signal transmission pads may include a first sub-input pad M1 and a second sub-input pad M2. The first differential signal line S1 includes a first sub-signal line S11 and a second sub-signal line S12 arranged in parallel. The second differential signal line S2 includes a third sub-signal line S21 and a fourth sub-signal line S22 arranged in parallel. The first sub-channel pad K1 is electrically connected to the first sub-pad P1 via the first sub-signal line S11, and the second sub-channel pad K2 is electrically connected to the third sub-pad P3 via the second sub-signal line S12. The second sub-pad P2 is electrically connected to the first sub-input pad M1 via the third sub-signal line S21, and the fourth sub-pad P4 is electrically connected to the second sub-input pad M2 via the fourth sub-signal line S22.

[0135] The number of groups of the common-mode inductor pad 120P, the first differential signal line S1 and the second differential signal line S2 can be determined according to the number of differential signal channels of the display interface 110 . FIG. 13 illustrates a 4-Lane display interface as an example.

[0136] As shown in FIG14 , each group of common-mode inductor pads 120P corresponds to two first resistor pads, one of which includes a fifth sub-pad P5 (i.e., the first connection end pad) and a sixth sub-pad P6 (i.e., the second connection end pad), and the other first resistor pad includes a seventh sub-pad P7 (i.e., the first connection end pad) and an eighth sub-pad P8 (i.e., the second connection end pad). In some embodiments, the first sub-pad P1 can at least partially overlap with the fifth sub-pad P5; the second sub-pad P2 can at least partially overlap with the sixth sub-pad P6; the third sub-pad P3 can at least partially overlap with the seventh sub-pad P7; and the fourth sub-pad P4 can at least partially overlap with the eighth sub-pad P8. At least partial overlap between the pads means that the pads themselves are electrically connected. This allows the common-mode inductor 120 and the jumper resistor to share the same connection line, simply replacing the welding components, avoiding additional signal transmission differences and saving wiring space.

[0137] As shown in FIG14 , the first sub-pad P1, the second sub-pad P2, the third sub-pad P3, and the fourth sub-pad P4 can be rectangular in shape and located within the silk-screen frame corresponding to the common-mode inductor 120. The fifth sub-pad P5, the sixth sub-pad P6, the seventh sub-pad P7, and the eighth sub-pad P8 can be square in shape and located within the silk-screen frame corresponding to the two first resistor pads, respectively. According to the positions of the two pads in FIG13 , the upper right corner of the first sub-pad P1 can overlap with the lower left corner of the fifth sub-pad P5; the upper left corner of the second sub-pad P2 can overlap with the lower right corner of the sixth sub-pad P6; the lower right corner of the third sub-pad P3 can overlap with the upper left corner of the seventh sub-pad P7; and the lower left corner of the fourth sub-pad P4 can overlap with the upper right corner of the eighth sub-pad P8, thereby saving pad layout space.

[0138] Figure 15A shows a schematic diagram of the stacking of a printed circuit board according to some embodiments of the present disclosure. It should be noted that Figure 15A only illustrates the conductive layers included in the printed circuit board 100, and an insulating layer (not shown in the figure) is also provided between adjacent conductive layers. As shown in Figure 15A, in some embodiments, the printed circuit board 100 may further include: a second conductive layer 102 stacked with the first conductive layer 103, and a third conductive layer 103 located between the first conductive layer 101 and the second conductive layer 102.

[0139] In some embodiments, at least the second differential signal line S2 can be located in the third conductive layer 103; the output pad of the common-mode inductor 120 is electrically connected to one end of the second differential signal line S2 through a first via V1; and the differential signal transmission pad of the timing controller 130 is electrically connected to the other end of the second differential signal line S2 through a second via V2. In some embodiments, the diameters of the first and second vias V1 and V2 can be greater than 0 and less than or equal to 2.5 mm to minimize parasitic capacitance introduced by the vias and reduce interference with the transmitted display differential signal. For example, the diameters of the first and second vias V1 and V2 can be 1 mm, 1.5 mm, 2 mm, or 2.5 mm, etc., and can be determined based on actual product requirements and process conditions.

[0140] In some embodiments, the first conductive layer, the second conductive layer, and the third conductive layer all serve as signal routing layers of the printed circuit board 100 to provide more routing space, thereby facilitating reduction of interference between signal lines.

[0141] Figure 15B shows a partial schematic diagram of the first conductive layer 101 according to other embodiments of the present disclosure, and Figure 15C shows a partial schematic diagram of the third conductive layer 103 according to some embodiments of the present disclosure. As shown in Figures 15B and 15C, the output pad of the common-mode inductor 120 is electrically connected to one end of the second differential signal line S2 located in the third conductive layer 103 through a first via V1, and the other end of the second differential signal line S2 is electrically connected to the differential signal receiving pad of the timing controller 130 through a second via V2. It should be noted that the number of signal lines and routing paths shown in Figure 15C is for reference only and will be determined based on actual product requirements. For example, the number of second differential signal lines S2 needs to be determined based on the actual display differential signal channels of the display interface 110.

[0142] Display differential signals such as LVDS signals or Edp signals are easily affected by electromagnetic interference, causing decoding errors in the back-end timing controller 130. Data decoding errors may cause display screen abnormalities, flashing lines, flashing screens, and flashing black screens. The second differential signal line S2 is arranged on the internal third conductive layer 103. Compared with being arranged on the top or bottom layer, it is less susceptible to external electromagnetic interference such as ESD interference, which is beneficial to reducing the screen flashing problem caused by external electromagnetic interference on the display differential signal.

[0143] In some embodiments, considering that the display differential signal transmitted by the first differential signal line S1 can be filtered for common-mode interference through the common-mode inductor 120, the first differential signal line S1 can be arranged on the first conductive layer 101. This can reduce the transmission of the display differential signal through the layer, which is beneficial to ensuring the signal quality. In some embodiments, after the display differential signal enters the display interface 110 on the display driver board from the mainboard connection line, it passes through the first differential signal line S1 and the electrostatic protection device 111 and the common-mode inductor 120 connected to the first differential signal line S1 in the first conductive layer 101, and then enters the second differential signal line S2 of the third conductive layer 103 through the first via V1 for transmission, and then is transmitted to the timing controller 130 set on the first conductive layer 101 through the second via V2. Of course, in other embodiments, the first differential signal line S1 can also be arranged on the third conductive layer 103, and this embodiment does not limit this.

[0144] In some embodiments, the printed circuit board 100 may further include a fourth conductive layer 104 and a fifth conductive layer 105. The fourth conductive layer 104 is located on a side of the third conductive layer 103 close to the first conductive layer 101, and the fifth conductive layer 105 is located on a side of the third conductive layer 103 close to the second conductive layer 102. The fourth conductive layer 104 and the fifth conductive layer 105 serve as the ground layer of the printed circuit board 100.

[0145] The fourth conductive layer 104 and the fifth conductive layer 105 can be designed to be substantially entirely copper-clad. This allows the second differential signal line S2 to be shielded by two layers of ground, one above the other, effectively shielding it from external electromagnetic interference signals. Furthermore, by substantially cladding the fourth conductive layer 104 and the fifth conductive layer 105 with copper as the reference plane ground (i.e., the "signal ground" discussed above), the area of ​​the reference ground of the third conductive layer 103 can be significantly increased, ensuring a more stable reference ground for the third conductive layer 103. This helps prevent data decoding errors caused by external radiation interference or changes in the reference ground, which could result in erroneous data display, in the display differential signals transmitted to the timing controller 130.

[0146] In some embodiments, the printed circuit board 100 may further include a sixth conductive layer 106, which serves as a power supply layer for the printed circuit board 100. As shown in FIG15A , the sixth conductive layer 106 may be stacked between the fifth conductive layer 105 and the second conductive layer 102. In this case, one of the first conductive layer 101 and the second conductive layer 102 is a top layer, and the other is a bottom layer.

[0147] FIG15D illustrates a schematic diagram of the stacking of printed circuit board 100 according to other embodiments of the present disclosure. As shown in FIG15D , unlike the arrangement shown in FIG15A , sixth conductive layer 106 may also be located between third conductive layer 103 and fifth conductive layer 105. This allows second conductive layer 102 to also have an adjacent ground layer, which helps reduce ESD interference to signals transmitted in second conductive layer 102. In some embodiments, printed circuit board 100 further includes a first insulating layer and multiple second insulating layers, wherein the first insulating layer is located between sixth conductive layer 106 and third conductive layer 103. The multiple second insulating layers are insulating layers between adjacent conductive layers of printed circuit board 100, excluding the first insulating layer.

[0148] In some embodiments, the thickness of the first insulating layer can be greater than the thickness of the second insulating layer. That is, the insulating layer between the third conductive layer 103 and the sixth conductive layer 106 serving as the power layer is thicker than the other insulating layers. For example, the thickness of the first insulating layer can be greater than or equal to 15 mils, which helps prevent crosstalk between the power signal and the differential signal. In some embodiments, the thickness ratio of the first insulating layer to the second insulating layer can be 4 to 6. For example, the thickness of the first insulating layer can be 4 times, 5 times, 5.5 times, or 6 times the thickness of the second insulating layer. The specific multiple can be determined based on the actual product needs and is not limited in this disclosure. In some embodiments, the thickness ratio of the first insulating layer to the conductive layer in the printed circuit board 100 can be 15 to 28. For example, the thickness of the first insulating layer can be 15 times, 16 times, 20 times, 25 times, 27 times, or 28 times the thickness of the conductive layer. The specific multiple can be determined based on the actual product needs and is not limited in this disclosure.

[0149] In some embodiments, the thickness of the first insulating layer may be greater than or equal to half the thickness of the printed circuit board 100. For example, the thickness of the printed circuit board 100 is about 0.8 mm, and the thickness of the first insulating layer is about 0.419 mm.

[0150] In some embodiments, the thickness of the top conductive layer and the bottom conductive layer of the printed circuit board 100 can be slightly greater than the thickness of the inner conductive layers. For example, the ratio of the thickness of the top conductive layer and the bottom conductive layer (such as the first conductive layer 101 and the second conductive layer 102 in FIG. 15D ) to the thickness of the inner conductive layers (such as the fourth conductive layer 104, the third conductive layer 103, the sixth conductive layer 106, and the fifth conductive layer 105 in FIG. 15D ) is greater than 1 and less than or equal to 2. In some embodiments, among the plurality of second insulating layers, the thickness of the second insulating layer adjacent to the top conductive layer and the second insulating layer adjacent to the bottom conductive layer can be slightly greater than the thickness of the other second insulating layers to minimize interference of external electromagnetic fields on inner layer signals.

[0151] 15D , the laminated structure of the printed circuit board 100 comprises, from top to bottom, a first conductive layer 101, a second insulating layer a (not shown), a fourth conductive layer 104, a second insulating layer b (not shown), a third conductive layer 103, a first insulating layer (not shown), a sixth conductive layer 106, a second insulating layer c (not shown), a fifth conductive layer 105, a second insulating layer d (not shown), and a second conductive layer 102. In some embodiments, the thickness of the first conductive layer 101 and the second conductive layer 102 can each be 0.025 mm, and the thickness of the fourth conductive layer 104, the third conductive layer 103, the sixth conductive layer 106, and the fifth conductive layer 105 can each be 0.015 mm. The thickness of the second insulating layer a and the second insulating layer d can both be 0.083 mm (thickness accuracy is ±0.018 mm), the thickness of the second insulating layer b and the second insulating layer c can both be 0.076 mm, and the thickness of the first insulating layer can be 0.419 mm (thickness accuracy is approximately ±0.038 mm) to prevent crosstalk between the power signal and the differential signal transmitted in the second differential signal line S2.

[0152] FIG15E shows a schematic diagram of the stacking of a printed circuit board 100 according to some further embodiments of the present disclosure. As shown in FIG15E , in other embodiments, the printed circuit board 100 may further include: a sixth conductive layer 106, which is located on a side of the second conductive layer 102 away from the fifth conductive layer 105, and the sixth conductive layer 106 is the ground layer of the printed circuit board 100. In this case, one of the first conductive layer 101 and the sixth conductive layer 106 is the top layer, and the other is the bottom layer. In some embodiments, the power line of the printed circuit board 100 can be located in the first conductive layer 101, or it can also be located in the third conductive layer 103.

[0153] Figure 15F shows a schematic diagram of the stacking of printed circuit boards 100 according to other embodiments of the present disclosure. As shown in Figure 15F, the printed circuit board 100 can also be a five-layer board, including: a first conductive layer 101, a fourth conductive layer 104, a third conductive layer 103, a fifth conductive layer 105, and a second conductive layer 102, which are stacked in sequence. The first conductive layer 101, the second conductive layer 102, and the third conductive layer 103 are signal routing layers. The first conductive layer 101 also includes power lines, and the fourth conductive layer 104 and the fifth conductive layer 105 are ground layers. The fifth conductive layer 105 can also include a small number of signal lines to reduce the number of layers in the printed circuit board 100 and lower costs. Of course, in other embodiments, the number of layers in the printed circuit board 100 can be more or less than that in Figures 15E and 15F, and can be set according to actual needs. This embodiment does not impose any restrictions on this.

[0154] It can be understood that the above-mentioned signal routing layer, which can also be called the signal layer, is a layer in the printed circuit board 100 used to transmit electronic signals; the power layer is a layer used to provide power connection, and is equipped with power lines; the bottom layer is a layer used to provide ground connection.

[0155] In some embodiments, the binding area of ​​the display driver board 10 includes a binding pin. The printed circuit board 100 also includes: a third differential signal line S3, one end of the third differential signal line S3 is electrically connected to the signal transmission pin of the timing controller, and the other end of the third differential signal line S3 is electrically connected to the binding pin. The third differential signal line S3 can be used to transmit the data signal output from the timing controller 130 to the source driver chip 220. In some embodiments, the third differential signal line S3 can also be located in the third conductive layer 103, as shown in Figure 15C, to reduce the impact of ESD interference on the data signal, further enhance the anti-ESD interference capability of the display driver board 10, and improve the display screen flickering problem.

[0156] In some embodiments, the printed circuit board 100 further includes, in addition to the differential signal lines, other sensitive signal lines S4 that are susceptible to electrostatic interference, such as a common voltage signal line, a pulse-width modulation signal line, a backlight enable signal line, a latch signal line, and a reset signal line. In some embodiments, the common voltage signal line electrically connects the power management chip 150 to a binding pin for connecting to the common voltage input of the source driver chip 220, thereby transmitting the common voltage signal output by the power management chip 150 to the source driver chip 220, and further to the common electrode of the pixels in the display panel. Any jitter in the common voltage signal can cause screen flicker. The pulse-width modulation signal line and the backlight enable signal line can electrically connect the power interface 160 to the backlight driver chip 170, and are configured to transmit the pulse-width modulation signal and the backlight enable signal. The communication bus can electrically connect the display interface 110 to the timing controller 130. The latch signal line can electrically connect the timing controller 130 to the source driver chip 220 to achieve a handshake connection between the two. The reset signal line can electrically connect the voltage conversion chip 140 and the gate driving circuit 210 to control the gate driving circuit 210 to reset.

[0157] In some embodiments, at least one of the above-mentioned sensitive signal lines S4, such as the common voltage signal line, the pulse width modulation signal line, the backlight enable signal line, the latch signal line, the communication bus, and the reset signal line, can be located in the conductive layer between the first conductive layer 101 and the second conductive layer 102, that is, avoiding routing on the top and bottom layers to reduce the impact of ESD interference on the signals transmitted in these signal lines, thereby helping to improve the display screen flickering problem. In some embodiments, at least one of the above-mentioned sensitive signal lines S4, such as the common voltage signal line, the pulse width modulation signal line, the backlight enable signal line, the latch signal line, the communication bus, and the reset signal line, can be located in the third conductive layer 103, as shown in Figure 15C. Of course, in other embodiments, the sensitive signal line S4 can also be set in the fourth conductive layer 104, the fifth conductive layer 105, or the sixth conductive layer 106.

[0158] In some embodiments, a card slot is provided around the target area in the first conductive layer 101, and the fourth conductive layer 104 is exposed at the bottom of the card slot. The target area is the area on the printed circuit board 100 where devices susceptible to electromagnetic interference, such as the timing controller 130, are arranged. The display driver board also includes: an electromagnetic shielding cover, which can be made of a metal material with electromagnetic shielding function, such as nickel, zinc or iron. The electromagnetic shielding cover is snapped into the card slot to cover the electronic devices arranged in the target area, such as the timing controller 130. The portion of the electromagnetic shielding cover snapped into the card slot contacts the fourth conductive layer 104, i.e., the ground layer of the printed circuit board 100, to achieve electrical connection, thereby forming an electromagnetic shielding space, which is beneficial for protecting the electronic devices located in the space from external electromagnetic interference.

[0159] In some embodiments, it is possible to avoid forming a closed loop around the timing controller 130 in the driver circuit board 10, so that the timing controller 130 has a large grounding area, thereby improving the anti-ESD interference capability of the timing controller 130. In some embodiments, the above-mentioned first conductive layer 101 is provided with a plurality of first conductive areas as the first ground terminal GND. The above-mentioned multiple first conductive areas include: a first conductive area and a second conductive area. The first conductive area is the first conductive area with the largest outer area of ​​the timing controller 130. The second conductive area is the first conductive area corresponding to the area enclosed by the timing controller pad 130P. For example, the formation of a closed loop around the timing controller 130, such as around the corners, can be avoided by staggered routing, reducing routing distance, and optimizing routing paths, so that the second conductive area is connected to the outer first conductive area as much as possible.

[0160] In some embodiments, the orthographic projection of the timing controller 130 on the surface of the printed circuit board 100 is a polygon, for example, a quadrilateral, a pentagon, or a hexagon. The shape of the silk screen frame corresponding to the timing controller 130 is substantially consistent with the above-mentioned orthographic projection shape. The timing controller pads 130P include: K groups of pads, where K is an integer greater than or equal to 3. Each group of pads is arranged along the extension direction of one side of the polygon. There is a corner area between each two adjacent groups of pads, and thus K corner areas can be formed. For example, the above-mentioned polygon includes adjacent first and second sides, and a corner is formed between the first and second sides. One group of pads is arranged along the extension direction of the first side, and the other group of pads is arranged along the extension direction of the second side. The area between the two groups of pads opposite the above-mentioned corner is the corner area. The second conductive area is connected to the first conductive area at least from the two corner areas, so that the timing controller 130 has a large grounding area.

[0161] Figure 16 shows another partial schematic diagram of the first conductive layer according to some embodiments of the present disclosure. Figure 16 uses a quadrilateral, such as a square, as an example. The K groups of pads include: a first group of pads PA1, a second group of pads PA2, a third group of pads PA3, and a fourth group of pads PA4. The quadrilateral includes a first side B1, a second side B2, a third side B3, and a fourth side B4, which are adjacent in sequence. The first side B1 is opposite the third side B3, and the second side B2 is opposite the fourth side B4. The first group of pads PA1 is arranged along the direction of extension of the first side B1, the second group of pads PA2 is arranged along the direction of extension of the second side B2, the third group of pads PA3 is arranged along the direction of extension of the third side B3, and the fourth group of pads PA4 is arranged along the direction of extension of the fourth side B4. Therefore, the first group of pads PA1 and the third group of pads PA3 are arranged opposite each other, and the second group of pads PA2 and the fourth group of pads PA4 are arranged opposite each other.

[0162] There is a first corner region AG1 (at the position of the oval dotted box in Figure 16) between the first group of pads PA1 and the second group of pads PA2, a second corner region AG2 between the second group of pads PA2 and the third group of pads PA3, a third corner region AG3 between the third group of pads PA3 and the fourth group of pads PA4, and a fourth corner region AG4 between the fourth group of pads PA4 and the first group of pads PA1. In some embodiments, the second conductive region 602 can be connected to the first conductive region 601 from two, three, or four of the first corner region AG1, the second corner region AG2, the third corner region AG3, and the fourth corner region AG4. In some embodiments, the second conductive region 602 is connected to the first conductive region 601 from the first corner region AG1, the third corner region AG3, and the fourth corner region AG4, effectively increasing the grounding area at the timing controller 130 to quickly release static electricity generated at the timing controller 130.

[0163] In some embodiments, the timing controller 130 includes: N groups of signal transmission pins that can be used to input or output signals. In some embodiments, the N groups of signal transmission pins include M groups of vacant pins, and at least some of the vacant pins are grounded. Wherein, M and N are integers greater than or equal to 2. At least some here include both some or all situations. Vacant pins refer to signal transmission pins that are not used to transmit signals. Grounding the vacant pins can avoid the interference introduced by directly floating these vacant pins, which is beneficial to reducing the interference to the timing controller 130 and improving the display screen flickering problem. In some embodiments, the vacant pins in the M groups of vacant pins that can be used to transmit differential signals can be grounded. It can be understood that the vacant pins that can be used to transmit differential signals are arranged in pairs.

[0164] In some embodiments, the number of vacant pins is m, and the number of signal transmission pins is n, wherein the ratio of m to n may be greater than or equal to 0.25, so that the timing controller 130 has sufficient ground area.

[0165] As shown in Figure 16, the first group of pads PA1 may include 32 pads, which are pads pad1 to pad 32 from the right side to the left side in Figure 16. The ellipsis in Figure 16 indicates pads that are not shown. Among them, pads pad2 to pad 13 and pads pad 16 to pad 27 are pads corresponding to vacant pins that can be used to transmit differential signals. The fourth group of pads PA4 may include 32 pads, which are pads pad33 to pad 64 from the top to the bottom side in Figure 16, among which pads pad49 to pad 52 and pad61 to pad 64 are pads corresponding to vacant pins that can be used to transmit differential signals. The third group of pads PA3 may include 32 pads, which are pads pad65 to pad 96 from the left side to the right side in Figure 16, among which pads pad73 to pad 80 are pads corresponding to vacant pins that can be used to transmit differential signals. The second group of pads PA2 can include 33 pads, from the bottom to the top in Figure 16, which are pads 97 to 129, of which pads 113 to 114 and pads 127 to 128 are pads corresponding to vacant pins that can be used to transmit differential signals. The pads corresponding to these vacant pins for transmitting differential signals can be grounded. On the one hand, it can avoid interference introduced by floating differential signal pins. On the other hand, it is beneficial for the timing controller 130 to have more grounding area, which is beneficial for electrostatic discharge. In addition, grounding the pads near the corner area is beneficial to reducing the wiring outside the corner area, which is beneficial for the second conductive area 602 to be connected to the first conductive area 601 from the corner area.

[0166] In some embodiments, the components and wiring paths arranged between other areas of the driver circuit board 10 that are susceptible to ESD interference (such as the above-mentioned binding area) or the ground pin of a chip (such as the display interface 110) and the peripheral first conductive area can also be optimized, such as increasing the spacing width between the two components directly facing the ground pin and changing the wiring path so that the first conductive area can extend from the spacing area between the two components directly facing the ground pin into electrical connection with the ground pin. This allows the ground pin to be connected to the larger ground area of ​​the same layer via a shorter path, which is conducive to quickly discharging static electricity and reducing ESD interference.

[0167] In some embodiments, the first conductive layer 101 is further provided with an electrostatic protection device pad 111P connected to the first sub-signal line S11 and the second sub-signal line S12, so as to weld the above-mentioned electrostatic protection device 111 at the electrostatic protection device pad 111P to further suppress ESD interference in the display differential signal. In some embodiments, the electrostatic protection device 111 is a TVS tube, and accordingly, the electrostatic protection device pad 111P can be a pad that can be welded to the TVS tube. For example, as shown in Figure 13B, for a 4Lane display interface, two TVS devices need to be connected. For each TVS device, 5 pairs of pads need to be provided on the first conductive layer 101, the middle pair of pads is connected to the first ground terminal GND (signal ground) in the first conductive layer 101, and two pairs of pads on the upper and lower sides are respectively connected to the first sub-signal line S11 and the second sub-signal line S12 of the two differential signal channels.

[0168] Figure 17A shows another partial schematic diagram of the first conductive layer according to some embodiments of the present disclosure, and Figure 17B shows another partial schematic diagram of the first conductive layer according to other embodiments of the present disclosure. As shown in Figures 17A and 17B, the first conductive layer 101 also includes: a first conductive area 501 serving as a first ground terminal GND (i.e., signal ground) and a second conductive area 502 serving as a second ground terminal Ground (i.e., shell ground). The first conductive area 501 and the second conductive area 502 of the first conductive layer 101 can be connected by a trace so that ESD interference is transmitted along the trace. The principle and effect of such a setting can be found in the relevant description above and will not be repeated here.

[0169] In some embodiments, the first conductive layer 101 is further provided with a pad for the electrostatic attenuation device 180 and a trace connecting the pad to the second conductive region 502 and / or the first conductive region 501. In some embodiments, the electrostatic attenuation device 180 has two pads, one of which overlaps with the first conductive region 501 to achieve conductivity, and the other pad is electrically connected to the second conductive region 502 via a trace.

[0170] There are many options for the ESD device 180. For example, one or more of a magnetic bead, a capacitor, and a jumper resistor (i.e., a 0-ohm resistor) can be used. Accordingly, the pads of the ESD device 180 can include one or more of a magnetic bead pad, a capacitor pad, and a second resistor pad.

[0171] Taking into account the different ESD interference situations faced by different display products, the choice of electrostatic attenuation device 180 is also different. In order to improve the scope of application of the printed circuit board 100, in some embodiments, the first conductive layer 101 is also provided with: a magnetic bead pad, a capacitor pad and a second resistor pad. In other words, in order to facilitate the flexible selection of the electrostatic attenuation device 180 to be used, a magnetic bead pad, a capacitor pad and a second resistor pad are arranged on the printed circuit board 100. Taking the 15.8-inch QHD strip screen as an example, the capacitor pad and the second resistor pad can correspond to the resistor and capacitor of the 0603 package respectively, and the magnetic bead pad can correspond to the magnetic bead of the 0402 package.

[0172] In some embodiments, an opening is provided on one side of the first conductive region 501 adjacent to the second conductive region, and the magnetic bead pad, capacitor pad, and second resistor pad are disposed within the opening, such that the magnetic bead pad, capacitor pad, and second resistor pad are located outside the safety distance d of the second conductive region 502, thereby reducing electrical coupling within the safety distance d between the first conductive region 501 and the second conductive region 502. In some embodiments, the magnetic bead pad, capacitor pad, and second resistor pad can be disposed in close proximity, for example, with a spacing of 0.5 to 3 mm between adjacent pads, such as 0.5 mm, 1 mm, 2 mm, or 3 mm, to reduce the area of ​​single-point grounding and limit ESD transmission along a single single-point grounding path.

[0173] The magnetic bead pads include: a first magnetic bead pad P9 and a second magnetic bead pad P10. The second resistor pads include: a first resistor sub-pad P11 and a second resistor sub-pad P12. The capacitor pads include: a first capacitor sub-pad P13 and a second capacitor sub-pad P14. In some embodiments, the first magnetic bead pad P9, the first resistor sub-pad P11, and the first capacitor sub-pad P13 at least partially overlap with the first conductive region 501; the second magnetic bead pad P10 is electrically connected to the second conductive region 502 via a first connection line L1; the second resistor sub-pad P12 is electrically connected to the second conductive region 502 via a second connection line L2; and the second capacitor sub-pad P14 is electrically connected to the second conductive region 502 via a third connection line L3. This facilitates electrical connection between the signal ground and the chassis ground via the magnetic bead circuit, the jumper resistor circuit, or the capacitor circuit, allowing ESD interference to be transmitted along a designated path and effectively suppressing ESD interference.

[0174] In some embodiments, the first connecting line L1, the second connecting line L2, and the third connecting line L3 are different routing lines. As shown in FIG17A, the routing width is set according to the layout wiring rules, and the line width of each connecting line is less than or equal to the pad size of the corresponding device. Since the pad size of the magnetic bead is smaller than the pad size of the jumper resistor and capacitor, the line width of the first connecting line L1 can be smaller than the line width of the second connecting line L2 and the third connecting line L3. In some embodiments, the first connecting line L1, the second connecting line L2, and the third connecting line L3 can be set closely according to the layout wiring rules and arranged neatly to reduce the difference in ESD interference transmission paths when using different electrostatic attenuation devices 180.

[0175] In other embodiments, the first connection line L1, the second connection line L2, and the third connection line L3 can also be the same line, as shown in FIG17B . In this case, the tenth sub-pad P10, the twelfth sub-pad P12, and the fourteenth sub-pad P14 at least partially overlap to achieve electrical continuity between the three sub-pads. In this way, regardless of which electrostatic attenuation device 180 is used, ESD interference can be transmitted along the same transmission path.

[0176] FIG18 shows a schematic cross-sectional view of a display module according to some embodiments of the present disclosure. As shown in FIG18 , the display module 1 includes: a display panel 20, a backlight module 30, and a display driver board 10. The display driver board 10 can adopt the display driver board 10 provided in any of the above embodiments. The structure and effect of the display driver board 10 can be referred to the relevant description above and will not be repeated here. As shown in FIG16 , the display driver board 10 can be mounted on the back panel 310 of the backlight module 30 by screws 11.

[0177] In some embodiments, the display module 1 further includes an insulating gasket 40, which is stacked between the display driver board 10 and the back plate 310. This increases the thickness and distance between the bottom conductive layer signal of the circuit board (i.e., PCB) and the back plate 310, maintaining electrical connection only at the screw holes 1002. This allows ESD to be discharged along a specified path, preventing ESD interference signals on the back plate 310 from being randomly coupled to the display driver board 10. This helps enhance the display module 1's ability to resist ESD interference, thereby further reducing screen flickering caused by ESD interference.

[0178] In some embodiments, the bottom conductive layer of the display driver board 10 includes: a first conductive region 501 serving as a first ground terminal GND and a second conductive region 502 serving as a second ground terminal Ground. The bottom conductive layer is the conductive layer of the display driver board 10 closest to the backplane 310, and may be, for example, the second conductive layer 102 described above. The first conductive region 501 and the second conductive region 502 are spaced apart, and the second conductive region 502 is electrically connected to the backplane 310. The insulating gasket 40 has a first opening 401, which at least partially overlaps with the orthographic projection of the second conductive region 502 on the backplane 310, thereby exposing the second conductive region 502 from the first opening 401 to facilitate electrical connection between the second conductive region 502 and the backplane 310. In some embodiments, the orthographic projection of the second conductive region 502 on the backplane 310 may be within the orthographic projection of the first opening 401 on the backplane 310.

[0179] In some embodiments, the orthographic projection of the space between the first conductive region 501 and the second conductive region 502 on the back plate 310 is a first projection area, and the orthographic projection of the insulating spacer 40 on the back plate 310 is a second projection area, with the second projection area covering the first projection area. In other words, the insulating spacer 40 covers the safe distance between the housing ground and the signal ground on the display driver board 10 to minimize the mutual influence between the two grounds due to electrical coupling through any path.

[0180] In some embodiments, the second conductive region 502 of the bottom conductive layer can also be referred to as the exposed copper area of ​​the display driver board 10. The exposed copper area is provided with screw holes 1002 for fixing and electrically connecting the display driver board 10 and the back plate 310. The insulating gasket 40 is opened at a position directly opposite the exposed copper area with the screw holes 1002. The opening size is the same as the size of the exposed copper area, so that the insulating gasket 40 leaks out of the entire exposed copper area at the first opening 401 and ensures that the insulating gasket 40 can cover the safe distance between the shell ground and the signal ground on the display driver board 10. The exposed copper area of ​​the display driver board 10 is screwed to the back plate 310, and the screw holes 1002 in the exposed copper area remain electrically connected to the back plate 310 through the screws, so that ESD within the display module 1 can be discharged along the path: display panel 20 → signal ground → electrostatic attenuation device 180 → shell ground → back plate 310.

[0181] FIG19 shows a planar schematic diagram of an insulating gasket 40 according to some embodiments of the present disclosure. The shape and size of the insulating gasket 40 can be adapted to the shape and size of the display driver board 10. As shown in FIG19 , taking the display driver board 10 shown in FIG6 as an example, the insulating gasket 40 can be in the shape of an elongated strip. In addition to the four corners of the elongated strip each being provided with a first opening 401, a first opening 401 is provided in the middle area of ​​the long side of the binding side, and two first openings 401 are provided on the long side of the non-binding side, for a total of seven first openings 401. Each first opening 401 exposes an exposed copper area on the display driver board 10.

[0182] As shown in FIG18 , in some embodiments, the display module 1 may further include an insulating coating layer 41 disposed on the surface of the display driver board 10 near the back plate 310. The insulating gasket 40 is disposed between the insulating coating layer 41 and the back plate 310. This can reduce the air gap between the display driver board 10 and the insulating gasket 40, further increase the insulation thickness between the bottom conductive layer signal of the circuit board and the back plate 310, and thus further enhance the anti-ESD interference capability of the display module 1. In some embodiments, the material of the insulating coating layer 41 can be a silk screen material, such as white paint can be applied to the side of the bottom conductive layer near the insulating gasket 40.

[0183] Figure 20 shows a schematic plan view of an insulating coating layer 41 according to some embodiments of the present disclosure. As shown in Figure 20, the insulating coating layer 41 has a second opening 411. The orthographic projections of the second conductive region 502, the first opening 401, and the second opening 411 on the back plate 310 at least partially overlap, exposing the second conductive region 502 from the first opening 401 and the second opening 411. This allows for electrical connection between the second conductive region 502 and the back plate 310, thereby enhancing the ESD resistance of the display module 1 while retaining the aforementioned ESD discharge path.

[0184] Similarly, in some embodiments, the insulating coating layer 41 may also be opened at a position opposite to the exposed copper area with the screw hole 1002, and the size of the opening is the same as the size of the exposed copper area, so that the insulating coating layer 41 leaks out of the entire exposed copper area at the second opening 411, and ensures that the insulating coating layer 41 can cover the safe distance between the shell ground and the signal ground on the display driver board 10.

[0185] Figure 21 shows a cross-sectional schematic diagram of a display module according to other embodiments of the present disclosure. As shown in Figure 21, the display module 1 may further include: a packaging cover (PCB cover) 610 and packaging tape (cell tape) 620. The display driver board 10 is disposed in the accommodation space formed between the packaging cover 610 and the backplate 310. The packaging tape 620 is attached to the side of the packaging cover 610 away from the display driver board 10, with the portion of the packaging tape 620 extending beyond the packaging cover being attached to the backplate 310. Both the packaging cover 610 and the packaging tape 620 are electrically conductive. In some embodiments, the packaging cover 610 may be made of metal; the packaging tape 620 may have a fully adhesive conductive design on the front side, for example, a material with good shielding properties such as copper foil or aluminum foil coated with conductive adhesive. After being attached to the packaging cover 610, the packaging tape 620 can conduct electricity with the packaging cover 610, thereby forming a common ground. After the packaging tape 620 is attached to the packaging cover plate 610 , it can extend 5 to 10 mm beyond the edge of the packaging cover plate 610 . The extended portion can be attached to the back plate 310 and be electrically conductive with the back plate 310 , thereby achieving a common ground.

[0186] The package cover 610 itself provides some physical protection and radiation resistance. However, due to issues such as poor grounding between the package cover 610 and the backplate 310, and a lack of complete sealing contact with the backplate 310, its electromagnetic shielding effectiveness is limited. Adding the package tape 620 to the package cover 610 effectively addresses these issues.

[0187] The packaging tape in the related art needs to be wrapped around the edge of the polarizer 500 on the light-emitting side of the display panel 20 to ensure that the display panel 20 does not leak light. Since the area of ​​the portion that wraps the display panel 20 is small, it is easily debonded due to stress, so the thickness of the aluminum in the packaging tape cannot be too thick, and materials such as copper foil with better shielding effects cannot be used. In some embodiments of the present disclosure, the packaging tape 620 does not need to be wrapped around the front screen portion, but only needs to wrap around the packaging cover plate 610 portion on the surface of the display driver board 10. The backplane located under the bottom layer of the display driver board 10 and the packaging cover plate 610 and the packaging tape 620 located above the top layer of the display driver board 10 can form a better overall spatial shielding, which is beneficial to protecting the display driver board 10 (including the printed circuit board 100 and the electronic devices arranged on the printed circuit board) from external electromagnetic interference such as ESD interference, and further reducing the display screen flickering problem caused by ESD interference.

[0188] Figure 22 shows a schematic diagram of the structure of a display device according to some embodiments of the present disclosure. As shown in Figure 22, some embodiments of the present disclosure provide a display device 1000, including the display module 1 provided in any of the embodiments above. In some embodiments, the display device 1000 may further include a mainboard, which is electrically connected to the display driver board 10 in the display module 1 and transmits a display differential signal to the display driver board 10.

[0189] The display device may be, for example, a monitor, a television, a tablet computer, a rail transit bar screen, a medical device such as a monitor, a vehicle-mounted display, a laptop computer, a mobile phone, a digital photo frame, a navigation system, or any other product or component with a display function. Of course, the display device provided in the embodiments of the present disclosure is not limited to the types listed above.

[0190] It should be noted that the drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to general designs. In the absence of conflict, the embodiments of the present disclosure and the features therein can be combined with each other to obtain new embodiments.

[0191] Although some embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present disclosure.

Claims

1. A display driver board, comprising: A printed circuit board and a display interface, a timing controller, and a common-mode inductor disposed on the printed circuit board, wherein the common-mode inductor is located between the display interface and the timing controller, the printed circuit board comprising a first conductive layer, the first conductive layer being provided with a display interface pad, a timing controller pad, and at least one group of common-mode inductor pads, the display interface, the timing controller, and the common-mode inductor being disposed on respective corresponding pads on the first conductive layer; The display interface pad includes at least one group of differential signal receiving pads to receive the display differential signal transmitted by the mainboard. The common mode inductor pad includes an input end pad and an output end pad. The timing controller pad includes: a differential signal transmission pad corresponding to each group of the differential signal receiving pads. The printed circuit board also includes: at least one group of differential signal lines to transmit differential signals; each group of differential signal lines includes: a first differential signal line and a second differential signal line, the differential signal receiving pad is electrically connected to the input end pad through the first differential signal line, and the output end pad is electrically connected to the differential signal transmission pad through the second differential signal line.

2. The display driver board according to claim 1, wherein: The printed circuit board further comprises: a second conductive layer and a third conductive layer serving as signal routing layers, wherein the third conductive layer is located between the first conductive layer and the second conductive layer; At least the second differential signal line is located in the third conductive layer; the output pad is electrically connected to one end of the second differential signal line through a first via, and the differential signal transmission pad is electrically connected to the other end of the second differential signal line through a second via.

3. The display driver board according to claim 2, wherein: The printed circuit board also includes: a fourth conductive layer and a fifth conductive layer, the fourth conductive layer is located on a side of the third conductive layer close to the first conductive layer, and the fifth conductive layer is located on a side of the third conductive layer close to the second conductive layer, and the fourth conductive layer and the fifth conductive layer are the ground layers of the printed circuit board.

4. The display driver board according to claim 3, wherein: The printed circuit board further includes a sixth conductive layer, which is a power supply layer of the printed circuit board.

5. The display driver board according to claim 4, wherein: The sixth conductive layer is located between the fifth conductive layer and the third conductive layer. The printed circuit board also includes a first insulating layer and multiple second insulating layers. The first insulating layer is located between the sixth conductive layer and the third conductive layer. The multiple second insulating layers are insulating layers other than the first insulating layer between adjacent conductive layers of the printed circuit board, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer; and / or the thickness of the first insulating layer is greater than or equal to half the thickness of the printed circuit board.

6. The display driver board according to claim 5, wherein: The thickness of the first insulating layer is greater than or equal to 15 mil.

7. The display driver board according to claim 3, wherein: The printed circuit board further includes a sixth conductive layer located on a side of the second conductive layer away from the fifth conductive layer, the sixth conductive layer serving as a ground layer of the printed circuit board; and / or the power line of the printed circuit board is located on the third conductive layer.

8. The display driver board according to claim 2, wherein: The diameters of the first via hole and the second via hole are less than or equal to 2.5 mm.

9. The display driver board according to claim 2, wherein: The printed circuit board also includes: a common voltage signal line, a pulse width modulation signal line, a backlight enable signal line, a latch signal line, a communication bus and a reset signal line, and at least one of the common voltage signal line, the pulse width modulation signal line, the backlight enable signal line, the latch signal line, the communication bus and the reset signal line is located in a conductive layer between the first conductive layer and the second conductive layer.

10. The display driver board according to claim 9, wherein: At least one of the common voltage signal line, the pulse width modulation signal line, the backlight enable signal line, the latch signal line, the communication bus line and the reset signal line is located in the third conductive layer.

11. The display driver board according to claim 2, further comprising: A binding area, the binding area includes a binding pin, and the printed circuit board also includes: a third differential signal line, one end of the third differential signal line is electrically connected to the signal transmission pin of the timing controller, the other end of the third differential signal line is electrically connected to the binding pin, and the third differential signal line is located in the third conductive layer.

12. The display driver board according to claim 1, wherein: The printed circuit board includes multiple groups of differential signal lines, and the length difference between different groups of differential signal lines is less than or equal to 20 mil; and / or, For the same group of differential signal lines, the first differential signal line includes a first sub-signal line and a second sub-signal line, the second differential signal line includes a third sub-signal line and a fourth sub-signal line, the sum of the lengths of the first sub-signal line and the third sub-signal line is a first length value, the sum of the lengths of the second sub-signal line and the fourth sub-signal line is a second length value, and the difference between the first length value and the second length value is less than or equal to 10 mil.

13. The display driver board according to claim 1, wherein: The orthographic projection of the timing controller on the surface of the printed circuit board is a polygon, the timing controller pads include K groups of pads, each group of pads is arranged along the extension direction of one side of the polygon, and there is a corner area between each two adjacent groups of pads, and K is an integer greater than or equal to 3; The printed circuit board includes multiple first conductive areas serving as first ground terminals, and the multiple first conductive areas include: a first conductive area and a second conductive area. The first conductive area is the first conductive area with the largest peripheral area of ​​the timing controller, and the second conductive area is the first conductive area corresponding to the area enclosed by the timing controller pads. The second conductive area is connected to the first conductive area at least from two corner areas.

14. The display driving board according to claim 13, wherein: The polygon is a quadrilateral, and the K groups of pads include: a first group of pads, a second group of pads, a third group of pads, and a fourth group of pads, the first group of pads and the third group of pads are arranged opposite to each other, and the second group of pads and the fourth group of pads are arranged opposite to each other; There is a first corner area between the first group of pads and the second group of pads, a second corner area between the second group of pads and the third group of pads, a third corner area between the third group of pads and the fourth group of pads, and a fourth corner area between the fourth group of pads and the first group of pads, and the second conductive area is connected to the first conductive area from the first corner area, the third corner area and the fourth corner area.

15. The display driver board according to claim 1, wherein: The timing controller includes: N groups of signal transmission pins, the N groups of signal transmission pins include M groups of vacant pins, the vacant pins are grounded, wherein M and N are integers greater than or equal to 2.

16. The display driving board according to claim 15, wherein: The number of the vacant pins is m, and the number of the signal transmission pins is n, wherein the ratio of m to n is greater than or equal to 0.

25.

17. The display driver board according to any one of claims 1 to 16, wherein: The timing controller is configured to detect whether the data enable signal from the differential signal receiving pin of the display interface is abnormal; if abnormal, determine whether the duration of the abnormality exceeds a preset time value; if exceeded, control the display panel to display a pre-stored picture, wherein the preset time value is T, the duration of one line cycle of the data enable signal is H, and the ratio of T to H is greater than 2.

18. The display driving board according to claim 16, wherein: The ratio of the T to the H is 3-10.

19. The display driver board according to any one of claims 1 to 16, wherein: Each conductive layer of the printed circuit board is provided with a first conductive area serving as a first grounding terminal and a second conductive area serving as a second grounding terminal. The first conductive areas of each conductive layer of the printed circuit board are electrically connected, and the second conductive areas of each conductive layer of the printed circuit board are electrically connected; the second conductive area is configured to be electrically connected to the backplane of the backlight module; and the spacing distance between the first conductive area and the second conductive area is greater than 0.2 mm.

20. The display driving board according to claim 19, wherein: The distance between the first conductive area and the second conductive area is 3 to 5 mm.

21. The display driver board according to any one of claims 1 to 16, wherein: The first conductive layer is further provided with a first resistance pad corresponding to each group of the common mode inductor pads, and the first resistance pad includes: a first connection end pad and a second connection end pad; The input pad and the first connection pad are electrically connected to the differential signal receiving pad through the first differential signal line, and the output pad and the second connection pad are electrically connected to the differential signal transmitting pad through the second differential signal line.

22. The display driving board according to claim 21, wherein: The input-end pad at least partially overlaps with the first connection-end pad, and the output-end pad at least partially overlaps with the second connection-end pad.

23. The display driver board according to any one of claims 1 to 16, wherein: The first conductive layer is further provided with a first conductive region serving as a first ground terminal and a second conductive region serving as a second ground terminal; The second conductive region is configured to be grounded; The display driving board further includes an electrostatic attenuation device electrically connected between the first conductive area and the second conductive area, and the electrostatic attenuation device includes at least one of a magnetic bead, a jumper resistor, and a capacitor.

24. The display driving board according to claim 23, wherein: The first conductive layer is further provided with a magnetic bead pad, a capacitor pad and a second resistor pad; The magnetic bead pad includes a first magnetic bead pad and a second magnetic bead pad; the second resistor pad includes: a first resistor sub-pad and a second resistor sub-pad; the capacitor pad includes a first capacitor sub-pad and a second capacitor sub-pad; the first magnetic bead pad, the first resistor sub-pad and the first capacitor sub-pad at least partially overlap with the first conductive area; the second magnetic bead pad is electrically connected to the second conductive area through a first connecting line; the second resistor sub-pad is electrically connected to the second conductive area through a second connecting line; and the second capacitor sub-pad is electrically connected to the second conductive area through a third connecting line.

25. The display driving board according to claim 24, wherein: An opening is provided on one side of the first conductive region close to the second conductive region, and the magnetic bead pad, the capacitor pad and the second resistor pad are arranged in the opening; and the spacing between adjacent pads among the magnetic bead pad, the capacitor pad and the second resistor pad is 0.5 to 3 mm.

26. A display module comprising: Display panel; as well as The display driver board according to any one of claims 1 to 25, wherein the display driver board is electrically connected to the display panel.

27. The display module according to claim 26, further comprising: Back panel; an insulating coating layer, disposed on a surface of the display driving board close to the back plate; as well as An insulating gasket is arranged between the insulating coating layer and the back plate.

28. The display module according to claim 26, further comprising: Back panel; A packaging cover plate, wherein the display driving board is arranged in a receiving space formed between the packaging cover plate and the back plate; as well as The packaging tape is attached to a side of the packaging cover plate away from the display driving board, and a portion of the packaging tape exceeding the packaging cover plate is attached to the back plate.

29. A display device comprising: The display module according to any one of claims 26 to 28.

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