Driving circuit, display panel, and display device

Abstract

Provided in the present disclosure are a driving circuit, a display panel, and a display device. The driving circuit comprises a driving signal generation circuit (100), an output inverting circuit (200), a control signal generation circuit (300), and a control circuit (400). The control circuit (400) is separately electrically connected to a control signal terminal (CN1) and a first control signal terminal (COT1). The control circuit (400) comprises a first control sub-circuit (41), a second control sub-circuit (42), a third control sub-circuit (43), a first isolation sub-circuit (46), a first storage sub-circuit (44), and a second storage sub-circuit (45). The first isolation sub-circuit (46) is electrically connected to a first signal input terminal (E1).

Description

Driving circuit, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410129344.6 filed on January 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a display panel, and a display device. Background Art

[0004] In related art, a drive circuit typically includes a drive signal generating circuit, an output inverting circuit electrically connected to the drive signal generating circuit, a control signal generating circuit directly controlled by an enable signal, and a control circuit controlled by the drive signal generating circuit and the control signal generating circuit. The drive signal generating circuit outputs an n-level drive signal at the n-level generating signal output terminal OUT1, the output inverting circuit outputs an n-level inverted drive signal at the n-level generating signal inverting output terminal FOUT1, and the control circuit outputs a valid voltage signal or an invalid voltage signal at the n-level driving output terminal NOUT1.

[0005] However, since the n-level driving signal output by the driving signal generating circuit has a wide variation edge (rising edge or falling edge), the n-level inverted driving signal is also erroneously output, causing the effective voltage signal output by the control circuit at the n-level driving output terminal NOUT1 to become abnormal; in particular, the threshold voltage (Vth) of the P-type transistor in the driving signal generating circuit is prone to negative drift, causing the variation edge of the n-level driving signal to become serious, thereby causing the stability of the electrical signal output by the n-level driving output terminal NOUT1 to become worse.

[0006] Summary of the Invention

[0007] The present disclosure provides a driving circuit, a display panel, and a display device, which can improve the above-mentioned problems.

[0008] In a first aspect of the present disclosure, a drive circuit is provided, comprising a drive signal generating circuit, an output inverting circuit, a control signal generating circuit, and a control circuit. The drive signal generating circuit is electrically connected to an n-th level generated signal output terminal, and is configured to generate and output an n-th level drive signal through the n-th level generated signal output terminal, where n is a positive integer. The output inverting circuit is electrically connected to the n-th level drive signal output terminal and the n-th level generated signal inverting output terminal, respectively, and is configured to invert the n-th level drive signal to obtain and output an n-th level inverted drive signal through the n-th level generated signal inverting output terminal. The control signal generating circuit is electrically connected to an enable signal line and a control signal terminal, and is configured to generate and output a control signal through the control signal terminal based on an enable signal provided by the enable signal line. The control circuit is electrically connected to the control signal terminal and a first control signal terminal, respectively, and is configured to output a valid voltage signal or an invalid voltage signal to the n-th level drive output terminal under the control of the signals at the control signal terminal and the first control signal terminal. The control circuit includes a first control subcircuit, a second control subcircuit, a third control subcircuit, a first isolation subcircuit, a first storage subcircuit, and a second storage subcircuit. The first control subcircuit is electrically connected to the control signal terminal, the high-voltage line, the low-voltage line, and the first control output terminal, respectively, and is configured to invert the control signal output by the control signal terminal to obtain an inverted control signal, and output the inverted control signal through the first control output terminal. The second control subcircuit is electrically connected to the first control signal terminal, the high-voltage line, the first signal input terminal, and the second control output terminal, respectively, and is configured to control the connection between the second control output terminal and the high-voltage line or the first signal input terminal under the control of the signal from the first control signal terminal. The first isolation subcircuit is electrically connected to the first signal input terminal and is configured to provide an electrical signal to the first signal input terminal. The third control subcircuit is electrically connected to the second control output terminal, the high-voltage line, the low-voltage line, and the n-th stage driver output terminal, respectively, and is configured to invert the signal output by the second control output terminal and output the inverted signal through the n-th stage driver output terminal. The first storage sub-circuit is electrically connected to the control signal terminal, and is used to maintain the potential of the control signal terminal. The second storage sub-circuit is electrically connected to the second control output terminal, and is used to maintain the potential of the second control output terminal.

[0009] In combination with the first aspect of the present disclosure, in some embodiments, the first control signal terminal is electrically connected to the nth stage generated signal output terminal, the invalid voltage signal is a low potential signal, and the valid voltage signal is a high potential signal.

[0010] In combination with the first aspect of the present disclosure, in some embodiments, the first isolation sub-circuit is electrically connected between the first control output terminal and the first signal input terminal.

[0011] In combination with the first aspect of the present disclosure, in some embodiments, the first isolation sub-circuit includes a first isolation transistor, the gate of the first isolation transistor is electrically connected to the first clock signal terminal, the first pole of the first isolation transistor is electrically connected to the first control output terminal, and the second pole of the first isolation transistor is electrically connected to the first signal input terminal.

[0012] In conjunction with the first aspect of the present disclosure, in some embodiments, the first isolation sub-circuit further includes a second isolation transistor, wherein a gate of the second isolation transistor is electrically connected to the second clock signal terminal, a first electrode of the second isolation transistor is electrically connected to the first control output terminal, and a second electrode of the second isolation transistor is electrically connected to the first signal input terminal. One of the first isolation transistor and the second isolation transistor is an N-type transistor, and the other is a P-type transistor.

[0013] In combination with the first aspect of the present disclosure, in some embodiments, the first control signal terminal is electrically connected to the nth stage generated signal reverse output terminal, the invalid voltage signal is a high potential signal, and the valid voltage signal is a low potential signal.

[0014] In combination with the first aspect of the present disclosure, in some embodiments, the first isolation sub-circuit is electrically connected between the low voltage line and the first signal input terminal.

[0015] In combination with the first aspect of the present disclosure, in some embodiments, the first isolation sub-circuit includes a third isolation transistor, the gate of the third isolation transistor is electrically connected to the first clock signal terminal, the first electrode of the third isolation transistor is electrically connected to the first signal input terminal, and the second electrode of the third isolation transistor is electrically connected to the low voltage line.

[0016] In conjunction with the first aspect of the present disclosure, in some embodiments, the first control subcircuit includes a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor. The gate of the first control transistor is electrically connected to the control signal terminal, the first electrode of the first control transistor is electrically connected to the high voltage line, and the second electrode of the first control transistor is electrically connected to the first control output terminal. The gate of the second control transistor is electrically connected to the control signal terminal, the first electrode of the second control transistor is electrically connected to the first control output terminal, and the second electrode of the second control transistor is electrically connected to the low voltage line. The gate of the third control transistor is electrically connected to the first control output terminal, the first electrode of the third control transistor is electrically connected to the high voltage line, and the second electrode of the third control transistor is electrically connected to the control signal terminal. The gate of the fourth control transistor is electrically connected to the first control output terminal, the first electrode of the fourth control transistor is electrically connected to the control signal terminal, and the second electrode of the fourth control transistor is electrically connected to the low voltage line.

[0017] In conjunction with the first aspect of the present disclosure, in some embodiments, the second control subcircuit includes a fifth control transistor and a sixth control transistor. The gate of the fifth control transistor is electrically connected to the first control signal terminal, the first electrode of the fifth control transistor is electrically connected to the high voltage line, and the second electrode of the fifth control transistor is electrically connected to the second control output terminal. The gate of the sixth control transistor is electrically connected to the first control signal terminal, the first electrode of the sixth control transistor is electrically connected to the second control output terminal, and the second electrode of the sixth control transistor is electrically connected to the first signal input terminal.

[0018] In conjunction with the first aspect of the present disclosure, in some embodiments, the third control subcircuit includes a seventh control transistor and an eighth control transistor. The gate of the seventh control transistor is electrically connected to the second control output terminal, the first electrode of the seventh control transistor is electrically connected to the high voltage line, and the second electrode of the seventh control transistor is electrically connected to the n-th stage driver output terminal. The gate of the eighth control transistor is electrically connected to the second control output terminal, the first electrode of the eighth control transistor is electrically connected to the n-th stage driver output terminal, and the second electrode of the eighth control transistor is electrically connected to the low voltage line.

[0019] In conjunction with the first aspect of the present disclosure, in some embodiments, the first storage sub-circuit includes a first capacitor, and the second storage sub-circuit includes a second capacitor. A first plate of the first capacitor is electrically connected to the control signal terminal, and a second plate of the first capacitor is electrically connected to the low-voltage line. A first plate of the second capacitor is electrically connected to the second control output terminal, and a second plate of the second capacitor is electrically connected to the low-voltage line.

[0020] In combination with the first aspect of the present disclosure, in some embodiments, the first control transistor, the third control transistor, the fifth control transistor and the seventh control transistor are all P-type transistors, and the second control transistor, the fourth control transistor, the sixth control transistor and the eighth control transistor are all N-type transistors.

[0021] In conjunction with the first aspect of the present disclosure, in some embodiments, the drive signal generation circuit includes a first node control subcircuit, a second node control subcircuit, a first output node control subcircuit, a second output node control subcircuit, a potential maintaining subcircuit, and an output subcircuit. The first node control subcircuit is electrically connected to the first node, the first clock signal terminal, the low voltage line, and the second output node, respectively, and is configured to control the connection between the first node and the low voltage line under the control of a first clock signal provided by the first clock signal terminal, and to control the connection or disconnection between the first node and the first clock signal terminal under the control of the potential of the second output node. The second node control subcircuit is electrically connected to the first node, the first intermediate node, the high voltage line, the first clock signal terminal, the second clock signal terminal, the second node, the input terminal, and the low voltage line, respectively, and is configured to control the connection between the first intermediate node and the high voltage line under the control of the potential of the first node, control the connection between the first intermediate node and the second clock signal terminal under the control of the potential of the second node, and control the potential of the second node based on the potential of the first intermediate node, and control the connection between the input terminal and the second node under the control of the first clock signal provided by the first clock signal terminal and the signal provided by the low voltage line. The first output node control subcircuit is electrically connected to the first output node, the first node, the second clock signal terminal, the second intermediate node, the second output node, and the high voltage line, and is configured to control the connection between the second intermediate node and the second clock signal terminal under the control of the potential of the first node, control the potential of the second intermediate node based on the potential of the first node, control the connection between the second intermediate node and the first output node under the control of the second clock signal provided by the second clock signal terminal, and control the connection between the first output node and the high voltage line under the control of the potential of the second output node. The second output node control subcircuit is electrically connected to the first clock signal terminal, the input terminal, the control voltage line, the high voltage line, the second node, and the second output node, respectively, and is configured to control the second output node to be connected to the input terminal under the control of the first clock signal provided by the first clock signal terminal, control the potential of the second output node based on the potential of the second node, and control the second output node to be connected to the high voltage line under the control of the control voltage provided by the control voltage line. The potential maintaining subcircuit is electrically connected to the first output node, and is configured to maintain the potential of the first output node.The output sub-circuit is electrically connected to the first output node, the second output node, the high voltage line, the low voltage line and the n-th level generated signal output terminal, respectively, and is used to control the connection between the n-th level generated signal output terminal and the high voltage line under the control of the potential of the first output node, and to control the connection between the n-th level generated signal output terminal and the low voltage line under the control of the potential of the second output node.

[0022] In conjunction with the first aspect of the present disclosure, in some embodiments, the output inverting circuit includes an output reversing subcircuit and a second isolation subcircuit. The output reversing subcircuit is electrically connected to the n-th stage generated signal output terminal, the high voltage line, and the second signal input terminal, respectively, and is configured to output an electrical signal from the high voltage line or the second signal input terminal to the n-th stage generated signal reversing output terminal. The second isolation subcircuit is electrically connected to the second output node, the second signal input terminal, and the low voltage line, respectively, and is configured to control whether the low voltage line is connected to the second signal input terminal or not.

[0023] In combination with the first aspect of the present disclosure, in some embodiments, the second isolation sub-circuit includes a fourth isolation transistor, the gate of the fourth isolation transistor is electrically connected to the second output node, the first electrode of the fourth isolation transistor is electrically connected to the second signal input terminal, and the second electrode of the fourth isolation transistor is electrically connected to the low voltage line.

[0024] In combination with the first aspect of the present disclosure, in some embodiments, the output inverting circuit further includes a reverse storage sub-circuit, which is electrically connected to the n-th level generated signal output terminal and is used to maintain the potential of the n-th level generated signal output terminal; or / and the drive signal generating circuit further includes a drive storage sub-circuit, which is electrically connected to the n-th level generated signal output terminal and the second output node and is used to maintain the potential of the n-th level generated signal output terminal.

[0025] In conjunction with the first aspect of the present disclosure, in some embodiments, the reverse storage subcircuit includes a third capacitor, a first plate of the third capacitor is electrically connected to the n-th stage generated signal output terminal, and a second plate of the third capacitor is electrically connected to the low-voltage line. The drive storage subcircuit includes a fourth capacitor, a first plate of the fourth capacitor is electrically connected to the n-th stage generated signal output terminal, and a second plate of the fourth capacitor is electrically connected to the second output node.

[0026] In conjunction with the first aspect of the present disclosure, in some embodiments, the output inversion circuit includes a first output inversion transistor and a second output inversion transistor. The gate of the first output inversion transistor is electrically connected to the n-th stage generated signal output terminal, the first electrode of the first output inversion transistor is electrically connected to the high voltage line, and the second electrode of the first output inversion transistor is electrically connected to the n-th stage generated signal inverse output terminal. The gate of the second output inversion transistor is electrically connected to the n-th stage generated signal output terminal, the first electrode of the second output inversion transistor is electrically connected to the n-th stage generated signal inverse output terminal, and the second electrode of the second output inversion transistor is electrically connected to the second signal input terminal. One of the first output inversion transistor and the second output inversion transistor is an N-type transistor, and the other is a P-type transistor.

[0027] In conjunction with the first aspect of the present disclosure, in some embodiments, the first node control subcircuit includes a first transistor, a second transistor, and a third transistor; and the second output node control subcircuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The gate of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the low voltage line, and the second electrode of the first transistor is electrically connected to the first electrode of the third transistor. The gate of the second transistor is electrically connected to the second electrode of the fourth transistor, the second electrode of the second transistor is electrically connected to the first clock signal terminal, and the first electrode of the second transistor is electrically connected to the first electrode of the third transistor. The gate of the third transistor is electrically connected to the low voltage line, and the second electrode of the third transistor is electrically connected to the first node. The gate of the fourth transistor is electrically connected to the first clock signal terminal, and the first electrode of the fourth transistor is electrically connected to the input terminal. The gate of the fifth transistor is electrically connected to the low voltage line, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the second output node. The gate and first electrode of the sixth transistor are both electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second output node. The gate of the seventh transistor is electrically connected to the control voltage line, the first electrode of the seventh transistor is electrically connected to the high voltage line, and the second electrode of the seventh transistor is electrically connected to the first electrode of the fifth transistor. The second node control subcircuit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a fifth capacitor. The gate of the eighth transistor is electrically connected to the second node, the second electrode of the eighth transistor is electrically connected to the second clock signal terminal, and the first electrode of the eighth transistor is electrically connected to the first intermediate node. The gate of the ninth transistor is electrically connected to the second electrode of the first transistor, the first electrode of the ninth transistor is electrically connected to the high voltage line, and the second electrode of the ninth transistor is electrically connected to the first intermediate node. The gate of the tenth transistor is electrically connected to the first clock signal terminal, the first electrode of the tenth transistor is electrically connected to the input terminal, and the second electrode of the tenth transistor is electrically connected to the first electrode of the eleventh transistor. The gate of the eleventh transistor is electrically connected to the low voltage line, and the second electrode of the eleventh transistor is electrically connected to the second node. The first plate of the fifth capacitor is electrically connected to the first intermediate node, and the second plate of the fifth capacitor is electrically connected to the second node. The first output node control subcircuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a sixth capacitor. The gate of the twelfth transistor is electrically connected to the first node, the first electrode of the twelfth transistor is electrically connected to the second clock signal terminal, and the second electrode of the twelfth transistor is electrically connected to the second intermediate node.The gate of the thirteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second intermediate node, and the second electrode of the thirteenth transistor is electrically connected to the first output node. The gate of the fourteenth transistor is electrically connected to the first electrode of the fifth transistor, the second electrode of the fourteenth transistor is electrically connected to the high voltage line, and the first electrode of the fourteenth transistor is electrically connected to the first output node. The first plate of the sixth capacitor is electrically connected to the first node, and the second plate of the sixth capacitor is electrically connected to the second intermediate node. The potential maintaining subcircuit includes a seventh capacitor. The first plate of the seventh capacitor is electrically connected to the first output node, and the second plate of the seventh capacitor is electrically connected to the high voltage line. The output subcircuit includes a fifteenth transistor and a sixteenth transistor. The gate of the fifteenth transistor is electrically connected to the first output node, the first electrode of the fifteenth transistor is electrically connected to the high voltage line, and the second electrode of the fifteenth transistor is electrically connected to the n-th stage generated signal output terminal. A gate of the sixteenth transistor is electrically connected to the second output node, a first electrode of the sixteenth transistor is electrically connected to the n-th stage generated signal output terminal, and a second electrode of the sixteenth transistor is electrically connected to the low voltage line.

[0028] In conjunction with the first aspect of the present disclosure, in some embodiments, the control signal generating circuit includes a ninth control transistor, a tenth control transistor, an eleventh control transistor, and a twelfth control transistor. The gate of the ninth control transistor is electrically connected to the n-1th stage generated signal inverting output terminal, the first electrode of the ninth control transistor is electrically connected to the enable signal line, and the second electrode of the ninth control transistor is electrically connected to the first electrode of the eleventh control transistor. The gate of the tenth control transistor is electrically connected to the n-1th stage generated signal output terminal, the first electrode of the tenth control transistor is electrically connected to the enable signal line, and the second electrode of the tenth control transistor is electrically connected to the first electrode of the eleventh control transistor. The gate of the eleventh control transistor is electrically connected to the nth stage generated signal output terminal, and the second electrode of the eleventh control transistor is electrically connected to the control signal terminal. The gate of the twelfth control transistor is electrically connected to the nth stage generated signal inverting output terminal, the first electrode of the twelfth control transistor is electrically connected to the first electrode of the eleventh control transistor, and the second electrode of the twelfth control transistor is electrically connected to the control signal terminal. The ninth control transistor and the eleventh control transistor are P-type transistors, and the tenth control transistor and the twelfth control transistor are N-type transistors.

[0029] In a second aspect of the present disclosure, a display panel is provided, comprising the driving circuit provided in the first aspect of the present disclosure.

[0030] In a third aspect of the present disclosure, a display device is provided, comprising the display panel provided in the second aspect of the present disclosure, or / and the display device comprises the driving circuit provided in the first aspect of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG1 is a schematic structural diagram of a first driving circuit according to some embodiments of the present disclosure;

[0032] FIG2 is a schematic structural diagram of a first driving circuit according to other embodiments of the present disclosure;

[0033] FIG3 is a schematic diagram comparing a partial signal waveform of the first driving circuit according to some embodiments of the present disclosure with a partial signal waveform of the related art;

[0034] FIG4 is a schematic structural diagram of a second driving circuit according to some embodiments of the present disclosure;

[0035] FIG5 is a schematic structural diagram of a second driving circuit according to other embodiments of the present disclosure;

[0036] FIG6 is a schematic diagram comparing a partial signal waveform of a second driving circuit according to some embodiments of the present disclosure with a partial signal waveform of a related art;

[0037] FIG7 is a schematic structural diagram of a control signal generating circuit and a control circuit according to some embodiments of the present disclosure;

[0038] FIG8 is a schematic structural diagram of a control signal generating circuit and a control circuit according to other embodiments of the present disclosure;

[0039] FIG9 is a schematic structural diagram of a control signal generating circuit and a control circuit according to yet other embodiments of the present disclosure;

[0040] FIG10 is a schematic structural diagram of a control signal generating circuit and a control circuit according to some further embodiments of the present disclosure;

[0041] FIG11 is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure;

[0042] FIG12 is a schematic structural diagram of a driving signal generating circuit and an output inverting circuit according to some embodiments of the present disclosure;

[0043] FIG13 is a schematic diagram comparing partial waveforms of the first structure illustrated in FIG12 with partial signal waveforms of the related art;

[0044] FIG14 is a schematic structural diagram of a driving signal generating circuit and an output inverting circuit according to other embodiments of the present disclosure;

[0045] FIG15 is a schematic structural diagram of a driving signal generating circuit and an output inverting circuit according to yet other embodiments of the present disclosure;

[0046] FIG16 is a circuit diagram of a first driving circuit according to some embodiments of the present disclosure;

[0047] FIG17 is a schematic diagram of electrical signals of the first driving circuit shown in FIG16 at stage (1);

[0048] FIG18 is a schematic diagram of electrical signals in stage (2) of the first driving circuit shown in FIG16 ;

[0049] FIG19 is a schematic diagram of electrical signals of the first driving circuit shown in FIG16 at stage (3);

[0050] FIG20 is a schematic diagram of electrical signals of the fourth stage of the first driving circuit shown in FIG16 ;

[0051] FIG21 is a circuit diagram of a first driving circuit according to other embodiments of the present disclosure;

[0052] FIG22 is a circuit diagram of a second driving circuit according to some embodiments of the present disclosure;

[0053] FIG23 is a schematic diagram of electrical signals in stage (1) of the second driving circuit shown in FIG22 ;

[0054] FIG24 is a schematic diagram of electrical signals in stage (2) of the second driving circuit shown in FIG22 ;

[0055] FIG25 is a schematic diagram of electrical signals of the second driving circuit shown in FIG22 in stage (3);

[0056] FIG26 is a schematic diagram of electrical signals of the fourth stage of the second driving circuit shown in FIG22; and

[0057] FIG27 is a circuit diagram of a second driving circuit according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0058] In order to better understand the technical solution provided by the present disclosure, the technical solution of the present disclosure is described in detail below with the help of the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present disclosure and the specific features in the embodiments are detailed descriptions of the technical solution of the present disclosure, rather than limitations on the technical solution of the present disclosure. In the absence of conflict, the embodiments of the present disclosure and the technical features in the embodiments can be combined with each other.

[0059] In this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprising a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. The term "two or more" includes two or more than two cases.

[0060] In the related art, since the n-level driving signal output by the driving signal generating circuit has a wide changing edge (rising edge or falling edge), the n-level inverted driving signal is also erroneously output, causing the effective voltage signal output by the control circuit at the n-level driving output terminal NOUT1 to become abnormal; in particular, the threshold voltage (Vth) of the P-type transistor in the driving signal generating circuit is prone to negative drift, causing the changing edge of the n-level driving signal to become serious, thereby causing the stability of the electrical signal output from the n-level driving output terminal NOUT1 to become worse.

[0061] For example, in some application scenarios, the n-level drive signal has a wide falling edge due to the inherent circuit characteristics of the drive signal generation circuit (such as the lack of a bootstrap structure at the output). The threshold voltage (Vth) of the P-type transistor in the drive signal generation circuit is prone to negative drift, resulting in a wide falling edge in the n-level drive signal. This voltage rises during the falling edge, causing the n-level drive signal to cause logic confusion in the inverter in the control circuit. This leads to competition between the inverter's intermediate states, resulting in an abnormal width of the effective voltage signal output by the n-level driver output terminal NOUT1.

[0062] In some other application scenarios, the n-stage drive signal has a changing edge due to the inherent circuit characteristics of the drive signal generation circuit (such as the lack of a bootstrap structure at the output). The threshold voltage (Vth) of the P-type transistor in the drive signal generation circuit is prone to negative drift, resulting in a wide falling edge in the n-stage drive signal. This also causes the n-stage inverted drive signal to be erroneously output. This erroneous output of the n-stage inverted drive signal causes logic confusion in the inverter in the control circuit, leading to competition in the inverter's intermediate state voltage, resulting in an abnormal width of the effective voltage signal outputted by the n-stage driver output terminal NOUT1.

[0063] In view of this, some embodiments of the present disclosure provide a driving circuit, a display panel, and a display device, which can effectively improve the above-mentioned problems.

[0064] The driving circuit provided in some embodiments of the present disclosure includes a driving signal generating circuit, an output inverting circuit, a control signal generating circuit and a control circuit. The driving signal generating circuit is electrically connected to the n-th level generating signal output terminal, and is used to generate and output the n-th level driving signal through the n-th level generating signal output terminal, where n is a positive integer. The output inverting circuit is electrically connected to the n-th level driving signal output terminal and the n-th level generating signal inverting output terminal, respectively, and is used to invert the n-th level driving signal, obtain and output the n-th level inverted driving signal through the n-th level generating signal inverting output terminal. The control signal generating circuit is electrically connected to the enable signal line and the control signal terminal, and is used to generate and output the control signal through the control signal terminal according to the enable signal provided by the enable signal line. The control circuit is electrically connected to the control signal terminal and the first control signal terminal, respectively, and is used to output a valid voltage signal or an invalid voltage signal to the n-th level driving output terminal under the control of the signals of the control signal terminal and the first control signal terminal.

[0065] In some embodiments, the control circuit includes a first control subcircuit, a second control subcircuit, a third control subcircuit, a first isolation subcircuit, a first storage subcircuit, and a second storage subcircuit.

[0066] The first control subcircuit is electrically connected to the control signal terminal, the high-voltage line, the low-voltage line, and the first control output terminal, respectively, and is configured to invert the control signal output by the control signal terminal to obtain an inverted control signal, and output the inverted control signal through the first control output terminal. The second control subcircuit is electrically connected to the first control signal terminal, the high-voltage line, the first signal input terminal, and the second control output terminal, respectively, and is configured to control the connection between the second control output terminal and the high-voltage line or the first signal input terminal under the control of the signal from the first control signal terminal. The first isolation subcircuit is electrically connected to the first signal input terminal and is configured to provide an electrical signal to the first signal input terminal. The third control subcircuit is electrically connected to the second control output terminal, the high-voltage line, the low-voltage line, and the n-th level driver output terminal, respectively, and is configured to invert the signal output by the second control output terminal and output the inverted signal through the n-th level driver output terminal. The first storage subcircuit is electrically connected to the control signal terminal and is configured to maintain the potential of the control signal terminal. The second storage subcircuit is electrically connected to the second control output terminal and is configured to maintain the potential of the second control output terminal.

[0067] Some embodiments of the present disclosure further provide a display panel including the driving circuit provided by the aforementioned embodiments.

[0068] Some embodiments of the present disclosure further provide a display device including the aforementioned driving circuit and / or the aforementioned display panel.

[0069] In the following detailed description, different embodiments are described to better illustrate the inventive spirit of the present disclosure. However, the description of different embodiments does not limit the combination of different implementation situations or implementation features in the present disclosure.

[0070] In this document, when a transistor is a thin film transistor or a field effect transistor, the transistor includes a gate, a source, and a drain. The upper portion of the schematic diagram represents the first electrode of the transistor, and the lower portion represents the second electrode of the transistor, or the left portion of the schematic diagram represents the first electrode of the transistor, and the right portion represents the second electrode of the transistor. The first electrode of the transistor is one of the source and drain of the transistor, and the second electrode of the transistor is the other of the source and drain of the transistor. Furthermore, depending on the high and low level settings in a specific circuit and the type and characteristics of the transistor, the source and drain of each transistor can be fully or partially interchangeable. This is easily achieved by those skilled in the art based on specific application scenarios and will not be elaborated on here.

[0071] Please refer to Figures 1 to 3, Figure 1 is a structural schematic diagram of the first driving circuit according to some embodiments of the present disclosure; Figure 2 is a structural schematic diagram of the first driving circuit according to other embodiments of the present disclosure; Figure 3 is a schematic diagram comparing a partial signal waveform of the first driving circuit according to some embodiments of the present disclosure with a partial signal waveform of the related technology.

[0072] Please refer to Figures 4 to 6, Figure 4 is a structural schematic diagram of the second driving circuit according to some embodiments of the present disclosure; Figure 5 is a structural schematic diagram of the second driving circuit according to other embodiments of the present disclosure; Figure 6 is a schematic diagram comparing a partial signal waveform of the second driving circuit according to some embodiments of the present disclosure with a partial signal waveform of the related art.

[0073] In some embodiments, the first driving circuit of Figures 1 to 3 is a normally low type adjustable high voltage circuit (invalid signal is a low potential signal, valid signal is a high potential signal). In some embodiments, the second driving circuit of Figures 4 to 6 is a normally high type adjustable low voltage circuit (invalid signal is a high potential signal, valid signal is a low potential signal).

[0074] Please refer to Figures 7 to 10, Figure 7 is a structural diagram of a control signal generating circuit and a control circuit according to some embodiments of the present disclosure; Figure 8 is a structural diagram of a control signal generating circuit and a control circuit according to other embodiments of the present disclosure; Figure 9 is a structural diagram of a control signal generating circuit and a control circuit according to still some embodiments of the present disclosure; Figure 10 is a structural diagram of a control signal generating circuit and a control circuit according to still some embodiments of the present disclosure.

[0075] Please refer to Figure 11, which is a schematic diagram of a pixel circuit according to some embodiments of the present disclosure. The driving circuit provided by the embodiments of the present disclosure can be used to drive the pixel circuit shown in Figure 11, but is not limited to driving the pixel circuit shown in Figure 11.

[0076] Some embodiments of the present disclosure provide a driving circuit, as shown in FIG. 1 to FIG. 10 , the driving circuit may include a driving signal generating circuit 100 , an output inverting circuit 200 , a control signal generating circuit 300 and a control circuit 400 .

[0077] The drive signal generating circuit 100 is electrically connected to the n-th level generated signal output terminal OUT1 and is configured to generate and output the n-th level drive signal through the n-th level generated signal output terminal OUT1, where n is a positive integer. The output inversion circuit 200 is electrically connected to the n-th level drive signal output terminal OUT1 and the n-th level generated signal inverting output terminal FOUT1, respectively, and is configured to invert the n-th level drive signal to obtain and output the n-th level inverted drive signal through the n-th level generated signal inverting output terminal FOUT1. The control signal generating circuit 300 is electrically connected to the enable signal line EN and the control signal terminal CN1, and is configured to generate and output the control signal through the control signal terminal CN1 based on the enable signal provided by the enable signal line EN. The control circuit 400 is electrically connected to the control signal terminal CN1 and the first control signal terminal COT1, respectively, and is configured to output a valid voltage signal or an invalid voltage signal to the n-th level drive output terminal NOUT1 under the control of the signals from the control signal terminal CN1 and the first control signal terminal COT1.

[0078] As shown in FIG. 2 , in some embodiments, the control circuit 400 may include a first control subcircuit 41 , a second control subcircuit 42 , a third control subcircuit 43 , a first isolation subcircuit 46 , a first storage subcircuit 44 , and a second storage subcircuit 45 .

[0079] The first control sub-circuit 41 is electrically connected to the control signal terminal CN1, the high voltage line VGH, the low voltage line VGL, and the first control output terminal CN2, respectively. It is configured to invert the control signal output from the control signal terminal CN1 to generate an inverted control signal, and output the inverted control signal through the first control output terminal CN2. The second control sub-circuit 42 is electrically connected to the first control signal terminal COT1, the high voltage line VGH, the first signal input terminal E1, and the second control output terminal CN3, respectively. It is configured to control the communication between the second control output terminal CN3 and the high voltage line VGH or the first signal input terminal E1 under the control of the signal from the first control signal terminal COT1. The first isolation sub-circuit 46 is electrically connected to the first signal input terminal E1 and is configured to provide an electrical signal to the first signal input terminal E1. The third control sub-circuit 43 is electrically connected to the second control output terminal CN3, the high voltage line VGH, the low voltage line VGL, and the n-th stage driver output terminal NOUT1, respectively. It is configured to invert the signal output from the second control output terminal CN3 and output the inverted signal through the n-th stage driver output terminal NOUT1. The first storage sub-circuit 44 is electrically connected to the control signal terminal CN1 for maintaining the potential of the control signal terminal CN1. The second storage sub-circuit 45 is electrically connected to the second control output terminal CN3 for maintaining the potential of the second control output terminal CN3.

[0080] As shown in Figure 11, in some embodiments, the pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, an eighth display control transistor M8, a storage capacitor Cst and an organic light emitting diode O1.

[0081] The gate of the first display control transistor M1 is electrically connected to the first reset terminal PR, the source of the first display control transistor M1 is electrically connected to the first starting voltage terminal I1, the second electrode of the first display control transistor M1 is electrically connected to the drain of the driving transistor M3, and the first starting voltage terminal I1 is used to provide a first starting voltage Vinit1.

[0082] The gate of the second display control transistor M2 is electrically connected to the first scanning terminal NT, the source of the second display control transistor M2 is electrically connected to the gate of the driving transistor M3 , and the drain of the second display control transistor M2 is electrically connected to the drain of the driving transistor M3 .

[0083] A gate of the fourth display control transistor M4 is electrically connected to the second scanning terminal PT, a source of the fourth display control transistor M4 is electrically connected to the data line DL, and a drain of the fourth display control transistor M4 is electrically connected to the source of the driving transistor M3.

[0084] The gate of the fifth display control transistor M5 is electrically connected to the light emitting control terminal E1 , the source of the fifth display control transistor M5 is electrically connected to the high level terminal VDD, and the drain of the fifth display control transistor M5 is electrically connected to the source of the driving transistor M3 .

[0085] The gate of the sixth display control transistor M6 is electrically connected to the light emitting control terminal E1, the source of the sixth display control transistor M6 is electrically connected to the drain of the driving transistor M3, and the drain of the sixth display control transistor M6 is electrically connected to the anode of the organic light emitting diode O1; the cathode of the organic light emitting diode O1 is electrically connected to the low level terminal VSS.

[0086] The gate of the seventh display control transistor M7 is electrically connected to the second reset terminal HR, the source of the seventh display control transistor M7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh display control transistor M7 is electrically connected to the anode of the organic light emitting diode O1.

[0087] The gate of the eighth display control transistor M8 is electrically connected to the second reset terminal HR, the source of the eighth display control transistor M8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth display control transistor M8 is electrically connected to the source of the driving transistor M3.

[0088] A first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor M3 , and a second plate of the storage capacitor Cst is electrically connected to the high level terminal VDD.

[0089] The first display control transistor M1 , the driving transistor M3 , the fourth display control transistor M4 , the fifth display control transistor M5 , the sixth display control transistor M6 , the seventh display control transistor M7 and the eighth display control transistor M8 are all P-type transistors, and the second display control transistor M2 is an N-type transistor.

[0090] In some embodiments, the n-th stage driving output terminal NOUT1 of the driving circuit may be used to drive the pixel circuit shown in FIG. 11 , but is not limited to the pixel circuit shown in FIG. 11 .

[0091] In some embodiments, the nth stage driving output terminal NOUT1 is electrically connected to at least one of the nth stage first scan terminal NT, the nth stage second scan terminal PT, the nth stage first reset terminal PR, and the nth stage second reset terminal HR, but is not limited thereto.

[0092] In the related art, as shown in FIG3 , the first control signal terminal COT1 has a falling edge indicated by the first dashed circle 51. The voltage of the falling edge in the first dashed circle 51 is lower than the potential of the high-voltage line VGH and greater than the potential of the low-voltage line VGL, causing the second control sub-circuit 42, under the control of the first control signal terminal COT1, to output an electrical signal more slowly. For example, in FIG7 , the second control sub-circuit 42 includes a fifth control transistor CT5 and a sixth control transistor CT6 (the related art does not include the first isolation sub-circuit 46). The falling edge in the first dashed circle 51 causes the fifth control transistor CT5 and the sixth control transistor CT6 to turn on simultaneously, forming a path between the electrical signal from the high-voltage line VGH and the electrical signal from the first signal input terminal E1 (or the low-voltage line VGL). This slows the switching speed of the fifth control transistor CT5 and the sixth control transistor CT6 of the inverter, resulting in a longer falling edge time of the electrical signal output from the n-th stage driver output terminal NOUT1, i.e., the falling edge indicated by the second dashed circle 52 in FIG3 . In addition, when the threshold voltage (Vth) of the P-type transistor in the drive signal generating circuit 100 is negative, the output step voltage of the n-th level generated signal output terminal OUT1 becomes high, and the voltage output by the fifth control transistor CT5 and the sixth control transistor CT6 may not cause the third control sub-circuit 43 to invert the signal output by the second control output terminal CN3. Ultimately, the electrical signal output by the n-th level drive output terminal NOUT1 is a high-potential signal rather than the expected low-potential signal.

[0093] In the first driving circuit provided by some embodiments of the present disclosure, as shown in Figures 1 to 3, a first isolation sub-circuit 46 is additionally provided, and an electrical signal of the first signal input terminal E1 is provided through the first isolation sub-circuit 46. The connection between the sixth control transistor CT6 and the low-potential signal is cut off (or the electrical connection between the first signal input terminal E1 and the low-voltage line VGL is blocked) during the corresponding working phase of the second control sub-circuit 42. Even if the sixth control transistor CT6 is mistakenly turned on, no current is generated, thereby improving the potential pull-up efficiency of the second control output terminal CN3 and avoiding the falling edge of the electrical signal output by the n-th stage driving output terminal NOUT1, as shown by the third dotted circle 53 in Figure 3. At the same time, when the threshold voltage (Vth) of the P-type transistor in the driving signal generating circuit 100 drifts negatively, the stability of the electrical signal output by the n-th stage driving output terminal NOUT1 is also improved.

[0094] In the related art, as shown in FIG6 , the first control signal terminal COT1 has a falling edge in the first dotted rectangle 61 . The voltage of the falling edge in the first dotted rectangle 61 is lower than the potential of the high-voltage line VGH and greater than the potential of the low-voltage line VGL. This causes the second control sub-circuit 42 to output an electrical signal more slowly under the control of the first control signal terminal COT1 . For example, the second control sub-circuit 42 in FIG9 includes a fifth control transistor CT5 and a sixth control transistor CT6 (the first isolation sub-circuit 46 is absent in the related art). The falling edge in the first dotted rectangle 61 causes the fifth control transistor CT5 and the sixth control transistor CT6 to turn on simultaneously, forming a path between the electrical signal of the high-voltage line VGH and the electrical signal of the first signal input terminal E1 . This causes the switching speed of the fifth control transistor CT5 and the sixth control transistor CT6 of the inverter to slow down, shortening the waveform time of the second control output terminal CN3 and shortening the effective electrical signal time output by the n-th stage driver output terminal NOUT1. In other words, there is the problem of shortened effective electrical signal time in the second dotted rectangle 62 in FIG6 .

[0095] In the second driving circuit provided in some embodiments of the present disclosure, as shown in Figures 4 to 6, a first isolation sub-circuit 46 is additionally provided, and an electrical signal of the first signal input terminal E1 is provided through the first isolation sub-circuit 46. The connection between the sixth control transistor CT6 and the low-potential signal is cut off (or the electrical connection between the first signal input terminal E1 and the low-voltage line VGL is blocked) during the corresponding working phase of the second control sub-circuit 42. Even if the sixth control transistor CT6 is mistakenly turned on, no current is generated, thereby improving the potential conversion efficiency of the second control output terminal CN3 and avoiding the effective electrical signal time output by the n-th stage driving output terminal NOUT1 from being shortened, as shown by the third dotted rectangle 63 in Figure 6. At the same time, it also improves the stability of the electrical signal output by the n-th stage driving output terminal NOUT1 when the threshold voltage (Vth) of the P-type transistor in the driving signal generating circuit 100 drifts negatively.

[0096] Therefore, in some embodiments of the present disclosure, a first isolation sub-circuit 46 is provided in the control circuit 400. The first isolation sub-circuit 46 provides an electrical signal to the first signal input terminal E1 in a corresponding time period, or blocks the electrical signal input to the first signal input terminal E1 in a corresponding time period, and cuts off the connection between the sixth control transistor CT6 and the low-potential signal (or blocks the electrical connection between the first signal input terminal E1 and the low-voltage line VGL) during the corresponding working phase of the fifth control transistor CT5 of the second control sub-circuit 42. This improves the abnormality of the effective electrical signal output by the n-th level driver output terminal NOUT1 caused by the falling edge or rising edge of the electrical signal of the first control signal terminal COT1. At the same time, it also improves the stability of the electrical signal output by the n-th level driver output terminal NOUT1 when the threshold voltage (Vth) of the P-type transistor in the drive signal generating circuit 100 drifts negatively.

[0097] In some embodiments of the present disclosure, the control signal generating circuit 300 is also electrically connected to the n-1th level generated signal output terminal OUT1(n-1), the n-1th level generated signal reverse output terminal FOUT1(n-1), the nth level generated signal output terminal OUT1 and the nth level generated signal reverse output terminal FOUT1, respectively, and is used to control the connection or disconnection between the enable signal line EN and the control signal terminal CN1 under the control of the n-1th level drive signal, the n-1th level inverted drive signal, the nth level drive signal and the nth level inverted drive signal.

[0098] In some embodiments, the n-1th stage generated signal output terminal OUT1(n-1) is used to provide the n-1th stage driving signal; the n-1th stage generated signal inverting output terminal FOUT1(n-1) is used to provide the n-1th stage inverted driving signal; and the n-1th stage driving output terminal NOUT1(n-1) is used to provide the n-1th stage valid voltage signal or invalid voltage signal. Wherein, n-1 is an integer greater than or equal to 1.

[0099] In some embodiments, as shown in Figures 1, 2, 3, 7, and 8, in the above-mentioned first driving circuit, the first control signal terminal COT1 is electrically connected to the n-th stage generated signal output terminal OUT1, the invalid voltage signal is a low-potential signal, and the valid voltage signal is a high-potential signal.

[0100] In some embodiments, when the n-th stage driving output terminal NOUT1 is a valid voltage signal (a high potential signal), the transistor electrically connected to the n-th stage driving output terminal NOUT1 in the pixel circuit is turned on.

[0101] In some embodiments, as shown in FIG. 1 , FIG. 2 , FIG. 3 , FIG. 7 , and FIG. 8 , in the first driving circuit described above, the first isolation sub-circuit 46 is electrically connected between the first control output terminal CN2 and the first signal input terminal E1 .

[0102] In some embodiments, as shown in Figures 1, 2, 3, and 7, the first isolation sub-circuit 46 may include a first isolation transistor CT15, a gate of the first isolation transistor CT15 electrically connected to the first clock signal terminal CK, a first electrode of the first isolation transistor CT15 electrically connected to the first control output terminal CN2, and a second electrode of the first isolation transistor CT15 electrically connected to the first signal input terminal E1.

[0103] In some embodiments, as shown in Figures 1, 2, 3, and 8, the first isolation sub-circuit 46 may further include a second isolation transistor CT16, wherein the gate of the second isolation transistor CT16 is electrically connected to the second clock signal terminal CB, the first electrode of the second isolation transistor CT16 is electrically connected to the first control output terminal CN2, and the second electrode of the second isolation transistor CT16 is electrically connected to the first signal input terminal E1. One of the first isolation transistor CT15 and the second isolation transistor CT16 is an N-type transistor, and the other is a P-type transistor.

[0104] In some embodiments, as shown in FIG8 , the first isolation sub-circuit 46 can include both a first isolation transistor CT15 and a second isolation transistor CT16. The first isolation transistor CT15 and the second isolation transistor CT16 form a transmission gate structure, with the first isolation transistor CT15 being an N-type transistor and the second isolation transistor CT16 being a P-type transistor. In this case, during the corresponding operating phase, the sixth control transistor CT6 can be electrically connected to the low voltage line VGL via the second isolation transistor CT16 to maintain output stability. The first isolation transistor CT15 and the second isolation transistor CT16 can be simultaneously turned on or off, improving signal transmission performance and facilitating enhanced stability of the electrical signal outputted by the n-th stage driver output terminal NOUT1.

[0105] In some embodiments, as shown in Figures 4, 5, 6, and 9, in the above-mentioned second driving circuit, the first control signal terminal COT1 is electrically connected to the n-th stage generated signal reverse output terminal FOUT1, the invalid voltage signal is a high potential signal, and the valid voltage signal is a low potential signal.

[0106] In some embodiments, when the n-th stage driving output terminal NOUT1 is a valid voltage signal (low potential signal), the transistor electrically connected to the n-th stage driving output terminal NOUT1 in the pixel circuit is turned on.

[0107] In some embodiments, as shown in FIG. 4 , FIG. 5 , FIG. 6 , and FIG. 9 , the first isolation sub-circuit 46 is electrically connected between the low voltage line VGL and the first signal input terminal E1 .

[0108] In some embodiments, as shown in Figures 4, 5, 6, and 9, the first isolation sub-circuit 46 includes a third isolation transistor CT17, a gate of the third isolation transistor CT17 is electrically connected to the first clock signal terminal CK, a first electrode of the third isolation transistor CT17 is electrically connected to the first signal input terminal E1, and a second electrode of the third isolation transistor CT17 is electrically connected to the low voltage line VGL.

[0109] It should be noted that, referring to FIG. 10 , in some other embodiments of the present disclosure, the first isolation sub-circuit 46 may not be provided in the control circuit 400 , and the first signal input terminal E1 is directly connected to the low voltage line VGL.

[0110] In some embodiments, as shown in Figures 7 to 10, the first control sub-circuit 41 may include a first control transistor CT1, a second control transistor CT2, a third control transistor CT3, and a fourth control transistor CT4. The gate of the first control transistor CT1 is electrically connected to the control signal terminal CN1, the first electrode of the first control transistor CT1 is electrically connected to the high voltage line VGH, and the second electrode of the first control transistor CT1 is electrically connected to the first control output terminal CN2. The gate of the second control transistor CT2 is electrically connected to the control signal terminal CN1, the first electrode of the second control transistor CT2 is electrically connected to the first control output terminal CN2, and the second electrode of the second control transistor CT2 is electrically connected to the low voltage line VGL. The gate of the third control transistor CT3 is electrically connected to the first control output terminal CN2, the first electrode of the third control transistor CT3 is electrically connected to the high voltage line VGH, and the second electrode of the third control transistor CT3 is electrically connected to the control signal terminal CN1. The gate of the fourth control transistor CT4 is electrically connected to the first control output terminal CN2, the first electrode of the fourth control transistor CT4 is electrically connected to the control signal terminal CN1, and the second electrode of the fourth control transistor CT4 is electrically connected to the low voltage line VGL.

[0111] In some embodiments, as shown in Figures 7 to 10, the second control sub-circuit 42 may include a fifth control transistor CT5 and a sixth control transistor CT6. The gate of the fifth control transistor CT5 is electrically connected to the first control signal terminal COT1, the first electrode of the fifth control transistor CT5 is electrically connected to the high voltage line VGH, and the second electrode of the fifth control transistor CT5 is electrically connected to the second control output terminal CN3. The gate of the sixth control transistor CT6 is electrically connected to the first control signal terminal COT1, the first electrode of the sixth control transistor CT6 is electrically connected to the second control output terminal CN3, and the second electrode of the sixth control transistor CT6 is electrically connected to the first signal input terminal E1.

[0112] In some embodiments, as shown in Figures 7 to 10, the third control sub-circuit 43 includes a seventh control transistor CT7 and an eighth control transistor CT8. The gate of the seventh control transistor CT7 is electrically connected to the second control output terminal CN3, the first electrode of the seventh control transistor CT7 is electrically connected to the high voltage line VGH, and the second electrode of the seventh control transistor CT7 is electrically connected to the n-th stage driver output terminal NOUT1. The gate of the eighth control transistor CT8 is electrically connected to the second control output terminal CN3, the first electrode of the eighth control transistor CT8 is electrically connected to the n-th stage driver output terminal NOUT1, and the second electrode of the eighth control transistor CT8 is electrically connected to the low voltage line VGL.

[0113] In some embodiments, as shown in Figures 7 to 10, the first storage sub-circuit 44 may include a first capacitor CC1, and the second storage sub-circuit 45 may include a second capacitor CC2. A first plate of the first capacitor CC1 is electrically connected to the control signal terminal CN1, and a second plate of the first capacitor CC1 is electrically connected to the low-voltage line VGL. A first plate of the second capacitor CC2 is electrically connected to the second control output terminal CN3, and a second plate of the second capacitor CC2 is electrically connected to the low-voltage line VGL.

[0114] In some embodiments, as shown in Figures 7 to 10, the first control transistor CT1, the third control transistor CT3, the fifth control transistor CT5 and the seventh control transistor CT7 are all P-type transistors, and the second control transistor CT2, the fourth control transistor CT4, the sixth control transistor CT6 and the eighth control transistor CT8 are all N-type transistors.

[0115] It should be noted that, in the embodiment of the present disclosure, the active layer of the P-type transistor may include polysilicon, and the active layer of the N-type transistor may include a metal oxide semiconductor, but the present invention is not limited thereto.

[0116] Please refer to Figures 12 to 15. Figure 12 is a structural schematic diagram of the drive signal generating circuit 100 and the output reverse circuit 200 according to some embodiments of the present disclosure; Figure 13 is a schematic diagram comparing partial waveforms of the first structure illustrated in Figure 12 with partial signal waveforms of the related art; Figure 14 is a structural schematic diagram of the drive signal generating circuit 100 and the output reverse circuit 200 according to other embodiments of the present disclosure; Figure 15 is a structural schematic diagram of the drive signal generating circuit 100 and the output reverse circuit 200 according to still other embodiments of the present disclosure.

[0117] In some embodiments, the drive signal generating circuit 100 may include a first node control subcircuit 11 , a second node control subcircuit 12 , a first output node control subcircuit 13 , a second output node control subcircuit 14 , a potential maintaining subcircuit 15 and an output subcircuit 16 .

[0118] The first node control sub-circuit 11 is electrically connected to the first node N1, the first clock signal terminal CK, the low voltage line VGL and the second output node NJ2, respectively, and is used to control the connection between the first node N1 and the low voltage line VGL under the control of the first clock signal provided by the first clock signal terminal CK, and to control the connection or disconnection between the first node N1 and the first clock signal terminal CK under the control of the potential of the second output node NJ2.

[0119] The second node control subcircuit 12 is electrically connected to the first node N1, the first intermediate node NZ1, the high voltage line VGH, the first clock signal terminal CK, the second clock signal terminal CB, the second node N2, the input terminal STV and the low voltage line VGL, respectively, and is used to control the connection between the first intermediate node NZ1 and the high voltage line VGH under the control of the potential of the first node N1, control the connection between the first intermediate node NZ1 and the second clock signal terminal CB under the control of the potential of the second node N2, and control the potential of the second node N2 according to the potential of the first intermediate node NZ1, and control the connection between the input terminal STV and the second node N2 under the control of the first clock signal provided by the first clock signal terminal CK and the signal provided by the low voltage line VGL.

[0120] The first output node control subcircuit 93 is electrically connected to the first output node NJ1, the first node N1, the second clock signal terminal CB, the second intermediate node NZ2, the second output node NJ2 and the high voltage line VGH, respectively, and is used to control the connection between the second intermediate node NZ2 and the second clock signal terminal CB under the control of the potential of the first node N1, control the potential of the second intermediate node NZ2 according to the potential of the first node N1, control the connection between the second intermediate node NZ2 and the first output node NJ1 under the control of the second clock signal provided by the second clock signal terminal CB, and control the connection between the first output node NJ1 and the high voltage line VGH under the control of the potential of the second output node NJ2.

[0121] The second output node control sub-circuit 14 is electrically connected to the first clock signal terminal CK, the input terminal STV, the control voltage line VEL, the high voltage line VGH, the second node N2 and the second output node NJ2, respectively, and is used to control the connection between the second output node NJ2 and the input terminal STV under the control of the first clock signal provided by the first clock signal terminal CK, control the potential of the second output node NJ2 according to the potential of the second node N2, and control the connection between the second output node NJ2 and the high voltage line VGH under the control of the control voltage provided by the control voltage line VEL.

[0122] The potential maintaining sub-circuit 15 is electrically connected to the first output node NJ1 and is configured to maintain the potential of the first output node NJ1 .

[0123] The output sub-circuit 16 is electrically connected to the first output node NJ1, the second output node NJ2, the high voltage line VGH, the low voltage line VGL and the n-th stage generated signal output terminal OUT1, respectively, and is used to control the connection between the n-th stage generated signal output terminal OUT1 and the high voltage line VGH under the control of the potential of the first output node NJ1, and to control the connection between the n-th stage generated signal output terminal OUT1 and the low voltage line VGL under the control of the potential of the second output node NJ2.

[0124] In some embodiments, as shown in FIG12 , the output inverting circuit 200 may include an output reversing sub-circuit 21 and a second isolation sub-circuit 22. The output reversing sub-circuit 21 is electrically connected to the n-th stage generated signal output terminal OUT1, the high voltage line VGH, and the second signal input terminal E2. The output reversing sub-circuit 21 is configured to output an electrical signal from the high voltage line VGH or the second signal input terminal E2 to the n-th stage generated signal reversing output terminal FOUT1. The second isolation sub-circuit 22 is electrically connected to the second output node NJ2, the second signal input terminal E2, and the low voltage line VGL. The second isolation sub-circuit 22 is configured to control the connection or disconnection between the low voltage line VGL and the second signal input terminal E2.

[0125] In some embodiments, as shown in FIG12 , the second isolation sub-circuit 22 may include a fourth isolation transistor CT18. A gate of the fourth isolation transistor CT18 is electrically connected to the second output node NJ2, a first electrode of the fourth isolation transistor CT18 is electrically connected to the second signal input terminal E2, and a second electrode of the fourth isolation transistor CT18 is electrically connected to the low voltage line VGL.

[0126] In the related art, as shown in FIG13 , the signal at the n-th level drive signal output terminal OUT1 has a falling edge in the first dotted ellipse 71. When the reverse sub-circuit 21 is working, the voltage of the falling edge in the first dotted ellipse 71 is lower than the potential of the high voltage line VGH and greater than the potential of the low voltage line VGL. This causes the reverse sub-circuit 21 to output the n-th level drive signal at the n-th level generated signal output terminal OUT1, and the n-th level inverted drive signal output at the n-th level generated signal reverse output terminal FOUT1 is abnormal (fails to change from a low potential to a high potential in time). The electrical signal waveform of the n-th level generated signal reverse output terminal FOUT1 becomes wider, as shown in the second dotted ellipse 72 in FIG13 . The widening of the electrical signal waveform of the n-th level generated signal reverse output terminal FOUT1 will cause the effective signal waveform output from the n-th level drive output terminal NOUT1 to become wider, as shown in the third dotted ellipse 73 in FIG12 .

[0127] In some embodiments of the present disclosure, as shown in FIG12 and FIG13 , a second isolation sub-circuit 22 (fourth isolation transistor CT18) is provided in the output inverter circuit 200. The second isolation sub-circuit 22 is used to control the connection or disconnection between the low voltage line VGL and the second signal input terminal E2. The second isolation sub-circuit 22 (fourth isolation transistor CT18) is electrically connected to the second output node NJ2. The second isolation sub-circuit 22 (fourth isolation transistor CT18) is controlled by the potential of the second output node NJ2. Only when the n-th stage generated signal output terminal OUT1 outputs a high potential signal, the second isolation sub-circuit 22 (the fourth isolation transistor CT18) is turned on, and the second isolation sub-circuit 22 (the fourth isolation transistor CT18) is turned off at other times, cutting off the electrical connection between the second signal input terminal E2 and the low voltage line VGL, thereby preventing the reverse sub-circuit 21 from outputting an electrical signal slower, and preventing the n-stage generated signal reverse output terminal FOUT1 from outputting an abnormal n-stage inverted drive signal (able to be converted from a low potential to a high potential in time), as shown by the fourth dotted ellipse 74 in FIG13 , thereby preventing the effective signal waveform outputted by the n-stage drive output terminal NOUT1 from becoming wider, as shown by the fifth dotted ellipse 75 in FIG13 . In addition, a second isolation sub-circuit 22 (fourth isolation transistor CT18) is additionally provided. The second isolation sub-circuit 22 (fourth isolation transistor CT18) provides an electrical signal to the second signal input terminal E2, and cuts off the connection between the second output inverting transistor CT14 and the low potential signal (or blocks the electrical connection between the second signal input terminal E2 and the low voltage line VGL) during the corresponding working phase of the first output inverting transistor CT13 of the inverting sub-circuit 21. Even if the second output inverting transistor CT14 is mistakenly turned on, no current is generated, thereby improving the potential conversion efficiency of the inverting sub-circuit 21 and preventing the electrical signal waveform at the n-stage generated signal inverting output terminal FOUT1 from widening, as shown by the fourth dotted ellipse 74 in FIG. 13 , thereby preventing the effective signal waveform output by the n-stage driver output terminal NOUT1 from widening, as shown by the fifth dotted ellipse 75 in FIG. 13 , thereby improving the stability of the electrical signal output by the n-stage driver output terminal NOUT1.

[0128] In some embodiments, as shown in FIG12 , the output inverting circuit 200 may further include an inverting storage sub-circuit 23. The inverting storage sub-circuit 23 is electrically connected to the n-th stage generated signal output terminal OUT1, and is used to maintain the potential of the n-th stage generated signal output terminal OUT1; or / and, the driving signal generating circuit further includes a driving storage sub-circuit 17, which is electrically connected to the n-th stage generated signal output terminal OUT1 and the second output node NJ2, and is used to maintain the potential of the n-th stage generated signal output terminal OUT1.

[0129] In some embodiments, as shown in FIG12 , the reverse storage sub-circuit 23 may include a third capacitor CC3 , a first plate of the third capacitor CC3 being electrically connected to the nth stage generated signal output terminal OUT1 , and a second plate of the third capacitor CC3 being electrically connected to the low voltage line VGL.

[0130] The driving storage sub-circuit 17 may include a fourth capacitor CC4 , a first plate of the fourth capacitor CC4 being electrically connected to the n-th stage generated signal output terminal OUT1 , and a second plate of the fourth capacitor CC4 being electrically connected to the second output node NJ2 .

[0131] It should be noted that, in order to meet the requirements of a narrow frame, the widths of the fifteenth transistor T15 and the sixteenth transistor T16 of the drive signal generating circuit 100 cannot be too large. When the sixteenth transistor T16 outputs a low-potential pull-down signal, the bootstrap function of the gate-source capacitance (Cgs) of the transistor is weakened, resulting in a step increase (rising or falling edge). Therefore, in some embodiments, to balance output quality and frame size, a drive storage sub-circuit 17 is added between the n-th stage generated signal output terminal OUT1 and the second output node NJ2 (a fourth capacitor CC4 is added between the gate and the first electrode of the sixteenth transistor T16) to assist in potential bootstrapping. When the potential of the n-stage generated signal output terminal OUT1 changes from a high potential to a low potential, after the size of the sixteenth transistor T16 is reduced, the gate-source capacitance of the sixteenth transistor T16 is reduced, and the ability of the n-stage generated signal output terminal OUT1 to pull down the voltage of the second output node NJ2 through the gate-source capacitance (Cgs) of the transistor is reduced. The driving storage sub-circuit 17 (the fourth capacitor CC4) replaces the gate-source capacitance (Cgs) of the sixteenth transistor T16 to play a bootstrap role. When the potential of the n-stage generated signal output terminal OUT1 changes from a high potential to a low potential, the potential of the second output node NJ2 can be pulled down in time.

[0132] At the same time, when the second output node NJ2 is pulled from a low potential to a high potential, the gate-source capacitance (Cgs) of the transistor in the conventional design is significantly reduced in the off state. At the same time, the load of the n-stage generated signal output terminal OUT1 includes multiple pixel circuits connected to the display area. Therefore, the voltage change of the second output node NJ2 has essentially no effect on the n-stage generated signal output terminal OUT1. When the drive storage sub-circuit 17 (fourth capacitor CC4) is added, the capacitance of the drive storage sub-circuit 17 (fourth capacitor CC4) is constant, causing the n-stage generated signal output terminal OUT1 (at this time, the fifteenth transistor T15 and the sixteenth transistor T16 are both turned off) to jump accordingly. Therefore, adding the reverse storage sub-circuit 23 (third capacitor CC3) to the n-stage generated signal output terminal OUT1 suppresses the impact of the potential jump of the second output node NJ2 on the potential of the n-stage generated signal output terminal OUT1.

[0133] It should be noted that in some other embodiments of the present disclosure, in the example of Figure 12, the output inversion circuit 200 may also only include the output reverse sub-circuit 21 and the second isolation sub-circuit 22, but not the reverse storage sub-circuit 23, and the drive signal generating circuit 100 may also not include the drive storage sub-circuit 17.

[0134] In some embodiments, as shown in FIG12 , the output inverter circuit 200 includes a first output inverter transistor CT13 and a second output inverter transistor CT14. The gate of the first output inverter transistor CT13 is electrically connected to the n-stage generated signal output terminal OUT1, the first electrode of the first output inverter transistor CT13 is electrically connected to the high voltage line VGH, and the second electrode of the first output inverter transistor CT13 is electrically connected to the n-stage generated signal inverting output terminal FOUT1. The gate of the second output inverter transistor CT14 is electrically connected to the n-stage generated signal output terminal OUT1, the first electrode of the second output inverter transistor CT14 is electrically connected to the n-stage generated signal inverting output terminal FOUT1, and the second electrode of the second output inverter transistor CT14 is electrically connected to the second signal input terminal E2. In some embodiments, one of the first output inverter transistor CT13 and the second output inverter transistor CT14 is an N-type transistor, and the other is a P-type transistor. FIG12 takes the example of the first output inverter transistor CT13 being a P-type transistor and the second output inverter transistor CT14 and the fourth isolation transistor CT18 being N-type transistors.

[0135] In some embodiments, as shown in Figures 12, 14 and 15, the first node control subcircuit 11 may include a first transistor T1, a second transistor T2 and a third transistor T3; the second output node control subcircuit 14 includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0136] The gate of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the low voltage line VGL, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the third transistor T3. The gate of the second transistor T2 is electrically connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the first electrode of the second transistor T2 is electrically connected to the first electrode of the third transistor T3. The gate of the third transistor T3 is electrically connected to the low voltage line VGL, and the second electrode of the third transistor T3 is electrically connected to the first node N1.

[0137] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK, and the first electrode of the fourth transistor T4 is electrically connected to the input terminal STV. The gate of the fifth transistor T5 is electrically connected to the low voltage line VGL, the first electrode of the fifth transistor T5 is electrically connected to the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 is electrically connected to the second output node NJ2. The gate of the sixth transistor T6 and the first electrode of the sixth transistor T6 are both electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the second output node NJ2. The gate of the seventh transistor T7 is electrically connected to the control voltage line VEL, the first electrode of the seventh transistor T7 is electrically connected to the high voltage line VGH, and the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the fifth transistor T5.

[0138] In some embodiments, the second node control subcircuit 12 may include an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C3. The gate of the eighth transistor T8 is electrically connected to the second node N2, the second electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal CB, and the first electrode of the eighth transistor T8 is electrically connected to the first intermediate node NZ1. The gate of the ninth transistor T9 is electrically connected to the second electrode of the first transistor T1, the first electrode of the ninth transistor T9 is electrically connected to the high voltage line VGH, and the second electrode of the ninth transistor T9 is electrically connected to the first intermediate node NZ1. The gate of the tenth transistor T10 is electrically connected to the first clock signal terminal CK, the first electrode of the tenth transistor T10 is electrically connected to the input terminal STV, and the second electrode of the tenth transistor T10 is electrically connected to the first electrode of the eleventh transistor T11. The gate of the eleventh transistor T11 is electrically connected to the low voltage line VGL, and the second electrode of the eleventh transistor T11 is electrically connected to the second node N2; the first plate of the fifth capacitor C3 is electrically connected to the first intermediate node NZ1, and the second plate of the fifth capacitor C3 is electrically connected to the second node N2.

[0139] In some embodiments, the first output node control subcircuit 13 may include a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a sixth capacitor C4. The gate of the twelfth transistor T12 is electrically connected to the first node N1, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the second intermediate node NZ2. The gate of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second intermediate node NZ2, and the second electrode of the thirteenth transistor T13 is electrically connected to the first output node NJ1. The gate of the fourteenth transistor T14 is electrically connected to the first electrode of the fifth transistor T5, the second electrode of the fourteenth transistor T14 is electrically connected to the high voltage line VGH, and the first electrode of the fourteenth transistor T14 is electrically connected to the first output node NJ1. The first plate of the sixth capacitor C4 is electrically connected to the first node N1, and the second plate of the sixth capacitor C4 is electrically connected to the second intermediate node NZ2.

[0140] In some embodiments, the potential maintaining subcircuit may include a seventh capacitor C5 , wherein a first plate of the seventh capacitor C5 is electrically connected to the first output node NJ1 , and a second plate of the seventh capacitor C5 is electrically connected to the high voltage line VGH.

[0141] In some embodiments, the output sub-circuit 16 may include a fifteenth transistor T15 and a sixteenth transistor T16. The gate of the fifteenth transistor T15 is electrically connected to the first output node NJ1, the first electrode of the fifteenth transistor T15 is electrically connected to the high voltage line VGH, and the second electrode of the fifteenth transistor T15 is electrically connected to the n-th stage generated signal output terminal OUT1. The gate of the sixteenth transistor T16 is electrically connected to the second output node NJ2, the first electrode of the sixteenth transistor T16 is electrically connected to the n-th stage generated signal output terminal OUT1, and the second electrode of the sixteenth transistor T16 is electrically connected to the low voltage line VGL.

[0142] In Figure 12, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the sixteenth transistor T16 are P-type transistors as an example, but the present invention is not limited thereto.

[0143] It should be noted that the output inverting circuit 200 illustrated in FIG12 includes an output inverting sub-circuit 21 and a second isolation sub-circuit 22, the output inverting circuit 200 also includes an inverting storage sub-circuit 23, and the drive signal generating circuit 100 also includes a drive storage sub-circuit 17. In other embodiments, the output inverting circuit 200 may include the output inverting sub-circuit 21 and the second isolation sub-circuit 22 but not the inverting storage sub-circuit 23, and the drive signal generating circuit 100 may also not include the drive storage sub-circuit 17. In still other embodiments, the output inverting circuit 200 may include the output inverting sub-circuit 21 and the second isolation sub-circuit 22, the output inverting circuit 200 may include the inverting storage sub-circuit 23, or the drive signal generating circuit 100 may include the drive storage sub-circuit 17.

[0144] It should be noted that, as shown in Figure 15, in some embodiments, the output inverting circuit 200 may not include the second isolation sub-circuit 22, the output inverting circuit 200 may not include the reverse storage sub-circuit 23, and the drive signal generating circuit 100 may not include the drive storage sub-circuit 17.

[0145] In some embodiments, as shown in Figures 7 to 10, the control signal generating circuit 300 may include a ninth control transistor CT9, a tenth control transistor CT10, an eleventh control transistor CT11, and a twelfth control transistor CT12. The gate of the ninth control transistor CT9 is electrically connected to the n-1th stage generated signal inverting output terminal FOUT1(n-1), the first electrode of the ninth control transistor CT9 is electrically connected to the enable signal line EN, and the second electrode of the ninth control transistor CT9 is electrically connected to the first electrode of the eleventh control transistor CT11. The gate of the tenth control transistor CT10 is electrically connected to the n-1th stage generated signal output terminal OUT1(n-1), the first electrode of the tenth control transistor CT10 is electrically connected to the enable signal line EN, and the second electrode of the tenth control transistor CT10 is electrically connected to the first electrode of the eleventh control transistor CT11. The gate of the eleventh control transistor CT11 is electrically connected to the nth stage generated signal output terminal OUT1, and the second electrode of the eleventh control transistor CT11 is electrically connected to the control signal terminal CN1. The gate of the twelfth control transistor CT12 is electrically connected to the nth stage generated signal inverting output terminal FOUT1, the first electrode of the twelfth control transistor CT12 is electrically connected to the first electrode of the eleventh control transistor CT11, and the second electrode of the twelfth control transistor CT12 is electrically connected to the control signal terminal CN1.

[0146] In some embodiments, the ninth control transistor CT9 and the eleventh control transistor CT11 may be P-type transistors, and the tenth control transistor CT10 and the twelfth control transistor CT12 may be N-type transistors.

[0147] Please refer to Figures 16 to 20, Figure 16 is a circuit diagram of the first driving circuit according to some embodiments of the present disclosure; Figure 17 is a schematic diagram of the electrical signals of the first driving circuit shown in Figure 16 at stage (1); Figure 18 is a schematic diagram of the electrical signals of the first driving circuit shown in Figure 16 at stage (2); Figure 19 is a schematic diagram of the electrical signals of the first driving circuit shown in Figure 16 at stage (3); Figure 20 is a schematic diagram of the electrical signals of the first driving circuit shown in Figure 16 at stage (4).

[0148] It should be noted that the first driving circuit is a normally low type adjustable high voltage waveform (the invalid signal is a low potential signal, and the valid signal is a high potential signal).

[0149] The first detailed circuit diagram of the first driving circuit illustrated in FIG16 is a combination of the control signal generating circuit and the first structure of the control circuit illustrated in FIG7 and the second structure of the driving signal generating circuit 100 illustrated in FIG14. FIG17 to FIG20 are schematic diagrams of electrical signals at various stages of the example in FIG16.

[0150] It should be noted that the thick dotted lines and thick dotted arrows in Figures 17 to 20 represent the transmission process of high-potential signals (or the signals of the high-voltage line VGH), and the thin dotted lines and thin dotted arrows in Figures 17 to 20 represent the transmission process of low-potential signals (or the signals of the low-voltage line VGL).

[0151] FIG3 is a timing diagram of the first detailed circuit of the first driving circuit of FIG16. The working process of the first detailed circuit of the first driving circuit is described below in conjunction with the timing diagram of FIG3 and FIG16 to FIG20.

[0152] In the first stage, as shown in FIG3 and FIG17 , the input terminal STV and the second clock signal terminal CB are at a high potential, and the first clock signal terminal CK is at a low potential. At this time, the fourth transistor T4, the first transistor T1, the ninth transistor T9, the twelfth transistor T12, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second transistor T2, the eighth transistor T8, the thirteenth transistor T13, the fourteenth transistor T4, the seventh transistor T7, and the sixth transistor T6 are turned off. The first internal node R1 (the second electrode of the fourth transistor T4), the second output node NJ2, and the second node N2 are at a high potential, and the second internal node R2 (the second electrode of the first transistor T1) and the first node N1 are at a low potential. At this time, since the thirteenth transistor T13 is turned off, the voltage of the first output node NJ1 remains at a high potential. At this time, the n-th level generated signal output terminal OUT1 maintains the original output voltage, i.e., a low potential. The first output inverting transistor CT13 is turned on, the second output inverting transistor CT14 is turned off, and the n-th level generated signal reverse output terminal FOUT1 is at a high potential. At this time, the high potential of the enable signal line EN is written to the control signal terminal CN1 through the turned-on ninth control transistor CT9, tenth control transistor CT10, eleventh control transistor CT11, and twelfth control transistor CT12. At this time, the first control transistor CT1, fourth control transistor CT4, sixth control transistor CT6, seventh control transistor CT7, and first isolation transistor CT15 are turned off. The n-th stage driver output terminal NOUT1 is at a low potential.

[0153] In the second stage, as shown in FIG3 and FIG18 , the input terminal STV and the first clock signal terminal CK are at a high potential, and the second clock signal terminal CB is at a low potential. At this time, the fourth transistor T4, the second transistor T2, the first transistor T1, the eighth transistor T8, the ninth transistor T9, the fourteenth transistor T14, the seventh transistor T7, the tenth transistor T10, and the sixth transistor T6 are turned off, the third transistor T3, the fifth transistor T5, and the eleventh transistor T11 are turned on, and the second internal node R2 (the second electrode of the first transistor T1) and the first node N1 are kept at a low potential because the associated transistors are all turned off. Therefore, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, the first output node NJ1 is reduced to a low potential, and the second output node NJ2 is kept at a high potential. At this time, the fifteenth transistor T15 is turned on, and the sixteenth transistor T16 is turned off. The voltage of the n-th stage generated signal output terminal OUT1 becomes a high potential. At this time, the first output inverting transistor CT13 is turned off, and the second output inverting transistor CT14 is turned on. At this time, the voltage of the N-th stage generated signal reverse output terminal FOUT1 becomes a low voltage. At this time, the eleventh and twelfth control transistors CT11 and CT12 are turned off, and the voltage at the control signal terminal CN1 remains high. The second control transistor CT2, the first isolation transistor CT15, and the sixth control transistor CT6 are turned on, and the second control output terminal CN3 is electrically connected to the low voltage line VGL, reaching a low voltage. At this time, the seventh control transistor CT7 is turned on, and the eighth control transistor CT8 is turned off. The n-th stage driver output terminal NOUT1 outputs a high voltage.

[0154] In the third stage, as shown in FIG3 and FIG19 , the input terminal STV and the second clock signal terminal CB are at a high potential, and the first clock signal terminal CK is at a low potential. At this time, the fourth transistor T4, the first transistor T1, the ninth transistor T9, the twelfth transistor T12, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second transistor T2, the eighth transistor T8, the thirteenth transistor T13, the fourteenth transistor T14, the seventh transistor T7, and the sixth transistor T6 are turned off. The first internal node R1 (the second electrode of the fourth transistor T4), the second output node NJ2, and the second internal node R2 (the second electrode of the first transistor T1) are at a high potential, and the second internal node R2 (the second electrode of the first transistor T1) and the first node N1 are at a low potential. At this time, since the thirteenth transistor T13 is turned off, the first output node NJ1 maintains the voltage of the second stage (i.e., the low voltage) through the seventh capacitor C5. At this time, the fifteenth transistor T15 is turned on and the sixteenth transistor T16 is turned off. The voltage of the n-th stage generated signal output terminal OUT1 is a high voltage. In this way, the second output inverting transistor CT14 is turned on and the first output inverting transistor CT13 is turned off, that is, the output voltage of the (2) stage is maintained. The eleventh control transistor CT11 and the twelfth control transistor CT12 are turned off, and the voltage of the control signal terminal CN1 maintains the voltage of the (1) stage, that is, a high voltage. At this time, the first control transistor CT1, the fourth control transistor CT4, the fifth control transistor CT5, the seventh control transistor CT7, and the first isolation transistor CT15 are turned off. The fifth control transistor CT5 is turned off and the connection between the second control output terminal CN3 and the low voltage line VGL is cut off by the first isolation transistor CT15. The second control output terminal CN3 maintains a low voltage through the voltage stabilization effect of the second capacitor CC2 voltage, ensuring that the seventh control transistor CT7 is turned on and the n-th level drive output terminal NOUT1 outputs a high potential.

[0155] The time between stage (3) and stage (4) is basically the circuit action cycle of stage (2) and stage (3).

[0156] In the fourth stage, as shown in FIG3 and FIG20 , the second clock signal terminal CB is at a high potential, and the input terminal STV and the first clock signal terminal CK are at a low potential. At this time, the fourth transistor T4, the second transistor T2, the ninth transistor T9, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on. At this time, the voltages of the first internal node R1 (the second electrode of the fourth transistor T4), the second internal node R2 (the second electrode of the first transistor T1), and the first node N1 are all low voltages. The twelfth transistor T12 and the fourteenth transistor T14 are in the on state. Since the thirteenth transistor T13 is turned off, the high voltage line VGH is connected to the first output node NJ1 through the fourteenth transistor T14. The first output node NJ1 is at a high voltage. At this time, the fifteenth transistor T15 is turned off. The tenth transistor T10 and the eleventh transistor T11 are turned on, the voltage of the second node N2 drops to a low voltage, and the sixth transistor T6 in the diode connection state is turned on. The second output node NJ2 is pulled low via two paths: the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10, the eleventh transistor T11, and the sixth transistor T6. The sixteenth transistor T16 turns on. The voltage at the n-stage generated signal output terminal OUT1 is pulled down from a high voltage. At this time, the first output inverting transistor CT13 turns on. The n-stage generated signal reverse output terminal FOUT1 outputs a high voltage. At this time, the ninth control transistor CT9 and the tenth control transistor CT10 turn off, and the control signal terminal CN1 continues to maintain a high potential. The second control transistor CT2, the third control transistor CT3, the fifth control transistor CT5, and the eighth control transistor CT8 turn on, and the first control transistor CT1, the fourth control transistor CT4, the sixth control transistor CT6, and the seventh control transistor CT7 turn off. At this time, the n-stage driver output terminal NOUT1 outputs a low potential.

[0157] In stage (4), the n-th stage generated signal output terminal OUT1 is theoretically pulled to a low potential (the voltage of the low-voltage line VGL). However, due to the characteristic limitations of the P-type transistor, the voltage of the second output node NJ2 is actually the first low voltage -Vth1, where the first low voltage is the voltage of the low-voltage line VGL, and the first threshold voltage Vth1 is the threshold voltage of the fifth transistor T5. The voltage output by the n-th stage generated signal output terminal OUT1 is the first low voltage -Vth1-Vth2, and the second threshold voltage Vth2 is the threshold voltage of the sixteenth transistor T16.

[0158] Because the related art lacks the first isolation sub-circuit 46 (first isolation transistor CT15), although the bootstrap effect of the sixteenth transistor T16 can further reduce the output voltage of the n-stage generated signal output terminal OUT1, this voltage is still sufficient to turn on the sixth control transistor CT6 (the source voltage is the voltage of the low-voltage line VGL). This results in current flowing between the fifth control transistor CT5 and the sixth control transistor CT6, increasing the time it takes for the second control output terminal CN3 to rise to a high potential (the voltage of the high-voltage line VGH). This widens the rising edge of the third control transistor CT3. As the input terminal of the inverter formed by the seventh control transistor CT7 and the eighth control transistor CT8, the widened rising edge of the second control output terminal CN3 causes a widening of the falling edge of the inverter output, even preventing it from being fully pulled down within the first clock signal terminal CK pulse time. In this case, the negative shift of the threshold voltage Vth of the P-type transistor due to external environmental factors, manufacturing variations, and other factors is more serious. The present application sets a first isolation sub-circuit 46 (first isolation transistor CT15) to cut off the electrical connection between the sixth control transistor CT6 and the low voltage line VGL during this time, that is, no current is generated when the sixth control transistor CT6 is mistakenly turned on, thereby improving the pull-up efficiency of the second control output terminal CN3 and improving the stability of the electrical signal output by the n-th level drive output terminal NOUT1.

[0159] Please refer to Figure 21, which is a circuit diagram of a first drive circuit according to other embodiments of the present disclosure. It should be noted that the second detailed circuit of the first drive circuit illustrated in Figure 21 is a combination of the control signal generation circuit and the second structure of the control circuit illustrated in Figure 8 and the third structure of the drive signal generation circuit 100 illustrated in Figure 15. The operating process of the second detailed circuit of the first drive circuit illustrated in Figure 21 is similar to the operating process of the first detailed circuit of the first drive circuit illustrated in Figure 16 and will not be repeated here.

[0160] The control circuit shown in FIG21 is a further improvement on the example shown in FIG16 . The first isolation sub-circuit 46 is configured as a transmission gate structure including a first isolation transistor CT15 and a second isolation transistor CT16. The first isolation transistor CT15 is an N-type transistor, and the second isolation transistor CT16 is a P-type transistor. In this case, the sixth control transistor CT6 can be electrically connected to the low-voltage line VGL via the second isolation transistor CT16 to maintain output stability. The first isolation transistor CT15 and the second isolation transistor CT16 can be turned on or off simultaneously, improving signal transmission performance and contributing to increased stability of the electrical signal outputted by the n-th-stage driver output terminal NOUT1.

[0161] Please refer to Figures 22 to 26, Figure 22 is a circuit diagram of the second driving circuit according to some embodiments of the present disclosure; Figure 23 is a schematic diagram of the electrical signals of the second driving circuit shown in Figure 22 at stage (1); Figure 24 is a schematic diagram of the electrical signals of the second driving circuit shown in Figure 22 at stage (2); Figure 25 is a schematic diagram of the electrical signals of the second driving circuit shown in Figure 22 at stage (3); Figure 26 is a schematic diagram of the electrical signals of the second driving circuit shown in Figure 22 at stage (4).

[0162] It should be noted that the second drive circuit uses a normally high, adjustable low-voltage waveform (the inactive signal is a high-voltage signal, and the active signal is a low-voltage signal). The first detailed circuit diagram of the second drive circuit illustrated in FIG22 is a combination of the control signal generation circuit and the fourth structure of the control circuit illustrated in FIG10 , and the first structure of the drive signal generation circuit 100 illustrated in FIG12 . FIG23 through FIG26 are schematic diagrams of electrical signals at various stages of the example in FIG22 .

[0163] Fig. 13 is a timing diagram of the first detailed circuit of the second driving circuit shown in Fig. 22. The operation process of the first detailed circuit of the second driving circuit will be described below in conjunction with the timing diagram of Fig. 13 and Figs. 22 to 26.

[0164] In the first stage, as shown in FIG13 and FIG23, the input terminal STV and the second clock signal terminal CB are at a high potential, and the first clock signal terminal CK is at a low potential. At this time, the fourth transistor T4, the first transistor T1, the ninth transistor T9, the twelfth transistor T12, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second transistor T2, the eighth transistor T8, the thirteenth transistor T13, the fourteenth transistor T14, the seventh transistor T7, and the sixth transistor T6 are turned off. The first internal node R1 (the second electrode of the fourth transistor T4), the second output node NJ2, and the second node N2 are at a high potential, and the second internal node R2 (the second electrode of the first transistor T1) and the first node N1 are at a low potential. At this time, since the thirteenth transistor T13 is turned off, the voltage of the first output node NJ1 remains at a high potential. At this time, the n-level generated signal output terminal OUT1 maintains the original output voltage, that is, a low potential. The first output inverting transistor CT13 is turned on, the second output inverting transistor CT14 is turned off, and the n-level generated signal reverse output terminal FOUT1 is at a high potential. At this time, the low potential of the enable signal line EN is written to the control signal terminal CN1 through the turned-on ninth control transistor CT9, tenth control transistor CT10, eleventh control transistor CT11, and twelfth control transistor CT12. At this time, the first control transistor CT1, fourth control transistor CT4, sixth control transistor CT6, and seventh control transistor CT7 are turned on. The n-th stage driver output terminal NOUT1 is at a high potential.

[0165] In the second stage, as shown in FIG13 and FIG24 , the input terminal STV and the first clock signal terminal CK are at a high potential, and the second clock signal terminal CB is at a low potential. At this time, the fourth transistor T4, the second transistor T2, the first transistor T1, the eighth transistor T8, the ninth transistor T9, the fourteenth transistor T14, the seventh transistor T7, the tenth transistor T10, and the sixth transistor T6 are turned off, and the third transistor T3, the fifth transistor T5, and the eleventh transistor T11 are turned on. The second internal node R2 (the second electrode of the first transistor T1) and the first node N1 are kept at a low potential because the associated transistors are all turned off. Therefore, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, the first output node NJ1 is reduced to a low potential, and the second output node NJ2 is kept at a high potential. At this time, the fifteenth transistor T15 is turned on, and the sixteenth transistor T16 is turned off. The voltage of the n-th stage generated signal output terminal OUT1 becomes a high potential. At this time, the first output inverting transistor CT13 is turned off, and the second output inverting transistor CT14 and the fourth isolation transistor CT18 are turned on. At this point, the voltage at the n-stage generated signal inverting output terminal FOUT1 becomes low. The eleventh and twelfth control transistors CT11 and CT12 are turned off, and the voltage at the control signal terminal CN1 remains low. The first, fourth, fifth, and eighth control transistors CT1, CT4, CT5, and CT8 are turned on. The n-stage driver output terminal NOUT1 outputs a low voltage.

[0166] In the third stage, as shown in FIG13 and FIG25 , the input terminal STV and the second clock signal terminal CB are at a high potential, and the first clock signal terminal CK is at a low potential. At this time, the fourth transistor T4, the first transistor T1, the ninth transistor T9, the twelfth transistor T12, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on, and the second transistor T2, the eighth transistor T8, the thirteenth transistor T13, the fourteenth transistor T14, the seventh transistor T7, and the sixth transistor T6 are turned off. The first internal node R1 (the second electrode of the fourth transistor T4), the second output node NJ2, and the second node N2 are at a high potential, and the second internal node R2 (the second electrode of the first transistor T1) and the first node N1 are at a low potential. At this time, since the thirteenth transistor T13 is turned off, the first output node NJ1 maintains the voltage of the second stage, i.e., the low voltage, through the seventh capacitor C5. At this time, the fifteenth transistor T15 is turned on, and the sixteenth transistor T16 is turned off. The voltage of the n-th stage generated signal output terminal OUT1 is a high voltage. In this way, the fourteenth control transistor CT14 and the fourth isolation transistor CT18 are turned on, and the thirteenth control transistor CT13 is turned off, that is, the n-stage generated signal reverse output terminal FOUT1 maintains the output voltage of stage (2). The eleventh control transistor CT11 and the twelfth control transistor CT12 are turned off, and the voltage of the control signal terminal CN1 maintains the voltage of stage (1), that is, a low voltage. At this time, the first control transistor CT1, the fourth control transistor CT4, the fifth control transistor CT5, and the eighth control transistor CT8 are turned on. The n-stage driver output terminal NOUT1 outputs a low potential.

[0167] The time between stage (3) and stage (4) is basically the circuit action cycle of stage (2) and stage (3).

[0168] In the fourth stage, as shown in FIG13 and FIG26 , the second clock signal terminal CB is at a high potential, and the input terminal STV and the first clock signal terminal CK are at a low potential. At this time, the fourth transistor T4, the second transistor T2, the ninth transistor T9, the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the eleventh transistor T11 are turned on. At this time, the voltages of the first internal node R1 (the second electrode of the fourth transistor T4), the second internal node R2 (the second electrode of the first transistor T1), and the first node N1 are all low voltages. The twelfth transistor T12 and the fourteenth transistor T14 are in the on state. Since the thirteenth transistor T13 is turned off, the high voltage line VGH is connected to the first output node NJ1 through the fourteenth transistor T14. The first output node NJ1 is at a high voltage. At this time, the fifteenth transistor T15 is turned off. The tenth transistor T10 and the eleventh transistor T11 are turned on, the voltage of the second node N2 drops to a low voltage, and the sixth transistor T6 in the diode connection state is turned on. The second output node NJ2 is pulled low via two paths, namely, the fourth transistor T4, the fifth transistor T5, and the tenth transistor T10, the eleventh transistor T11, and the sixth transistor T6. At this time, the fourth isolation transistor CT18 is turned off. The sixteenth transistor T16 is turned on. The voltage at the n-stage generated signal output terminal OUT1 is pulled down from a high potential (to the potential of the low voltage line VGL). At this time, the first output inverting transistor CT13 is turned on. The n-stage generated signal reverse output terminal FOUT1 outputs a high voltage. At this time, the ninth control transistor CT9 and the tenth control transistor CT10 are turned off, and the control signal terminal CN1 continues to maintain a low potential. The first control transistor CT1, the fourth control transistor CT4, the sixth control transistor CT6, and the seventh control transistor CT7 are turned on, and the second control transistor CT2, the third control transistor CT3, the fifth control transistor CT5, and the eighth control transistor CT8 are turned off. At this time, the n-stage driver output terminal NOUT1 outputs a high potential.

[0169] In stage (4), the n-th stage generated signal output terminal OUT1 is theoretically pulled to a low potential (the voltage of the low-voltage line VGL). However, due to the characteristic limitations of the P-type transistor, the voltage of the second output node NJ2 is actually the first low voltage -Vth1, where the first low voltage is the voltage of the low-voltage line VGL, and the first threshold voltage Vth1 is the threshold voltage of the fifth transistor T5. The voltage output by the n-th stage generated signal output terminal OUT1 is the first low voltage -Vth1-Vth2, and the second threshold voltage Vth2 is the threshold voltage of the sixteenth transistor T16.

[0170] Because the related art lacks the second isolation sub-circuit 22 (fourth isolation transistor CT18), although the bootstrap effect of the sixteenth transistor T16 can further reduce the output voltage of the n-stage generated signal output terminal OUT1, this voltage is still sufficient to turn on the second output inverting transistor CT14 (the source voltage of which is the voltage of the low voltage line VGL). This results in a current flowing between the first output inverting transistor CT13 and the second output inverting transistor CT14, increasing the time it takes for the n-stage generated signal inverting output terminal FOUT1 to be pulled up to a high potential (the voltage of the high voltage line VGH). In other words, the rising edge of the output of the first output inverting transistor CT13 (the n-stage generated signal inverting output terminal FOUT1) becomes wider, thereby causing a wider falling edge of the second control output terminal CN3. As the input terminal of the inverter composed of the seventh control transistor CT7 and the eighth control transistor CT8, the wider rising edge of the n-stage generated signal inverting output terminal FOUT1 (or the wider falling edge of the second control output terminal CN3) causes a wider falling edge of the inverter output, which may even prevent the inverter from being fully pulled up within the pulse time of the first clock signal terminal CK. This further causes the final output pulse of the n-stage driver output terminal NOUT1 to become wider. In this case, the threshold voltage Vth of the P-type transistor shifts negatively under the influence of the external environment, manufacturing differences, etc., which is more serious. The present application sets a second isolation sub-circuit 22 (fourth isolation transistor CT18) to cut off the connection between the second output inverting transistor CT14 and the low voltage line VGL during this time, increasing the actual resistance between the second output inverting transistor CT14 and the low voltage line VGL. That is, no current is generated when the second output inverting transistor CT14 is mistakenly turned on, thereby improving the pull-up efficiency of the n-stage generated signal reverse output terminal FOUT1 and improving the stability of the electrical signal output by the n-stage driver output terminal NOUT1 when the threshold voltage (Vth) of the P-type transistor in the drive signal generating circuit 100 shifts negatively.

[0171] Please refer to Figure 27, which is a circuit diagram of a second driving circuit according to other embodiments of the present disclosure. The second detailed circuit diagram of the second driving circuit illustrated in Figure 27 is a combination of the control signal generating circuit and the third structure of the control circuit illustrated in Figure 9, and the second structure of the driving signal generating circuit 100 illustrated in Figure 14.

[0172] It should be noted that the working process of the second detailed circuit of the first driving circuit shown in FIG27 is similar to the working process of the first detailed circuit of the second driving circuit shown in FIG22 , and will not be described in detail here.

[0173] In the control circuit of the example of FIG27 , compared with the example of FIG22 , the example of FIG27 does not have the second isolation sub-circuit 22 (fourth isolation transistor CT18 ), but the example of FIG27 may also have the second isolation sub-circuit 22 (fourth isolation transistor CT18 ).

[0174] In the control circuit of the example of Figure 27, compared with the example of Figure 22, the example of Figure 27 is also provided with a first isolation sub-circuit (third isolation transistor CT17). The function of the third isolation transistor CT17 is the same as or similar to that of the first isolation transistor CT15, and will not be repeated here.

[0175] It should be noted that Figure 7 illustrates the first structural intention of the control signal generating circuit and the control circuit; Figure 8 illustrates the second structural intention of the control signal generating circuit and the control circuit; Figure 9 illustrates the third structural intention of the control signal generating circuit and the control circuit; Figure 10 illustrates the fourth structural intention of the control signal generating circuit and the control circuit. Some embodiments of the present disclosure also provide a fifth structure of the control signal generating circuit and the control circuit. Compared with the example in Figure 7, in the fifth structure of the control signal generating circuit and the control circuit, the first signal input terminal E1 can be directly electrically connected to the low voltage line VGL.

[0176] It should be noted that the first type of drive circuit has a normally low, adjustable high voltage waveform (an invalid signal is a low-voltage signal, and a valid signal is a high-voltage signal). In some embodiments, the control circuit of the first type of drive circuit may include a first isolation sub-circuit 46 (a first isolation transistor CT15); in other embodiments, the control circuit of the first type of drive circuit may include a first isolation sub-circuit 46 (a first isolation transistor CT15 and a second isolation transistor CT17); in still other embodiments, the control circuit of the first type of drive circuit causes the first signal input terminal E1 to be directly electrically connected to the low-voltage line VGL.

[0177] It should be noted that, in some embodiments, the first driving circuit may include the second isolation sub-circuit 22 (fourth isolation transistor CT18); in other embodiments, the first driving circuit may include the second isolation sub-circuit 22 (fourth isolation transistor CT18) and the reverse storage sub-circuit 23 (third capacitor CC3); in still other embodiments, the first driving circuit may include the second isolation sub-circuit 22 (fourth isolation transistor CT18) and the driving storage sub-circuit 17 (fourth capacitor CC4); in still other embodiments, the first driving circuit may include the reverse storage sub-circuit 23 (third capacitor CC3) and the driving storage sub-circuit 17 (fourth capacitor CC4); in still other embodiments, the first driving circuit may include the reverse storage sub-circuit 23 (third capacitor CC3); in still other embodiments, the first driving circuit may include the driving storage sub-circuit 17 (fourth capacitor CC4); in still other embodiments, the first driving circuit may not include at least one of the second isolation sub-circuit 22 (fourth isolation transistor CT18), the reverse storage sub-circuit 23 (third capacitor CC3), and the driving storage sub-circuit 17 (fourth capacitor CC4).

[0178] It should be noted that the second drive circuit has a normally high adjustable low voltage waveform (an invalid signal is a high voltage signal, and a valid signal is a low voltage signal). In some embodiments, the control circuit of the second drive circuit may include a first isolation sub-circuit 46 (a third isolation transistor CT17); in other embodiments, the control circuit of the second drive circuit causes the first signal input terminal E1 to be directly electrically connected to the low voltage line VGL.

[0179] It should be noted that, in some embodiments, the second driving circuit may include the second isolation sub-circuit 22 (fourth isolation transistor CT18); in other embodiments, the second driving circuit may include the second isolation sub-circuit 22 (fourth isolation transistor CT18) and the reverse storage sub-circuit 23 (third capacitor CC3); in still other embodiments, the second driving circuit may include the second isolation sub-circuit 22 (fourth isolation transistor CT18) and the driving storage sub-circuit 17 (fourth capacitor CC4); in still other embodiments, the second driving circuit may include the reverse storage sub-circuit 23 (third capacitor CC3) and the driving storage sub-circuit 17 (fourth capacitor CC4); in still other embodiments, the second driving circuit may include the reverse storage sub-circuit 23 (third capacitor CC3); in still other embodiments, the second driving circuit may include the driving storage sub-circuit 17 (fourth capacitor CC4); in still other embodiments, the second driving circuit may not include at least one of the second isolation sub-circuit 22 (fourth isolation transistor CT18), the reverse storage sub-circuit 23 (third capacitor CC3), and the driving storage sub-circuit 17 (fourth capacitor CC4).

[0180] Some embodiments of the present disclosure further provide a display panel, which may include the driving circuit provided in any of the above embodiments.

[0181] In some embodiments, the display panel may be an organic light emitting display panel (OLED).

[0182] In some embodiments, the display panel may include a plurality of cascaded driving circuits of any one of the above items, and the plurality of cascaded driving circuits may drive pixel circuits arranged in multiple rows in the display panel.

[0183] Some embodiments of the present disclosure further provide a display device, which may include the driving circuit provided by any of the above embodiments, or / and, the display device may include the display panel provided by any of the above embodiments.

[0184] For example, the display device may be a smart phone, a laptop computer, a television, a tablet computer, or other displays, and is not specifically limited in the embodiments of the present application.

[0185] It should be noted that the technical features in the above-mentioned embodiments / examples can be combined with each other to obtain a new driving circuit; the technical features in the above-mentioned embodiments / examples can be combined with each other to obtain a new display panel; the technical features in the above-mentioned embodiments / examples can be combined with each other to obtain a new display device.

[0186] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0187] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

[0188] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0189] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A driving circuit comprising a driving signal generating circuit (100), an output inverting circuit (200), a control signal generating circuit (300) and a control circuit (400); The driving signal generating circuit (100) is electrically connected to the n-th level generating signal output terminal (OUT1), and is used to generate and output the n-th level driving signal through the n-th level generating signal output terminal (OUT1), where n is a positive integer; The output inversion circuit (200) is electrically connected to the n-th level drive signal output terminal (OUT1) and the n-th level generated signal inverting output terminal (FOUT1) respectively, and is used to invert the n-th level drive signal, obtain and output the n-th level inverted drive signal through the n-th level generated signal inverting output terminal (FOUT1); The control signal generating circuit (300) is electrically connected to the enable signal line (EN) and the control signal terminal (CN1), and is used to generate and output a control signal through the control signal terminal (CN1) according to the enable signal provided by the enable signal line (EN); as well as The control circuit (400) is electrically connected to the control signal terminal (CN1) and the first control signal terminal (COT1) respectively, and is used to output a valid voltage signal or an invalid voltage signal to the n-th stage driving output terminal (NOUT1) under the control of the signals of the control signal terminal (CN1) and the first control signal terminal (COT1); The control circuit (400) includes a first control subcircuit (41), a second control subcircuit (42), a third control subcircuit (43), a first isolation subcircuit (46), a first storage subcircuit (44), and a second storage subcircuit (45); The first control subcircuit (41) is electrically connected to the control signal terminal (CN1), the high voltage line (VGH), the low voltage line (VGL) and the first control output terminal (CN2), respectively, and is used to invert the control signal output by the control signal terminal (CN1) to obtain an inverted control signal, and output the inverted control signal through the first control output terminal (CN2); The second control subcircuit (42) is electrically connected to the first control signal terminal (COT1), the high voltage line (VGH), the first signal input terminal (E1) and the second control output terminal (CN3) respectively, and is used to control the communication between the second control output terminal (CN3) and the high voltage line (VGH) or the first signal input terminal (E1) under the control of the signal of the first control signal terminal (COT1); The first isolation subcircuit (46) is electrically connected to the first signal input terminal (E1) and is used to provide an electrical signal to the first signal input terminal (E1); The third control subcircuit (43) is electrically connected to the second control output terminal (CN3), the high voltage line (VGH), the low voltage line (VGL) and the n-th level driving output terminal (NOUT1) respectively, and is used to invert the signal output by the second control output terminal (CN3) and output the inverted signal through the n-th level driving output terminal (NOUT1); The first storage subcircuit (44) is electrically connected to the control signal terminal (CN1) and is used to maintain the potential of the control signal terminal (CN1); as well as The second storage subcircuit (45) is electrically connected to the second control output terminal (CN3) and is used to maintain the potential of the second control output terminal (CN3).

2. The driving circuit according to claim 1, wherein: The first control signal terminal (COT1) is electrically connected to the n-th stage generated signal output terminal (OUT1), the invalid voltage signal is a low potential signal, and the valid voltage signal is a high potential signal.

3. The driving circuit according to claim 2, wherein: The first isolation sub-circuit (46) is electrically connected between the first control output terminal (CN2) and the first signal input terminal (E1).

4. The driving circuit according to claim 3, wherein: The first isolation subcircuit (46) includes: A first isolation transistor (CT15), wherein a gate of the first isolation transistor (CT15) is electrically connected to a first clock signal terminal (CK), a first electrode of the first isolation transistor (CT15) is electrically connected to the first control output terminal (CN2), and a second electrode of the first isolation transistor (CT15) is electrically connected to the first signal input terminal (E1).

5. The driving circuit according to claim 4, wherein: The first isolation sub-circuit (46) further includes: a second isolation transistor (CT16), wherein a gate of the second isolation transistor (CT16) is electrically connected to a second clock signal terminal (CB), a first electrode of the second isolation transistor (CT16) is electrically connected to the first control output terminal (CN2), and a second electrode of the second isolation transistor (CT16) is electrically connected to the first signal input terminal (E1); Wherein, one of the first isolation transistor (CT15) and the second isolation transistor (CT16) is an N-type transistor, and the other is a P-type transistor. The driving circuit according to claim 1 , wherein: The first control signal terminal (COT1) is electrically connected to the n-th stage generated signal inverting output terminal (FOUT1), the invalid voltage signal is a high potential signal, and the valid voltage signal is a low potential signal.

7. The driving circuit according to claim 6, wherein: The first isolation sub-circuit (46) is electrically connected between the low voltage line (VGL) and the first signal input terminal (E1).

8. The driving circuit according to claim 7, wherein: The first isolation subcircuit (46) includes: a third isolation transistor (CT17), wherein a gate of the third isolation transistor (CT17) is electrically connected to a first clock signal terminal (CK), a first electrode of the third isolation transistor (CT17) is electrically connected to the first signal input terminal (E1), and a second electrode of the third isolation transistor (CT17) is electrically connected to the low voltage line (VGL).

9. The driving circuit according to any one of claims 1 to 8, wherein: The first control subcircuit (41) includes a first control transistor (CT1), a second control transistor (CT2), a third control transistor (CT3) and a fourth control transistor (CT4); The gate of the first control transistor (CT1) is electrically connected to the control signal terminal (CN1), the first electrode of the first control transistor (CT1) is electrically connected to the high voltage line (VGH), and the second electrode of the first control transistor (CT1) is electrically connected to the first control output terminal (CN2); The gate of the second control transistor (CT2) is electrically connected to the control signal terminal (CN1), the first electrode of the second control transistor (CT2) is electrically connected to the first control output terminal (CN2), and the second electrode of the second control transistor (CT2) is electrically connected to the low voltage line (VGL); The gate of the third control transistor (CT3) is electrically connected to the first control output terminal (CN2), the first electrode of the third control transistor (CT3) is electrically connected to the high voltage line (VGH), and the second electrode of the third control transistor (CT3) is electrically connected to the control signal terminal (CN1); and The gate of the fourth control transistor (CT4) is electrically connected to the first control output terminal (CN2), the first electrode of the fourth control transistor (CT4) is electrically connected to the control signal terminal (CN1), and the second electrode of the fourth control transistor (CT4) is electrically connected to the low voltage line (VGL).

10. The driving circuit according to claim 9, wherein: The second control subcircuit (42) includes a fifth control transistor (CT5) and a sixth control transistor (CT6); The gate of the fifth control transistor (CT5) is electrically connected to the first control signal terminal (COT1), the first electrode of the fifth control transistor (CT5) is electrically connected to the high voltage line (VGH), and the second electrode of the fifth control transistor (CT5) is electrically connected to the second control output terminal (CN3); as well as The gate of the sixth control transistor (CT6) is electrically connected to the first control signal terminal (COT1), the first electrode of the sixth control transistor (CT6) is electrically connected to the second control output terminal (CN3), and the second electrode of the sixth control transistor (CT6) is electrically connected to the first signal input terminal (E1).

11. The driving circuit according to claim 10, wherein: The third control subcircuit (43) includes a seventh control transistor (CT7) and an eighth control transistor (CT8); The gate of the seventh control transistor (CT7) is electrically connected to the second control output terminal (CN3), the first electrode of the seventh control transistor (CT7) is electrically connected to the high voltage line (VGH), and the second electrode of the seventh control transistor (CT7) is electrically connected to the n-th stage driving output terminal (NOUT1); as well as The gate of the eighth control transistor (CT8) is electrically connected to the second control output terminal (CN3), the first electrode of the eighth control transistor (CT8) is electrically connected to the n-th stage drive output terminal (NOUT1), and the second electrode of the eighth control transistor (CT8) is electrically connected to the low voltage line (VGL).

12. The driving circuit according to claim 11, wherein: The first storage subcircuit (44) includes a first capacitor (CC1), and the second storage subcircuit (45) includes a second capacitor (CC2); The first plate of the first capacitor (CC1) is electrically connected to the control signal terminal (CN1), and the second plate of the first capacitor (CC1) is electrically connected to the low voltage line (VGL); The first electrode plate of the second capacitor (CC2) is electrically connected to the second control output terminal (CN3), and the second electrode plate of the second capacitor (CC2) is electrically connected to the low voltage line (VGL).

13. The driving circuit according to claim 12, wherein: The first control transistor (CT1), the third control transistor (CT3), the fifth control transistor (CT5) and the seventh control transistor (CT7) are all P-type transistors, and the second control transistor (CT2), the fourth control transistor (CT4), the sixth control transistor (CT6) and the eighth control transistor (CT8) are all N-type transistors.

14. The driving circuit according to claim 1, wherein: The drive signal generating circuit (100) comprises a first node control subcircuit (11), a second node control subcircuit (12), a first output node control subcircuit (13), a second output node control subcircuit (14), a potential maintaining subcircuit (15) and an output subcircuit (16); The first node control subcircuit (11) is electrically connected to the first node (N1), the first clock signal terminal (CK), the low voltage line (VGL) and the second output node (NJ2) respectively, and is used to control the connection between the first node (N1) and the low voltage line (VGL) under the control of the first clock signal provided by the first clock signal terminal (CK), and to control the connection or disconnection between the first node (N1) and the first clock signal terminal (CK) under the control of the potential of the second output node (NJ2); The second node control subcircuit (12) is electrically connected to the first node (N1), the first intermediate node (NZ1), the high voltage line (VGH), the first clock signal terminal (CK), the second clock signal terminal (CB), the second node (N2), the input terminal (STV) and the low voltage line (VGL) respectively, and is used to control the connection between the first intermediate node (NZ1) and the high voltage line (VGH) under the control of the potential of the first node (N1), control the connection between the first intermediate node (NZ1) and the second clock signal terminal (CB) under the control of the potential of the second node (N2), and control the potential of the second node (N2) according to the potential of the first intermediate node (NZ1), and control the connection between the input terminal (STV) and the second node (N2) under the control of the first clock signal provided by the first clock signal terminal (CK) and the signal provided by the low voltage line (VGL); The first output node control subcircuit (93) is electrically connected to the first output node (NJ1), the first node (N1), the second clock signal terminal (CB), the second intermediate node (NZ2), the second output node (NJ2) and the high voltage line (VGH) respectively, and is used to control the second intermediate node (NZ2) to be connected to the second clock signal terminal (CB) under the control of the potential of the first node (N1), control the potential of the second intermediate node (NZ2) according to the potential of the first node (N1), control the second intermediate node (NZ2) to be connected to the first output node (NJ1) under the control of the second clock signal provided by the second clock signal terminal (CB), and control the first output node (NJ1) to be connected to the high voltage line (VGH) under the control of the potential of the second output node (NJ2); The second output node control subcircuit (14) is electrically connected to the first clock signal terminal (CK), the input terminal (STV), the control voltage line (VEL), the high voltage line (VGH), the second node (N2) and the second output node (NJ2) respectively, and is used to control the second output node (NJ2) to be connected to the input terminal (STV) under the control of the first clock signal provided by the first clock signal terminal (CK), control the potential of the second output node (NJ2) according to the potential of the second node (N2), and control the second output node (NJ2) to be connected to the high voltage line (VGH) under the control of the control voltage provided by the control voltage line (VEL); The potential maintaining subcircuit (15) is electrically connected to the first output node (NJ1) and is used to maintain the potential of the first output node (NJ1); as well as The output sub-circuit (16) is electrically connected to the first output node (NJ1), the second output node (NJ2), the high voltage line (VGH), the low voltage line (VGL) and the n-th stage generated signal output terminal (OUT1), respectively, and is used to control the connection between the n-th stage generated signal output terminal (OUT1) and the high voltage line (VGH) under the control of the potential of the first output node (NJ1), and to control the connection between the n-th stage generated signal output terminal (OUT1) and the low voltage line (VGL) under the control of the potential of the second output node (NJ2).

15. The driving circuit according to claim 14, wherein: The output inverting circuit (200) comprises an output reverse subcircuit (21) and a second isolation subcircuit (22); The output reverse sub-circuit (21) is electrically connected to the n-th stage generated signal output terminal (OUT1), the high voltage line (VGH) and the second signal input terminal (E2), and the output reverse sub-circuit (21) is used to output the electrical signal of the high voltage line (VGH) or the second signal input terminal (E2) to the n-th stage generated signal reverse output terminal (FOUT1); and The second isolation subcircuit (22) is electrically connected to the second output node (NJ2), the second signal input terminal (E2) and the low voltage line (VGL), respectively. The second isolation subcircuit (22) is used to control the connection or disconnection between the low voltage line (VGL) and the second signal input terminal (E2).

16. The driving circuit according to claim 15, wherein: The second isolation sub-circuit (22) comprises: a fourth isolation transistor (CT18), wherein the gate of the fourth isolation transistor (CT18) is electrically connected to the second output node (NJ2), and the fourth isolation transistor (CT18) A first electrode of the fourth isolation transistor (CT18) is electrically connected to the second signal input terminal (E2), and a second electrode of the fourth isolation transistor (CT18) is electrically connected to the low voltage line (VGL).

17. The driving circuit according to claim 14, wherein: The output inverting circuit (200) further comprises a reverse storage subcircuit (23), the reverse storage subcircuit (23) being electrically connected to the n-th stage generated signal output terminal (OUT1) and being used to maintain the potential of the n-th stage generated signal output terminal (OUT1); or / and The drive signal generating circuit further includes a drive storage subcircuit (17), wherein the drive storage subcircuit (17) is electrically connected to the n-th stage generated signal output terminal (OUT1) and the second output node (NJ2), and is used to maintain the potential of the n-th stage generated signal output terminal (OUT1).

18. The driving circuit according to claim 17, wherein: The reverse storage subcircuit (23) includes a third capacitor (CC3), a first plate of the third capacitor (CC3) is electrically connected to the n-th stage generated signal output terminal (OUT1), and a second plate of the third capacitor (CC3) is electrically connected to the low voltage line (VGL); The drive storage subcircuit (17) includes a fourth capacitor (CC4), a first plate of the fourth capacitor (CC4) is electrically connected to the n-th stage generated signal output terminal (OUT1), and a second plate of the fourth capacitor (CC4) is electrically connected to the second output node (NJ2).

19. The driving circuit according to claim 14, wherein: The output inverting circuit (200) comprises a first output inverting transistor (CT13) and a second output inverting transistor (CT14); The gate of the first output inverting transistor (CT13) is electrically connected to the n-th stage generated signal output terminal (OUT1), the first electrode of the first output inverting transistor (CT13) is electrically connected to the high voltage line (VGH), and the second electrode of the first output inverting transistor (CT13) is electrically connected to the n-th stage generated signal reverse output terminal (FOUT1); and The gate of the second output inverting transistor (CT14) is electrically connected to the n-th stage generated signal output terminal (OUT1), the first electrode of the second output inverting transistor (CT14) is electrically connected to the n-th stage generated signal reverse output terminal (FOUT1), and the second electrode of the second output inverting transistor (CT14) is electrically connected to the second signal input terminal (E2); One of the first output inverting transistor (CT13) and the second output inverting transistor (CT14) is an N-type transistor, and the other is a P-type transistor.

20. The driving circuit according to any one of claims 14 to 19, characterized in that: The first node control subcircuit (11) includes a first transistor (T1), a second transistor (T2), and a third transistor (T3); the second output node control subcircuit (14) includes a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7); The gate of the first transistor (T1) is electrically connected to the first clock signal terminal (CK), the first electrode of the first transistor (T1) is electrically connected to the low voltage line (VGL), and the second electrode of the first transistor (T1) is electrically connected to the first electrode of the third transistor (T3); The gate of the second transistor (T2) is electrically connected to the second electrode of the fourth transistor (T4), the second electrode of the second transistor (T2) is electrically connected to the first clock signal terminal (CK), and the first electrode of the second transistor (T2) is electrically connected to the first electrode of the third transistor (T3); The gate of the third transistor (T3) is electrically connected to the low voltage line (VGL), and the second electrode of the third transistor (T3) is electrically connected to the first node (N1); The gate of the fourth transistor (T4) is electrically connected to the first clock signal terminal (CK), and the first electrode of the fourth transistor (T4) is electrically connected to the input terminal (STV); a gate of the fifth transistor (T5) being electrically connected to the low voltage line (VGL), a first electrode of the fifth transistor (T5) being electrically connected to the second electrode of the fourth transistor (T4), and a second electrode of the fifth transistor (T5) being electrically connected to the second output node (NJ2); The gate of the sixth transistor (T6) and the first electrode of the sixth transistor (T6) are both electrically connected to the second node (N2), and the second electrode of the sixth transistor (T6) is electrically connected to the second output node (NJ2); and The gate of the seventh transistor (T7) is electrically connected to the control voltage line (VEL), the first electrode of the seventh transistor (T7) is electrically connected to the high voltage line (VGH), and the second electrode of the seventh transistor (T7) is electrically connected to the first electrode of the fifth transistor (T5); The second node control subcircuit (12) includes an eighth transistor (T8), a ninth transistor (T9), a tenth transistor (T10), an eleventh transistor (T11) and a fifth capacitor (C3); The gate of the eighth transistor (T8) is electrically connected to the second node (N2), the second electrode of the eighth transistor (T8) is electrically connected to the second clock signal terminal (CB), and the first electrode of the eighth transistor (T8) is electrically connected to the first intermediate node (NZ1); The gate of the ninth transistor (T9) is electrically connected to the second electrode of the first transistor (T1), the first electrode of the ninth transistor (T9) is electrically connected to the high voltage line (VGH), and the second electrode of the ninth transistor (T9) is electrically connected to the first intermediate node (NZ1); The gate of the tenth transistor (T10) is electrically connected to the first clock signal terminal (CK), the first electrode of the tenth transistor (T10) is electrically connected to the input terminal (STV), and the second electrode of the tenth transistor (T10) is electrically connected to the first electrode of the eleventh transistor (T11); The gate of the eleventh transistor (T11) is electrically connected to the low voltage line (VGL), and the second electrode of the eleventh transistor (T11) is electrically connected to the second node (N2); and The first electrode plate of the fifth capacitor (C3) is electrically connected to the first intermediate node (NZ1), and the second electrode plate of the fifth capacitor (C3) is electrically connected to the second node (N2); The first output node control subcircuit (13) includes a twelfth transistor (T12), a thirteenth transistor (T13), a fourteenth transistor (T14) and a sixth capacitor (C4); The gate of the twelfth transistor (T12) is electrically connected to the first node (N1), the first electrode of the twelfth transistor (T12) is electrically connected to the second clock signal terminal (CB), and the second electrode of the twelfth transistor (T12) is electrically connected to the second intermediate node (NZ2); The gate of the thirteenth transistor (T13) is electrically connected to the second clock signal terminal (CB), the first electrode of the thirteenth transistor (T13) is electrically connected to the second intermediate node (NZ2), and the second electrode of the thirteenth transistor (T13) is electrically connected to the first output node (NJ1); The gate of the fourteenth transistor (T14) is electrically connected to the first electrode of the fifth transistor (T5), the second electrode of the fourteenth transistor (T14) is electrically connected to the high voltage line (VGH), and the first electrode of the fourteenth transistor (T14) is electrically connected to the first output node (NJ1); and The first electrode plate of the sixth capacitor (C4) is electrically connected to the first node (N1), and the second electrode plate of the sixth capacitor (C4) is electrically connected to the second intermediate node (NZ2); The potential maintaining subcircuit includes a seventh capacitor (C5), a first plate of the seventh capacitor (C5) is electrically connected to the first output node (NJ1), and a second plate of the seventh capacitor (C5) is electrically connected to the high voltage line (VGH); The output sub-circuit (16) includes a fifteenth transistor (T15) and a sixteenth transistor (T16); The gate of the fifteenth transistor (T15) is electrically connected to the first output node (NJ1), the first electrode of the fifteenth transistor (T15) is electrically connected to the high voltage line (VGH), and the second electrode of the fifteenth transistor (T15) is electrically connected to the n-th stage generated signal output terminal (OUT1); as well as The gate of the sixteenth transistor (T16) is electrically connected to the second output node (NJ2), the first electrode of the sixteenth transistor (T16) is electrically connected to the n-th stage generated signal output terminal (OUT1), and the second electrode of the sixteenth transistor (T16) is electrically connected to the low voltage line (VGL).

21. The driving circuit according to claim 1, wherein: The control signal generating circuit (300) includes a ninth control transistor (CT9), a tenth control transistor (CT10), an eleventh control transistor (CT11), and a twelfth control transistor (CT12); The gate of the ninth control transistor (CT9) is electrically connected to the n-1th stage generated signal inverting output terminal (FOUT1(n-1)), the first electrode of the ninth control transistor (CT9) is electrically connected to the enable signal line (EN), and the second electrode of the ninth control transistor (CT9) is electrically connected to the first electrode of the eleventh control transistor (CT11); The gate of the tenth control transistor (CT10) is electrically connected to the n-1th stage generated signal output terminal (OUT1(n-1)), the first electrode of the tenth control transistor (CT10) is electrically connected to the enable signal line (EN), and the second electrode of the tenth control transistor (CT10) is electrically connected to the first electrode of the eleventh control transistor (CT11); The gate of the eleventh control transistor (CT11) is electrically connected to the n-th stage generated signal output terminal (OUT1), and the second electrode of the eleventh control transistor (CT11) is electrically connected to the control signal terminal (CN1); and The gate of the twelfth control transistor (CT12) is electrically connected to the n-th stage generated signal inverting output terminal (FOUT1), the first electrode of the twelfth control transistor (CT12) is electrically connected to the first electrode of the eleventh control transistor (CT11), and the second electrode of the twelfth control transistor (CT12) is electrically connected to the control signal terminal (CN1); The ninth control transistor (CT9) and the eleventh control transistor (CT11) are P-type transistors, and the tenth control transistor (CT10) and the twelfth control transistor (CT12) are N-type transistors.

22. A display panel comprising the driving circuit according to any one of claims 1 to 21.

23. A display device comprising the display panel according to claim 22.

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