Image sensor and electronic device

Abstract

The present application discloses an image sensor and an electronic device. The image sensor comprises a pixel array and read circuits. The pixel array comprises pixels and read-out lines connected to the pixels; the pixels each comprise first photosensitive units and second photosensitive units; the read circuits each comprise a mode selection circuit and an analog quantization circuit; and the mode selection circuit outputs, to the analog quantization circuit, pre-determination voltages corresponding to the first photosensitive units, such that the analog quantization circuit generates a feedback signal and feeds back the feedback signal to the mode selection circuit. In response to the feedback signal, the mode selection circuit outputs, to the analog quantization circuit, a reset voltage and a signal voltage of a first mode or a second mode corresponding to the second photosensitive units, such that the analog quantization circuit outputs a target digital quantization value of the first mode or the second mode corresponding to the second photosensitive units, and there is no need to quantize signal voltages of both the first mode and the second mode corresponding to the second photosensitive units, thereby decreasing the frequency of quantization, reducing a frame period, and increasing a frame rate.

Description

Image sensor and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 2, 2024, with application number 202410161088.9 and application name “An Image Sensor and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of image processing technology, and in particular to an image sensor and electronic equipment. Background Art

[0004] Image sensors are widely used in electronic devices such as digital cameras and mobile phones to capture digital images. Traditional image sensors consist of multiple pixels, each of which includes a photodiode (PD) and a pixel circuit. The PD is used to convert light signals into electrical signals, and the pixel circuit is used to output a voltage related to the electrical signal to construct the image. Furthermore, the voltage output by the pixel circuit is fed into an analog quantization circuit, where an analog-to-digital converter (ADC) quantizes the voltage into a digital value representing the intensity of the incident light. Traditional high dynamic range (HDR) image sensors with dual conversion gain (DCG) functionality require the ADC to quantize these voltages in both high conversion gain (HCG) and low conversion gain (LCG) modes. This results in traditional image sensors requiring HCG and LCG quantization during pixel processing, leading to long quantization times, increased frame periods, and reduced frame rates.

[0005] Summary of the Invention

[0006] The present application provides an image sensor and an electronic device for reducing the number of quantization times of an image sensor with a DCG function, reducing the frame period, and improving the frame rate.

[0007] In a first aspect, an embodiment of the present application provides an image sensor, which includes a pixel array and a readout circuit. The pixel array includes pixels and readout lines connected to the pixels, and the pixels include a first photosensitive unit and a second photosensitive unit. The pixels are used to output a pre-judgment voltage corresponding to the first photosensitive unit, and a reset voltage and a signal voltage of a first mode and a second mode corresponding to the second photosensitive unit to the readout line. In addition, the readout circuit is connected to the readout line in a one-to-one correspondence, and the readout circuit includes a mode selection circuit and an analog quantization circuit, and the analog quantization circuit is connected to the readout line through the mode selection circuit. The mode selection circuit can be used to output the pre-judgment voltage to the analog quantization circuit, so that the analog quantization circuit generates a feedback signal, and the analog quantization circuit feeds the feedback signal back to the mode selection circuit. In addition, the mode selection circuit is also used to output the reset voltage and signal voltage of the first mode or the second mode corresponding to the second photosensitive unit to the analog quantization circuit in response to the feedback signal, so that the analog quantization circuit outputs the target digital quantization value of the first mode or the second mode corresponding to the second photosensitive unit, so that the reading circuit quantizes the signal voltage of the first mode or the second mode corresponding to the second photosensitive unit, without quantizing both the signal voltages of the first mode and the second mode corresponding to the second photosensitive unit, which can reduce the number of quantization times, reduce the frame period, and improve the frame rate.

[0008] The target digital quantization value of the first mode includes: the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the first mode, or the difference between the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the first mode. The target digital quantization value of the second mode includes: the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the second mode, or the difference between the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the second mode.

[0009] Moreover, in the embodiment of the present application, there is no need to set up an additional feedback line between the reading circuit and the pixel, and there is no need to change the various control signals of the pixel. Instead, the various control signals of the pixel in the related technology can be reused, thereby reducing the development cost, cycle and risk of the pixel.

[0010] Furthermore, in the embodiments of the present application, the mode selection circuit in the readout circuit is configured on the readout line, making it applicable to a rolling shutter and compatible with the most commonly used circuit architectures in related technologies, thus having broad application value. Of course, the readout circuit in the embodiments of the present application can also be applied to architectures other than a rolling shutter.

[0011] In some embodiments, the image sensor further includes a data transmitter, and each readout circuit is connected to the image signal processor via the data transmitter. Each readout circuit outputs the target digital quantization value of the first mode or the second mode to the data transmitter, and the data transmitter transmits the target digital quantization value of the first mode or the second mode to the image signal processor.

[0012] In some embodiments, the feedback signal has a first level or a second level, and the mode selection circuit can output the reset voltage and signal voltage of the first mode or the second mode corresponding to the second photosensitive unit to the analog quantization circuit in response to the level of the feedback signal. Wherein, if the level of the feedback signal is the first level, the mode selection circuit outputs the reset voltage and signal voltage of the first mode corresponding to the second photosensitive unit to the analog quantization circuit in response to the level of the feedback signal being the first level, so that the analog quantization circuit generates the target digital quantization value of the first mode. Alternatively, if the level of the feedback signal is the second level, the mode selection circuit outputs the reset voltage and signal voltage of the second mode corresponding to the second photosensitive unit to the analog quantization circuit in response to the level of the feedback signal being the second level, so that the analog quantization circuit generates the target digital quantization value of the second mode.

[0013] In some embodiments, the analog quantization circuit is further configured to generate a feedback signal in response to the predicted voltage and the reference voltage.

[0014] In some embodiments, the pixel can output a signal voltage of the second mode corresponding to the first photosensitive unit to the readout line, and the pre-judgment voltage includes the signal voltage of the second mode corresponding to the first photosensitive unit. Based on this, the analog quantization circuit can compare the signal voltage of the second mode corresponding to the first photosensitive unit with a reference voltage. In response to the signal voltage of the second mode corresponding to the first photosensitive unit being less than the reference voltage, the analog quantization circuit feeds back a feedback signal having a first level to the mode selection circuit. Furthermore, in response to the signal voltage of the second mode corresponding to the first photosensitive unit being greater than the reference voltage, the analog quantization circuit feeds back a feedback signal having a second level to the mode selection circuit.

[0015] In some embodiments, the analog quantization circuit is further configured to generate a feedback signal in response to the digital quantization value of the predicted voltage.

[0016] In some embodiments, the pixel can output a reset voltage and a signal voltage of the second mode corresponding to the first photosensitive unit to the readout line. The pre-judgment voltage then includes the reset voltage and the signal voltage of the second mode corresponding to the first photosensitive unit. Based on this, the analog quantization circuit is further configured to output a feedback signal based on the reset voltage and the signal voltage of the second mode corresponding to the first photosensitive unit and the ramp signal.

[0017] In some embodiments, the analog quantization circuit may obtain a difference between a reset voltage and a digital quantization value of a signal voltage in a second mode corresponding to the first photosensitive unit, and set the difference between the reset voltage and the digital quantization value of the signal voltage in the second mode corresponding to the first photosensitive unit as a target digital quantization difference. The analog quantization circuit is further configured to feed back a feedback signal having a first level to the mode selection circuit in response to a product of the target digital quantization difference and an exposure time ratio being greater than a digital voltage threshold. Furthermore, the analog quantization circuit is further configured to feed back a feedback signal having a second level to the mode selection circuit in response to a product of the target digital quantization difference and an exposure time ratio being less than a digital voltage threshold.

[0018] In some embodiments, the analog quantization circuit is further configured to output a target digital quantization value of the second mode corresponding to the first photosensitive unit based on the reset voltage and signal voltage of the second mode corresponding to the first photosensitive unit and the ramp signal. Thus, the reset voltage and signal voltage of the second mode corresponding to the first photosensitive unit can be quantized.

[0019] In some embodiments, the pixel is further configured to output a reset voltage and a signal voltage of the first mode corresponding to the first photosensitive unit to a readout line. Furthermore, the mode selection circuit is further configured to output the reset voltage and the signal voltage of the first mode corresponding to the first photosensitive unit to the analog quantization circuit. The analog quantization circuit is further configured to output a target digital quantization value of the first mode corresponding to the first photosensitive unit based on the reset voltage and the signal voltage of the first mode corresponding to the first photosensitive unit and the ramp signal. With this configuration, the reset voltage and the signal voltage of the first mode corresponding to the first photosensitive unit can be quantized.

[0020] In some embodiments, the mode selection circuit includes a first control circuit, a second control circuit, and a third control circuit, wherein the first control circuit is respectively connected to the readout line and the analog quantization circuit, the second control circuit is respectively connected to the third control circuit and the analog quantization circuit, and the third control circuit is further connected to the first control circuit. Furthermore, the first control circuit is configured to control the connection or disconnection between the readout line and the analog quantization circuit. The second control circuit is configured to output a feedback signal to the third control circuit. The third control circuit is configured to control the first control circuit to connect the readout line and the analog quantization circuit in response to the voltage corresponding to the first photosensitive unit transmitted by the readout line, and to control the first control circuit to connect the readout line and the analog quantization circuit in response to the feedback signal having a first level and the readout line transmitting a reset voltage and a signal voltage of a first mode output by the pixel based on the second photosensitive unit, and to control the first control circuit to connect the readout line and the analog quantization circuit in response to the feedback signal having a second level and the readout line transmitting a reset voltage and a signal voltage of a second mode output by the pixel based on the second photosensitive unit. This configuration can realize the function of the mode selection circuit.

[0021] In some embodiments, the first control circuit includes a first switch and a storage capacitor, wherein the control terminal of the first switch is connected to the third control circuit, the first terminal of the first switch is connected to the readout line, and the second terminal of the first switch is connected to the analog quantization circuit. Furthermore, the first terminal of the storage capacitor is connected to the second terminal of the first switch, and the second terminal of the storage capacitor is grounded. This configuration can achieve the functions of the first control circuit.

[0022] In some embodiments, the second control circuit includes a second switch, a control terminal of the second switch is configured to receive a switch control signal, a first terminal of the second switch is connected to the analog quantization circuit, and a second terminal of the second switch is connected to the third control circuit. This configuration enables the function of the second control circuit to be realized.

[0023] In some embodiments, the third control circuit includes a first multiplexer, a second multiplexer, a third switch, a first inverter, a second inverter, and a first memory. The control terminal of the first multiplexer is configured to receive a first selection control signal, the first input terminal of the first multiplexer is configured to receive a first input signal, the second input terminal of the first multiplexer is connected to the output terminal of the second multiplexer, and the output terminal of the first multiplexer is connected to the first control circuit. The input terminal of the first inverter is respectively connected to the second control circuit and the first terminal of the third switch, the output terminal of the first inverter is respectively connected to the input terminal of the second inverter and the first input terminal of the second multiplexer. The output terminal of the second inverter is respectively connected to the second terminal of the third switch and the second input terminal of the second multiplexer. The control terminal of the third switch is configured to receive a latch control signal, and the control terminal of the second multiplexer is configured to receive a second selection control signal. The first memory is connected to the output terminal of the second inverter and is configured to store and output a feedback signal. This configuration enables the functions of the third control circuit.

[0024] The analog quantization circuit in the present application may be an analog to digital converter (ADC).

[0025] In some embodiments, the analog quantization circuit includes a first comparator, a first counter, and a second memory. The first comparator's first input is connected to a mode selection circuit, its second input is used to receive a comparison signal, and its output is connected to the first counter and the mode selection circuit. The first comparator is configured to output a feedback signal in response to a pre-judgment voltage input to its first input and a reference voltage for the comparison signal, and to output a comparison result in response to a voltage input to its first input and a ramp signal for the comparison signal. The first counter is configured to generate a count value related to time. The second memory is configured to store the count value in the first counter based on the comparison result output by the first comparator, with the count value stored in the second memory being a digital quantization value. This configuration enables the functionality of the analog quantization circuit.

[0026] In some embodiments, the analog quantization circuit includes a switching control circuit, a first quantization circuit, a second quantization circuit, a quantization gating circuit, and a digital comparison circuit. The first quantization circuit and the second quantization circuit are each connected to a mode selection circuit via the switching control circuit, and each receives a comparison signal via the switching control circuit. The first quantization circuit is connected to the quantization gating circuit, and the second quantization circuit is respectively connected to the quantization gating circuit and the digital comparison circuit, which is connected to the mode selection circuit. Furthermore, the switching control circuit is configured to connect the mode selection circuit and the comparison signal to the first quantization circuit in response to a voltage outputted by the mode selection circuit corresponding to the second photosensitive unit, and to connect the mode selection circuit and the comparison signal to the second quantization circuit in response to a pre-judgment voltage outputted by the mode selection circuit. The first quantization circuit is configured to generate a target digital quantization value for the first or second mode corresponding to the second photosensitive unit, and to store the target digital quantization value in response to a control output of the quantization gating circuit. The second quantization circuit is configured to generate a target digital quantization value for the second mode corresponding to the first photosensitive unit, and to store the target digital quantization value in response to a control output of the quantization gating circuit. The digital comparison circuit is used to output a feedback signal in response to a target digital quantization value of the second mode corresponding to the first photosensitive unit and a digital voltage threshold.

[0027] In some embodiments, the switching control circuit includes a first switching switch and a second switching switch, wherein a control terminal of the first switching switch is used to receive a switching control signal, a first terminal of the first switching switch is connected to a mode selection circuit, a second terminal of the first switching switch is connected to a first quantization circuit, and a third terminal of the first switching switch is connected to a second quantization circuit. Furthermore, a control terminal of the second switching switch is used to receive a switching control signal, a first terminal of the second switching switch is used to receive a comparison signal, a second terminal of the second switching switch is connected to the first quantization circuit, and a third terminal of the second switching switch is connected to the second quantization circuit.

[0028] In some embodiments, the analog quantization circuit is further used to receive a ramp signal and a reset voltage and a signal voltage of a first mode corresponding to the second photosensitive unit, and output a target digital quantization value of the first mode corresponding to the second photosensitive unit, and the slope of the ramp signal is a first slope. In addition, the analog quantization circuit is further used to receive a ramp signal and a reset voltage and a signal voltage of a second mode corresponding to the second photosensitive unit, and output a target digital quantization value of the second mode corresponding to the second photosensitive unit, and the slope of the ramp signal is a second slope. The first slope and the second slope can be the same. Alternatively, the first slope and the second slope can be different, for example, the first slope is smaller than the second slope, so as to select ramp signals with different slopes to quantize the voltage output by the pixel, thereby further improving HDR.

[0029] In some embodiments, when the analog quantization circuit receives a reset voltage and a signal voltage of a first mode corresponding to the first photosensitive unit, the slope of the corresponding ramp signal may also be the first slope. Furthermore, when the analog quantization circuit receives a reset voltage and a signal voltage of a second mode corresponding to the first photosensitive unit, the slope of the corresponding ramp signal may also be the second slope.

[0030] In some embodiments, the read circuit further includes a slope selection circuit connected to the analog quantization circuit. The slope selection circuit is configured to receive a plurality of ramp signals having different slopes. Furthermore, in response to the analog quantization circuit receiving a reset voltage and a signal voltage in a first pattern, the slope selection circuit may output a ramp signal having a first slope from among the plurality of ramp signals to the analog quantization circuit. Furthermore, in response to the analog quantization circuit receiving a reset voltage and a signal voltage in a second pattern, the slope selection circuit may output a ramp signal having a second slope from among the plurality of ramp signals to the analog quantization circuit.

[0031] In a second aspect, an embodiment of the present application further provides an electronic device, comprising an image signal processor and an image sensor, wherein the image sensor is connected to the image signal processor. Furthermore, the image sensor is configured to output a feedback signal and a digital quantization value for each pixel to the image signal processor, and the image signal processor is configured to generate an image based on the feedback signal and the digital quantization value for each pixel. The image sensor is the image sensor described in the first aspect or any possible implementation of the first aspect.

[0032] In addition, the technical effects of the corresponding scheme in the second aspect can refer to the technical effects that can be obtained by the corresponding scheme in the first aspect, and the repeated parts will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0034] FIG2 is a schematic diagram of the structure of an image sensor provided in an embodiment of the present application;

[0035] FIG3 is a circuit diagram of a pixel provided in an embodiment of the present application;

[0036] FIG4 is a signal timing diagram in a DCG mode provided by an embodiment of the present application;

[0037] FIG5 is another circuit diagram of a pixel provided in an embodiment of the present application;

[0038] FIG6 is another circuit diagram of a pixel provided in an embodiment of the present application;

[0039] FIG7 is a schematic diagram of another structure of an image sensor provided in an embodiment of the present application;

[0040] FIG8 is a schematic diagram of another structure of an image sensor provided in an embodiment of the present application;

[0041] FIG9 is a schematic structural diagram of a reading circuit provided in an embodiment of the present application;

[0042] FIG10 is a schematic diagram of a circuit structure of a reading circuit provided in an embodiment of the present application;

[0043] FIG11 a is a signal timing diagram of a read circuit in LCG mode provided by an embodiment of the present application;

[0044] FIG11 b is a signal timing diagram of a read circuit in HCG mode provided by an embodiment of the present application;

[0045] FIG12 is a schematic diagram of another circuit structure of a reading circuit provided in an embodiment of the present application;

[0046] FIG13a is another signal timing diagram of the read circuit in the LCG mode provided by an embodiment of the present application;

[0047] FIG13 b is another signal timing diagram of the read circuit in the HCG mode provided by an embodiment of the present application;

[0048] FIG14 is a schematic diagram of another circuit structure of a reading circuit provided in an embodiment of the present application;

[0049] FIG15 is a signal timing diagram of a ramp signal provided in an embodiment of the present application;

[0050] FIG16 is a schematic diagram of a circuit structure of a slope selection circuit provided in an embodiment of the present application;

[0051] FIG17 a is another signal timing diagram of the read circuit in the LCG mode provided by an embodiment of the present application;

[0052] FIG17 b is another signal timing diagram of the reading circuit provided in the HCG mode according to an embodiment of the present application.

[0053] Reference numerals

[0054] 1-housing; 2-image sensor; 3-mainboard; 100-pixel array; 110-pixel circuit; 200-reading circuit; 210-mode selection circuit; 211-first control circuit; 212-second control circuit; 213-third control circuit; 220-analog quantization circuit; 2201-first comparator; 2202-first counter; 2203-second memory; 221-first quantization circuit; 2211-second comparator; 2212-second counter; 2213-third memory; 222-second quantization circuit; 2221-third comparator; 2222-third counter; 2223-fourth memory; 223-switching control circuit; 224-quantization gating circuit; 225-digital comparison circuit; 230-slope selection circuit; KC1-first switching switch; KC2-second switching switch; K1-first switch; K2-second switch; K3-third switch; 300-image signal processor; PX-pixel; VSL-readout line; M1-reset transistor; M2-conversion gain control transistor; M3-charge transfer transistor; M4-source follower transistor; M5-row selection transistor; CS-capacitor; D1-first inverter; D2-second inverter; D3-third inverter; U1-first multiplexer; U2-second multiplexer; U3-third multiplexer; U4-fourth multiplexer; U5-fifth multiplexer; CG-storage capacitor. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0056] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0057] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the following first describes its specific application scenarios. The image sensor provided by the embodiments of the present application can be applied to electronic devices, including but not limited to common devices with camera functions such as digital cameras, mobile phones, tablet computers, and wearable devices. Of course, the image sensor provided by the embodiments of the present application can also be applied to other types of electronic devices with camera functions.

[0058] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Referring to Figure 1 , the electronic device may include: a housing 1, an image sensor 2, and a mainboard 3. The image sensor 2 and mainboard 3 are disposed within the housing 1, and the image sensor 2 is disposed on and electrically connected to the mainboard 3. For example, the mainboard 3 includes, but is not limited to, a printed circuit board (PCB).

[0059] FIG2 is a schematic diagram of the structure of an image sensor provided in an embodiment of the present application. Referring to FIG2 , the image sensor includes a pixel array 100, a readout circuit 200, and an image signal processor (ISP) 300, and each readout circuit 200 is connected to the image signal processor 300. The pixel array 100 includes a plurality of pixels PX and a plurality of readout lines VSL arranged in an array, and each readout line VSL is connected to the readout circuit 200 in a one-to-one correspondence. For example, the plurality of pixels PX can be arranged in the form of multiple rows and multiple columns, and a column of pixels PX can be connected to one or more readout lines VSL. In addition, each pixel PX has a photodiode (PD) and a pixel circuit composed of a transistor, the pixel circuit is connected to the negative electrode of the photodiode, and the pixel circuit is also connected to the readout line VSL. In actual applications, light from a target object enters the PD of the image sensor, where it converts the optical signal into an electrical signal. The pixel circuit then transfers the electrical signal from the PD to the readout line VSL. The readout circuit 200 quantizes the signal on the readout line VSL and outputs it to the image signal processor 300. The image signal processor 300 then performs image synthesis based on the received signal. It is understood that this application uses the example of a column of pixels PX connected to a single readout line VSL for detailed description.

[0060] FIG3 is a circuit diagram of a pixel provided in an embodiment of the present application. Referring to FIG3 , the pixel includes a PD operating at a reverse bias voltage and a pixel circuit. The pixel circuit 110 may include a reset transistor M1, a conversion gain control transistor M2, a charge transfer transistor M3, a source follower transistor M4, a row select transistor M5, and a capacitor CS. The positive electrode of the PD is grounded, and the negative electrode of the PD is connected to the first electrode of the charge transfer transistor M3. Furthermore, the capacitor CS is connected between the first and second electrodes of the reset transistor M1. It is understood that the capacitor CS may be a physical capacitor or a parasitic capacitor. The gate of the reset transistor M1 is connected to the reset signal line RST. The first electrode of the reset transistor M1 is used to receive the voltage VDD. The second electrode of the reset transistor M1 is connected to the first electrode of the conversion gain control transistor M2. The gate of the conversion gain control transistor M2 is connected to the gain control signal line DCGX, and the second electrode of the conversion gain control transistor M2 is connected to the gate of the source follower transistor M4. The gate of the charge transfer transistor M3 is connected to the charge transfer signal line TG, and the second electrode of the charge transfer transistor M3 is connected to the gate of the source follower transistor M4. The first electrode of the source follower transistor M4 is used to receive the voltage VDD, and the second electrode of the source follower transistor M4 is connected to the first electrode of the row selection transistor M5. The gate of the row selection transistor M5 is connected to the row selection signal line RS, and the second electrode of the row selection transistor M5 is connected to the readout line VSL. The signals on the reset signal line RST, the gain control signal line DCGX, the charge transfer signal line TG and the row selection signal line RS are controlled by the row driver. It can be understood that the above is only an example to illustrate the specific structure of the pixel circuit provided in the embodiment of the present application. In specific implementation, the specific structure of the pixel circuit is not limited to the above structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which are not limited here.

[0061] In a specific implementation, the reset transistor M1, the conversion gain control transistor M2, the charge transfer transistor M3, and the row selection transistor M5 can be turned on by a high-level signal and turned off by a low-level signal. Furthermore, the first electrode of the transistor can be a source and the second electrode can be a drain, or the first electrode of the transistor can be a drain and the second electrode can be a source.

[0062] In conjunction with Figure 3, the second electrode of the conversion gain control transistor M2, the gate of the source follower transistor M4, and the second electrode of the charge transfer transistor M3 are connected to a floating diffusion potential (FD) point. In a specific implementation, when light from a target object enters the pixel PX, photoelectric conversion is completed in the PD, generating photogenerated electrons, which are stored in the PD. When the charge transfer transistor M3 is turned on, the photogenerated electrons in the PD are diverted to the FD point, causing the voltage value at the FD point to change. This voltage value controls the source follower transistor M4 to generate a corresponding voltage. The voltage is input to the readout line VSL through the turned-on row select transistor M5, thereby enabling the readout line VSL to transmit the corresponding voltage.

[0063] Moreover, DCG is one of the methods for image sensors to implement HDR. Compared with the technical solution of implementing HDR through multiple exposures, the DCG technical solution only requires a single exposure, so it can effectively avoid the problem of motion artifacts. The pixel PX provided in the embodiment of the present application may have a DCG function. Specifically, the parasitic capacitance of the FD point is recorded as Cpar, and Cpar includes the capacitance of the metal wiring, the coupling capacitance between the gate and the second pole of the charge transfer transistor M3, the coupling capacitance between the gate and the second pole of the conversion gain control transistor M2, etc. Among them, when the conversion gain control transistor M2 and the reset transistor M1 are both in the off state, the FD point capacitance CFD1 includes Cpar. When the conversion gain control transistor M2 is in the on state and the reset transistor M1 is in the off state, the FD point capacitance CFD2 includes both Cpar and Ccs (Ccs represents the capacitance of the capacitor CS). Therefore, CFD2>CFD1. For DCG HDR, when the incident light intensity is low, the number of photogenerated electrons generated in the PD is small, and the high conversion gain (HCG) mode is adopted. In the HCG mode, the conversion gain control transistor M2 is in the off state. Although the CFD1 capacitance value is small, the FD point can fully carry the number of photogenerated electrons derived by the PD. When the incident light intensity is high, the number of photon electrons generated in the PD is large, and the parasitic capacitance Cpar of the FD point itself cannot fully carry the photogenerated electrons derived by the PD, resulting in the voltage change amplitude of the FD point not being able to accurately reflect the number of photogenerated electrons generated in the PD. Therefore, the low conversion gain (LCG) mode is adopted at this time. In the LCG mode, the conversion gain control transistor M2 is in the on state, the CFD2 capacitance value is large, and the FD point can fully carry the number of photogenerated electrons derived by the PD. It can be understood that the conversion gain is defined as the voltage change at the FD point caused by each electron, and the unit is usually μV / e-, which is inversely proportional to the capacitance of the FD point. That is, the smaller the capacitance at point FD is, the higher the conversion gain is; and the larger the capacitance at point FD is, the lower the conversion gain is.

[0064] For example, taking the reset transistor M1, the conversion gain control transistor M2, the charge transfer transistor M3, and the row selection transistor M5 as an example, which are turned on under the control of a high-level signal and turned off under the control of a low-level signal, FIG4 is a signal timing diagram under a DCG mode provided by an embodiment of the present application. Referring to FIG4 , rs represents the signal transmitted by the row selection signal line RS, rst represents the signal transmitted by the reset signal line RST, dcgx represents the signal transmitted by the gain control signal line DCGX, tg represents the signal transmitted by the charge transfer signal line TG, and vsl represents the signal transmitted by the readout line VSL. The pixel shown in FIG3 operates under the control of the signal in the signal timing diagram shown in FIG4 , and can output to the readout line VSL in sequence: the reset voltage V LR 、HCG mode reset voltage V HR 、HCG mode signal voltage V HS and the signal voltage V in LCG mode LS Furthermore, in a specific implementation, in a column of pixels PX, the previous pixel PX can sequentially output the reset voltage V LR , reset voltage V HR , signal voltage V HS and signal voltage V LS After that, the next pixel PX outputs the reset voltage V to the readout line VSL in turn: LR , reset voltage V HR , signal voltage V HS and signal voltage V LS .

[0065] In the related art, in order to reconstruct the HDR image, it is necessary to reset the voltage V output by each pixel through the reading circuit. LR 、V HR , signal voltage V HS 、V LS All are digitally quantized to obtain the reset voltage V LR The digital quantization value D LR , reset voltage V HR The digital quantization value D HR , signal voltage V HS The digital quantization value D HS and signal voltage V LS The digital quantization value D LS Among them, in LCG mode, the exposure quantization result D in LCG mode is obtained by performing subtraction through Correlated Double Sampling (CDS). LCG , and D LCG =D LS -D LRIn HCG mode, the exposure quantification result D in HCG mode is obtained by making a difference through CDS. HCG , and D HCG =D HS -D HR Exposure quantification results D LCG and D HCG The images are synthesized in the image signal processor 300 to obtain an HDR image.

[0066] Generally speaking, the frame period of the image sensor when working in DCG mode is: n×t ADC +t idle , n represents the total number of rows of pixels PX in the image sensor, t ADC Represents the quantized time of the output voltage of each pixel PX after exposure, t idle Represents the idle time between frames. From the formula, we can see that if t ADC If it decreases, the frame period will decrease, that is, t ADC This limits the improvement of the frame rate. Since the above-mentioned related art solution needs to quantize the reset voltage V twice LR 、V HR and twice the signal voltage V HS 、V LS , that is, it is necessary to perform quantization process 4 times on the 4 voltages output by each pixel, which increases the frame period and reduces the frame rate. To this end, the embodiment of the present application provides an image sensor, which reduces the number of quantization times by including the mode selection circuit 210 and the analog quantization circuit 220 in the reading circuit, thereby enabling t ADC Reducing it can reduce the frame period and increase the frame rate.

[0067] As the size of PDs continues to shrink, a pixel may contain several PDs, and these several PDs are covered with the same color filter, such as the red, green and blue color filters used in conventional image sensors. Figure 5 is another circuit schematic diagram of a pixel provided in an embodiment of the present application. Referring to Figure 5, Figure 5 is a structural schematic diagram of a pixel array provided in an embodiment of the present application, for example, each pixel is covered with the same color filter, and each pixel PX includes 4 PDs, namely PD1, PD2, PD3 and PD4, and the 4 PDs in the same pixel PX are arranged in a 2-phenomenon arrangement. Figure 6 is another circuit schematic diagram of a pixel provided in an embodiment of the present application. The pixel circuit corresponding to the pixel shown in Figure 5 can be as shown in Figure 6. The pixel circuit may include: a reset transistor M1, a conversion gain control transistor M2, a source follower transistor M4, a row selection transistor M5, a capacitor CS and four charge transfer transistors, namely M31, M32, M33 and M34. The working principles and connection relationships of the reset transistor M1, the conversion gain control transistor M2, the source follower transistor M4, the row selection transistor M5 and the capacitor CS refer to the above description and are not repeated here.

[0068] Continuing with Figure 6, PD1-PD4 are respectively connected to the gate of the source-follower transistor M4 through charge transfer transistors M31-M34. With this arrangement, if the charge transfer signal lines TG1-TG4 input the same control signal, then PD1-PD4 can be equivalent to a large photosensitive unit. If the charge transfer signal lines TG1-TG4 input different control signals, for example, the charge transfer signal lines TG1 and TG4 input the same control signal TGCS1, and the charge transfer signal lines TG2 and TG3 input the same control signal TGCS2, and the signals TGCS1 and TGCS2 are different, then PD1 and PD4 are equivalent to the first photosensitive unit, and PD2 and PD3 are equivalent to the second photosensitive unit. Alternatively, if the charge transfer signal line inputs the control signal TGCS1 and the charge transfer signal lines TG1-TG3 input the same control signal TGCS2, then PD4 is equivalent to the first photosensitive unit, and PD1, PD2, and PD3 are equivalent to the second photosensitive unit. Based on this, PD1-PD4 can also be equivalent to three photosensitive units or four photosensitive units. It is worth mentioning that the number of charge transfer transistors in each pixel is the same as the number of PDs and they are connected one-to-one. In addition, the number of PDs in each pixel unit is not limited to 2*2, but can be expanded to m*n, where m≥2 and n≥1, or m≥1 and n≥2, and m and n can be equal or different.

[0069] Based on this, in the embodiment of the present application, part of the PD in the pixel is equivalent to the first photosensitive unit, and part of the PD is equivalent to the second photosensitive unit. By controlling the pixel circuit to work based on the first photosensitive unit, the pixel PX can output the pre-judgment voltage corresponding to the first photosensitive unit to the readout line VSL. In addition, by controlling the pixel circuit to work based on the second photosensitive unit, the pixel PX can output the reset voltage and signal voltage of the first mode and the second mode corresponding to the second photosensitive unit to the readout line VSL, and then obtain a feedback signal based on the pre-judgment voltage. The feedback signal is used as the basis for determining whether the second photosensitive unit is in the HCG mode or the LCG mode, so that the second photosensitive unit performs the digital quantization process in the HCG mode or the LCG mode, reducing the number of quantization times and lowering t ADC , thereby reducing the frame period and improving the frame rate.

[0070] In the embodiment of the present application, the pixel can output the pre-judgment voltage corresponding to the first photosensitive unit to the readout line VSL. In addition, the pixel can also sequentially output the reset voltage of the first mode, the reset voltage of the second mode, the signal voltage of the second mode, and the signal voltage of the first mode corresponding to the second photosensitive unit to the readout line VSL. For example, the first mode can be the LCG mode and the second mode can be the HCG mode. Then, the pixel can sequentially output the reset voltage V of the LCG mode corresponding to the second photosensitive unit to the readout line VSL. LR2 、HCG mode reset voltage V HR2 、HCG mode signal voltage V HS2 and the signal voltage V in LCG mode LS2 The following describes the working process of the image sensor provided in the embodiment of the present application in detail by taking the first mode being the LCG mode and the second mode being the HCG mode as an example.

[0071] FIG7 is another structural diagram of the image sensor provided by an embodiment of the present application. Referring to FIG7 , the reading circuit 200 includes: a mode selection circuit 210 and an analog quantization circuit 220, and the analog quantization circuit 220 is connected to the readout line VSL through the mode selection circuit 210. In a specific implementation, when a pre-judgment voltage is transmitted on the readout line VSL, the mode selection circuit 210 can conduct the mode selection circuit 210 with the readout line VSL to output the pre-judgment voltage to the analog quantization circuit 220. The analog quantization circuit 220 can generate a feedback signal according to the pre-judgment voltage, and feed the generated feedback signal back to the mode selection circuit 210. Based on this, the mode selection circuit 210 can respond to the feedback signal and reset the reset voltage V corresponding to the second photosensitive unit to V LR2 , signal voltage V LS2 or reset voltage V HR2 , signal voltage V HS2Output to the analog quantization circuit 220, so that the analog quantization circuit 220 generates a corresponding target digital quantization value, so that the read circuit 200 can reset the voltage V LR2 , signal voltage V LS2 or reset voltage V HR2 , signal voltage V HS2 Quantization is performed without the need for reset voltage V LR2 , signal voltage V LS2 , reset voltage V HR2 , signal voltage V HS2 Therefore, the analog quantization circuit 220 only needs to perform two quantization processes on the four voltages corresponding to the second photosensitive unit with DCG function to obtain the exposure quantization result of the HCG mode or the exposure quantization result of the LCG mode, which can reduce the number of quantization times and reduce t ADC , thereby reducing the frame period and improving the frame rate.

[0072] In the embodiment of the present application, there is no need to set an additional feedback line between the reading circuit 200 and the pixel PX, and there is no need to change the various control signals of the pixel PX. Instead, the various control signals of the pixel PX in the related art can be reused, thereby reducing the development cost, cycle and risk of the pixel PX.

[0073] Furthermore, in the embodiment of the present application, the mode selection circuit 210 in the readout circuit 200 is configured on the readout line VSL, making it applicable to a rolling shutter and compatible with the most commonly used circuit architectures in related technologies, thus having a wide range of applications. Of course, the readout circuit 200 in the embodiment of the present application can also be applied to architectures other than a rolling shutter.

[0074] In a specific implementation, the feedback signal has a first level or a second level, and the mode selection circuit 210 can respond to the level of the feedback signal and reset the voltage V LR2 , signal voltage V LS2 or reset voltage V HR2 , signal voltage V HS2 Output to the analog quantization circuit 220.

[0075] If the level of the feedback signal is the first level, the reset voltage V is transmitted on the readout line VSL. LR2 , signal voltage V LS2 When the mode selection circuit 210 connects the readout line VSL to the analog quantization circuit, the reset voltage V LR2 , signal voltage V LS2 Output to the analog quantization circuit 220, so that the analog quantization circuit 220 outputs the target digital quantization value of the first mode. The target digital quantization value of the first mode may include: reset voltage V LR2The digital quantization value D LR2 and signal voltage V LS2 The digital quantization value D LS2 Alternatively, the target digital quantization value of the first mode may also include: reset voltage V LR2 The digital quantization value D LR2 and signal voltage V LS2 The digital quantization value D LS2 The difference D LS2 -D LR2 .

[0076] If the level of the feedback signal is the second level, the reset voltage V is transmitted on the readout line VSL. HR2 , signal voltage V HS2 When the mode selection circuit 210 connects the readout line VSL to the analog quantization circuit, the reset voltage V HR2 , signal voltage V HS2 Output to the analog quantization circuit 220, so that the analog quantization circuit 220 outputs the target digital quantization value of the second mode. The target digital quantization value of the second mode may include: reset voltage V HR2 The digital quantization value D HR2 and signal voltage V HS2 The digital quantization value D HS2 Alternatively, the target digital quantization value of the second mode may also include: reset voltage V HR2 The digital quantization value D HR2 and signal voltage V HS2 The digital quantization value D HS2 The difference D HS2 -D HR2 .

[0077] FIG8 is a schematic diagram of another embodiment of the image sensor structure provided by the present application. Referring to FIG8 , the image sensor further includes a data transmitter 400. Each readout circuit 200 is connected to the image signal processor 300 via the data transmitter 400. Each readout circuit 200 outputs the target digital quantization value of the first mode or the target digital quantization value of the second mode to the data transmitter 400, which then transmits the target digital quantization value of the first mode or the target digital quantization value of the second mode to the image signal processor 300.

[0078] In order to improve the accuracy of constructing the HDR image, the mode selection circuit 210 also outputs the feedback signal of each sub-pixel PX to the data transmitter 400, and the feedback signal of each sub-pixel PX is also sent to the image signal processor 300 through the data transmitter 400, so that the image signal processor 300 constructs the HDR image based on the feedback signal of each sub-pixel PX and the exposure quantization result of the corresponding mode.

[0079] In some embodiments, to improve data synchronization and accuracy, the mode selection circuit 210 may also output a feedback signal for the pixel PX when the analog quantization circuit 220 outputs the target digital quantization value of the first mode or the target digital quantization value of the second mode corresponding to the pixel PX. For example, the feedback signal for the pixel PX may be directly output to the image signal processor 300, or the feedback signal for the pixel PX may be output to the data transmitter 400, which then outputs the feedback signal for the pixel PX to the image signal processor 300. This configuration enables the image signal processor 300 to determine, based on the feedback signal, whether the exposure quantization result for the pixel PX was obtained using the high conversion gain mode or the low conversion gain mode.

[0080] In some embodiments of the present application, the pixel can output a signal voltage V of the second mode (ie, HCG mode) corresponding to the first photosensitive unit to the readout line VSL. HS1 For example, when the pixel outputs a reset voltage V to the readout line VSL, LR2 、V HR2 , signal voltage V HS2 、V LS2 Before, the pixel outputs the signal voltage V of the second mode corresponding to the first photosensitive unit to the readout line VSL HS1 Based on this, the pre-judgment voltage can be set to the signal voltage V HS1 , and input the reference voltage V to the analog quantization circuit 220 REF , the analog quantization circuit 220 converts the signal voltage V HS1 With reference voltage V REF Compare. If V HS1 <V REF , the analog quantization circuit 220 responds to V HS1 <V REF , the feedback signal with the first level is fed back to the mode selection circuit 210. If V HS1 >V REF , the analog quantization circuit 220 responds to V HS1 >V REF, the feedback signal with the second level is fed back to the mode selection circuit 210. Moreover, the first level can be a high level and the second level can be a low level. Alternatively, the first level can also be a low level and the second level can be a high level. It is understandable that the reference voltage V REF The specific value of can be determined according to the application scenario and is not limited here. Alternatively, when the pixel outputs a reset voltage V LR2 、V HR2 , signal voltage V HS2 、V LS2 Before, the pixel outputs the signal voltage V of the first mode corresponding to the first photosensitive unit to the readout line VSL LS1 Based on this, the predicted voltage can also be set as the signal voltage V LS1 Therefore, this application does not limit how to select the pre-judgment voltage.

[0081] FIG9 is a schematic diagram of a readout circuit according to an embodiment of the present application. Referring to FIG9 , the mode selection circuit 210 may include a first control circuit 211, a second control circuit 212, and a third control circuit 213. The first control circuit 211 is connected to the readout line VSL and the analog quantization circuit 220, respectively. The second control circuit 212 is connected to the third control circuit 213 and the analog quantization circuit 220, respectively. The third control circuit 213 is also connected to the first control circuit 211. Furthermore, the analog quantization circuit 220 is connected to the readout line VSL via the first control circuit 211, thereby controlling the connection or disconnection between the readout line VSL and the analog quantization circuit 220 through the first control circuit 211.

[0082] The readout line VSL transmits the signal voltage V HS1 When the third control circuit 213 can respond to the readout line VSL transmission signal voltage V HS1 , controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, thereby turning on the signal voltage V HS1 The analog quantization circuit 220 is input to generate a feedback signal. In addition, the analog quantization circuit 220 is connected to the third control circuit 213 through the second control circuit 212, thereby outputting the feedback signal generated by the analog quantization circuit 220 to the third control circuit 213 through the second control circuit 212.

[0083] If the level of the feedback signal is the second level, the reset voltage V is transmitted on the readout line VSL. HR2 and signal voltage V HS2 When the third control circuit controls the first control circuit to connect the readout line VSL to the analog quantization circuit, so as to set the reset voltage V HR2 and signal voltage V HS2The digital quantization value is output to the analog quantization circuit 220, so that the analog quantization circuit 220 outputs the target digital quantization value of the second mode.

[0084] If the level of the feedback signal is the first level, the reset voltage V is transmitted on the readout line VSL. LR2 and signal voltage V LS2 When the third control circuit controls the first control circuit to connect the readout line VSL to the analog quantization circuit, so as to set the reset voltage V LR2 and signal voltage V LS2 The digital quantization value is output to the analog quantization circuit 220, so that the analog quantization circuit 220 outputs the target digital quantization value of the first mode.

[0085] FIG10 is a schematic diagram of a circuit structure of a readout circuit provided in an embodiment of the present application. Referring to FIG10 , the first control circuit 211 includes a first switch K1 and a storage capacitor CG. The control terminal of the first switch K1 is connected to the third control circuit, the first terminal of the first switch K1 is connected to the readout line VSL, the second terminal of the first switch K1 is connected to the analog quantization circuit 220, the first terminal of the storage capacitor CG is connected to the second terminal of the first switch K1, and the second terminal of the storage capacitor CG is grounded.

[0086] The second control circuit 212 includes a second switch K2 , wherein a control end of the second switch K2 is used to receive a switch control signal Φ1 , a first end of the second switch K2 is connected to the analog quantization circuit 220 , and a second end of the second switch K2 is connected to the third control circuit 213 .

[0087] The third control circuit 213 includes: a first multiplexer U1, a second multiplexer U2, a third switch K3, a first inverter D1, a second inverter D2, and a first memory 2131. The control terminal of the first multiplexer U1 is configured to receive a first selection control signal U1_sel. The first input terminal of the first multiplexer U1 is configured to receive a first input signal V4. The second input terminal of the first multiplexer U1 is connected to the output terminal of the second multiplexer U2. The output terminal of the first multiplexer U1 is connected to the first control circuit (e.g., the control terminal of the first switch K1). The input terminal of the first inverter D1 is respectively connected to the second control circuit (e.g., the second terminal of the second switch K2) and the first terminal of the third switch K3. The output terminal of the first inverter D1 is respectively connected to the input terminal of the second inverter D2 and the first input terminal of the second multiplexer U2. The output terminal of the second inverter D2 is respectively connected to the second terminal of the third switch K3 and the second input terminal of the second multiplexer U2. The control terminal of the third switch K3 is used to receive the latch control signal Φ2. The control terminal of the second multiplexer U2 is used to receive the second selection control signal U2_sel. In addition, the first memory 2131 is connected to the output terminal of the second inverter D2 and is used to store and output the feedback signal.

[0088] The analog quantization circuit in the present application may be an analog to digital converter (ADC). For example, referring to FIG10 , the analog quantization circuit 220 includes: a first comparator 2201, a first counter 2202, and a second memory 2203, wherein a first input terminal of the first comparator 2201 is connected to the mode selection circuit 210 (e.g., a second terminal of the first switch K1), and a second input terminal of the first comparator 2201 is used to receive a comparison signal V RAMP The output terminal of the first comparator 2201 is connected to the first counter 2202 and the mode selection circuit 210 (for example, the first terminal of the second switch K2). Then, the first comparator 2201 can receive the voltage on the readout line VSL through the first input terminal and receive the comparison signal V through the second input terminal. RAMP , wherein the first input terminal of the first comparator 2201 inputs the pre-judgment voltage (ie, the signal voltage V HS1 ) and compare the signal V RAMP The voltage is the reference voltage V REF When the first comparator 2201 is set to the pre-judgment voltage (i.e., the signal voltage V HS1 ) and the reference voltage V REF Compare and output feedback signal. For example, if V HS1 <V REF , the first comparator 2201 outputs a feedback signal with a first level. HS1 >V REF , the first comparator 2201 outputs a feedback signal with a second level. And, the first input terminal of the first comparator 2201 can also input a reset voltage V LR2 、V HR2 and signal voltage V HS2 、V LS2 , and the comparison signal V RAMP Set as a ramp signal, the first comparator 2201 resets the voltage V LR2 、V HR2 and signal voltage V HS2 、V LS2 The first counter 2202 can generate a count value related to time. The second memory 2203 can store the count value in the first counter 2202 based on the comparison result output by the first comparator 2201. The count value stored in the second memory 2203 is a digital quantization value. It is understood that the first input terminal of the first comparator 2201 is a negative input terminal, and the second input terminal is a positive input terminal. In addition, in Figure 10, "-" represents the negative input terminal and "+" represents the positive input terminal.

[0089] In the embodiment of the present application, the analog quantization circuit 220 receives a reset voltage V LR2 and signal voltage V LS2 When the slope of the corresponding ramp signal can be set to the first slope. The analog quantization circuit 220 receives the reset voltage V HR2 and signal voltage V HS2 When the slope of the corresponding ramp signal can be set to the second slope. For example, the first slope can be the same as the second slope. Based on this, a ramp signal with the same slope can be generated by the ramp generator to serve as the comparison signal V RAMP Alternatively, the first slope can be different from the second slope, for example, the first slope is smaller than the second slope, so as to select ramp signals with different slopes to quantize the voltage output by the pixel, thereby further improving HDR.

[0090] For example, the image sensor may further include a ramp generator connected to each comparator in the read circuit. The ramp generator can generate a comparison signal V RAMP , and V RAMP Input to each analog quantization circuit.

[0091] The switch in the embodiment of the present application can be one or more of various types of switching devices such as a relay, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a silicon carbide (SiC) MOSFET, etc., which are not listed one by one in the embodiment of the present application. In addition, each switch can include a first end, a second end and a control end, wherein the control end is used to control the closing or opening of the switch. When the switch is closed, current can be transmitted between the first end and the second end of the switch. When the switch is open, current cannot be transmitted between the first end and the second end of the switch. Taking MOSFET as an example, the control end of the switch is the gate, the first end of the switch can be the source, and the second end can be the drain, or the first end can be the drain and the second end can be the source. In addition, the first memory 2131 and the second memory 2203 in the embodiment of the present application include but are not limited to static random access memory (SRAM).

[0092] It is worth mentioning that the above is only an example to illustrate the specific structure of the reading circuit provided in the embodiment of the present application. In specific implementation, the specific structure of the reading circuit is not limited to the above structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which is not limited here.

[0093] The following takes the structure of the reading circuit shown in Figure 10 as an example, and takes PD4 as equivalent to the first photosensitive unit and PD1~PD3 as equivalent to the second photosensitive unit as an example, combined with the signal timing diagram, to specifically describe the working process of the reading circuit in the image sensor provided in the embodiment of the present application.

[0094] FIG11a is a signal timing diagram of a read circuit in LCG mode provided by an embodiment of the present application, wherein vsl represents the signal on the readout line VSL, V CMP represents the signal at the output of the first comparator 2201, V1 represents the signal at the output of the first inverter D1, V2 represents the signal at the output of the second inverter D2, V3 represents the signal at the output of the second multiplexer U2, Φ IN represents the signal of the output end of the first multiplexer U1, tg1 represents the signal transmitted by the charge transfer signal line TG1, tg2 represents the signal transmitted by the charge transfer signal line TG2, tg3 represents the signal transmitted by the charge transfer signal line TG3, and tg4 represents the signal transmitted by the charge transfer signal line TG4.

[0095] At time t1, the first and second photosensitive units are exposed and the pre-judgment begins. Also, at time t1, signal rst turns on reset transistor M1 and signal dcgx turns on conversion gain control transistor M2, resetting point FD in the pixel circuit.

[0096] At time t2, the signal rst controls the reset transistor M1 to turn off, and the signal dcgx controls the conversion gain control transistor M2 to turn off, completing the reset operation of the FD point, and the pixel enters the HCG mode.

[0097] At time t3, signal tg4 controls the charge transfer transistor M4 to turn on, and the photogenerated electrons of the first photosensitive unit are introduced from PD4 to the FD point, causing the voltage of the FD point to drop. Then the pixel outputs the signal voltage V HCG mode to the readout line VSL. HS1 (i.e., the pre-judgment voltage). In addition, the first multiplexer U1 selects V4 in response to the control of U1_Sel, and V4 is constantly at a high level, then Φ IN is high, the first switch K1 is turned on, and the signal voltage V HS1 Input to the first comparator 2201.

[0098] At time t4, the voltage of the comparison signal is set to the reference voltage V REF, V HS1 With V HS1 Make a comparison to determine the current incident light intensity. HS1 <V REF , indicating that the incident light intensity is large, the second photosensitive unit should adopt the LCG mode. The signal V output by the first comparator 2201 CMP In addition, Φ1 controls the second switch K2 to be turned on, then V1 is at a low level and V2 is at a high level. The high level signal can be used as a feedback signal, and the high level signal V CMP Stored in the first memory 2131.

[0099] At time t5, Φ1 controls the second switch K2 to be closed, and Φ2 controls the third switch K3 to be turned on, and the voltages of V1 and V2 are latched. In addition, the first multiplexer U1 responds to the control of U1_Sel to select V3, that is, from time t5, the signal Φ IN Same as signal V3. So far, the pre-judgment process of LCG mode and HCG mode is completed.

[0100] At time t6, the pixel begins quantizing the voltage corresponding to the second photosensitive unit output to the readout line VSL. Signal rst turns on reset transistor M1, and signal dcgx turns on conversion gain control transistor M2, clearing the photogenerated electrons stored at point FD during the pre-judgment.

[0101] At time t7, the signal rst controls the reset transistor M1 to turn off, the signal dcgx controls the conversion gain control transistor M2 to turn on, and the pixel outputs the reset voltage V to the readout line VSL. LR2 The second multiplexer U2 selects V2 in response to the control of U2_Sel. Since V2 is high, V3 and Φ IN is also high level, the first switch K1 is turned on, and the reset voltage V LR2 Stored in storage capacitor CG.

[0102] At time t8, the signal rst controls the reset transistor M1 to turn off, the signal dcgx controls the conversion gain control transistor M2 to turn off, and the pixel outputs the reset voltage V to the readout line VSL. HR2 The second multiplexer U2 responds to the control of U2_Sel and selects V1. Since V1 is at a low level, V3 and Φ IN is also low level, the first switch K1 is closed, and the reset voltage V HR2 No storage is performed on the storage capacitor CG.

[0103] At time t9, the comparison signal input to the first comparator 2201 is a ramp signal, and the reset voltage V LR2 It is also input to the first comparator 2201, and the reset voltage V LR2Quantize and get the reset voltage V LR2 The digital quantization value D LR2 , and D LR2 Stored in the second memory 2203.

[0104] At time t10, signals tg1-tg3 control the charge transfer transistors M1-M3 to turn on, and the photogenerated electrons generated by the exposure of PD1-PD3 in the second photosensitive unit are introduced into the FD point. Since the signal dcgx controls the conversion gain control transistor M2 to remain in the off state, it is still in HCG mode, and the pixel outputs a signal voltage V to the readout line VSL. HS2 Since the second multiplexer U2 selects V1 in response to the control of U2_Sel, and V1 is at a low level, V3 and ΦIN are both at a low level, the first switch K1 is disconnected, and the signal voltage V HS2 The charge transfer transistors M1 to M3 are then turned off by signals tg1 to tg3.

[0105] At time t11, signals tg1-tg3 control the charge transfer transistors M1-M3 to turn on again, and signal dcgx controls the conversion gain control transistor M2 to turn on as well. The pixel enters the LCG mode and outputs a signal voltage V to the readout line VSL. LS2 The second multiplexer U2 responds to the control of U2_Sel and selects V2. Since V2 is at a high level, V3 and ΦIN are both at a high level, the first switch K1 is turned on, and the signal voltage V LS2 Stored in storage capacitor CG.

[0106] At time t12, the comparison signal input to the first comparator 2201 is a ramp signal, and the signal voltage V LS2 It is also input to the first comparator 2201, and the signal voltage V LS2 Quantize and get the signal voltage V LS2 The digital quantization value D LS2 , and D LS2 Stored in the second memory 2203. Afterwards, the feedback signal in the first memory 2131 and the digital quantization value D in the second memory 2203 are combined. LR2 、D LS2 Read out, send to data transmitter 400, output to image signal processor 300 through data transmitter 400, for HDR image reconstruction. LS2 When quantizing, the digital quantization value D is also called LR2 , to get the difference D LS2 -D LR2 , and the difference D LS2 -D LR2Stored in the second memory 2203. Afterwards, the feedback signal in the first memory 2131 and the difference D in the second memory 2203 are LS2 -D LR2 The data is read out and sent to the data transmitter 400 , and then output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0107] FIG11b is a signal timing diagram of the read circuit provided by an embodiment of the present application in the HCG mode, wherein vsl represents the signal on the readout line VSL, V CMP represents the signal at the output of the first comparator 2201, V1 represents the signal at the output of the first inverter D1, V2 represents the signal at the output of the second inverter D2, V3 represents the signal at the output of the second multiplexer U2, Φ IN represents the signal of the output end of the first multiplexer U1, tg1 represents the signal transmitted by the charge transfer signal line TG1, tg2 represents the signal transmitted by the charge transfer signal line TG2, tg3 represents the signal transmitted by the charge transfer signal line TG3, and tg4 represents the signal transmitted by the charge transfer signal line TG4.

[0108] The working process from time t1 to time t3 is substantially the same as the working process from time t1 to time t3 shown in FIG11 a , and will not be described in detail here.

[0109] At time t4, the voltage of the comparison signal is set to the reference voltage V REF , V HS1 With V HS1 Make a comparison to determine the current incident light intensity. HS1 >V REF , indicating that the incident light intensity is small, the second photosensitive unit should use the HCG mode. The first comparator 2201 outputs a signal V CMP Furthermore, Φ1 controls the second switch K2 to be turned on, so that V1 is at a high level and V2 is at a low level. The low level signal can be used as a feedback signal and stored in the first memory 2131 .

[0110] The working process from time t5 to time t6 is substantially the same as the working process from time t5 to time t6 shown in FIG11 a , and will not be described in detail here.

[0111] At time t7, the signal rst controls the reset transistor M1 to turn off, the signal dcgx controls the conversion gain control transistor M2 to turn on, and the pixel outputs the reset voltage V to the readout line VSL. LR2 The second multiplexer U2 responds to the control of U2_Sel and selects V2. Since V2 is low, V3 and Φ IN is also low level, the first switch K1 is closed, and the reset voltage V LR2No storage is performed on the storage capacitor CG.

[0112] At time t8, the signal rst controls the reset transistor M1 to turn off, the signal dcgx controls the conversion gain control transistor M2 to turn off, and the pixel outputs the reset voltage V to the readout line VSL. HR2 The second multiplexer U2 responds to the control of U2_Sel and selects V1. Since V1 is at a high level, V3 and ΦIN are also at a high level. The first switch K1 is opened, and the reset voltage V HR2 Stored in storage capacitor CG.

[0113] At time t9, the comparison signal input to the first comparator 2201 is a ramp signal, and the reset voltage V HR2 Input the first comparator 2201, the reset voltage V HR2 Quantize and get the reset voltage V HR2 The digital quantization value D HR2 , and D HR2 Stored in the second memory 2203.

[0114] At time t10, signals tg1-tg3 control the charge transfer transistors M1-M3 to turn on, and the photogenerated electrons generated by the exposure of PD1-PD3 in the second photosensitive unit are introduced into the FD point. Since the signal dcgx controls the conversion gain control transistor M2 to remain in the off state, it is still in HCG mode, and the pixel outputs a signal voltage V to the readout line VSL. HS2 Since the second multiplexer U2 selects V1 in response to the control of U2_Sel, and V1 is high, V3 and ΦIN are both high, the first switch K1 is opened, and the signal voltage V HS2 The charge is stored in the storage capacitor CG. Afterwards, signals tg1-tg3 control the charge transfer transistors M1-M3 to be turned off.

[0115] At time t11, signals tg1-tg3 control the charge transfer transistors M1-M3 to turn on again, and signal dcgx controls the conversion gain control transistor M2 to turn on as well. The pixel enters the LCG mode and outputs a signal voltage V to the readout line VSL. LS2 The second multiplexer U2 responds to the control of U2_Sel and selects V2. Since V2 is at a low level, V3 and ΦIN are both at a low level. The first switch K1 is disconnected, and the signal voltage V LS2 No storage is performed on the storage capacitor CG.

[0116] At time t12, the comparison signal input to the first comparator 2201 is a ramp signal, and the signal voltage V HS2 Input the first comparator 2201, the signal voltage V HS2 Quantize and get the signal voltage V HS2 The digital quantization value DHS2 , and D HS2 Then, the feedback signal in the first memory 2131 and the digital quantization value D in the second memory 2203 are combined. HR2 、D HS2 Read out, send to the data transmitter 400, and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction. Alternatively, the signal voltage V HS2 When quantizing, the digital quantization value D is also called HR2 , to get the difference D HS2 -D HR2 , and the difference D HS2 -D HR2 Then, the feedback signal in the first memory 2131 and the difference D in the second memory 2203 are stored. HS2 -D HR2 The data is read out and sent to the data transmitter 400 , and then output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0117] It is understandable that a row of pixels in a pixel array may have multiple pixels, and the multiple pixels in the row may have a first target pixel and a second target pixel, that is, some pixels in the row are first target pixels, and some pixels are second target pixels. The working process of the read circuit connected to the first target pixel can refer to the working process of the read circuit shown in Figure 10 combined with the signal timing diagram shown in Figure 11a. The working process of the read circuit connected to the second target pixel can refer to the working process of the read circuit shown in Figure 10 combined with the signal timing diagram shown in Figure 11b. Based on this, the read circuit connected to the first target pixel and the read circuit connected to the second target pixel both perform a quantization process of the reset voltage at time t9, and both perform a quantization process of the signal voltage at time t12. In some other embodiments, the multiple pixels in the row may all be first target pixels or all be second target pixels, which is not limited to the specific details here.

[0118] It is understood that since each readout circuit 200 is connected to a column of pixels PX via a readout line VSL, each readout circuit 200 can output digital quantization values ​​corresponding to a column of pixels PX. The image signal processor 300 can then receive the digital quantization values ​​corresponding to all pixels PX, thereby constructing an HDR image based on the digital quantization values ​​corresponding to all pixels PX. It is understood that the digital quantization values ​​corresponding to a column of pixels PX output by each readout circuit 200 can all be the target digital quantization values ​​of the first mode corresponding to the second photosensitive cells, or all be the target digital quantization values ​​of the second mode corresponding to the second photosensitive cells, or some can be the target digital quantization values ​​of the first mode corresponding to the second photosensitive cells and some can be the target digital quantization values ​​of the second mode corresponding to the second photosensitive cells. The digital quantization values ​​corresponding to all pixels PX received by the image signal processor 300 can all be the target digital quantization values ​​of the first mode corresponding to the second photosensitive cells, or all be the target digital quantization values ​​of the second mode corresponding to the second photosensitive cells, or some can be the target digital quantization values ​​of the first mode corresponding to the second photosensitive cells and some can be the target digital quantization values ​​of the second mode corresponding to the second photosensitive cells.

[0119] It is understandable that the image sensor may further include a clock generator, which is respectively connected to the mode selection circuit in each reading circuit, so as to input signals V4, U1_sel, U2_sel, Φ1, and Φ2 to the mode selection circuit through the clock generator.

[0120] Based on the same concept, in some other embodiments of the present application, HDR image synthesis can also be performed in combination with long exposure and short exposure. For example, referring to Figure 8, if PD1 and PD4 are equivalent to the first photosensitive unit, and the first photosensitive unit is subjected to short exposure. PD2 and PD3 are equivalent to the second photosensitive unit, and the first photosensitive unit is subjected to long exposure. Among them, if the current incident light intensity is very small, the image adopts the digital quantization value of the HCG mode corresponding to the second photosensitive unit. If the current incident light intensity is very large, the image adopts the digital quantization value of the LCG mode corresponding to the first photosensitive unit. In addition, the digital quantization value of the LCG mode corresponding to the second photosensitive unit and the digital quantization value of the HCG mode corresponding to the first photosensitive unit are used to quantify the incident light intensity of medium intensity. Therefore, in order to obtain a frame of HDR image, according to the existing technology, four groups of quantization processes are required (each group of quantization processes includes a reset voltage quantization process and a signal voltage quantization process), that is, the reset voltage and signal voltage of the HCG mode and LCG mode corresponding to the second photosensitive unit need to be quantized, and the reset voltage and signal voltage of the HCG mode and LCG mode corresponding to the first photosensitive unit also need to be quantized, resulting in a long quantization time and a low frame rate. To this end, the embodiment of the present application provides another image sensor, which uses the signal voltage and reset voltage of the second mode corresponding to the first photosensitive unit as a pre-judgment voltage to determine whether the second photosensitive unit performs a digital quantization process in the HCG mode or the LCG mode, which can reduce the number of quantization times and reduce t ADC , thereby reducing the frame period and improving the frame rate.

[0121] In some other embodiments of the present application, FIG12 is another circuit structure diagram of a reading circuit provided in an embodiment of the present application. Referring to FIG12, the first control circuit 211, the second control circuit 212, and the third control circuit 213 not only have the functions of the above-mentioned embodiments, but also have the following functions. The pixel outputs the signal voltage V of the second mode (i.e., HCG mode) corresponding to the first photosensitive unit to the readout line VSL. HS1 Before that, the reset voltage V corresponding to the second mode (ie, HCG mode) of the first photosensitive unit is output to the readout line VSL. HR1 Based on this, the reset voltage V is transmitted on the readout line VSL HR1 When the third control circuit 213 controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, the reset voltage V HR1 Input analog quantization circuit 220. And, the readout line VSL transmits the signal voltage V HS1 When the third control circuit 213 controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, the signal voltage V HS1 Input analog quantization circuit 220. Then the analog quantization circuit 220 can receive the reset voltage V HR1and signal voltage V HS1 , and the analog quantization circuit 220 also receives a ramp signal, according to the reset voltage V HR1 and signal voltage V HS1 And the ramp signal outputs the feedback signal.

[0122] For example, the analog quantization circuit 220 can be configured to generate a reset voltage V HR1 and ramp signal, the reset voltage V HR1 Quantize and get the reset voltage V HR1 The digital quantization value D HR1 The analog quantization circuit 220 can also be used according to the signal voltage V HS1 And ramp signal, the signal voltage V HS1 Quantize and get the signal voltage V HS1 The digital quantization value D HS1 From this, we can get the difference D HS1 -D HR1 , and the difference D HS1 -D HR1 Set as the target digital quantization difference D HCG1 , that is, D HCG1 =D HS1 -D HR1 Alternatively, for the signal voltage V HS1 When quantizing, the digital quantization value D is also called HR1 , thus directly obtaining the difference D HS1 -D HR1 .

[0123] Generally, the long exposure time and the short exposure time have an exposure time ratio k. Based on this, the analog quantization circuit 220 can generate a feedback signal according to the relationship between the target digital quantization difference, the exposure time ratio k, and the digital voltage threshold. For example, the analog quantization circuit 220 can generate a feedback signal according to the relationship between the target digital quantization difference D HCG1 The product of the exposure time ratio k (ie D HCG1 *k) and digital voltage threshold D REF Compare to generate feedback signal. HCG1 *k>D REF , the analog quantization circuit 220 can generate a feedback signal with a first level and feed the feedback signal back to the mode selection circuit 210. HCG1 *k <D REF , the analog quantization circuit 220 can generate a feedback signal with a second level and feed the feedback signal back to the mode selection circuit 210. It can be understood that the digital voltage threshold D REF The specific value of can be determined according to the application scenario and is not limited here.

[0124] Furthermore, the analog quantization circuit 220 can also convert the digital quantization value D HR1 、D HS1 or difference D HS1 -D HR1 The target digital quantization value of the second mode corresponding to the first photosensitive unit is output to the image signal processor 300 .

[0125] 12, the pixel outputs the reset voltage V corresponding to the first photosensitive unit to the readout line VSL. HR1 Before that, the reset voltage V corresponding to the first mode (ie, LCG mode) of the first photosensitive unit is output to the readout line VSL. LR1 The readout line VSL transmits the reset voltage V LR1 When the third control circuit 213 controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, so as to turn on the reset voltage V LR1 Input analog quantization circuit 220, analog quantization circuit 220 receives reset voltage V LR1 and comparison signal, and the comparison signal V RAMP Set as ramp signal, reset voltage V LR1 Quantize and get the reset voltage V LR1 The digital quantization value D LR1 And, the pixel outputs a signal voltage V to the readout line VSL HS1 Afterwards, the signal voltage V corresponding to the first mode (ie, LCG mode) of the first photosensitive unit is output to the readout line VSL. LS1 , that is, the pixels can sequentially output the reset voltage V corresponding to the first photosensitive unit to the readout line VSL: LR1 、V HR1 , signal voltage V HS1 、V LS1 The readout line VSL transmits a signal voltage V LS1 When the third control circuit 213 controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, so as to turn the signal voltage V LS1 Input analog quantization circuit 220, analog quantization circuit 220 receives signal voltage V LS1 and comparison signal, and the comparison signal V RAMP Set as ramp signal, the signal voltage V LS1 Quantize and get the signal voltage V LS1 The digital quantization value D LS1 Based on this, the analog quantization circuit 220 can convert the digital quantization value D LR1 、D LS1 As the target digital quantization value of the first mode corresponding to the first photosensitive unit, the signal voltage V LS1When quantizing, D is also called LR1 , to get the signal voltage V LS1 The digital quantization value D LS1 and reset voltage V LR1 The digital quantization value D LR1 The difference D LS1 -D LR1 So that the analog quantization circuit 220 can convert the difference D LS1 -D LR1 The target digital quantization value of the first mode corresponding to the first photosensitive unit is output.

[0126] In the embodiment of the present application, the control signals of the first photosensitive unit and the second photosensitive unit can be multiplexed with the control signals in the signal timing diagram shown in FIG4 , which can reduce the development cost, cycle and risk of the pixel PX. HR1 and signal voltage V LS1 As the predicted voltage.

[0127] 12 , the analog quantization circuit 220 includes a switching control circuit 223, a first quantization circuit 221, a second quantization circuit 222, a quantization gating circuit 224, and a digital comparison circuit 225. The first quantization circuit 221 and the second quantization circuit 222 are respectively connected to the mode selection circuit 210 through the switching control circuit 223, and the first quantization circuit 221 and the second quantization circuit 222 respectively receive comparison signals through the switching control circuit 223. The first quantization circuit 221 is connected to the quantization gating circuit 224, the second quantization circuit 222 is respectively connected to the quantization gating circuit 224 and the digital comparison circuit 225, and the digital comparison circuit 225 is connected to the mode selection circuit 210.

[0128] For example, referring to FIG12 , the switching control circuit 223 may include: a first switching switch KC1 and a second switching switch KC2, wherein the control terminal of the first switching switch KC1 is used to receive the switching control signal CKS, the first terminal of the first switching switch KC1 is connected to the mode selection circuit 210 (e.g., the second terminal of the first switch KC1), the second terminal of the first switching switch KC1 is connected to the first quantization circuit 221, and the third terminal of the first switching switch KC1 is connected to the second quantization circuit 222. Furthermore, the control terminal of the second switching switch KC2 is used to receive the switching control signal CKS, and the first terminal of the second switching switch KC2 is used to receive the comparison signal V RAMP The second end of the second switch KC2 is connected to the first quantization circuit 221 , and the third end of the second switch KC2 is connected to the second quantization circuit 222 .

[0129] In some embodiments, for quantizing the voltage of the LCG mode corresponding to the first photosensitive unit and quantizing the voltage of the LCG mode and the HCG mode corresponding to the second photosensitive unit, the switching control circuit 223 can be controlled to select the first quantization circuit 221. For example, referring to FIG. 12, the switching control circuit 223 can output the voltage corresponding to the second photosensitive unit (for example, the reset voltage V LR1 、V HR1 and signal voltage V LS1 、V HS1 ), the mode selection circuit 210 and the comparison signal V RAMP The first quantization circuit 221 is turned on, and the first quantization circuit 221 receives the voltage corresponding to the second photosensitive unit (for example, the reset voltage V LR1 、V HR1 and signal voltage V LS1 、V HS1 ) and comparison signal, and the comparison signal V RAMP is a ramp signal, which is used to adjust the voltage corresponding to the second photosensitive unit (for example, the reset voltage V LR1 、V HR1 and signal voltage V LS1 、V HS1 ) is quantized. The switching control circuit 223 can also output a reset voltage V corresponding to the first photosensitive unit in response to the mode selection circuit 210. LR1 and signal voltage V LS1 , the mode selection circuit 210 and the comparison signal are connected to the first quantization circuit 221, and the first quantization circuit 221 receives the reset voltage V LR1 and signal voltage V LS1 and comparison signal V RAMP , and the comparison signal V RAMP is a ramp signal, which is used to reset the voltage V LR1 and signal voltage V LS1 For example, the analog quantization circuit 220 receives a reset voltage V LR1 and signal voltage V LS1 When the analog quantization circuit 220 receives the reset voltage V of the first mode corresponding to the second photosensitive unit LR1 and signal voltage V LS1 The analog quantization circuit 220 receives the reset voltage V of the second mode corresponding to the second photosensitive unit. HR1 and signal voltage V HS1 When , the slope of the corresponding ramp signal can be set to the second slope.

[0130] Exemplarily, the first quantization circuit 221 includes a second comparator 2211, a second counter 2212, and a third memory 2213, wherein the first input terminal and the second input terminal of the second comparator 2211 are connected to the switching control circuit 223. For example, the first input terminal of the second comparator 2211 is connected to the second terminal of the first switching switch KC1, and the second input terminal of the second comparator 2211 is connected to the second terminal of the second switching switch KC2. The output terminal of the second comparator 2211 is connected to the second counter 2212. Then, the second comparator 2211 can receive the voltage on the readout line VSL through the first input terminal and receive the comparison signal V through the second input terminal. RAMP , the comparison signal V RAMP Set to a ramp signal, the first comparator 2201 compares the voltage received at its first input terminal with the ramp signal and outputs a comparison result. The second counter 2212 can generate a count value related to time. The third memory 2213 can store the count value in the second counter 2212 based on the comparison result output by the second comparator 2211. The count value stored in the third memory 2213 is a digital quantization value. It is understandable that the first input terminal of the second comparator 2211 is a negative input terminal and the second input terminal is a positive input terminal. In addition, in Figure 12, "-" represents the negative input terminal and "+" represents the positive input terminal.

[0131] In some embodiments, for quantizing the voltage of the HCG mode corresponding to the first photosensitive unit, the switching control circuit 223 can be controlled to select the second quantization circuit 222. For example, referring to FIG. 12 , the switching control circuit 223 can output a pre-judgment voltage (e.g., a reset voltage V HR1 and signal voltage V HS1 ), the mode selection circuit 210 and the comparison signal V RAMP The second quantization circuit 222 is connected to the second quantization circuit 222, and the second quantization circuit 222 receives the pre-determined voltage (for example, the reset voltage V HR1 and signal voltage V HS1 ) and the comparison signal V RAMP , and the comparison signal V RAMP is a ramp signal, which is used to determine the pre-judgment voltage (for example, the reset voltage V HR1 and signal voltage V HS1 ) is quantized. For example, the analog quantization circuit 220 receives a pre-judgment voltage (eg, a reset voltage V HR1 and signal voltage V HS1 ), the slope of the corresponding ramp signal can be set to the second slope.

[0132] Exemplarily, the second quantization circuit 222 includes a third comparator 2221, a third counter 2222, and a fourth memory 2223, wherein the first input terminal and the second input terminal of the third comparator 2221 are connected to the switching control circuit 223. For example, the first input terminal of the third comparator 2221 is connected to the third terminal of the first switching switch KC1, and the second input terminal of the third comparator 2221 is connected to the third terminal of the second switching switch KC2. The output terminal of the third comparator 2221 is connected to the third counter 2222. Then, the third comparator 2221 can receive the voltage on the readout line VSL through the first input terminal and receive the comparison signal V through the second input terminal. RAMP , the comparison signal V RAMP Set to a ramp signal, the third comparator 2221 compares the voltage received at its first input terminal with the ramp signal and outputs a comparison result. The third counter 2222 can generate a count value related to time. The fourth memory 2223 can store the count value in the third counter 2222 based on the comparison result output by the third comparator 2221. The count value stored in the fourth memory 2223 is a digital quantization value. In addition, the fourth memory 2223 is also connected to the digital comparison circuit. It is understandable that the first input terminal of the third comparator 2221 is a negative input terminal, and the second input terminal is a positive input terminal. In addition, in Figure 12, "-" represents the negative input terminal and "+" represents the positive input terminal.

[0133] In the embodiment of the present application, the first slope may be the same as the second slope. Based on this, a ramp signal with the same slope may be generated by a ramp generator to serve as the comparison signal V RAMP Just enter it.

[0134] In the embodiment of the present application, the second quantization circuit 222 generates a digital quantization value D HS1 、D LS1 or difference D HS1 -D LS1 After that, the digital quantization value D HS1 、D LS1 or difference D HS1 -D LS1 Output to digital comparison circuit 225. Digital comparison circuit 225 can respond to the digital quantization value D HS1 、D LS1 or difference D HS1 -D LS1 Get the target digital quantization difference D HCG1 , thereby quantizing the difference D according to the target number HCG1 , digital voltage threshold k and digital voltage threshold D REF For example, the digital comparison circuit 225 responds to the relationship between D HCG1 *k>D REF, generates a feedback signal with a first level, and feeds the feedback signal back to the mode selection circuit 210. The digital comparison circuit 225 responds to D HCG1 *k <D REF , generating a feedback signal with a second level, and feeding the feedback signal back to the mode selection circuit 210. In some examples, the digital comparison circuit 225 may include a digital comparator, then D HCG1 Input digital comparator and D REF / k input digital comparator, so that the digital comparator will HCG1 With D REF / k for comparison and outputting a feedback signal. In some other examples, the digital comparison circuit 225 may include an amplifier and a digital comparator, D HCG1 Input amplifier, the amplifier will D HCG1 Convert to D HCG1 *k, D HCG1 *k input to the digital comparator, and D REF It also inputs the digital comparator, so that the digital comparator will convert D HCG1 *k and D REF Make comparison and output feedback signal.

[0135] The quantization selection circuit 224 can be used to select the first quantization circuit 221 and the second quantization circuit 222. For example, if the quantization selection circuit 224 selects the first quantization circuit 221, the first quantization circuit 221 can output the target digital quantization value of the first mode corresponding to the second photosensitive unit, the target digital quantization value of the second mode corresponding to the second photosensitive unit, or the target digital quantization value of the first mode corresponding to the first photosensitive unit to the data transmitter 400, and then output it to the image signal processor 300 via the data transmitter 400 for HDR image reconstruction. If the quantization selection circuit 224 selects the second quantization circuit 222, the second quantization circuit 222 can output the target digital quantization value of the second mode corresponding to the first photosensitive unit to the data transmitter 400, and then output it to the image signal processor 300 via the data transmitter 400 for HDR image reconstruction. In some examples, the quantization selection circuit 224 may include a third multiplexer U3, the control end of the third multiplexer U3 is used to receive a third selection control signal, the first input end of the third multiplexer U3 is connected to the third memory 2213 in the first quantization circuit 221, the second input end of the third multiplexer U3 is connected to the fourth memory 2223 in the second quantization circuit 222, and the output end of the third multiplexer U3 is connected to the data transmitter 400.

[0136] Below, taking the structure of the reading circuit shown in Figure 12 as an example, and taking PD1 and PD4 as equivalent to the first photosensitive unit, and making the first photosensitive unit perform short exposure, and PD2 and PD3 as equivalent to the second photosensitive unit, and making the first photosensitive unit perform long exposure as an example, combined with the signal timing diagram, the working process of the reading circuit in the image sensor provided in the embodiment of the present application is specifically described.

[0137] FIG13a is another signal timing diagram of the read circuit provided in the LCG mode according to an embodiment of the present application, wherein vsl represents the signal on the readout line VSL, V5 represents the signal output by the digital comparison circuit 225, V1 represents the signal at the output end of the first inverter D1, V2 represents the signal at the output end of the second inverter D2, V3 represents the signal at the output end of the second multiplexer U2, and Φ IN represents the signal at the output of the first multiplexer U1, and DF represents the feedback signal stored in the first memory 2131. LR1 , signal voltage V LS1 , reset voltage V LR2 , signal voltage V LS2 , or reset voltage V HR2 , signal voltage V HS2 When the quantization reset voltage V HR1 and signal voltage V HS1 When , the switching control signal controls the first switch KC1 and the second switch KC2 to connect the readout line VSL and the comparison signal to the second quantization circuit 222 .

[0138] At time t1, that is, before quantization begins, the first selection control signal U1_Sel is set to a low level to control the first multiplexer U1 to select V4. Among them, V4 is always at a high level to make Φ IN is also at a high level, controlling the first switch K1 to be turned on.

[0139] At time t2, the pixel outputs a reset voltage V to the readout line VSL. LR1 , reset voltage V LR1 The first quantization circuit 221 is inputted through the first switch K1 for quantization to obtain a reset voltage V LR1 The digital quantization value D LR1 , and D LR1 Stored in the third memory 2213.

[0140] At time t3, the pixel outputs a reset voltage V to the readout line VSL. HR1 , reset voltage V HR1The first switch K1 is turned on and input to the second quantization circuit 222 for quantization to obtain a reset voltage V HR1 The digital quantization value D HR1 , and D HR1 Stored in the fourth memory 2223.

[0141] At time t4, the pixel outputs a signal voltage V to the readout line VSL. HS1 , signal voltage V HS1 The first switch K1 is turned on and input to the second quantization circuit 222 for quantization, and based on the reset voltage V HR1 The digital quantization value D HR1 , and get the difference D HS1 -D HR1 , and the difference D HS1 -D HR1 Stored in the fourth memory 2223. For example, the second counter 2212 in the embodiment of the present application adopts an Up / Down counter, and waits for the signal voltage V HS1 After quantization is completed, the correlated double sampling (CDS) is completed and the difference D is obtained. HS1 -D HR1 , and D HCG1 =D HS1 -D HR1 , D HS1 >D HR1 .

[0142] At time t5, the third multiplexer U3 selects the fourth memory 2223 in response to the control of U3_Sel, and switches D HCG1 is read out to the data transmitter 400 and sent to the image signal processor 300 via the data transmitter 400. HCG1 It is also sent to the digital comparison circuit 225 for D HCG1 *k and D REF Compare and judge the incident light intensity. HCG1 *k>DREF, indicating that the incident light intensity is relatively large, the second photosensitive unit should adopt LCG mode, the digital comparison circuit 225 output voltage V5 is high, then V1 is low, V2 is high, and the high-level feedback signal is stored in the first memory 2131. In addition, D REF It can also have two values, namely D REF1 and D REF2 , if D HCG1 *k>DREF1, indicating that the incident light intensity is relatively high, the second photosensitive unit should adopt LCG mode, the output voltage V5 of the digital comparison circuit 225 is high, and the target digital quantization value of the first photosensitive unit corresponding to the LCG mode or HCG mode is used when synthesizing the HDR image. REF2 >D HCG1*k>D REF1 , indicating that the incident light intensity is medium. When synthesizing the HDR image, the target digital quantization value of the second photosensitive unit corresponding to the LCG mode is used, and the output voltage V5 of the digital comparator is still high.

[0143] At time t6, Φ1 controls the second switch K2 to be turned off, and Φ2 controls the third switch K3 to be turned on, and V1 and V2 are latched.

[0144] At time t7, the comparison signal is set to a ramp signal with a first slope, and the pixel outputs a signal voltage V to the readout line VSL. LS1 , signal voltage V LS1 The first quantization circuit 221 is inputted through the turned-on first switch K1 for quantization, and the reset voltage V LR1 The digital quantization value D LR1 , and get the difference D LS1 -D LR1 , and the difference D LS1 -D LR1 Stored in the third memory 2213. For example, the third counter 2222 in the embodiment of the present application adopts an Up / Down counter, and waits for the signal voltage V LS1 After quantization is completed, the correlated double sampling (CDS) is completed and the difference D is obtained. LS1 -D LR1 , and D LS1 >D LR1 .

[0145] At time t8, the third multiplexer U3 selects the third memory 2213 in response to the control of U3_Sel, and stores the difference D LS1 -D LR1 The data is read out to the data transmitter 400 and sent to the image signal processor 300 via the data transmitter 400 .

[0146] At time t9, the voltage corresponding to the first photosensitive unit is quantized, and the voltage corresponding to the second photosensitive unit is quantized. U1_Sel switches from low level to high level, and the first multiplexer U1 selects V2 in response to the control of U1_Sel, so that V3 and ΦIN are both high level.

[0147] At time t10, the pixel outputs a reset voltage V to the readout line VSL. LR2 , and V3 and ΦIN are both high level, the first switch K1 is controlled to be turned on, and the reset voltage V LR2 The voltage is stored in the storage capacitor CG via the turned-on first switch K1.

[0148] At time t11, the pixel outputs a reset voltage V to the readout line VSL. HR2, the first multiplexer U1 responds to the control of U1_Sel and selects V1, then V3 and ΦIN are both low level, the first switch K1 is turned off, and the reset voltage V HR2 The reset voltage V LR2 .

[0149] At time t12, the comparison signal V RAMP The ramp signal with the first slope is set to be input into the first quantization circuit 221, and the reset voltage V LR2 It is also input to the first quantization circuit 221, and the reset voltage V LR2 Quantize and get the reset voltage V LR2 The digital quantization value D LR2 , and D LR2 Stored in the third memory 2213.

[0150] At time t13, the pixel outputs a signal voltage V to the readout line VSL. HS2 , the first multiplexer U1 responds to the control of U1_Sel and selects V1, then V3 and ΦIN are both low level, the first switch K1 is turned off, and the signal voltage V HS2 No storage is performed on the storage capacitor CG.

[0151] At time t14, the pixel outputs a signal voltage V to the readout line VSL. LS2 The first multiplexer U1 responds to the control of U1_Sel and selects V2, V3 and ΦIN to be high level, controlling the first switch K1 to be turned on, and the signal voltage V LS2 The voltage is stored in the storage capacitor CG via the turned-on first switch K1.

[0152] At t15, the comparison signal V RAMP The ramp signal with the first slope is set to be input into the first quantization circuit 221, and the signal voltage V LS2 It is also input into the first quantization circuit 221, and the signal voltage V LS2 quantized and based on the reset voltage V LR2 The digital quantization value D LR2 , and get the difference D LS2 -D LR2 , and the difference D LS2 -D LR2 Stored in the third memory 2213. For example, the second counter 2212 in the embodiment of the present application adopts an Up / Down counter, and waits for the signal voltage V LS2 After quantization is completed, the correlated double sampling (CDS) is completed and the difference D is obtained. LS2 -D LR2 , and D LS2 >D LR2 .

[0153] After that, the voltage corresponding to the second photosensitive unit is quantized and the difference D LS2 -D LR2 The data is read out from the third memory 2213 , and the feedback signal stored in the first memory 2131 is also read out together, and output to the image signal processor 300 via the data transmitter 400 for HDR image reconstruction.

[0154] FIG13 b is another signal timing diagram of the read circuit provided in the HCG mode according to an embodiment of the present application, wherein vsl represents the signal on the readout line VSL, V5 represents the signal output by the digital comparison circuit 225, V1 represents the signal at the output end of the first inverter D1, V2 represents the signal at the output end of the second inverter D2, V3 represents the signal at the output end of the second multiplexer U2, and Φ IN represents the signal at the output of the first multiplexer U1, and DF represents the feedback signal stored in the first memory 2131. The operation process of the first switch KC1 and the second switch KC2 is substantially the same as that of FIG13a, and will not be described in detail here.

[0155] The working process from time t1 to time t4 is substantially the same as the working process from time t1 to time t4 shown in FIG13 a , and will not be described in detail here.

[0156] At time t5, the third multiplexer U3 selects the fourth memory 2223 in response to the control of U3_Sel, and switches D HCG1 is read out to the data transmitter 400 and sent to the image signal processor 300 via the data transmitter 400. HCG1 It is also sent to the digital comparison circuit 225 for D HCG1 *k and D REF Compare and judge the incident light intensity. HCG1 *k <D REF , indicating that the incident light intensity is relatively small, the second photosensitive unit should adopt the HCG mode, the digital comparison circuit 225 outputs a voltage V5 of low level, then V1 is high level, V2 is low level, and a low level feedback signal is stored in the first memory 2131.

[0157] The working process from time t6 to time t9 is basically the same as the working process from time t6 to time t9 shown in FIG13 a , and will not be described in detail here.

[0158] At time t10, the pixel outputs a reset voltage V to the readout line VSL. LR2 , and V3 and ΦIN are both low, the first switch K1 is controlled to be turned off, and the reset voltage V LR2 No storage is performed on the storage capacitor CG.

[0159] At time t11, the pixel outputs a reset voltage V to the readout line VSL. HR2 , the first multiplexer U1 responds to the control of U1_Sel and selects V1, then V3 and ΦIN are both high level, the first switch K1 is turned on, and the reset voltage V HR2 Stored in storage capacitor CG.

[0160] At time t12, the comparison signal V RAMP The ramp signal with the second slope is set to be input into the first quantization circuit 221, and the reset voltage V HR2 It is also input to the first quantization circuit 221, and the reset voltage V HR2 Quantize and get the reset voltage V HR2 The digital quantization value D HR2 , and D HR2 Stored in the third memory 2213.

[0161] At time t13, the pixel outputs a signal voltage V to the readout line VSL. HS2 , the first multiplexer U1 responds to the control of U1_Sel and selects V1, then V3 and ΦIN are both high level, the first switch K1 is turned on, and the signal voltage V HS2 Input storage capacitor CG.

[0162] At time t14, the pixel outputs a signal voltage V to the readout line VSL. LS2 , the first multiplexer U1 responds to the control of U1_Sel and selects V2, V3 and ΦIN are all low level, controlling the first switch K1 to turn off, and the signal voltage V LS2 The storage capacitor CG will not be stored, and the storage capacitor CG will still store the signal voltage V HS2 .

[0163] At t15, the comparison signal V RAMP The ramp signal with the second slope is input into the first quantization circuit 221. The signal voltage V HS2 It is also input into the first quantization circuit 221, and the signal voltage V HS2 quantized and based on the reset voltage V HR2 The digital quantization value D HR2 , and get the difference D HS2 -D HR2 , and the difference D HS2 -D HR2 , stored in the third memory 2213. For example, the second counter 2212 in the embodiment of the present application adopts an Up / Down counter, and waits for the signal voltage V HS2 After quantization is completed, the correlated double sampling (CDS) is completed and the difference D is obtained. HS2 -D HR2 , and D HS2>D HR2 .

[0164] After that, the voltage corresponding to the second photosensitive unit is quantized and the difference D after CDS is obtained. HS2 -D HR2 The data is read out from the third memory 2213 , and the feedback signal stored in the first memory 2131 is also read out together, and output to the image signal processor 300 via the data transmitter 400 for HDR image reconstruction.

[0165] Based on the working process corresponding to Figure 13a and Figure 13b, the quantization process of the reset voltage and signal voltage corresponding to the first mode and the second mode of the first photosensitive unit and the second photosensitive unit in a pixel is completed, and a total of 3 groups of quantization processes are performed (each group of quantization processes includes a reset voltage quantization process and a signal voltage quantization process). Compared with the 4 groups of quantization processes in the related technology, the number of quantization times can be reduced, the frame period can be reduced, and the frame rate can be improved.

[0166] On the basis of the above embodiment, it is also possible to select ramp signals with different slopes to quantify the voltage output by the pixel, so as to further enhance the HDR. Based on this, the first slope is different from the second slope, for example, the first slope is smaller than the second slope, so as to select ramp signals with different slopes to quantify the voltage output by the pixel, so as to further enhance the HDR. For example, referring to FIG14, FIG14 is another circuit structure diagram of the reading circuit provided in the embodiment of the present application, each reading circuit further includes a slope selection circuit 230, and the slope selection circuit 230 is connected to the analog quantization circuit 220. The slope selection circuit 230 can receive multiple ramp signals (for example, V XAMP1 、V XAMP2 ), and the slope selection circuit 230 receives the reset voltage V in response to the analog quantization circuit 220. LR1 , signal voltage V LS1 , reset voltage V LR2 And the signal voltage V LS2 , the ramp signal with the first slope (eg V XAMP1 ) is output to the analog quantization circuit 220. Alternatively, the slope selection circuit 230 receives the reset voltage V in response to the analog quantization circuit 220. HR1 , signal voltage V HS1 , reset voltage V HR2 And the signal voltage V HS2 , the ramp signal with the second slope (eg V XAMP2 ) is output to the analog quantization circuit 220. Based on this, the quantization accuracy can be improved, thereby improving the accuracy of the HDR image.

[0167] For example, the ramp generator generates a corresponding ramp signal according to the input digital value (Digital Number, DN), and inputs the ramp signal into the slope selection circuit 230. For example, referring to FIG15, FIG15 is a signal timing diagram of the ramp signal provided by the embodiment of the present application, and the DN value increases from the minimum value DN to the maximum value DN. MIN (ie 0) changes to the maximum value of DN MAX (For example, DN MAX =1023, 12-bit quantization DN MAX =4095), therefore, the starting voltage of each ramp signal output by the ramp generator is the same, and the ending voltage is different. The ramp signal output by the ramp generator includes: the first ramp signal V XAMP1 and the second ramp signal V XAMP2 For example, the first ramp signal V XAMP1 The slope of the second ramp signal V XAMP2 The slope of the first ramp signal V XAMP1 and the second ramp signal V XAMP2 If the starting voltages are the same but the ending voltages are different, and both the first slope and the second slope are negative, then the first slope is smaller than the second slope. It is understood that the slope selection circuit 230 may receive three, four, or more ramp signals, without limitation. Furthermore, the slope selection circuit 230 selects one of these ramp signals as a comparison signal and sends it to the analog quantization circuit 220.

[0168] FIG16 is a schematic diagram of a circuit structure of a slope selection circuit provided in an embodiment of the present application. Referring to FIG16 , the slope selection circuit 230 may include: a fourth multiplexer U4, a fifth multiplexer U5, and a third inverter D3, wherein the control end of the fourth multiplexer U4 is connected to the output end of the fifth multiplexer U5, and the input end of the fourth multiplexer U4 receives the multiple ramp signals (e.g., V XAMP1 、V XAMP2 ), the output end of the fourth multiplexer U4 is connected to the analog quantization circuit 220, the control end of the fifth multiplexer U5 is used to receive the fifth selection control signal U5_sel, the first input end of the fifth multiplexer U5 is used to receive the second input signal V6, the third input end of the fifth multiplexer U5 is used to receive the third input signal V7, the second input end of the fifth multiplexer U5 is connected to the output end of the third inverter D3, and the input end of the third inverter D3 is connected to the output end of the second inverter D2 in the mode selection circuit 210.

[0169] The following describes the working process of the slope selection circuit 230 provided in the embodiment of the present application by taking the structures shown in Figures 14 and 16 as an example, combined with the signal timing diagrams shown in Figures 17a and 17b. Since Figure 14 only adds the slope selection circuit 230 compared to Figure 12, and Figure 14 adds signals V9 and V8 on the basis of Figure 13a, and Figure 14 adds signals V9 and V8 on the basis of Figure 13b, only the working process of the slope selection circuit 230 is described below. The working processes of the mode selection circuit 210 and the analog quantization circuit 220 can refer to the above description and are not repeated here.

[0170] 17a and 17b, the second input signal V6 is always at a high level, the third input signal V7 is always at a low level, V9 is the voltage at the output terminal of the third inverter D3, and V8 is the voltage at the output terminal of the fifth multiplexer U5. Moreover, from time t1 to time t3', the fifth multiplexer U5 selects V7 in response to the control of the fifth selection control signal, and V8 is at a low level, controlling the fourth multiplexer U4 to select the first ramp signal, so that the reset voltage V LR1 The first ramp signal can be used for quantization. From time t3' to time t5, the fifth multiplexer U5 responds to the control of U5_sel and selects V6, then V8 is high, and controls the fourth multiplexer U4 to select the second ramp signal, so that the reset voltage V HR1 and signal voltage V HS1 The second ramp signal can be used for quantization. From time t5 to time t10, the fifth multiplexer U5 responds to the control of U5_sel and selects V7, then V8 is low, and controls the fourth multiplexer U4 to select the first ramp signal, so that the signal voltage V LS1 The first ramp signal can be used for quantization. From time t10 to time t16, the fifth multiplexer U5 responds to the control of U5_sel and selects V9. Since V9 is the inverse voltage of V2, that is, when V2 is high, V9 is low; conversely, when V2 is low, V9 is high. Based on this, if V2 is high, the second photosensitive unit should adopt the LCG mode, V9 and V8 are both low, and the fourth multiplexer U4 can be controlled to select the first ramp signal to set the comparison signal to the first ramp signal, so that the reset voltage V LR2 and signal voltage V LS2 The first ramp signal can be used for quantization. If V2 is low, the second photosensitive unit should adopt HCG mode, V9 and V8 are both high, which can control the fourth multiplexer U4 to select the second ramp signal to set the comparison signal to the second ramp signal, so that the reset voltage V HR2 and signal voltage V HS2 A second ramp signal can be used for quantization.

[0171] It is worth mentioning that, based on the same concept, the read circuit shown in FIG10 can also be provided with a slope selection circuit to select ramp signals with different slopes. Moreover, in FIG11a, FIG11b, FIG13a, FIG13b, FIG17a and FIG17b, since some signals have no effect on the working process of the circuit in some time periods, it is not divided into whether the signals are high or low in these time periods. Therefore, in FIG11a, FIG11b, FIG13a, FIG13b, FIG17a and FIG17b, the slope selection circuit is used. To express.

[0172] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. An image sensor, characterized in that: include: pixel array and readout circuitry; The pixel array includes: a pixel and a readout line connected to the pixel, the pixel including a first photosensitive unit and a second photosensitive unit, the pixel being configured to output a pre-judgment voltage corresponding to the first photosensitive unit, and a reset voltage and a signal voltage of a first mode and a second mode corresponding to the second photosensitive unit to the readout line; The readout circuit is connected to the readout line in a one-to-one correspondence, and the readout circuit includes: a mode selection circuit and an analog quantization circuit, and the analog quantization circuit is connected to the readout line through the mode selection circuit; The mode selection circuit is used to output the pre-judgment voltage to the analog quantization circuit, so that the analog quantization circuit generates a feedback signal, and the analog quantization circuit feeds the feedback signal back to the mode selection circuit; The mode selection circuit is also used to output the reset voltage of the first mode or the second mode corresponding to the second photosensitive unit and the signal voltage to the analog quantization circuit in response to the feedback signal, so that the analog quantization circuit outputs the target digital quantization value of the first mode or the second mode corresponding to the second photosensitive unit; wherein the target digital quantization value includes: the digital quantization value of the reset voltage and the digital quantization value of the signal voltage, or the difference between the digital quantization value of the reset voltage and the digital quantization value of the signal voltage.

2. The image sensor according to claim 1, wherein The mode selection circuit is further configured to: In response to the level of the feedback signal being the first level, outputting the reset voltage of the first mode and the signal voltage corresponding to the second photosensitive unit to the analog quantization circuit; In response to the level of the feedback signal being the second level, the reset voltage of the second mode corresponding to the second photosensitive unit and the signal voltage are output to the analog quantization circuit.

3. The image sensor according to claim 2, wherein: The pre-judgment voltage includes a signal voltage of a second mode corresponding to the first photosensitive unit; The analog quantization circuit is further configured to: In response to the signal voltage of the second mode corresponding to the first photosensitive unit being less than the reference voltage, feeding back a feedback signal having a first level to the mode selection circuit; In response to the signal voltage of the second mode corresponding to the first photosensitive unit being greater than the reference voltage, a feedback signal with a second level is fed back to the mode selection circuit.

4. The image sensor according to claim 2, wherein The pre-judgment voltage includes a reset voltage and a signal voltage of the second mode corresponding to the first photosensitive unit; The analog quantization circuit is further configured to: The feedback signal is output according to the reset voltage and signal voltage of the second mode corresponding to the first photosensitive unit and the ramp signal.

5. The image sensor according to claim 4, wherein: The analog quantization circuit is further configured to: In response to a product of a target digital quantization difference and an exposure time ratio being greater than a digital voltage threshold, feeding back a feedback signal having a first level to the mode selection circuit; the target digital quantization difference being a difference between a reset voltage and a digital quantization value of a signal voltage in a second mode corresponding to the first photosensitive unit; In response to a product of the target digital quantization difference and the exposure time ratio being smaller than the digital voltage threshold, a feedback signal having a second level is fed back to the mode selection circuit.

6. The image sensor according to claim 4 or 5, wherein: The analog quantization circuit is further used for: According to the reset voltage and signal voltage of the second mode corresponding to the first photosensitive unit and the ramp signal, a target digital quantization value of the second mode corresponding to the first photosensitive unit is output.

7. The image sensor according to claim 6, wherein: The pixel is further configured to output a reset voltage and a signal voltage of a first mode corresponding to the first photosensitive unit to the readout line; The mode selection circuit is further configured to output a reset voltage and a signal voltage of the first mode corresponding to the first photosensitive unit to the analog quantization circuit; The analog quantization circuit is further configured to output a target digital quantization value of the first mode corresponding to the first photosensitive unit according to a reset voltage and a signal voltage of the first mode corresponding to the first photosensitive unit and a ramp signal.

8. The image sensor according to any one of claims 1 to 7, wherein: The mode selection circuit includes: a first control circuit, a second control circuit and a third control circuit; The first control circuit is connected to the readout line and the analog quantization circuit respectively, and is used to control the readout line and the analog quantization circuit. Quantify the conduction or disconnection between circuits; The second control circuit is connected to the third control circuit and the analog quantization circuit respectively, and is used to: output the feedback signal to the third control circuit; The third control circuit is also connected to the first control circuit and is used to: in response to the voltage corresponding to the first photosensitive unit transmitted by the readout line, control the first control circuit to connect the readout line and the analog quantization circuit; and, in response to the level of the feedback signal being a first level and the readout line transmitting the reset voltage and the signal voltage of the first mode of the pixel based on the output of the second photosensitive unit, control the first control circuit to connect the readout line and the analog quantization circuit; and, in response to the level of the feedback signal being a second level and the readout line transmitting the reset voltage and the signal voltage of the second mode of the pixel based on the output of the second photosensitive unit, control the first control circuit to connect the readout line and the analog quantization circuit.

9. The image sensor according to claim 8, wherein The first control circuit includes: a first switch and a storage capacitor; The control end of the first switch is connected to the third control circuit, the first end of the first switch is connected to the readout line, and the second end of the first switch is connected to the analog quantization circuit; A first end of the storage capacitor is connected to a second end of the first switch, and a second end of the storage capacitor is grounded.

10. The image sensor according to claim 8 or 9, wherein: The second control circuit includes: a second switch, a control end of the second switch is used to receive a switch control signal, a first end of the second switch is connected to the analog quantization circuit, and a second end of the second switch is connected to the third control circuit.

11. The image sensor according to any one of claims 8 to 10, wherein: The third control circuit includes: a first multiplexer, a second multiplexer, a third switch, a first inverter, a second inverter and a first memory; The control terminal of the first multiplexer is used to receive a first selection control signal, the first input terminal of the first multiplexer is used to receive a first input signal, the second input terminal of the first multiplexer is connected to the output terminal of the second multiplexer, and the output terminal of the first multiplexer is connected to the first control circuit; The input end of the first inverter is connected to the second control circuit and the first end of the third switch respectively, and the output end of the first inverter is connected to the input end of the second inverter and the first input end of the second multiplexer respectively; The output terminal of the second inverter is connected to the second terminal of the third switch and the second input terminal of the second multiplexer respectively; The control terminal of the third switch is used to receive a latch control signal; The control terminal of the second multiplexer is used to receive a second selection control signal; The first memory is connected to the output end of the second inverter, and is configured to store the feedback signal and output the feedback signal.

12. The image sensor according to any one of claims 1 to 11, wherein: The analog quantization circuit includes: a first comparator, a first counter and a second memory; The first input terminal of the first comparator is connected to the mode selection circuit, the second input terminal of the first comparator is used to receive a comparison signal, and the output terminal of the first comparator is connected to the first counter and the mode selection circuit; the first comparator is configured to output the feedback signal in response to the pre-judgment voltage being input to the first input terminal and the voltage of the comparison signal being a reference voltage, and to output a comparison result in response to the voltage being input to the first input terminal and the comparison signal being a ramp signal; The first counter is used to: generate a count value related to time; The second memory is used to store the count value in the first counter based on the comparison result output by the first comparator, and the count value stored in the second memory is a digital quantized value.

13. The image sensor according to any one of claims 4 to 11, wherein: The analog quantization circuit includes: a switching control circuit, a first quantization circuit, a second quantization circuit, a quantization gating circuit, and a digital comparison circuit; The first quantization circuit and the second quantization circuit are respectively connected to the mode selection circuit via the switching control circuit, and the first quantization circuit and the second quantization circuit respectively receive a comparison signal via the switching control circuit, wherein the switching control circuit is configured to: in response to the mode selection circuit outputting a voltage corresponding to the second photosensitive unit, connect the mode selection circuit and the comparison signal to the first quantization circuit; and in response to the mode selection circuit outputting the pre-judgment voltage, connect the mode selection circuit and the comparison signal to the second quantization circuit; The first quantization circuit is connected to the quantization gating circuit and is configured to: generate a target digital quantization value of the first mode or the second mode corresponding to the second photosensitive unit, and output the stored target digital quantization value in response to control of the quantization gating circuit; The second quantization circuit is connected to the quantization gating circuit and the digital comparison circuit respectively, and is used to: generate a target digital quantization value of the second mode corresponding to the first photosensitive unit, and output the stored target digital quantization value in response to the control of the quantization gating circuit; The digital comparison circuit is connected to the mode selection circuit and is used to respond to the target of the second mode corresponding to the first photosensitive unit. The digital quantization value and the digital voltage threshold are used to output the feedback signal.

14. The image sensor according to claim 13, wherein: The switching control circuit includes: a first switching switch and a second switching switch; The control end of the first switch is used to receive a switching control signal, the first end of the first switch is connected to the mode selection circuit, the second end of the first switch is connected to the first quantization circuit, and the third end of the first switch is connected to the second quantization circuit; The control end of the second switching switch is used to receive the switching control signal, the first end of the second switching switch is used to receive the comparison signal, the second end of the second switching switch is connected to the first quantization circuit, and the third end of the second switching switch is connected to the second quantization circuit.

15. The image sensor according to any one of claims 1 to 14, wherein: The analog quantization circuit is further configured to: receiving a ramp signal and a reset voltage and a signal voltage of the first mode corresponding to the second photosensitive unit, and outputting a target digital quantization value of the first mode corresponding to the second photosensitive unit, wherein the slope of the ramp signal is a first slope; receiving a ramp signal and a reset voltage and a signal voltage of the second mode corresponding to the second photosensitive unit, and outputting a target digital quantization value of the second mode corresponding to the second photosensitive unit, wherein the slope of the ramp signal is a second slope; The first slope is less than or equal to the second slope.

16. The image sensor according to claim 15, wherein: When the analog quantization circuit receives the reset voltage and signal voltage of the first mode corresponding to the first photosensitive unit, the slope of the corresponding ramp signal is the first slope; When the analog quantization circuit receives the reset voltage and signal voltage of the second mode corresponding to the first photosensitive unit, the slope of the corresponding ramp signal is the second slope.

17. The image sensor according to claim 16, wherein: The reading circuit further includes: a slope selection circuit, wherein the slope selection circuit is connected to the analog quantization circuit; The slope selection circuit is used to: receiving a plurality of ramp signals having different slopes; In response to the analog quantization circuit receiving the reset voltage and the signal voltage of the first mode, outputting a ramp signal having the first slope among the plurality of ramp signals to the analog quantization circuit; In response to the analog quantization circuit receiving the reset voltage and the signal voltage of the second pattern, the ramp signal having the second slope among the plurality of ramp signals is output to the analog quantization circuit.

18. An electronic device, characterized in that: comprising a processor and an image sensor according to any one of claims 1 to 17, The image sensor is connected to the processor and is used to output a feedback signal and a digital quantization value of each pixel to the processor; The processor is used to generate an image according to the feedback signal and the digital quantization value of each pixel.

Images