Vertical-cavity surface-emitting laser, laser array and light-emitting device

Abstract

The present disclosure relates to a vertical-cavity surface-emitting laser (VCSEL), a laser array and a light-emitting device. The VCSEL comprises an N-type substrate (11), an upper distributed Bragg reflector, and an N-type buffer layer (12), a first tunnel junction (13), a P-type distributed Bragg reflector (14), an active layer (15), a second tunnel junction (17), a P-type metal contact layer (18) and a cathode electrode (19), which are sequentially stacked in a direction perpendicular to the substrate (11), wherein the first tunnel junction (13) is used for inverting N-type carriers in the N-type buffer layer (12) to P-type carriers; the second tunnel junction (17) is used for inverting carriers in the upper distributed Bragg reflector to carriers of an opposite conductivity type; and the surface of the N-type substrate (11) that faces away from the N-type buffer layer (12) comprises an anode electrode. The present disclosure can at least improve the driving frequency and speed of the VCSEL and also reduce the size of a driving system.

Description

Vertical cavity surface emitting lasers, laser arrays and light-emitting devices

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure claims priority to U.S. patent application No. 63 / 626,171, filed with the U.S. Patent Office on January 29, 2024, with the invention title “A VCSEL structure containing two tunnel junctions,” and Chinese patent application No. 202410929560.9, filed with the China Patent Office on July 11, 2024, with the invention title “Vertical Cavity Surface Emitting Laser, Laser Array and Light-Emitting Device,” the entire contents of which are incorporated by reference into the present disclosure. Technical Field

[0003] The present disclosure relates to the field of semiconductor lasers, and in particular to a vertical cavity surface emitting laser, a laser array, and a light-emitting device. Background Art

[0004] VCSEL (Vertical-Cavity Surface-Emitting Laser) is the full name of vertical cavity surface emitting laser, which is a type of semiconductor laser. Its basic structure is mainly composed of an active layer and a DBR (Distributed Bragg Reflector-DBR) reflector with optical feedback function.

[0005] In related VCSELs, the cathode used to apply a low-potential voltage is generally arranged on the back of the substrate, and the anode used to apply a high-potential voltage is generally arranged above the front of the substrate. This makes it difficult to adopt a common anode driving method, resulting in limited reduction in the size of the driving system, and it is difficult to adopt N-type transistors with faster response speeds, which limits the application of VCSELs in high-frequency and high-speed driving applications. Summary of the Invention

[0006] According to some embodiments, the present disclosure provides, on one hand, a vertical cavity surface emitting laser, comprising an N-type substrate, an upper distributed Bragg reflector, and an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, a second tunnel junction, a P-type metal contact layer, and a cathode electrode stacked in sequence along a direction perpendicular to the substrate; the first tunnel junction is used to invert carriers in the N-type buffer layer into carriers of the opposite conductivity type; the second tunnel junction is used to invert carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type; the upper distributed Bragg reflector is located between the active layer and the P-type metal contact layer, and the upper distributed Bragg reflector is associated with the second tunnel junction; wherein, the surface of the N-type substrate facing away from the N-type buffer layer includes an anode electrode.

[0007] According to some embodiments, the active layer includes a target stacked structure; the target stacked structure includes a P-type semiconductor layer, a quantum well layer and an N-type semiconductor layer stacked in sequence in a direction perpendicular to the substrate; the P-type semiconductor layer is adjacent to a P-type distributed Bragg reflector; and the quantum well layer includes at least one quantum well.

[0008] According to some embodiments, the central cross-section of the quantum well region of the quantum well layer is located within the antinode interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the antinode is z, the antinode interval is [z-λ / 8, z+λ / 8], and λ is the wavelength of the standing wave.

[0009] According to some embodiments, the active layer includes a plurality of target stacked structures stacked sequentially in a direction perpendicular to the substrate; adjacent target stacked structures are connected via interlayer tunnel junctions; and in adjacent target stacked structures, the N-type semiconductor layer of one target stacked structure is adjacent to the P-type semiconductor layer of another target stacked structure.

[0010] According to some embodiments, the central cross-section of the interlayer tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the central cross-section is parallel to the substrate; the position of the node is p, and the node interval is [p-λ / 8, p+λ / 8], where λ is the wavelength of the standing wave.

[0011] According to some embodiments, the upper distributed Bragg reflector includes a P-type distributed Bragg reflective layer, and the P-type distributed Bragg reflective layer is located between the second tunnel junction and the P-type metal contact layer.

[0012] According to some embodiments, the upper distributed Bragg reflector includes an N-type distributed Bragg reflective layer, and the N-type distributed Bragg reflective layer is located between the active layer and the second tunnel junction.

[0013] According to some embodiments, the upper distributed Bragg reflector includes a sub-N-type distributed Bragg reflector layer and a sub-P-type distributed Bragg reflector layer. The sub-N-type distributed Bragg reflector layer is located between the active layer and the second tunnel junction; the sub-P-type distributed Bragg reflector layer is located between the second tunnel junction and the P-type metal contact layer.

[0014] According to some embodiments, the central cross section of the first tunnel junction is located within a node interval of the standing wave electric field of the vertical cavity surface emitting laser; the node position is p, the node interval is [p-λ / 8, p+λ / 8], and λ is the wavelength of the standing wave.

[0015] According to some embodiments, the present disclosure further provides a laser array on the other hand, comprising a plurality of vertical cavity surface emitting lasers as described in any of the aforementioned embodiments arranged in rows and columns; wherein the vertical cavity surface emitting lasers located in the same row are all connected to the corresponding row selection line; the vertical cavity surface emitting lasers located in the same column are all connected to the corresponding column selection line; the vertical cavity surface emitting lasers in different rows are respectively connected to different row selection lines; the vertical cavity surface emitting lasers in different columns are respectively connected to different column selection lines; by selecting a row selection line and a column selection line to select the vertical cavity surface emitting lasers connected to the selected row selection line and the selected column selection line, a common anode driving mode is realized, and an N-type transistor with a faster response speed is used to drive the light-emitting structure of the vertical cavity surface emitting laser, thereby reducing the volume of the driving system while improving the driving frequency and speed of the VCSEL.

[0016] According to some embodiments, a plurality of vertical cavity surface emitting lasers arranged in rows and columns share an anode electrode; wherein, among the plurality of vertical cavity surface emitting lasers sharing the anode electrode, cathode electrodes of any adjacent vertical cavity surface emitting lasers are insulated from each other.

[0017] According to some embodiments, an isolation structure is included between adjacent vertical cavity surface emitting lasers, and the isolation structure extends in a direction perpendicular to the substrate to the top surface of the P-type distributed Bragg reflector.

[0018] According to some embodiments, the present disclosure further provides a light emitting device, including:

[0019] A vertical cavity surface emitting laser as described in any one of the preceding embodiments.

[0020] According to some embodiments, the present disclosure further provides a light emitting device, including:

[0021] A laser array as described in any one of the preceding embodiments.

[0022] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0024] FIG1a is a schematic longitudinal cross-sectional view of a vertical cavity surface emitting laser provided in one embodiment of the present disclosure;

[0025] FIG1 b is a schematic longitudinal cross-sectional view of a vertical cavity surface emitting laser provided in another embodiment of the present disclosure;

[0026] FIG1c is a schematic longitudinal cross-sectional view of a vertical cavity surface emitting laser provided in another embodiment of the present disclosure;

[0027] FIG2 is a schematic top view of a laser array provided in one embodiment of the present disclosure;

[0028] FIG3 is a schematic longitudinal cross-sectional view of a laser array provided in another embodiment of the present disclosure, wherein FIG3 may be a schematic longitudinal cross-sectional view taken along the AA′ direction shown in FIG2 ;

[0029] FIG4 is a schematic flow chart showing a method for preparing a vertical cavity surface emitting laser provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. The terms used herein in the specification of this disclosure are for the purpose of describing specific embodiments only and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

[0036] The multi-layer structure described in the embodiment of the present disclosure can be formed layer by layer or formed as a whole; wherein two adjacent layer structures can be in contact or isolated from each other.

[0037] The vertical substrate described in the embodiment of the present disclosure may be a vertical substrate upper surface, and the parallel substrate may be a parallel substrate upper surface.

[0038] Please refer to Figures 1a to 3. It should be noted that the figures provided in this embodiment are merely schematic illustrations of the basic concept of the present disclosure. Although the figures only show components relevant to the present disclosure and are not drawn according to the number, shape, and size of components in actual implementation, the type, quantity, and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complex.

[0039] The basic structure of a VCSEL consists of an active layer and a DBR (Distributed Bragg Reflector) reflector with optical feedback. The active layer is sandwiched between two DBRs, forming a Fabry-Perot resonant cavity. The excitation source generates optical gain through spontaneous emission from the gain medium in the active layer. Light waves within the cavity reflect between the top and bottom DBRs, forming a stable standing wave. This wave is amplified through stimulated emission, ultimately generating laser light.

[0040] Typically, the upper reflector and lower reflector of a VCSEL are doped into P-type and N-type materials, respectively, to form a diode junction.

[0041] In the case of MOSFETs, N-channel transistors generally offer superior performance characteristics to P-channel transistors. For example, due to the higher mobility of electrons to holes, N-channel transistors have relatively high response speeds and lower resistance. For semiconductor transistors, NPN transistors generally offer superior performance characteristics to PNP transistors. Therefore, when driving VCSELs or VCSEL arrays, using N-channel or NPN transistors can help improve device performance.

[0042] 1a-1c , in some embodiments, a vertical cavity surface emitting laser is provided, comprising an N-type substrate 11, an upper distributed Bragg reflector (not shown), and an N-type buffer layer 12, a first tunnel junction 13, a P-type distributed Bragg reflector 14, an active layer 15, a second tunnel junction 17, a P-type metal contact layer 18, and a cathode electrode 19 stacked in sequence along a direction perpendicular to the substrate (e.g., the oz direction); the first tunnel junction 13 is used to invert N-type carriers in the N-type buffer layer 12 into P-type carriers; the second tunnel junction 17 is used to invert carriers in the upper distributed Bragg reflector into carriers of the opposite conductivity type; the upper distributed Bragg reflector is located between the active layer 15 and the P-type metal contact layer 18, and is associated with the second tunnel junction 17; wherein the surface of the N-type substrate 11 facing away from the N-type buffer layer 12 comprises an anode electrode (not shown).

[0043] As an example, referring again to FIG1a , the upper distributed Bragg reflector includes an N-type distributed Bragg reflector layer 16, which is located between the active layer 15 and the second tunnel junction 17. The second tunnel junction 17 can be used to invert N-type carriers in the N-type distributed Bragg reflector layer 16 into P-type carriers.

[0044] As an example, referring again to FIG. 1 b , the upper distributed Bragg reflector includes a P-type distributed Bragg reflector layer 16 m , which is located between a second tunnel junction 17 and a P-type metal contact layer 18 . The second tunnel junction 17 can be used to invert P-type carriers in the P-type distributed Bragg reflector layer 16 m into N-type carriers to match the conductivity type of the active layer 15 .

[0045] As an example, referring again to FIG1c , the upper distributed Bragg reflector includes a sub-N-type distributed Bragg reflector layer 161 and a sub-P-type distributed Bragg reflector layer 162. The sub-N-type distributed Bragg reflector layer 161 is located between the active layer 15 and the second tunnel junction 17; the sub-P-type distributed Bragg reflector layer 162 is located between the second tunnel junction 17 and the P-type metal contact layer 18. The second tunnel junction 17 can be used to invert N-type carriers in the sub-N-type distributed Bragg reflector layer 161 into P-type carriers.

[0046] As an example, please continue to refer to Figure 1a. In the direction away from the top surface of the substrate, an N-type buffer layer 12, a first tunnel junction 13, a P-type distributed Bragg reflector 14, an active layer 15, an N-type distributed Bragg reflector 16, a second tunnel junction 17, a P-type metal contact layer 18 and a cathode electrode 19 are stacked in sequence; the first tunnel junction 13 is used to invert N-type carriers in the N-type buffer layer 12 into P-type carriers, and the second tunnel junction 17 is used to invert N-type carriers in the N-type distributed Bragg reflector 16 into P-type carriers. As a result, an anode electrode can be set on the back side of the substrate and a cathode electrode 19 can be set above the front side of the substrate, so that the light-emitting structure of the vertical cavity surface emitting laser can be driven by an N-type transistor with a faster response speed, and it is convenient to adopt a common anode driving method, thereby reducing the volume of the driving system while increasing the driving frequency and speed of the VCSEL.

[0047] As an example, please continue to refer to Figures 1a to 1c. The N-type substrate 11 can be composed of semiconductor materials, insulating materials, semi-insulating materials or any combination thereof. The N-type substrate 11 can be a single-layer structure or a multi-layer structure. For example, the N-type substrate 11 can be a gallium arsenide (GaAs) substrate, an indium phosphide (INP) substrate or other III / V semiconductor substrate or II / VI semiconductor substrate. The type of substrate should not limit the scope of protection of the present disclosure. The N-type substrate 11 may include one or more components such as word lines, bit lines and transistors, which are omitted because they are not closely related to the invention of this solution.

[0048] As an example, please continue to refer to Figures 1a to 1c. One or more components such as word lines, bit lines and transistors generally need to be prepared in the N-type substrate 11. In order to reduce the lattice mismatch between the first tunnel junction 13 and the N-type substrate 11, or to prevent possible defects in the N-type substrate 11 from adversely affecting the first tunnel junction 13, an N-type buffer layer 12 is set between the N-type substrate 11 and the first tunnel junction 13 to effectively improve the yield and reliability of the semiconductor device.

[0049] As an example, referring again to Figures 1a-1c, the active layer 15 comprises a target stacked structure comprising a P-type semiconductor layer (not shown), a quantum well layer (not shown), and an N-type semiconductor layer (not shown) stacked sequentially in a direction perpendicular to the substrate (e.g., the oz direction). The P-type semiconductor layer is adjacent to the P-type distributed Bragg reflector 14, and the quantum well layer includes at least one quantum well. The optical thicknesses of the active layer 15, the P-type distributed Bragg reflector 14, and the upper distributed Bragg reflector collectively define the resonant wavelength of the VCSEL, which can be designed to be within the emission wavelength range of the active layer 15 to achieve laser emission.

[0050] As an example, the central cross-section of the quantum well region of the quantum well layer is located within the antinode interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the antinode is z, and the antinode interval is [z-λ / 8, z+λ / 8], where λ is the wavelength of the standing wave, so as to avoid energy loss in the internal film layer as much as possible and improve the light output efficiency and quality of the VCSEL.

[0051] As an example, the active layer includes multiple target stacked structures stacked sequentially in a direction perpendicular to the substrate. Adjacent target stacked structures are connected via interlayer tunnel junctions. Within adjacent target stacked structures, the N-type semiconductor layer of one target stacked structure is adjacent to the P-type semiconductor layer of another target stacked structure. The optical thickness of the active layer is set by combining the optical thickness of the P-type distributed Bragg reflector and the optical thickness of the upper distributed Bragg reflector to adjust the resonant wavelength of the VCSEL.

[0052] As an example, the central cross-section of the interlayer tunnel junction is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the central cross-section is parallel to the substrate; the position of the node is p, and the node interval is [p-λ / 8, p+λ / 8], where λ is the wavelength of the standing wave, so as to avoid energy loss in the internal film layer as much as possible and improve the light output efficiency and quality of the VCSEL.

[0053] As an example, please continue to refer to Figures 1a-1c. The central cross-section of the first tunnel junction 13 (perpendicular to the oz direction) is located within the node interval of the standing wave electric field of the vertical cavity surface emitting laser; the position of the node is p, and the node interval is [p-λ / 8, p+λ / 8], where λ is the wavelength of the standing wave, so as to avoid energy loss in the internal film layer and improve the light extraction efficiency and quality of the VCSEL.

[0054] In some embodiments, please continue to refer to Figures 1a to 1c. The P-type distributed Bragg reflector 14 may include a stacked multi-layer first reflective layer (not shown), the first reflective layer includes a first sub-reflective layer (not shown) and a second sub-reflective layer (not shown) with different refractive indices, the first sub-reflective layer in the P-type distributed Bragg reflector 14 is adjacent to the N-type substrate 11; the first sub-reflective layer adjacent to the first reflective layer is adjacent to the second sub-reflective layer; the first sub-reflective layer includes indium gallium phosphide, and the lattice constant of the compound in the second sub-reflective layer is greater than the lattice constant of indium gallium phosphide.

[0055] In some embodiments, please continue to refer to Figures 1a to 1c. The first sub-reflection layer includes indium gallium phosphide, and the lattice constant of the compound in the second sub-reflection layer is greater than the lattice constant of indium gallium phosphide, which can make the stresses in the first reflective layer in the P-type distributed Bragg reflector 14 offset each other and reduce the warping. The current related vertical cavity surface emitting laser can obtain a very high reflectivity (>99%) by alternately growing an epitaxial layer reflector made of two materials with different refractive indices according to an optical thickness of one-quarter wavelength, which can meet the special requirements of the device structure for the reflector. However, due to the lattice difference between the substrate and the epitaxial layer, stress accumulates in each thin epitaxial layer. At the same time, because the overall thickness of the epitaxial layer reflector is too thick, the warping of the epitaxial wafer becomes larger, thereby affecting the yield of the semiconductor chip. In the vertical cavity surface emitting laser of the embodiment of the present disclosure, a stacked multi-layer first reflective layer is provided in the P-type distributed Bragg reflector 14. The first reflective layer includes a first sub-reflective layer and a second sub-reflective layer of InGaP with different refractive indices. The first sub-reflective layer in the P-type distributed Bragg reflector 14 is adjacent to the N-type substrate 11, and the first sub-reflective layer and the second sub-reflective layer of the adjacent first reflective layer are adjacent to each other. The lattice constant of the compound in the second sub-reflective layer is set to be greater than the lattice constant of InGaP. This can make the stresses between the sub-reflective layers in the P-type distributed Bragg reflector 14 offset each other, reduce the degree of warping, and improve the yield of the semiconductor chip.

[0056] In some embodiments, please continue to refer to Figures 1a-1c. The upper distributed Bragg reflector includes a stacked multi-layer second reflective layer (not shown), the second reflective layer includes a third sub-reflective layer (not shown) and a fourth sub-reflective layer (not shown) with different refractive indices, and the third sub-reflective layer adjacent to the second reflective layer is adjacent to the fourth sub-reflective layer; the third sub-reflective layer and the fourth sub-reflective layer both include aluminum gallium arsenide, and the aluminum content of the third sub-reflective layer and the fourth sub-reflective layer is different.

[0057] For example, the third sub-reflection layer and the fourth sub-reflection layer include Al x Ga 1-x As, Al x Ga 1-x As material is formed by uniform recombination of AlAs and GaAs, and has the advantages of high carrier mobility, adjustable Al composition, and small lattice mismatch with GaAs. x Ga 1-x As, x<0.1; Al in the fourth sub-reflection layer x Ga 1-x As, x>0.9, the third sub-reflection layer with a high refractive index and the fourth sub-reflection layer with a low refractive index are grown alternately. The number of cycles can be increased to obtain high reflectivity, meeting the special requirements of the VCSEL structure for the reflector.

[0058] In some embodiments, the first sub-reflective layer includes In y Ga 1-y P; where y∈[0, 0.48], for example, 0, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4 or 0.48, etc.

[0059] In some embodiments, the second sub-reflective layer includes aluminum arsenide or aluminum gallium arsenide.

[0060] As an example, the first sub-reflection layer may be In 0.48 Ga 0.52 P, the substrate can be GaAs, In 0.48 Ga 0.52 The lattice constant of P is smaller than that of GaAs substrate. The first sub-reflection layer is under tensile stress. The second sub-reflection layer includes Al x Ga 1-x As, usually x>0.9, the lattice constant of the second sub-reflection layer is greater than In 0.48 Ga 0.52 P, the second sub-reflection layer is subjected to compressive stress, so that the tensile stress and compressive stress in each DBR period (i.e., the first reflective layer) offset each other, reducing the warpage of the epitaxial wafer.

[0061] Specifically, for a VCSEL with a wavelength of 940 nm, the refractive index difference between high and low Al content AlGaAs is about 0.465. 0.48 Ga 0.52 The refractive index difference between P and AlGaAs is about 0.246. Using InGaP as the DBR material can achieve sufficient reflectivity and maintain a low warpage when the DBR thickness is relatively thick.

[0062] In some embodiments, a laser array is provided, comprising a plurality of vertical cavity surface emitting lasers as described in any of the foregoing embodiments arranged in rows and columns; wherein the vertical cavity surface emitting lasers located in the same row are all connected to the corresponding row selection line; the vertical cavity surface emitting lasers located in the same column are all connected to the corresponding column selection line; the vertical cavity surface emitting lasers in different rows are respectively connected to different row selection lines; the vertical cavity surface emitting lasers in different columns are respectively connected to different column selection lines; by selecting a row selection line and a column selection line to select the vertical cavity surface emitting lasers connected to the selected row selection line and the selected column selection line, a common anode driving mode is realized, and an N-type transistor with a faster response speed is used to drive the light-emitting structure of the vertical cavity surface emitting laser, thereby reducing the volume of the driving system while improving the driving frequency and speed of the VCSEL. By arranging that the vertical cavity surface emitting lasers located in the same row are connected to the corresponding row selection line, the vertical cavity surface emitting lasers located in the same column are connected to the corresponding column selection line, the vertical cavity surface emitting lasers in different rows are connected to different row selection lines, and the vertical cavity surface emitting lasers in different columns are connected to different column selection lines, when a vertical cavity surface emitting laser fails, the faulty laser can be quickly located, thereby improving the operating efficiency of the device.

[0063] As an example, please refer to Figures 2-3. The first vertical cavity surface emitting laser 100a, the second vertical cavity surface emitting laser 100b, the third vertical cavity surface emitting laser 100c, the fourth vertical cavity surface emitting laser 100d, the fifth vertical cavity surface emitting laser 100e, and the sixth vertical cavity surface emitting laser 100f arranged in rows and columns share an anode electrode; among the first vertical cavity surface emitting laser 100a, the second vertical cavity surface emitting laser 100b, the third vertical cavity surface emitting laser 100c, the fourth vertical cavity surface emitting laser 100d, the fifth vertical cavity surface emitting laser 100e, and the sixth vertical cavity surface emitting laser 100f, the cathode electrodes of any adjacent vertical cavity surface emitting lasers are insulated from each other, which facilitates independent cathode driving of different VCSELs while simplifying the anode drive, thereby meeting the drive control requirements of the customized light output solution of the laser array.

[0064] As an example, adjacent vertical cavity surface emitting lasers include an isolation structure, which extends to the top surface of the P-type distributed Bragg reflector along the direction perpendicular to the substrate (for example, the oz direction), thereby avoiding mutual influence between adjacent VCSELs while simplifying the structure and preparation process steps of the laser array.

[0065] As an example, please continue to refer to Figure 3. The isolation structure can be an isolation trench. An isolation trench is provided between the first vertical cavity surface emitting laser 100a and the second vertical cavity surface emitting laser 100b. The isolation trench extends along a direction perpendicular to the substrate (for example, the oz direction) to the top surface of the P-type distributed Bragg reflector 14; the active layer 15a, N-type distributed Bragg reflector 16a, second tunnel junction 17a, P-type metal contact layer 18a, and cathode electrode 19a of the first vertical cavity surface emitting laser 100a are isolated and insulated from the active layer 15b, N-type distributed Bragg reflector 16b, second tunnel junction 17b, P-type metal contact layer 18b, and cathode electrode 19b of the second vertical cavity surface emitting laser 100b via the isolation trench; the first vertical cavity surface emitting laser 100a and the second vertical cavity surface emitting laser 100b share the N-type substrate 11, N-type buffer layer 12, first tunnel junction 13 and P-type distributed Bragg reflector 14.

[0066] In some embodiments, a light emitting device is provided, comprising the vertical cavity surface emitting laser as described in any one of the aforementioned embodiments.

[0067] In some embodiments, a light emitting device is provided, comprising the laser array as described in any one of the preceding embodiments.

[0068] As an example, referring to FIG4 , a method for preparing a vertical cavity surface emitting laser is provided, including:

[0069] Step S602: providing an N-type substrate, wherein the back surface of the N-type substrate includes an anode electrode;

[0070] Step S604: An upper distributed Bragg reflector (DBR) is formed on the front surface of the N-type substrate, along with an N-type buffer layer, a first tunnel junction, a P-type DBR, an active layer, a second tunnel junction, a P-type metal contact layer, and a cathode electrode stacked in sequence perpendicular to the substrate. The first tunnel junction is used to invert N-type carriers in the N-type buffer layer into P-type carriers. The second tunnel junction is used to invert carriers in the upper DBR into carriers of the opposite conductivity type.

[0071] As an example, please continue to refer to Figure 1a. In the direction away from the top surface of the substrate, an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, an N-type distributed Bragg reflector, a second tunnel junction, a P-type metal contact layer and a cathode electrode are stacked in sequence; the first tunnel junction is used to invert the N-type carriers in the N-type buffer layer into P-type carriers, and the second tunnel junction is used to invert the N-type carriers in the N-type distributed Bragg reflector into P-type carriers, so that an anode electrode can be set on the back side of the substrate and a cathode electrode can be set above the front side of the substrate, realizing the use of a faster-response N-type transistor to drive the light-emitting structure of the vertical cavity surface emitting laser, and facilitating the use of a common anode driving method, thereby reducing the volume of the driving system while increasing the driving frequency and speed of the VCSEL.

[0072] It should be understood that although the various steps in the flow chart of Figure 4 are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in Figure 4 may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0073] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0074] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A vertical cavity surface emitting laser, wherein: It includes an N-type substrate, an upper distributed Bragg reflector, and an N-type buffer layer, a first tunnel junction, a P-type distributed Bragg reflector, an active layer, a second tunnel junction, a P-type metal contact layer and a cathode electrode stacked in sequence in a direction perpendicular to the substrate; The first tunnel junction is used to invert carriers in the N-type buffer layer into carriers of opposite conductivity type; The second tunnel junction is used to invert carriers in the upper distributed Bragg reflector into carriers of opposite conductivity type; The upper distributed Bragg reflector is located between the active layer and the P-type metal contact layer, and the upper distributed Bragg reflector is associated with the second tunnel junction; Wherein, the surface of the N-type substrate facing away from the N-type buffer layer includes an anode electrode.

2. The vertical cavity surface emitting laser according to claim 1, wherein: The active layer includes a target stacked structure; The target stacked structure includes a P-type semiconductor layer, a quantum well layer, and an N-type semiconductor layer stacked in sequence in a direction perpendicular to the substrate; the P-type semiconductor layer is adjacent to the P-type distributed Bragg reflector; The quantum well layer includes at least one quantum well; or The central cross section of the first tunnel junction is located within a node interval of the standing wave electric field of the vertical cavity surface emitting laser; The position of the node is p, the node interval is [p-λ / 8, p+λ / 8], and λ is the wavelength of the standing wave.

3. The vertical cavity surface emitting laser according to claim 2, wherein: The central cross section of the quantum well region of the quantum well layer is located within the antinode interval of the standing wave electric field of the vertical cavity surface emitting laser; The position of the antinode is z, and the antinode interval is [z-λ / 8, z+λ / 8]; or The active layer includes a plurality of target stacked structures stacked in sequence along a direction perpendicular to the substrate; Adjacent target stack structures are connected via interlayer tunnel junctions; In the adjacent target stacked structures, the N-type semiconductor layer of one target stacked structure is adjacent to the P-type semiconductor layer of another target stacked structure.

4. The vertical cavity surface emitting laser according to claim 3, wherein: The central cross section of the interlayer tunnel junction is located within a node interval of the standing wave electric field of the vertical cavity surface emitting laser; the central cross section is parallel to the substrate; The position of the node is p, and the node interval is [p-λ / 8, p+λ / 8].

5. The vertical cavity surface emitting laser according to claim 1, wherein: The upper distributed Bragg reflector comprises: A P-type distributed Bragg reflection layer is located between the second tunnel junction and the P-type metal contact layer; or The N-type distributed Bragg reflection layer is located between the active layer and the second tunnel junction.

6. The vertical cavity surface emitting laser according to claim 1, wherein: The upper distributed Bragg reflector comprises: a sub-N-type distributed Bragg reflection layer, located between the active layer and the second tunnel junction; and The sub-P-type distributed Bragg reflection layer is located between the second tunnel junction and the P-type metal contact layer.

7. A laser array, wherein: comprising a plurality of vertical cavity surface emitting lasers according to any one of claims 1 to 6 arranged in rows and columns; Wherein, the vertical cavity surface emitting lasers located in the same row are all connected to corresponding row selection lines; The vertical cavity surface emitting lasers located in the same column are all connected to the corresponding column selection line; The vertical cavity surface emitting lasers in different rows are respectively connected to different row selection lines; The vertical cavity surface emitting lasers in different columns are respectively connected to different column selection lines; A vertical cavity surface emitting laser connected to the selected row selection line and the selected column selection line is selected by selecting a row selection line and a column selection line.

8. The laser array according to claim 7, wherein: The plurality of vertical cavity surface emitting lasers arranged in rows and columns share an anode electrode; Among the plurality of vertical cavity surface emitting lasers that share one anode electrode, cathode electrodes of any adjacent vertical cavity surface emitting lasers are insulated from each other.

9. The laser array according to claim 8, wherein: An isolation structure is included between adjacent vertical cavity surface emitting lasers, and the isolation structure extends along a direction perpendicular to the substrate to the top surface of the P-type distributed Bragg reflector.

10. A light emitting device, wherein: include: The vertical cavity surface emitting laser according to any one of claims 1 to 6; or The laser array according to any one of claims 7 to 9.

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