Power semiconductor module having double-sided heat dissipation, and power semiconductor packaging assembly

Abstract

The present invention provides a power semiconductor module having a double-sided heat dissipation, and a power semiconductor packaging assembly. The power semiconductor module comprises a first substrate and a second substrate; the first substrate and the second substrate each comprise a connecting copper layer, an insulating dielectric layer, and an outer copper coating layer which are attached; the connecting copper layer of the first substrate is arranged opposite to the connecting copper layer of the second substrate; upper bridge arm chips are arranged on the connecting copper layer of the first substrate; the connecting copper layer of the first substrate is connected to welding spot surfaces of the upper bridge arm chips; the connecting copper layer of the second substrate is connected to the upper surfaces of the upper bridge arm chips; lower bridge arm chips are arranged on the connecting copper layer of the second substrate; the connecting copper layer of the second substrate is connected to welding spot surfaces of the lower bridge arm chips; the connecting copper layer of the first substrate is connected to the upper surfaces of the lower bridge arm chips; and signal terminals and power terminals are respectively arranged on two sides between the connecting copper layer of the first substrate and the connecting copper layer of the second substrate. The use of the technical solution can reduce the size of the power semiconductor module and the size of the power semiconductor packaging assembly, and achieve double-sided heat dissipation.

Description

A double-sided heat dissipation power semiconductor module and packaging assembly Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a double-sided heat dissipation power semiconductor module and a packaging assembly. Background Art

[0002] Power semiconductor modules are widely used in applications requiring power conversion, such as industrial frequency conversion, converters, and automotive electrode controllers. Traditional power semiconductor modules utilize a single-sided cooling structure, where heat generated by power chip losses is transferred unidirectionally to the heat sink through the DBC and substrate. However, for highly integrated or high-power power semiconductors, single-sided cooling is inefficient due to the high heat generated by the chips, making it difficult to dissipate the high heat required. Consequently, the demand for double-sided cooling solutions is becoming increasingly urgent.

[0003] Existing double-sided heat dissipation solutions suffer from complex manufacturing processes, high implementation difficulties, and large module footprint. However, automotive modules have high requirements for both volume and power density. Therefore, a double-sided heat dissipation power semiconductor module with a compact overall size and high power density is needed. Summary of the Invention

[0004] In order to overcome the above technical defects, the purpose of the present invention is to provide a double-sided heat dissipation power semiconductor module and packaging assembly, which can perform double-sided heat dissipation while having a smaller thickness and lateral size, and a higher power density.

[0005] The present invention discloses a power semiconductor module with double-sided heat dissipation.

[0006] The invention comprises a first substrate and a second substrate, wherein the first substrate and the second substrate each comprise a connecting copper layer, an insulating dielectric layer and an outer copper cladding layer which are bonded together, and the insulating dielectric layer is arranged between the connecting copper layer and the outer copper cladding layer;

[0007] The first substrate and the second substrate are spaced apart and overlap in a vertical direction, so that the connecting copper layer of the first substrate is opposite to the connecting copper layer of the second substrate;

[0008] An upper bridge arm chip is provided on the connection copper layer of the first substrate, the connection copper layer of the first substrate is connected to the solder joint surface of the upper bridge arm chip, and the connection copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip;

[0009] A lower bridge arm chip is provided on the connection copper layer of the second substrate, the connection copper layer of the second substrate is connected to the solder joint surface of the lower bridge arm chip, and the connection copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip;

[0010] A signal terminal and a power terminal are respectively provided on both sides between the connection copper layer of the first substrate and the connection copper layer of the second substrate.

[0011] Preferably, a first conductive pad is provided between the connection copper layer of the first substrate and the upper bridge arm chip, the connection copper layer of the first substrate is connected to the bottom surface of the first conductive pad, and the top surface of the first conductive pad is connected to the solder joint surface of the upper bridge arm chip, so that the height of the upper surface of the upper bridge arm chip is equal to the height of the upper surface of the signal terminal;

[0012] A second conductive pad is arranged between the connecting copper layer of the second substrate and the lower bridge arm chip, so that the connecting copper layer of the second substrate is connected to the bottom surface of the second conductive pad, and the top surface of the second conductive pad is connected to the solder joint surface of the lower bridge arm chip, so that the height of the upper surface of the lower bridge arm chip is equal to the height of the lower surface of the signal terminal.

[0013] Preferably, the first substrate and the second substrate are installed in the insulating housing at intervals and overlap in the vertical direction, so that the connecting copper layer of the first substrate is opposite to the connecting copper layer of the second substrate, and the outer copper layer of the first substrate is opposite to the outer copper layer of the second substrate and is respectively exposed outside the insulating housing;

[0014] The signal terminal and the power terminal are respectively exposed outside two sides of the insulating shell along a horizontal direction.

[0015] Preferably, a positioning groove is provided on a side of the insulating housing close to the signal terminal, offset from the center line of the insulating housing.

[0016] Preferably, the connecting copper layer of the first substrate comprises a first main copper foil, a second main copper foil and a third main copper foil which are insulated from each other, and the connecting copper layer of the second substrate comprises a fourth main copper foil, a fifth main copper foil and a sixth main copper foil which are insulated from each other;

[0017] The first main copper foil is connected to the solder joint surface of the upper bridge arm chip, the second main copper foil is connected to the upper surface of the lower bridge arm chip, and the sixth main copper foil is connected to the solder joint surface of the lower bridge arm chip and the upper surface of the upper bridge arm chip;

[0018] The power terminal includes a DC positive terminal, a DC negative terminal, and an AC terminal. The DC positive terminal is connected to the first main copper foil and the fourth main copper foil, the DC negative terminal is connected to the second main copper foil and the fifth main copper foil, and the AC terminal is connected to the third main copper foil and the sixth main copper foil.

[0019] The commutation loop current enters the first main copper foil from the DC positive terminal, flows through the upper bridge arm chip and then enters the sixth main copper foil, flows through the AC terminal and the lower bridge arm chip, then enters the second main copper foil, and flows out of the power semiconductor module from the DC negative terminal.

[0020] Preferably, the connecting copper layer of the first substrate further comprises a first auxiliary copper foil, a second auxiliary copper foil, a third auxiliary copper foil, a fourth auxiliary copper foil and a fifth auxiliary copper foil which are insulated from each other, and the third auxiliary copper foil and the fourth auxiliary copper foil are respectively connected to the upper surface of the lower bridge arm chip;

[0021] The connecting copper layer of the second substrate further includes a sixth auxiliary copper foil, a seventh auxiliary copper foil, an eighth auxiliary copper foil, a ninth auxiliary copper foil and a tenth auxiliary copper foil that are insulated from each other, and the seventh auxiliary copper foil and the eighth auxiliary copper foil are respectively connected to the upper surface of the upper bridge arm chip;

[0022] The signal terminals include a first collector signal terminal, a second collector signal terminal, a first emitter signal terminal, a second emitter signal terminal, a first gate signal terminal and a second gate signal terminal;

[0023] The first collector signal terminal is connected to the first main copper foil and the sixth auxiliary copper foil, the first emitter signal terminal is connected to the first auxiliary copper foil and the seventh auxiliary copper foil, the first gate signal terminal is connected to the second auxiliary copper foil and the eighth auxiliary copper foil, the second collector signal terminal is connected to the fifth auxiliary copper foil and the sixth main copper foil, the second emitter signal terminal is connected to the fourth auxiliary copper foil and the tenth auxiliary copper foil, and the second gate signal terminal is connected to the third auxiliary copper foil and the ninth auxiliary copper foil;

[0024] The commutation loop current enters the first main copper foil from the DC positive terminal, flows through the first collector signal terminal and the upper bridge arm chip, and then enters the sixth main copper foil, the seventh auxiliary copper foil and the eighth auxiliary copper foil, respectively flows through the first emitter signal terminal, the first gate signal terminal, the AC terminal, the second collector signal terminal and the lower bridge arm chip, and then enters the second main copper foil, the third auxiliary copper foil and the fourth auxiliary copper foil, flows through the second emitter signal terminal and the second gate signal terminal, and flows out of the power semiconductor module from the DC negative terminal.

[0025] Preferably, the upper arm chip includes an upper arm IGBT chip and an upper arm diode chip, and the lower arm chip includes a lower arm IGBT chip and a lower arm diode chip.

[0026] Preferably, the connection copper layer of the first substrate is connected to the solder joint surface of the upper bridge arm chip by vacuum reflow soldering, and the connection copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip by vacuum reflow soldering;

[0027] The connecting copper layer of the second substrate is connected to the solder joint surface of the lower bridge arm chip through vacuum reflow soldering, and the connecting copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip through vacuum reflow soldering.

[0028] Preferably, the material of the first conductive pad and the second conductive pad includes aluminum silicon carbide, molybdenum copper alloy or copper.

[0029] The present invention further discloses a power semiconductor package assembly, comprising at least three power semiconductor modules as described above, wherein the power semiconductor modules are arranged in parallel in the same direction;

[0030] A heat sink is connected to the outer copper layer of the first substrate and the outer copper layer of the second substrate of each power semiconductor module respectively.

[0031] After adopting the above technical solution, compared with the existing technology, it has the following beneficial effects: the solder joint surface of the chip is directly connected to the connecting copper layer through the flip-chip technology, thereby reducing the vertical size of the power semiconductor module; by installing the upper bridge arm chip and the lower bridge arm chip on the first substrate and the second substrate in opposite directions, the pads connecting the first substrate and the second substrate can be reduced, thereby reducing the lateral size of the power semiconductor module; by providing an exposed outer copper layer, the power semiconductor module can perform double-sided heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic structural diagram of a power semiconductor module according to the present invention;

[0033] FIG2 is a schematic diagram of a three-dimensional assembly of a power semiconductor module according to the present invention;

[0034] FIG3 is a schematic cross-sectional view of a power semiconductor module of the present invention;

[0035] FIG4 is a schematic structural diagram of a power semiconductor module according to the present invention;

[0036] FIG5 is a schematic structural diagram of a first substrate of the present invention;

[0037] FIG6 is a schematic structural diagram of a second substrate of the present invention;

[0038] FIG7 is a schematic diagram of the circuit topology structure of the present invention.

[0039] Reference numerals: 1-first substrate; 11-connecting copper layer of first substrate; 12-insulating dielectric layer of first substrate; 13-outer copper layer of first substrate; 2-second substrate; 21-connecting copper layer of second substrate; 22-insulating dielectric layer of second substrate; 23-outer copper layer of second substrate; 3-upper arm chip; 4-lower arm chip; 5-power terminal; 6-signal terminal; 7-insulating housing; 71-positioning groove; 111-first main copper foil; 112-second main copper foil Foil; 113-third main copper foil; 211-fourth main copper foil; 212-fifth main copper foil; 213-sixth main copper foil; 1110-first auxiliary copper foil; 1120-second auxiliary copper foil; 1130-third auxiliary copper foil; 1140-fourth auxiliary copper foil; 1150-fifth auxiliary copper foil; 2110-sixth auxiliary copper foil; 2120-seventh auxiliary copper foil; 2130-eighth auxiliary copper foil; 2140-ninth auxiliary copper foil; 2150-tenth auxiliary copper foil. DETAILED DESCRIPTION

[0040] The advantages of the present invention are further described below with reference to the accompanying drawings and specific embodiments.

[0041] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0042] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. As used in this disclosure and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0043] It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this disclosure, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining."

[0044] In the description of the present invention, it should be understood that the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0045] In the description of the present invention, unless otherwise specified and limited, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the internal communication between two components. It can be a direct connection or an indirect connection through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances.

[0046] In the following description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention and have no specific meaning. Therefore, "module" and "component" can be used interchangeably.

[0047] As shown in Figures 1 to 6, the present invention discloses a power semiconductor module with double-sided heat dissipation.

[0048] The present invention comprises a first substrate 1 and a second substrate 2, each of which comprises a connection copper layer, an insulating dielectric layer and an outer copper cladding layer which are bonded together. The insulating dielectric layer is arranged between the connection copper layer and the outer copper cladding layer. The first substrate 1 and the second substrate 2 are spaced apart and overlap in the vertical direction, so that the connection copper layer 11 of the first substrate is opposite to the connection copper layer 21 of the second substrate. An upper bridge arm chip 3 is arranged on the connection copper layer 11 of the first substrate, so that the connection copper layer 11 of the first substrate is connected to the soldering surface of the upper bridge arm chip 3, and the connection copper layer 21 of the second substrate is connected to the upper surface of the upper bridge arm chip 3. A lower bridge arm chip 4 is arranged on the connection copper layer 21 of the second substrate, so that the connection copper layer 21 of the second substrate is connected to the soldering surface of the lower bridge arm chip 4, and the connection copper layer 11 of the first substrate is connected to the upper surface of the lower bridge arm chip 4. Signal terminals 6 and power terminals 5 are respectively arranged on both sides between the connection copper layer 11 of the first substrate and the connection copper layer 21 of the second substrate.

[0049] Specifically, both the first substrate 1 and the second substrate 2 have a three-layer structure, including a connecting copper layer, an insulating dielectric layer, and an outer copper layer, which are sequentially bonded. The first substrate 1 and the second substrate 2 are spaced apart and arranged opposite each other. It is understood that the first substrate 1 and the second substrate 2 have exactly the same dimensions, so that the first substrate 1 and the second substrate 2 overlap vertically. When the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate are aligned, the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate can be electrically connected via the chip and terminals, allowing a commutation circuit to be formed when the power semiconductor module is powered. The outer copper layer 13 of the first substrate and the outer copper layer 13 of the second substrate face away from each other, enabling heat transfer from the power semiconductor to the outside in two directions, enabling the power semiconductor module to achieve double-sided heat dissipation. Furthermore, heat dissipation devices can be connected to the outer copper layer 13 of the first substrate and the outer copper layer 13 of the second substrate, for example, heat dissipation channels can be provided on the outer copper layer 13 of the first substrate and the outer copper layer 13 of the second substrate, respectively, to improve the efficiency of double-sided heat dissipation of the power semiconductor module.

[0050] The insulating dielectric layer is placed between the connecting copper layer and the outer copper layer to insulate the connection copper layer and prevent interference between the connection copper layer's current commutation function and the outer copper layer's heat dissipation function. The insulating dielectric layer can be made of materials such as zirconia-toughened alumina ceramic, silicon nitride ceramic, and aluminum nitride ceramic.

[0051] Preferably, the thicknesses of the connecting copper layer, the insulating dielectric layer and the outer copper cladding layer can be set to 0.3 mm, 0.32 mm and 0.4 mm respectively.

[0052] Signal terminals 6 are metal strips that can be connected to the driver board via welding or connectors, extracting signals from different locations in the power semiconductor module's commutation circuit. Power terminals 5 are metal sheets that can be connected to capacitors via laser welding, inputting DC current into the power semiconductor module and extracting AC current.

[0053] In the present invention, the solder joint surface of a chip refers to the surface formed by depositing protruding solder joints on the IO unit side of the chip, and the top surface of a chip refers to the surface of the chip opposite the solder joint surface. The connecting copper layer 11 of the first substrate is connected to the solder joint surface of the upper bridge arm chip 3, and the connecting copper layer 21 of the second substrate is connected to the solder joint surface of the lower bridge arm chip 4. That is, the upper bridge arm chip 3 is connected to the connecting copper layer 11 of the first substrate via a flip-chip method, and the lower bridge arm chip 4 is connected to the connecting copper layer 21 of the second substrate via a flip-chip method, so that the upper bridge arm chip 3 and the lower bridge arm chip 4 are flip-chipped on two opposing connecting copper layers in opposite directions. Furthermore, the connecting copper layer 21 of the second substrate is connected to the top surface of the upper bridge arm chip 3, and the connecting copper layer 11 of the first substrate is connected to the top surface of the lower bridge arm chip 4, so that current can flow between the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate, thereby forming a commutation circuit between the first and second substrates.

[0054] Because the flip-chip method directly connects the chip to a substrate, carrier, or circuit board via its solder joints, it has a smaller vertical dimension than wire bonding. Furthermore, because the upper-arm chip 3 and the lower-arm chip 4 are mounted in opposite directions on the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate, respectively, a commutation circuit can be formed without the need for conductive pads connecting the connecting copper layer 11 of the first substrate and the connecting copper layer 21 of the second substrate, thereby reducing the use of components and the lateral size of the power semiconductor module.

[0055] It can be understood that since the connecting copper layer 21 of the second substrate is connected to the upper surface of the upper bridge arm chip 3, the connecting copper layer 11 of the first substrate is connected to the upper surface of the lower bridge arm chip 4, and the signal terminal 6 and the power terminal 5 are respectively arranged on both sides between the connecting copper layer 11 of the first substrate and the connecting copper layer 13 of the second substrate, therefore, after the above-mentioned components complete their respective connection relationships, the spacing between the first substrate 1 and the second substrate 2, the thickness of the upper bridge arm chip 3, the thickness of the lower bridge arm chip 4, the thickness of the signal terminal 6, and the thickness of the power terminal 5 will all be equal.

[0056] When the above-mentioned components are connected by welding, a solder layer will be formed on the surface of any component connected to other components, so that the spacing between the first substrate 1 and the second substrate 2, the thickness of the upper bridge arm chip 3 and the solder layers on both sides, the thickness of the lower bridge arm chip 4 and the solder layers on both sides, the thickness of the signal terminal 6 and the solder layers on both sides, and the thickness of the power terminal 5 and the solder layers on both sides are all equal.

[0057] In an optional embodiment, a first conductive pad is arranged between the connecting copper layer 11 of the first substrate and the upper bridge arm chip 3, the connecting copper layer 11 of the first substrate is connected to the bottom surface of the first conductive pad, and the top surface of the first conductive pad is connected to the solder point surface of the upper bridge arm chip 3, so that the height of the upper surface of the upper bridge arm chip 3 is equal to the height of the upper surface of the signal terminal 6; a second conductive pad is arranged between the connecting copper layer 21 of the second substrate and the lower bridge arm chip 4, so that the connecting copper layer 21 of the second substrate is connected to the bottom surface of the second conductive pad, and the top surface of the second conductive pad is connected to the solder point surface of the lower bridge arm chip 4, so that the height of the upper surface of the lower bridge arm chip 4 is equal to the height of the lower surface of the signal terminal 6.

[0058] Specifically, the thickness of commonly used signal terminal components is greater than that of chip components. Therefore, to compensate for this height difference, a first conductive spacer can be provided between the connecting copper layer 11 of the first substrate and the upper bridge arm chip 3, and a second conductive spacer can be provided between the connecting copper layer 21 of the second substrate and the lower bridge arm chip 4, so that the height of the upper surface of the upper bridge arm chip 3 is equal to the height of the upper surface of the signal terminal 6, and the height of the upper surface of the lower bridge arm chip 4 is equal to the height of the lower surface of the signal terminal 6. It will be understood that the upper surface of the signal terminal 6 refers to the surface of the signal terminal 6 close to the second substrate 2, and the lower surface of the signal terminal 6 refers to the surface of the signal terminal 6 close to the first substrate 1.

[0059] Therefore, after the above-mentioned components complete their respective connection relationships, the spacing between the first substrate 1 and the second substrate 2, the overall thickness of the upper bridge arm chip 3 and the first conductive pad, the overall thickness of the lower bridge arm chip 4 and the second conductive pad, the thickness of the signal terminal 6, and the thickness of the power terminal 5 will all be equal.

[0060] When the above-mentioned components are connected by welding, a solder layer will be formed on the surface of any component connected to the other components, so that the spacing between the first substrate 1 and the second substrate 2, the overall thickness of the upper bridge arm chip 3 and its two-sided solder layers and the first conductive pad and its two-sided solder layers, the overall thickness of the lower bridge arm chip 4 and its two-sided solder layers and the first conductive pad and its two-sided solder layers, the thickness of the signal terminal 6 and its two-sided solder layers, and the thickness of the power terminal 5 and its two-sided solder layers are all equal.

[0061] In an optional embodiment, as shown in FIG4 , a first substrate 1 and a second substrate 2 are installed within an insulating housing 7 with spacing therebetween and vertically overlapped, such that the connecting copper layer 11 of the first substrate faces the connecting copper layer 21 of the second substrate, and the outer copper layer 13 of the first substrate faces the outer copper layer 31 of the second substrate, both of which are exposed outside the insulating housing 7. The signal terminals 6 and the power terminals 5 are exposed outside the insulating housing 7 on either side thereof in the horizontal direction.

[0062] Specifically, the insulating housing 7 can be made of epoxy resin. The first substrate 1 and the second substrate 2 are installed in the insulating housing 7 at intervals, forming a structure in which the insulating housing 7 encloses the first substrate 1 and the second substrate 2. The insulating housing 7 can provide an insulating environment for the components included therein, further improving the stability of the power semiconductor module during use. The outer copper layer 13 of the first substrate and the outer copper layer 31 of the second substrate are respectively exposed outside the insulating housing 7. It can be understood that the top and bottom surfaces of the insulating housing 7 are provided with a similar hollow structure, which does not cover the outer copper layer 13 of the first substrate and the outer copper layer 31 of the second substrate. This allows the power semiconductor module to achieve a double-sided heat dissipation effect through the outer copper layer 13 of the first substrate and the outer copper layer 31 of the second substrate. Furthermore, a heat dissipation device can be connected to the top and bottom surfaces of the insulating housing 7. Since the outer copper layer 13 of the first substrate and the outer copper layer 31 of the second substrate are respectively exposed outside the insulating housing 7, they can both be in contact with the heat dissipation device, thereby improving the double-sided heat dissipation efficiency of the power semiconductor module.

[0063] In an optional embodiment, a positioning groove 71 is provided on a side of the insulating housing 7 close to the signal terminal 6 and offset from the center line of the insulating housing 7 .

[0064] It is understandable that, after the aforementioned arrangement of the power semiconductor module, the first substrate 1 and the second substrate 2 have similar structures and are arranged opposite each other in the insulating housing 7. When the power semiconductor module is flipped, it is difficult to quickly distinguish the direction of the power semiconductor, which may cause confusion between the specific functions of each signal terminal 6 and each power terminal 5, and have a negative impact on the subsequent connection of devices such as driver boards or capacitors. Therefore, in this embodiment, a positioning groove 71 is set on the side of the insulating housing 7 close to the signal terminal 6, deviating from the center line of the insulating housing 7. Because the positioning groove 71 deviates from the center line of the insulating housing 7, the direction of the first substrate 1 and the second substrate 2 can be determined based on the direction in which the positioning groove 7 is currently deviated. For example, in Figure 4, when the positioning groove 71 deviates to the horizontal left side of the insulating housing 7, it can be determined that the current direction of the power semiconductor module is that the second substrate 2 is located above the first substrate 1, and the position of each signal terminal 6 and each power terminal 5 can be confirmed based on this direction, avoiding incorrect installation during the application of the power semiconductor module.

[0065] In an optional embodiment, as shown in Figures 5 and 6, the connecting copper layer 11 of the first substrate includes a first main copper foil 111, a second main copper foil 112, and a third main copper foil 113, which are insulated from each other. The connecting copper layer 21 of the second substrate includes a fourth main copper foil 211, a fifth main copper foil 212, and a sixth main copper foil 213, which are insulated from each other. The first main copper foil 111 is connected to the solder joint surface of the upper bridge arm chip 3, the second main copper foil 112 is connected to the upper surface of the lower bridge arm chip 4, and the sixth main copper foil 213 is connected to the solder joint surface of the lower bridge arm chip 4 and the upper surface of the upper bridge arm chip 3.

[0066] The power terminal 5 includes a DC positive terminal DC+, a DC negative terminal DC-, and an AC terminal AC. The DC positive terminal DC+ connects the first main copper foil 111 and the fourth main copper foil 211, the DC negative terminal DC- connects the second main copper foil 112 and the fifth main copper foil 212, and the AC terminal AC connects the third main copper foil 113 and the sixth main copper foil 213.

[0067] After the above configuration, the commutation loop current enters the first main copper foil 111 from the DC positive terminal DC+, flows through the solder joint surface of the upper bridge arm chip 3, and enters the sixth main copper foil 213 through the upper surface of the upper bridge arm chip 3. It then flows through the AC terminal AC and the solder joint surface of the lower bridge arm chip 4, then enters the second main copper foil 112 through the upper surface of the lower bridge arm chip 4, and flows out of the power semiconductor module from the DC negative terminal DC-.

[0068] Preferably, as shown in Figures 5 to 6, the connecting copper layer 11 of the first substrate also includes a first auxiliary copper foil 1110, a second auxiliary copper foil 1120, a third auxiliary copper foil 1130, a fourth auxiliary copper foil 1140 and a fifth auxiliary copper foil 1150 that are insulated from each other, and the third auxiliary copper foil 1130 and the fourth auxiliary copper foil 1140 are respectively connected to the upper surface of the lower bridge arm chip 4.

[0069] The connecting copper layer 21 of the second substrate further includes a sixth auxiliary copper foil 2110 , a seventh auxiliary copper foil 2120 , an eighth auxiliary copper foil 2130 , a ninth auxiliary copper foil 2140 and a tenth auxiliary copper foil 2150 , which are insulated from each other. The seventh auxiliary copper foil 2120 and the eighth auxiliary copper foil 2130 are respectively connected to the upper surface of the upper bridge arm chip 3 .

[0070] The signal terminals 6 include a first collector signal terminal C1, a second collector signal terminal C2, a first emitter signal terminal E1, a second emitter signal terminal E2, a first gate signal terminal G1, and a second gate signal terminal G2. The first collector signal terminal C1 connects the first main copper foil 111 and the sixth auxiliary copper foil 2110, the first emitter signal terminal E1 connects the first auxiliary copper foil 1110 and the seventh auxiliary copper foil 2120, the first gate signal terminal G1 connects the second auxiliary copper foil 1120 and the eighth auxiliary copper foil 2130, the second collector signal terminal C2 connects the fifth auxiliary copper foil 1140 and the sixth main copper foil 213, the second emitter signal terminal E2 connects the fourth auxiliary copper foil 1140 and the tenth auxiliary copper foil 2150, and the second gate signal terminal G2 connects the third auxiliary copper foil 1130 and the ninth auxiliary copper foil 2140.

[0071] After the above configuration, the commutation loop current enters the first main copper foil 111 from the DC positive terminal DC+, flows through the first collector signal terminal C1 and the solder joint surface of the upper bridge arm chip 3 in the first main copper foil 111, and enters the sixth main copper foil 213, the seventh auxiliary copper foil 2120, and the eighth auxiliary copper foil 2130 through the upper surface of the upper bridge arm chip 3, respectively flowing through the first emitter signal terminal E1, the first gate signal terminal G1, the AC terminal AC, the second collector signal terminal C2, and the solder joint surface of the lower bridge arm chip 4, and then enters the second main copper foil 112, the third auxiliary copper foil 1130, and the fourth auxiliary copper foil 1140 through the upper surface of the lower bridge arm chip 4, flows through the second emitter signal terminal E2 and the second gate signal terminal G2, and flows out of the power semiconductor module from the DC negative terminal DC-.

[0072] Preferably, the upper arm chip 3 includes an upper arm IGBT chip UG and an upper arm diode chip UD, and the lower arm chip 4 includes a lower arm IGBT chip LG and a lower arm diode chip LD. The circuit topology of the implemented commutation loop is shown in FIG7 .

[0073] Preferably, the connection copper layer 11 of the first substrate is connected to the solder joint surface of the upper bridge arm chip 3 by vacuum reflow soldering, and the connection copper layer 21 of the second substrate is connected to the upper surface of the upper bridge arm chip 3 by vacuum reflow soldering. The connection copper layer 21 of the second substrate is connected to the solder joint surface of the lower bridge arm chip 4 by vacuum reflow soldering, and the connection copper layer 11 of the first substrate is connected to the upper surface of the lower bridge arm chip 4 by vacuum reflow soldering.

[0074] It can be understood that in the embodiment using the first conductive pad and the second conductive pad, the connection copper layer 11 of the first substrate is connected to the bottom surface of the first conductive pad by vacuum reflow soldering, the top surface of the first conductive pad is connected to the solder joint surface of the upper bridge arm chip 3 by vacuum reflow soldering, the connection copper layer 21 of the second substrate is connected to the bottom surface of the second conductive pad by vacuum reflow soldering, and the top surface of the second conductive pad is connected to the solder joint surface of the lower bridge arm chip 4 by vacuum reflow soldering.

[0075] Preferably, the materials of the first conductive pad and the second conductive pad include aluminum silicon carbide, molybdenum copper alloy or copper.

[0076] The present invention also discloses a power semiconductor package assembly, comprising at least three power semiconductor modules as described above, each of which is arranged in parallel in the same direction. A heat sink is connected to the outer copper layer of the first substrate and the outer copper layer of the second substrate of each power semiconductor module.

[0077] Specifically, in the above-mentioned packaging assembly, each power semiconductor module is arranged in parallel in the same direction. It can be understood that the power terminals of each power semiconductor module are distributed on the same side, and the first substrate and the second substrate in each power semiconductor module are in the same direction. Furthermore, the packaging assembly can be externally connected to a heat dissipation device that contacts the outer copper layer of each power semiconductor module, while achieving double-sided heat dissipation for each power semiconductor module in the packaging assembly. The packaging assembly obtained by the above is compatible with silicon-based power chips and silicon carbide power chips, and can be used to form a single three-phase full-bridge inverter, a dual three-phase full-bridge inverter, a boost circuit and other power electronic circuits, and can be used in motor control modules and vehicle assembly.

[0078] After adopting the above technical solution, compared with the existing technology, it has the following beneficial effects: the solder joint surface of the chip is directly connected to the connecting copper layer through the flip-chip technology, thereby reducing the vertical size of the power semiconductor module; by installing the upper bridge arm chip and the lower bridge arm chip on the first substrate and the second substrate in opposite directions, the pads connecting the first substrate and the second substrate can be reduced, thereby reducing the lateral size of the power semiconductor module; by providing an exposed outer copper layer, the power semiconductor module can perform double-sided heat dissipation.

[0079] It should be noted that the embodiments of the present invention have better practicability and do not impose any form of limitation on the present invention. Any technician familiar with the field may use the technical content disclosed above to change or modify it into an equivalent effective embodiment. However, any modification or equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A power semiconductor module with double-sided heat dissipation, characterized in that: The invention comprises a first substrate and a second substrate, wherein the first substrate and the second substrate each comprise a connection copper layer, an insulating dielectric layer, and an outer copper cladding layer, the insulating dielectric layer being arranged between the connection copper layer and the outer copper cladding layer; the first substrate and the second substrate are spaced apart and overlap in a vertical direction, so that the connection copper layer of the first substrate is opposite to the connection copper layer of the second substrate; An upper bridge arm chip is provided on the connection copper layer of the first substrate, the connection copper layer of the first substrate is connected to the solder joint surface of the upper bridge arm chip, and the connection copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip; A lower bridge arm chip is provided on the connection copper layer of the second substrate, the connection copper layer of the second substrate is connected to the solder joint surface of the lower bridge arm chip, and the connection copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip; A signal terminal and a power terminal are respectively provided on both sides between the connection copper layer of the first substrate and the connection copper layer of the second substrate.

2. The power semiconductor module according to claim 1, wherein: A first conductive pad is provided between the connection copper layer of the first substrate and the upper bridge arm chip, the connection copper layer of the first substrate is connected to the bottom surface of the first conductive pad, and the top surface of the first conductive pad is connected to the solder joint surface of the upper bridge arm chip, so that the height of the upper surface of the upper bridge arm chip is equal to the height of the upper surface of the signal terminal; A second conductive pad is arranged between the connecting copper layer of the second substrate and the lower bridge arm chip, so that the connecting copper layer of the second substrate is connected to the bottom surface of the second conductive pad, and the top surface of the second conductive pad is connected to the solder joint surface of the lower bridge arm chip, so that the height of the upper surface of the lower bridge arm chip is equal to the height of the lower surface of the signal terminal.

3. The power semiconductor module according to claim 1, wherein: The first substrate and the second substrate are installed in an insulating housing at intervals and overlap in the vertical direction, so that the connecting copper layer of the first substrate faces the connecting copper layer of the second substrate, and the outer copper layer of the first substrate faces the outer copper layer of the second substrate and is exposed outside the insulating housing respectively; The signal terminal and the power terminal are respectively exposed outside two sides of the insulating shell along a horizontal direction.

4. The power semiconductor module according to claim 3, characterized in that A positioning groove is provided on a side of the insulating housing close to the signal terminal and deviated from the center line of the insulating housing.

5. The power semiconductor module according to claim 1, wherein: The connecting copper layer of the first substrate includes a first main copper foil, a second main copper foil and a third main copper foil which are insulated from each other, and the connecting copper layer of the second substrate includes a fourth main copper foil, a fifth main copper foil and a sixth main copper foil which are insulated from each other; The first main copper foil is connected to the solder joint surface of the upper bridge arm chip, the second main copper foil is connected to the upper surface of the lower bridge arm chip, and the sixth main copper foil is connected to the solder joint surface of the lower bridge arm chip and the upper surface of the upper bridge arm chip; The power terminal includes a DC positive terminal, a DC negative terminal, and an AC terminal. The DC positive terminal is connected to the first main copper foil and the fourth main copper foil, the DC negative terminal is connected to the second main copper foil and the fifth main copper foil, and the AC terminal is connected to the third main copper foil and the sixth main copper foil. The commutation loop current enters the first main copper foil from the DC positive terminal, flows through the upper bridge arm chip and then enters the sixth main copper foil, flows through the AC terminal and the lower bridge arm chip, then enters the second main copper foil, and flows out of the power semiconductor module from the DC negative terminal.

6. The power semiconductor module according to claim 5, characterized in that The connecting copper layer of the first substrate further includes a first auxiliary copper foil, a second auxiliary copper foil, a third auxiliary copper foil, a fourth auxiliary copper foil and a fifth auxiliary copper foil that are insulated from each other, and the third auxiliary copper foil and the fourth auxiliary copper foil are respectively connected to the upper surface of the lower bridge arm chip; The connecting copper layer of the second substrate further includes a sixth auxiliary copper foil, a seventh auxiliary copper foil, an eighth auxiliary copper foil, a ninth auxiliary copper foil and a tenth auxiliary copper foil that are insulated from each other, and the seventh auxiliary copper foil and the eighth auxiliary copper foil are respectively connected to the upper surface of the upper bridge arm chip; The signal terminals include a first collector signal terminal, a second collector signal terminal, a first emitter signal terminal, a second emitter signal terminal, a first gate signal terminal and a second gate signal terminal; The first collector signal terminal is connected to the first main copper foil and the sixth auxiliary copper foil, the first emitter signal terminal is connected to the first auxiliary copper foil and the seventh auxiliary copper foil, the first gate signal terminal is connected to the second auxiliary copper foil and the eighth auxiliary copper foil, the second collector signal terminal is connected to the fifth auxiliary copper foil and the sixth main copper foil, the second emitter signal terminal is connected to the fourth auxiliary copper foil and the tenth auxiliary copper foil, and the second gate signal terminal is connected to the third auxiliary copper foil and the ninth auxiliary copper foil; The commutation loop current enters the first main copper foil from the DC positive terminal, flows through the first collector signal terminal and the upper bridge arm chip, and then enters the sixth main copper foil, the seventh auxiliary copper foil and the eighth auxiliary copper foil, respectively flows through the first emitter signal terminal, the first gate signal terminal, the AC terminal, the second collector signal terminal and the lower bridge arm chip, and then enters the second main copper foil, the third auxiliary copper foil and the fourth auxiliary copper foil, flows through the second emitter signal terminal and the second gate signal terminal, and flows out of the power semiconductor module from the DC negative terminal.

7. The power semiconductor module according to claim 1, wherein: The upper bridge arm chip includes an upper bridge arm IGBT chip and an upper bridge arm diode chip, and the lower bridge arm chip includes a lower bridge arm IGBT chip and a lower bridge arm diode chip.

8. The power semiconductor module according to claim 1, wherein: The connection copper layer of the first substrate is connected to the solder joint surface of the upper bridge arm chip by vacuum reflow soldering, and the connection copper layer of the second substrate is connected to the upper surface of the upper bridge arm chip by vacuum reflow soldering; The connecting copper layer of the second substrate is connected to the solder joint surface of the lower bridge arm chip through vacuum reflow soldering, and the connecting copper layer of the first substrate is connected to the upper surface of the lower bridge arm chip through vacuum reflow soldering.

9. The power semiconductor module according to claim 2, wherein: The materials of the first conductive pad and the second conductive pad include aluminum silicon carbide, molybdenum copper alloy or copper.

10. A power semiconductor package assembly, characterized in that: comprising at least three power semiconductor modules according to any one of claims 1 to 9, wherein the power semiconductor modules are arranged in parallel in the same direction; A heat sink is connected to the outer copper layer of the first substrate and the outer copper layer of the second substrate of each power semiconductor module respectively.

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