Circuit boards and fabrication method therefor, display module and display apparatus

Abstract

Provided in the present disclosure are circuit boards and a fabrication method therefor, a display module and a display apparatus, which can solve the problem of poor impedance matching effect in the prior art. A circuit board comprises: an insulating layer; a wire layer, which is located on the surface of one side of the insulating layer, the wire layer comprising an impedance unit and ground wires both extending in a first direction, two sides of the impedance unit being respectively provided with the ground wires in a second direction, and the second direction intersecting with the first direction; and a reference layer, which is located on the side of the insulating layer facing away from the wire layer, the reference layer comprising at least one reference line. The impedance unit comprises a plurality of impedance lines, and overlap positions of the orthographic projections of the at least two impedance lines on the reference layer and the reference line have an identical arrangement pattern.

Description

Circuit board and manufacturing method thereof, display module and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 2024101344791, filed on January 31, 2024, entitled “Circuit board, preparation method and wiring method thereof, display module, display device, computer equipment and storage medium,” and the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the technical field of electronic equipment, and in particular to a circuit board and a manufacturing method thereof, a display module, and a display device.

[0004] Background of the Invention

[0005] With the rapid development of electronic information technology, high-frequency signal transmission is increasingly being used in various fields. As a carrier for high-frequency signal transmission, circuit boards (PCBs) must ensure impedance matching during their design and manufacturing. However, current impedance matching in PCBs is poor. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a circuit board and a wiring method thereof, a display module, a display device, a computer equipment, and a storage medium to solve the problem of poor impedance matching in the prior art.

[0007] According to a first aspect of the present disclosure, a circuit board is provided, comprising: an insulating layer; a conductive wire layer, located on one surface of the insulating layer, the conductive wire layer comprising an impedance unit and a ground wire, both extending in a first direction; ground wires are provided on both sides of the impedance unit in a second direction, the second direction intersecting the first direction; and a reference layer, located on a side of the insulating layer facing away from the conductive wire layer, the reference layer comprising at least one reference wire; wherein the impedance unit comprises a plurality of impedance wires, and at least two impedance lines have the same arrangement pattern at a position where an orthographic projection of the reference layer and a reference line overlap.

[0008] A second aspect of the present disclosure provides another circuit board, comprising: an insulating layer; a conductor layer, located on one side surface of the insulating layer, the conductor layer comprising a single-ended wire and a ground wire, both extending in a first direction; ground wires are provided on both sides of the single-ended wire in a second direction, and the second direction intersects the first direction; and a reference layer, located on a side of the insulating layer facing away from the conductor layer, the reference layer comprising at least one reference wire; wherein the single-ended wire has multiple overlapping positions at which an orthographic projection of the reference layer overlaps with the reference line, and the multiple overlapping positions are arranged at equal intervals in the first direction.

[0009] A third aspect of the present disclosure provides a method for preparing a circuit board, comprising: providing an insulating layer; preparing a reference layer on one side of the insulating layer, the reference layer including at least one reference line; preparing a conductor layer on a side of the insulating layer facing away from the reference layer, the conductor layer including an impedance unit and a ground line extending along a first direction, ground lines being provided on both sides of the impedance unit in a second direction, and the second direction intersecting the first direction; the impedance unit including multiple impedance lines, at least two impedance lines having the same arrangement pattern at an overlapping position between an orthographic projection of the reference layer and the reference line; or, the conductor layer including a single-ended line and a ground line extending along a first direction, ground lines being provided on both sides of the single-ended line in a second direction, the second direction intersecting the first direction, the single-ended line having multiple overlapping positions between an orthographic projection of the reference layer and the reference line, and the multiple overlapping positions being arranged at equal intervals in the first direction.

[0010] A fourth aspect of the present disclosure provides a wiring method for a circuit board, which is used to design wiring for a reference line in the circuit board. The wiring method includes: obtaining a wire layer wiring diagram and a user-specified basic graphic, the wire layer wiring diagram including an impedance unit and a ground line both arranged along a first direction, and ground lines are respectively arranged on both sides of the impedance unit in a second direction, the second direction intersects with the first direction, the basic graphic includes any one of a basic grid and a basic sub-line, and the basic grid is an axisymmetric graphic; determining the position and size of the basic graphic based on any adjacent ground lines, the basic graphic is located between adjacent ground lines; copying the basic graphic, and arranging the copied graphics of the basic graphic in sequence along the first direction between adjacent ground lines to obtain a repeated unit to form a reference line; wherein the impedance unit includes multiple impedance lines, and at least two partial impedance lines have the same arrangement pattern at the overlapping position of the orthographic projection of the reference layer and the reference line.

[0011] A fifth aspect of the present disclosure provides a display module, comprising: a display panel; and a circuit board provided by any one of the above embodiments, wherein the circuit board and the display panel are electrically connected.

[0012] A sixth aspect of the present disclosure provides a display device, comprising the display module provided by the above embodiment.

[0013] The seventh aspect of the present disclosure provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor implements the steps of the wiring method provided in any embodiment of the present disclosure when executing the computer program.

[0014] An eighth aspect of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the wiring method provided in any embodiment of the present disclosure.

[0015] According to the circuit board and its preparation method and wiring method, display module, display device, computer equipment and storage medium provided by the embodiments of the present disclosure, by setting a regular arrangement of multiple impedance lines at the overlapping position of the orthographic projection of the reference layer and the reference line, it is ensured that the reference paths of different impedance lines on the reference line are consistent, thereby improving the impedance matching effect.

[0016] BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 a is a schematic diagram of a top view of a circuit board in the related art.

[0018] FIG1b is an enlarged schematic diagram of a local area Q in FIG1a.

[0019] FIG2 a is a schematic diagram of a top view of the circuit board provided in an embodiment of the present disclosure.

[0020] FIG2 b is a schematic diagram of the cross-sectional structure of the circuit board shown in FIG2 a along line A1A2.

[0021] FIG. 2 c is a schematic diagram of a first partial structure of the circuit board shown in FIG. 2 a .

[0022] FIG2 d is a schematic diagram of a second partial structure of the circuit board shown in FIG2 a .

[0023] FIG3 a is a schematic top view of the structure of a circuit board provided in another embodiment of the present disclosure.

[0024] FIG3 b is a schematic diagram of a partial structure of the circuit board shown in FIG3 a .

[0025] FIG3 c is a schematic diagram of a partial structure of the local structure shown in FIG3 b .

[0026] FIG4 is a schematic diagram of a top view of a circuit board provided in yet another embodiment of the present disclosure.

[0027] FIG5 is a schematic diagram of a top view of the structure of a circuit board provided in yet another embodiment of the present disclosure.

[0028] FIG6 is a schematic diagram of a top view of a circuit board provided in another embodiment of the present disclosure.

[0029] FIG7 is a schematic diagram of a top view of a circuit board provided in another embodiment of the present disclosure.

[0030] FIG8 is a schematic diagram of a top view of a circuit board provided in another embodiment of the present disclosure.

[0031] FIG9 is a schematic diagram of a top view of a circuit board provided in another embodiment of the present disclosure.

[0032] FIG10 is a schematic diagram of a top view of the structure of a circuit board provided in yet another embodiment of the present disclosure.

[0033] FIG11 is a schematic diagram of a top view of the structure of a circuit board provided in yet another embodiment of the present disclosure.

[0034] FIG12 is a flow chart of a wiring method for a circuit board provided in an embodiment of the present disclosure.

[0035] 13a to 13d are schematic diagrams of a first wiring process of executing the wiring method shown in FIG. 12 .

[0036] 14a to 14d are schematic diagrams of a second wiring process of executing the wiring method shown in FIG. 12 .

[0037] FIG15 is a flow chart of a wiring method for a circuit board provided in another embodiment of the present disclosure.

[0038] 16a-16c are schematic diagrams of the wiring process of executing the wiring method shown in FIG15.

[0039] FIG17 is a flowchart of a wiring method for a circuit board provided in yet another embodiment of the present disclosure.

[0040] FIG18 is a schematic structural diagram of a display module provided in accordance with an embodiment of the present disclosure.

[0041] FIG19 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.

[0042] FIG20 is a structural block diagram of a computer device provided in an embodiment of the present disclosure.

[0043] FIG21 is a flow chart of a method for preparing a circuit board provided in one embodiment of the present disclosure.

[0044] Modes for Carrying Out the Invention

[0045] Printed Circuit Board (PCB) and Flexible Printed Circuit (FPC) are carriers of high-speed transmission lines and are widely used in various electronic devices.

[0046] During the design and manufacturing of PCBs and FPCs, impedance matching is often required. Impedance matching is a strategy designed to efficiently transfer signal power from the source to the load while minimizing reflections. Impedance mismatches can lead to reflections, which can result in incomplete energy and signal transmission and adverse effects such as radiated interference.

[0047] Figure 1a is a schematic top view of a circuit board in the related art. As shown in Figure 1a, the circuit board includes multiple differential lines 210, which are used to transmit high-speed signals. A ground line 22 is provided on each side of a differential line pair. The circuit board also includes a reference line 31, which is located on a different conductive layer than the differential lines 210 and ground lines 22. Reference line 31 is electrically connected to ground line 22 via ground via 11. Reference line 31 and ground line 22 are used to provide impedance matching for the differential lines 210.

[0048] As shown in Figure 1a, to improve the impedance value, the reference line 31 is typically implemented as a mesh copper line. Figure 1b is an enlarged schematic diagram of the local area Q in Figure 1a. Combining Figures 1a and 1b, for ease of description, the two differential lines in a differential line pair are respectively denoted as the first differential line 211 and the second differential line 212. In the local area Q, the reference position of the first differential line 211 with respect to the reference line 31 includes the first reference point a1 and the second reference point a2, and the reference position of the second differential line 212 with respect to the reference line 31 includes the third reference point a3 and the fourth reference point a4. The first reference point a1 and the third reference point a3 are located at different positions on the corresponding reference line 31, and the second reference point a2 and the fourth reference point a4 are located at different positions on the corresponding reference line 31. It can be seen that the reference positions of different differential lines 210 with respect to the reference line 31 are not uniform. At the same time, as shown in Figure 1a, some ground vias 11 need to be connected to the reference line 31 via connecting ribs 32, causing the previously consistent mesh size and shape in the reference line 31 to become inconsistent. The above two reasons lead to inconsistent reference paths of reference lines of different differential line pairs, which in turn leads to impedance mismatch.

[0049] In view of this, the embodiments of the present disclosure provide a circuit board and its preparation method, wiring method, and display module, which redesign the reference lines so that the reference paths of different differential lines on the reference lines are consistent, thereby improving the impedance matching effect.

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0051] In addition, in order to better illustrate the present disclosure, numerous specific details are provided in the following detailed description. Those skilled in the art will understand that the present disclosure can be practiced without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the main purpose of the present disclosure.

[0052] Figure 2a is a schematic top view of a circuit board according to one embodiment of the present disclosure. Figure 2b is a schematic cross-sectional view of the circuit board shown in Figure 2a taken along line A1A2. As shown in Figures 2a and 2b , the circuit board includes an insulating layer 10, a conductive layer 20, and a reference layer 30, with the conductive layer 20 and the reference layer 30 located on opposite sides of the insulating layer 10.

[0053] The insulating layer 10 may be made of epoxy resin fiberglass cloth, pure resin glue or other materials.

[0054] The conductor layer 20 is located on one side of the insulating layer 10. The conductor layer 20 includes an impedance unit and a ground line 22, both extending along a first direction x. The impedance unit includes multiple impedance lines 21. Ground lines 22 are provided on either side of the impedance unit in a second direction y, intersecting the first direction x. Exemplarily, the second direction y is perpendicular to the first direction x. The impedance lines 21 are used to transmit high-speed signals and can be either differential or single-ended.

[0055] In the second direction y, a ground line 22 is provided on at least one side of each impedance line 21. For example, as shown in FIG2a , the impedance line 21 includes a differential line, and a ground line 22 is provided on both sides of each differential line pair. In this case, the ground lines 22 between adjacent differential line pairs can be combined into one, that is, a ground line 22 is provided between adjacent differential line pairs, and the ground line 22 is shared by the two groups of differential line pairs. In one embodiment, as shown in FIG2a , adjacent ground lines 22 are symmetrical about the first axis of symmetry L1, and the differential line pairs between adjacent ground lines 22 are axially symmetrically distributed about the first axis of symmetry L1. For another example, the impedance line 21 includes a single-ended line, and in the second direction y, the single-ended line and the ground line 22 are arranged alternately. In one embodiment, adjacent ground lines 22 are symmetrical about the first axis of symmetry L1, and the single-ended line between adjacent ground lines 22 coincides with the first axis of symmetry L1.

[0056] The reference layer 30 is located on a side of the insulating layer 10 away from the conductive layer 20. The reference layer 30 includes a reference line 31. The reference line 31 can be made of a metal with good conductivity, such as copper, silver, gold, or aluminum.

[0057] In the circuit boards shown in Figures 2a and 2b, the ground line 22 is connected to the reference line 31 through a ground hole 11 that penetrates the insulating layer 10, and the overlapping positions of the orthographic projections of at least two impedance lines 21 on the reference layer 30 and the reference line 31 have the same arrangement rule, and the arrangement rule includes the number of overlapping positions and the position coordinates of the overlapping positions in the first direction x; specifically, the same arrangement rule includes having the same number of overlapping positions, and the position coordinates of each overlapping position in the first direction x are the same.

[0058] Taking differential lines as an example, as shown in Figure 2a, the impedance unit includes at least one differential line pair, each of which includes two differential lines. The orthographic projections of the two differential lines in the at least one differential line pair on the reference layer 30 overlap with the reference line 31 in the same arrangement pattern, i.e., the number of overlapping locations corresponding to the two differential lines and the coordinates of each overlapping location are the same. Generally speaking, when an impedance unit includes differential lines, the number of differential lines is even and they are arranged in pairs, with each pair of differential lines forming a group.

[0059] For example, Figure 2c is a schematic diagram of a first partial structure of the circuit board shown in Figure 2a. As shown in Figure 2c, the impedance line 21 includes a set of differential line pairs, respectively denoted as a first differential line 211 and a second differential line 212. As can be seen from Figure 2c, there are four intersections between the orthographic projection of the first differential line 211 on the reference layer 30 and the reference line 31. In the first direction x, the coordinates of the four overlapping positions are denoted as P i , i = 1, 3, 5, 7. The second differential line 212 also includes four overlapping positions of the orthographic projection on the reference layer 30 and the reference line 31. In the first direction x, the coordinates of the four overlapping positions are sequentially recorded as Q j , j = 1, 3, 5, 7, when i = j, P i =Q j , that is, the arrangement rules of the first differential line 211 and the second differential line 212 are consistent. In addition, when i=j, P i =Q j , the overlapping position P of the first differential line 211 i The distance between the endpoint position of the orthographic projection of the first differential line 211 on the reference layer 30 and the overlapping position Q of the second differential line 212 j The distances from the endpoints of the orthographic projection of the second differential line 212 on the reference layer 30 are equal.

[0060] In one embodiment, the plurality of impedance lines include a plurality of differential line pairs, and the orthographic projections of the two differential lines in each differential line pair on the reference layer 30 and the overlapping positions of the reference line 31 have the same arrangement rule.

[0061] In one embodiment, the plurality of impedance lines include a plurality of differential line pairs, and the intersection positions of the orthographic projections of the differential lines in different differential line pairs on the reference layer 30 and the reference line 31 have the same arrangement pattern, but may also have different patterns. For example, the plurality of impedance lines include three differential line pairs, wherein the corresponding overlapping positions of the two differential lines in the first differential line pair have a first arrangement pattern, the corresponding overlapping positions of the two differential lines in the second differential line pair have a second arrangement pattern, and the corresponding overlapping positions of the two differential lines in the third differential line pair have a third arrangement pattern. Of course, in other embodiments, the first arrangement pattern is the same as the second arrangement pattern, and the first arrangement pattern is different from the third arrangement pattern; or the first arrangement pattern, the second arrangement pattern, and the third arrangement pattern are all the same.

[0062] In this embodiment, as shown in FIG2c , the orthographic projection of the same differential line on the reference layer 30 overlaps with the reference line 31 at multiple locations, and the multiple overlapping locations are arranged at equal intervals in the first direction x. Taking the first differential line 211 as an example, P1P3=P3P5=P5P7, where P1P3 refers to the spacing between the overlapping position P1 and the overlapping position P3. Similarly, P3P5 refers to the spacing between the overlapping position P3 and the overlapping position P5, and P5P7 refers to the spacing between the overlapping position P5 and the overlapping position P7. In other embodiments, the orthographic projection of the same differential line on the reference layer 30 overlaps with the reference line 31 at multiple locations, and the multiple overlapping locations are periodically arranged in the first direction x. For example, within the same arrangement period, the spacing between adjacent overlapping locations in the first direction x varies. In this embodiment, the variation means that the spacing between two adjacent overlapping locations increases or decreases in sequence, or decreases first and then increases, or increases first and then decreases. For example, taking the first differential line 211 as an example, P1P3<P3P5<P5P7 or P1P3>P3P5>P5P7 or P1P3>P3P5<P5P7 or P1P3<P3P5>P5P7, wherein P1P3 refers to the spacing between the overlapping position P1 and the overlapping position P3. Similarly, P3P5 refers to the spacing between the overlapping position P3 and the overlapping position P5, and P5P7 refers to the spacing between the overlapping position P5 and the overlapping position P7.

[0063] In one embodiment, the impedance unit includes an odd number of impedance lines, such as three impedance lines, five impedance lines, etc., and the impedance lines are single-ended lines. The intersection positions of the orthographic projection of each impedance line on the reference layer 30 and the reference line 31 have the same arrangement pattern. There are multiple intersection positions of the orthographic projection of the impedance line on the reference layer 30 and the reference line 31, and in the first direction x, the spacing between adjacent overlapping positions is equal or unequal. For example, the spacing between the second overlapping position and the third overlapping position corresponding to one impedance line is equal or unequal to the spacing between the second overlapping position and the third overlapping position corresponding to another impedance line.

[0064] Preferably, the spacing between adjacent overlapping positions corresponding to the same impedance line is equal, and the spacing between adjacent overlapping positions corresponding to different impedance lines in the first direction x is equal. In the above embodiments, the impedance lines all refer to the impedance lines in the same impedance unit.

[0065] According to the display panel provided in this embodiment, by setting the impedance line 21 to have an arrangement regularity at the overlapping position of the orthographic projection of the reference layer 30 and the reference line 31, the arrangement regularities corresponding to different impedance lines 21 are consistent, ensuring that the reference paths of different impedance lines 21 on the reference line 31 are consistent, thereby improving the impedance matching effect.

[0066] Figure 2d is a schematic diagram of a second partial structure of the circuit board shown in Figure 2a. As shown in Figure 2d and Figure 2a, the circuit board includes a reference line 31, which includes grid lines with uniform line width. The grid lines enclose multiple grids, each of which includes multiple basic grids BG. The multiple basic grids BG are arranged in an array along the first direction x and / or the second direction y. This regular arrangement is mainly located in the area where the ground wires and impedance units are located, and similar designs can be used in other areas. The orthographic projection of the basic grid BG on the conductor layer 20 is located between adjacent ground wires 22. Specifically, it can be located between the center lines of adjacent ground wires 22, that is, the orthographic projection of the basic grid BG partially overlaps with the ground wires 22. The basic grid BG is an axially symmetrical figure, symmetrical about the second axis of symmetry L2, which is parallel to the first direction x. For example, the orthographic projection of the first axis of symmetry L1 in the reference layer 30 coincides with the second axis of symmetry L2.

[0067] Specifically, as shown in FIG2d , adjacent ground lines 22 include a first ground line 221 and a second ground line 222 that are adjacently arranged. The first ground line 221 includes a first outer edge away from the second ground line 222, and the second ground line 222 includes a second outer edge away from the first ground line 221. As mentioned herein, the orthographic projection of the base grid BG on the conductor layer 20 is located between the adjacent ground lines 22, which means that the orthographic projection of the base grid BG does not exceed the area between the first outer edge and the second outer edge. Exemplarily, the first ground line 221 includes a first center line, the second ground line 222 includes a second center line, and the orthographic projection of the base grid BG on the conductor layer 20 is located between the first center line and the second center line.

[0068] In the array of basic grids BG, adjacent basic grids BG in the first direction x can intersect or be spaced apart; adjacent basic grids BG in the second direction y can intersect or be spaced apart. The adjacent basic grids BG intersecting here means that the adjacent basic grids BG have common vertices or common edges. Correspondingly, adjacent basic grids BG spaced apart means that the adjacent basic grids BG do not have common vertices and common edges. When adjacent basic grids BG are spaced apart, the adjacent basic grids BG can be connected by connecting lines to form a reference line 31 of the mesh structure.

[0069] In an array of base grids BG, as shown in FIG2a , adjacent base grids BG are symmetrical about a third axis of symmetry L3 in a first direction x, and the third axis of symmetry L3 is parallel to the second direction y. In a second direction y, adjacent base grids BG are symmetrical about a fourth axis of symmetry L4, and the fourth axis of symmetry L4 is parallel to the first direction x. In this case, the shapes of adjacent base grids BG in the first direction x can be identical, as shown in FIG2a ; of course, the shapes of adjacent base grids BG in the first direction x can also be different. The different shapes of adjacent base grids BG can mean that one of the adjacent base grids BG is obtained by rotating the other, as shown in FIG7 (details are provided below).

[0070] As shown in Figures 2a and 2d, the base grid BG can be a rectangular grid. The impedance lines 21 include differential lines. A ground line 22 is provided on either side of each differential line pair, and a ground line 22 is provided between adjacent differential line pairs. The orthographic projection of the first axis of symmetry L1 is located between the differential line pairs, and the differential line pairs are symmetrical about the first axis of symmetry L1. This ensures that the reference positions of the base grid BG of two differential line pairs in the group are consistent, and that the reference positions of the base grids BG of different differential line pairs are consistent. The reference position mentioned here is also the overlapping position mentioned above.

[0071] It should be understood that if the impedance line 21 includes a single-ended line, the single-ended line and the ground line 22 are arranged alternately in the second direction y. The orthographic projection of the middle single-ended line among the odd-numbered lines coincides with the first symmetry axis L1. This ensures that the reference positions of different single-ended lines with respect to the base grid BG are consistent.

[0072] In one embodiment, as shown in FIG2a , the ground hole 11 is located on the reference line 31. In this way, there is no need to provide additional connecting ribs on the reference layer 30 to connect the ground hole 11 and the reference line 31, thereby preventing the connecting ribs from destroying the structural consistency of the reference line 31.

[0073] In one embodiment, as shown in FIG. 2 a , the ground holes 11 on adjacent ground lines 22 are axially symmetrically distributed about the first symmetry axis L1 .

[0074] In one embodiment, as shown in FIG2a , at least some of the ground holes 11 are located at the intersections of the grid lines. Grid lines include intersections and connecting lines, and the connecting lines intersect at the intersections to form grid lines. For example, the orthographic projections of all ground holes 11 on the reference layer 30 are located at the intersections of the grid lines. For another example, some of the ground holes 11 are located at the intersections of the grid lines, and the remaining ground holes 11 are located at the connecting lines of the grid lines. For example, referring to FIG2a , additional ground holes 11 can be provided on the grid lines extending along the first direction x and between adjacent ground holes 11, as shown by the hollow dots in FIG2a . The additional ground holes 11 are located on the connecting lines of the grid lines, rather than on the intersections of the grid lines.

[0075] Figure 3a is a schematic diagram of the top structure of a circuit board provided by another embodiment of the present disclosure. As shown in Figure 3a, the difference between the circuit board provided by this embodiment and the circuit board shown in Figure 2a is that, in this embodiment, in the first direction x, the adjacent vertices of adjacent basic grids BG overlap, in the second direction y, the adjacent vertices of adjacent basic grids BG overlap, and in the first direction x and the second direction y, the adjacent edges of adjacent basic grids BG do not overlap. In this case, the multiple grids also include a reconstructed grid CG. In the array of basic grids BG, the adjacent edges of multiple adjacent basic grids BG enclose to form a reconstructed grid CG. The shapes of the basic grid BG and the reconstructed grid CG may be the same or different. The area of ​​the reconstructed grid CG may be equal to or different from the area of ​​the basic grid BG.

[0076] For example, as shown in Figure 3a, the base grid BG is a diamond grid. In this case, the two diagonals of the base grid BG are parallel to the first direction x and the second direction y, respectively. In the array of base grids BG, the adjacent edges of four adjacent base grids BG enclose a reconstructed grid CG, which is also a diamond grid, and the area of ​​the reconstructed grid CG is equal to the area of ​​the base grid BG. In this way, the multiple diamond grids in the entire reference line 31 are arranged in an array along the third direction z and the fourth direction p. The third direction z and the fourth direction p are the extension directions of two adjacent edges of the diamond grid, respectively.

[0077] Figure 3b is a schematic diagram of a partial structure of the circuit board shown in Figure 3a. Figure 3c is a schematic diagram of a portion of the partial structure shown in Figure 3b. In conjunction with Figures 3b and 3c, in this embodiment, the arrangement pattern of the intersections of the orthographic projection of impedance lines 21 on reference layer 30 and reference lines 31 includes: the intersections corresponding to the same impedance lines 21 are arranged according to a pattern alternating between first intervals D1 and second intervals D2. The first intervals D1 and second intervals D2 are unequal.

[0078] Specifically, as shown in FIG3b and FIG3c, the same impedance line 21 corresponds to six overlapping positions. In the first direction x, the six overlapping positions are sequentially denoted as Pm , m=1, 2, 3, 4, 5, 6. Among them, P1P2=P3P4=P5P6=D1, P2P3=P4P5=D2, among which P1P2 refers to the spacing between the overlapping position P1 and the overlapping position P2. Similarly, P3P4 refers to the spacing between the overlapping position P3 and the overlapping position P4, P5P6 refers to the spacing between the overlapping position P5 and the overlapping position P6, P2P3 refers to the spacing between the overlapping position P2 and the overlapping position P3, and P4P5 refers to the spacing between the overlapping position P4 and the overlapping position P5.

[0079] Figure 4 is a schematic top view of a circuit board according to another embodiment of the present disclosure. As shown in Figure 4 , the circuit board according to this embodiment differs from the circuit board shown in Figure 3a in that the area of ​​the base grid BG in the circuit board according to this embodiment is smaller than that in the circuit board shown in Figure 3a.

[0080] Specifically, in this embodiment, the angles of the two diagonal corners of the basic grid BG in the first direction x are α1, and the angles of the two diagonal corners in the second direction y are β1. In the circuit board shown in Figure 3a, the angles of the two diagonal corners of the basic grid BG in the first direction x are α2, and the angles of the two diagonal corners in the second direction y are β2. Here, |α1-β1|<|α2-β2|. Accordingly, in this embodiment, the spacing between adjacent ground vias 11 in the first direction x is smaller than the spacing between adjacent ground vias 11 in the first direction x in the circuit board shown in Figure 3a.

[0081] The area of ​​the base grid BG can be determined based on the residual copper ratio, which needs to be determined based on the actual impedance requirements. The reference line 31 can be obtained by etching the entire copper layer. In this case, the residual copper ratio refers to the ratio of the area of ​​the reference line 31 to the area of ​​the entire copper layer.

[0082] Figure 5 is a schematic diagram of a top view of a circuit board provided by another embodiment of the present disclosure. As shown in Figure 5 , the difference between this circuit board and the circuit board shown in Figure 4 is that the shapes of the base grid BG and the reconstructed grid CG are different.

[0083] Specifically, as shown in Figure 5, in this embodiment, the base grid BG is an elliptical grid. The base grids BG are arranged in an array along the first direction x and the second direction y. Within the array of base grids BG, adjacent segments of four adjacent base grids BG form a reconstructed grid CG, which is an irregular shape. As shown in Figure 5, the reconstructed grid CG includes four concave curved edges, which intersect in pairs to form the reconstructed grid CG.

[0084] In this embodiment, the ground hole 11 and the vertices of the basic grid BG in the second direction y coincide with each other.

[0085] Figure 6 is a schematic top view of a circuit board according to another embodiment of the present disclosure. As shown in Figure 6, this circuit board differs from the circuit boards shown in Figures 3a, 4, and 5 in that, in this embodiment, adjacent vertices of adjacent base meshes BG overlap in the first direction x, and adjacent edges of adjacent base meshes BG overlap in the second direction y. The reconstructed mesh CG and the base mesh BG have different shapes.

[0086] For example, the base grid BG includes a hexagonal grid, each of which includes two sides parallel to the first direction x, and the two sides are arranged opposite each other. Multiple base grids BG are arranged in an array in the first direction x and the second direction y. In this case, in the array of base grids BG, adjacent sides of four adjacent base grids BG form a reconstructed grid CG, which is a diamond grid, and the two diagonals of the diamond grid are parallel to the first direction x and the second direction y.

[0087] In this embodiment, the ground hole 11 and the vertices of the base grid BG coincide with each other. For example, as shown in Figure 6 , one vertex of an edge of the base grid BG extending along the first direction x coincides with the ground hole 11. In other embodiments, two vertices of an edge of the base grid BG extending along the first direction x may each coincide with a ground hole 11.

[0088] Figure 7 is a top-down schematic diagram of a circuit board according to another embodiment of the present disclosure. As shown in Figure 7 , this circuit board differs from any of the aforementioned embodiments in that, in this embodiment, the base grid BG is axially symmetrical rather than centrosymmetrical. In this case, adjacent base grids BG are axially symmetrical in the first direction x, with the axis of symmetry parallel to the second direction y.

[0089] Specifically, as shown in Figure 7, the base grid BG comprises isosceles trapezoidal grids, each with its upper and lower bases parallel to the second direction y. In the first direction x, the upper bases of adjacent isosceles trapezoidal grids coincide, or the lower bases of adjacent isosceles trapezoidal grids coincide. In an array of base grids BG, adjacent edges of four adjacent base grids BG form a diamond grid, i.e., the reconstructed grid CG.

[0090] In this embodiment, two vertices of the side of the basic grid BG extending along the second direction y respectively coincide with one ground hole 11 .

[0091] Figure 8 is a top-down schematic diagram of a circuit board provided in yet another embodiment of the present disclosure. As shown in Figure 8 , this circuit board differs from any of the aforementioned embodiments in that, in this embodiment, the circuit board includes multiple reference lines 31, which are arranged along a first direction x. Multiple reference lines are spaced apart along a second direction y, with the first direction x and the second direction y intersecting. For example, the first direction x is perpendicular to the second direction y. The orthographic projections of the reference lines on the conductor layer 20 are located between adjacent ground lines 22.

[0092] In one embodiment, as shown in FIG. 8 , the reference line 31 includes basic sub-lines ab, and the basic sub-lines are sequentially connected to form the reference line 31 .

[0093] For example, the basic sub-line ab includes a central segment cd, whose orthographic projection in the conductor layer 20 is located between adjacent edge lines of adjacent ground lines 22. The orthographic projection of the central segment cd in the reference layer 30 is symmetrical about the first symmetry axis L1. This ensures that the reference position of the impedance line 21 between adjacent ground lines 22 with respect to the basic sub-line ab is consistent.

[0094] In one embodiment, as shown in FIG8 , the basic sub-line ab further includes a first straight segment ae, a first arc segment ec, a second arc segment df, a second straight segment fg, and a third straight segment gb. In the first direction x, the first straight segment ae, the first arc segment ec, the central segment cd, the second arc segment df, the second straight segment fg, and the third straight segment gb are sequentially connected. The arc centers of the first arc segment ec and the second arc segment df are located on either side of the central segment cd, respectively. In other embodiments, the first arc segment ec and the second arc segment df may also be line segments or an inflection point.

[0095] In one embodiment, the ground hole 11 at least coincides with the endpoint of the basic sub-line ab. In the first direction x, among adjacent basic sub-lines ab, the rear endpoint b of the preceding basic sub-line ab coincides with the front endpoint a of the succeeding basic sub-line ab, i.e., the rear endpoint b of the preceding basic sub-line ab is also the front endpoint a of the succeeding basic sub-line ab.

[0096] Figure 9 is a schematic top view of a circuit board according to another embodiment of the present disclosure. As shown in Figure 9 , the circuit board according to this embodiment differs from the circuit board shown in Figure 8 in that the shapes of the basic sub-lines ab are different.

[0097] Specifically, in this embodiment, adjacent basic sub-lines ab are symmetrical about the fifth symmetry axis L5, that is, a basic sub-line ab is provided on both sides of the fifth symmetry axis L5, and the two basic sub-lines ab are connected end to end. The fifth symmetry axis L5 is parallel to the second direction y.

[0098] In this embodiment, there are multiple ways to divide the basic sub-lines ab.

[0099] For example, in the first division method, the basic sub-line ab includes a central segment cd, a first straight segment ae, a first arc segment ec, a second arc segment df, and a second straight segment fb. In the first direction x, the first straight segment ae, the first arc segment ec, the central segment cd, the second arc segment df, and the second straight segment fb are sequentially connected, with the arc centers of the first arc segment ec and the second arc segment df located on either side of the central segment cd, respectively. In other embodiments, the first arc segment ec and the second arc segment df may also be line segments.

[0100] In the second division method, the basic sub-line ab includes two adjacent basic sub-lines ab in the first division method. For easy distinction, the basic sub-line ab in the first division method is recorded as basic sub-line ab1, and the basic sub-line ab in the second division method is recorded as basic sub-line ab2, as shown in FIG9 .

[0101] The third division method is to record the basic sub-line ab as the basic sub-line ab3 for the convenience of distinction. The basic sub-line ab3 includes the first straight line segment ag, the first arc segment gh, the second straight line segment hi, the second arc segment ij, the third straight line segment jk, the third arc segment kl, the fourth straight line segment lm, the fourth arc segment mn, and the fifth straight line segment nb connected in sequence.

[0102] Figure 10 is a schematic top view of a circuit board provided in another embodiment of the present disclosure. As shown in Figure 10, in this embodiment, the conductor layer includes multiple ground lines 22 and multiple impedance units, which are alternately arranged in the second direction y. At least one impedance unit includes multiple single-ended lines 220, and the remaining impedance units include at least one set of differential line pairs 210. That is, the circuit board provided in this embodiment includes both single-ended lines 220 and differential line pairs 210. The single-ended lines 220 and the differential lines in the differential line pairs 210 are both arranged along the first direction x.

[0103] In one embodiment, the impedance unit includes an odd number of single-ended lines, such as three or five single-ended lines. The overlapping positions corresponding to the single-ended lines are arranged at equal intervals. Among the multiple overlapping positions corresponding to different single-ended lines, the spacing between adjacent overlapping positions is equal or unequal.

[0104] In one embodiment, each single-ended line has the same arrangement rule at the overlapping position of the orthographic projection of the reference layer 30 and the reference line.

[0105] In one embodiment, the single-ended line has multiple overlapping positions between its orthographic projection on the reference layer 30 and the reference line, and the spacing between adjacent overlapping positions in the first direction x is equal among the multiple overlapping positions; of course, in other embodiments, the spacing between adjacent overlapping positions in the first direction x is not equal among the multiple overlapping positions.

[0106] In one embodiment, the differential line pair 210 includes two differential lines. The two differential lines in at least one differential line pair 210 have the same arrangement rule at the intersection of their orthographic projections on the reference layer 30 and the reference line.

[0107] In one embodiment, the plurality of impedance lines include a plurality of differential line pairs, and the arrangement pattern of the two differential lines in each differential line pair at the overlapping positions of the orthographic projections of the two differential lines on the reference layer 30 and the reference lines is the same.

[0108] In one embodiment, the plurality of impedance lines include a plurality of differential line pairs, and the arrangement rules of the overlapping positions of the orthographic projections of the differential lines of different differential line pairs on the reference layer 30 and the reference lines are the same or different.

[0109] In one embodiment, there are multiple overlapping positions between the orthographic projection of the differential line on the reference layer 30 and the reference line, and the multiple overlapping positions are arranged at equal intervals in the first direction x.

[0110] In one embodiment, there are multiple overlapping positions between the orthographic projection of the differential line on the reference layer 30 and the reference line, and the multiple overlapping positions are periodically arranged in the first direction x.

[0111] Furthermore, within the same arrangement period, the spacing between adjacent overlapping positions in the first direction x changes gradually.

[0112] In one embodiment, adjacent ground lines are symmetrical about a first symmetry axis, and differential line pairs between adjacent ground lines are axially symmetrically distributed about the first symmetry axis.

[0113] Technical details not described in this embodiment can be found in any of the above embodiments and will not be repeated here.

[0114] Figure 11 is a schematic top view of a circuit board according to another embodiment of the present disclosure. As shown in Figure 11 , in this embodiment, the conductor layer includes a single-ended conductor 220 and a ground conductor 22, both extending along a first direction x. In a second direction y, ground conductors 22 are provided on either side of the single-ended conductor 220, i.e., the single-ended conductor 220 and the ground conductor 22 are alternately arranged in the second direction y. Multiple single-ended conductors 220 are provided at the intersection of the orthographic projection of the reference layer and the reference conductor, and these overlapping locations are evenly spaced in the first direction x.

[0115] In one embodiment, the device further includes an impedance unit and a ground line 22 extending along a first direction x, and ground lines 22 are provided on both sides of the impedance unit in a second direction y, wherein the second direction y intersects the first direction x;

[0116] The impedance unit includes multiple impedance lines, and at least two of the impedance lines have the same arrangement pattern at the intersection of the orthographic projection of the reference layer and the reference line. This structural design is the same as any embodiment in the previous solution, and the specific description can refer to the previous embodiment.

[0117] For example, as shown in FIG11 , the impedance unit includes a differential line pair 210, with ground lines 22 disposed on both sides of the differential line pair 210 in the second direction y. The differential line pair 210 includes two differential lines, one extending in the first direction x and the other arranged in the second direction y. This means that the circuit board provided in this embodiment includes both single-ended lines 220 and differential line pairs 210.

[0118] The difference between the circuit board shown in FIG11 and the circuit board shown in FIG10 is that part of the impedance units in the circuit board shown in FIG10 include multiple single-ended lines, while part of the impedance units in the circuit board shown in FIG11 include one single-ended line.

[0119] Technical details not described in this embodiment can be found in any of the above embodiments and will not be repeated here.

[0120] In addition, in other embodiments, multiple single-ended lines can be set between two adjacent ground lines 22. For the same single-ended line, it is arranged at equal intervals at adjacent overlapping positions on the reference layer, and the spacing between adjacent overlapping positions on different single-ended lines in the first direction x may not be equal.

[0121] The present disclosure also provides a wiring method for a circuit board. FIG12 is a flow chart of a wiring method for a circuit board provided in one embodiment of the present disclosure. FIG13a-FIG13d are schematic diagrams of a first wiring process for executing the wiring method shown in FIG12. The wiring method shown in FIG12 is used to draw reference lines in a circuit board provided in any of the above embodiments, given a known wiring diagram of a ground line and an impedance line. The wiring method can be executed by a computer. As shown in FIG12, wiring method 1200 includes:

[0122] Referring to FIG. 13 a , step S1210 , a conductor layer wiring diagram and a user-specified basic graphic are obtained.

[0123] The conductor layer wiring diagram is pre-stored in the computer. The basic graphics can be pre-stored in the computer or drawn by the user in real time.

[0124] The conductor layer wiring diagram includes an impedance unit and multiple ground lines 22, all arranged along a first direction x. The impedance unit includes multiple impedance lines 21. Ground lines 22 are provided on either side of the impedance unit in a second direction y, intersecting the first direction x. Exemplarily, the second direction y is perpendicular to the first direction x. Impedance lines 21 are used to transmit high-speed signals and can be differential or single-ended lines.

[0125] For example, as shown in FIG13a , the impedance line 21 includes differential lines, and a ground line 22 is provided on both sides of a differential line pair. In this case, the ground lines 22 between adjacent differential line pairs can be combined into one, that is, a ground line 22 is provided between adjacent differential line pairs, and the ground line 22 is shared by the two groups of differential line pairs. In one embodiment, as shown in FIG13a , adjacent ground lines 22 have a first axis of symmetry L1, and the differential line pairs between adjacent ground lines 22 are axially symmetric about the first axis of symmetry L1. For another example, the impedance line 21 includes single-ended lines, and in the second direction y, the single-ended lines and the ground lines 22 are arranged alternately. In one embodiment, adjacent ground lines 22 have a first axis of symmetry L1, and the middle single-ended line among the odd-numbered adjacent ground lines 22 coincides with the first axis of symmetry L1.

[0126] The basic graphic includes a basic grid BG. The basic grid BG is axially symmetrical and has a second axis of symmetry L2. The basic grid BG includes any one of a polygon, an ellipse, and a circle. The polygon is, for example, a rhombus, a hexagon, a trapezoid, a rectangle, etc.

[0127] Referring to FIG. 13 b , step S1220 , the position and size of the basic graphic are determined based on any adjacent ground lines. The basic graphic is located between the adjacent ground lines, and the symmetry axis of the basic graphic is located on the first symmetry axis of the adjacent ground lines.

[0128] On the premise that the wiring pattern of the conductor layer is known, the position of the basic pattern can be determined based on the first symmetry axis L1 of any adjacent ground line 22 .

[0129] Specifically, referring to Figure 13b , the second symmetry axis L2 of the base grid BG is set on the first symmetry axis L1, i.e., the second symmetry axis L2 and the first symmetry axis L1 coincide. The size of the base grid BG is then adjusted based on the distance between adjacent ground lines 22, so that the base grid BG is located exactly between the adjacent ground lines 22. For example, in this embodiment, the base grid BG is located exactly between the center lines of adjacent ground lines 22.

[0130] Referring to FIG. 13 c , step S1230 , the basic pattern is copied, and the copied patterns of the basic pattern are sequentially arranged along the first direction between adjacent ground lines to obtain repeating units to form reference lines.

[0131] Among them, at least two impedance lines have the same arrangement rule at the overlapping position of the orthographic projection of the reference layer and the reference line. The arrangement rule is the same as any embodiment in the previous scheme. For specific description, please refer to the previous embodiment.

[0132] In the first direction x, adjacent replicated graphics 41 intersect, for example, adjacent vertices or adjacent edges of adjacent replicated graphics 41 overlap. Alternatively, adjacent replicated graphics 41 are arranged at intervals. In this case, adjacent replicated graphics 41 can be connected by line segments.

[0133] The copied graphic 41 is actually also a basic graphic. For the convenience of description, the graphic obtained by copying the basic graphic is referred to as the copied graphic.

[0134] The wiring method 1200 in this embodiment further includes the following steps performed after step S1230: referring to FIG. 13 d , step S1240 : replicating the repeating units and arranging the repeating units in sequence along the second direction.

[0135] In the second direction y, adjacent repeating units intersect; alternatively, adjacent repeating units are arranged in an alternating pattern. Adjacent repeating units intersect, meaning that adjacent vertices or edges of adjacent basic figures in the second direction y coincide. Adjacent repeating units are arranged in an alternating pattern, meaning that adjacent basic figures in the second direction y are arranged in an alternating pattern.

[0136] According to the wiring method provided in this embodiment, it can be ensured that the impedance line 21 has an arrangement regularity at the overlapping position of the orthographic projection of the reference layer 30 and the reference line 31, and the arrangement regularities corresponding to different impedance lines 21 are consistent, thereby making the reference paths of different impedance lines 21 on the reference line 31 consistent, thereby improving the impedance matching effect.

[0137] In one embodiment, the basic graphic in the wiring method 1200 may also be a basic sub-line ab. Figures 14a to 14d are schematic diagrams of a second wiring process for executing the wiring method shown in Figure 12. Figures 14a to 14d illustrate the process of obtaining the reference line 31 based on the wiring method 1200 shown in Figure 12 when the basic graphic is the basic sub-line ab. The basic sub-line ab may be a curve or a line segment, or any combination of the two. For example, the basic sub-line ab has a virtual symmetry axis L0, and after the portion of the basic sub-line on one side of the virtual symmetry axis L0 is mirror-flipped, it becomes symmetrical with the portion on the other side of the virtual symmetry axis L0 about the virtual symmetry axis L0.

[0138] 14a, according to step S1210, a wiring diagram of a conductor layer and a basic graphic specified by a user are obtained. For example, the basic graphic is a basic sub-line ab.

[0139] 14b, according to step S1220, the position and size of the basic graphic are determined based on any adjacent ground lines. The basic graphic is located between the adjacent ground lines, and the (virtual) symmetry axis of the basic graphic is located on the first symmetry axis of the adjacent ground lines.

[0140] Given a known conductor layer layout, the position of the basic pattern can be determined based on the first axis of symmetry L1 of any adjacent ground lines 22. Specifically, the virtual axis of symmetry L0 of the basic sub-line ab is set on the first axis of symmetry L1. The size of the basic sub-line ab is then adjusted based on the distance between adjacent ground lines 22, so that the basic sub-line af is located exactly between the adjacent ground lines 22. For example, in this embodiment, the basic sub-line ab is located exactly between the centerlines of adjacent ground lines 22.

[0141] Referring to FIG. 14 c , according to step S1230 , the basic pattern is copied, and the copied patterns of the basic pattern are sequentially arranged along the first direction between adjacent ground lines to obtain repeating units, thereby forming a reference line.

[0142] In the first direction x, adjacent replicated graphics 41 intersect, for example, adjacent vertices or adjacent edges of adjacent replicated graphics 41 overlap. Alternatively, adjacent replicated graphics 41 are arranged at intervals. In this case, adjacent replicated graphics 41 can be connected by lines.

[0143] The copied graphic 41 is actually also a basic graphic. For the convenience of description, the graphic obtained by copying the basic graphic is referred to as the copied graphic.

[0144] Referring to FIG. 14 d , the repeating unit 40 is replicated and arranged sequentially along the second direction y.

[0145] In the second direction y, adjacent repeating units 40 are arranged at intervals.

[0146] Figure 15 is a flow chart of a wiring method for a circuit board provided in another embodiment of the present disclosure. Figures 16a and 16c are schematic diagrams of the wiring process for executing the wiring method shown in Figure 15. As shown in Figure 15, the wiring method 1500 provided in this embodiment differs from the wiring method 1200 shown in Figure 12 in that, in this embodiment, step S1230 includes step S1231 and step S1232. Wiring method 1500 also includes step S1510, which is performed between step S1231 and step S1232, and step S1520, which is performed after step S1230.

[0147] Specifically, referring to Figure 16a, step S1210 is first performed. For example, the reference pattern is an isosceles trapezoidal grid.

[0148] Next, referring to FIG. 16 a , step S1220 is executed to determine the position and size of the basic graphic based on any adjacent ground lines. The basic graphic is located between the adjacent ground lines, and the symmetry axis of the basic graphic is located on the first symmetry axis of the adjacent ground lines.

[0149] Again, referring to FIG. 16 b , according to step S1231 , the basic graphic is copied to obtain a copied graphic.

[0150] Next, referring to FIG. 16 b , according to step S1510 , the duplicated graphic of the basic graphic is rotated to obtain a secondary duplicated graphic.

[0151] The secondary copy graphic 42 is actually also a basic graphic. For the convenience of description, the basic graphic is copied and rotated 180° to obtain the graphic referred to as the secondary copy graphic 42 .

[0152] Then, referring to FIG. 16 b , according to step S1032 , secondary replicated patterns are arranged at even positions and replicated patterns are arranged at odd positions between adjacent ground lines along the first direction to obtain repeating units and form reference lines.

[0153] Finally, referring to FIG. 16 c , step S1520 is executed to replicate the repeating unit and arrange the repeating units in sequence along the second direction.

[0154] FIG17 is a flow chart of a wiring method for a circuit board provided in a third embodiment of the present disclosure. As shown in FIG17 , the wiring method 1700 provided in this embodiment is based on the wiring method provided in any of the above embodiments, taking the wiring method 1200 as an example, and further includes:

[0155] 2a-9, step S1710, at least one fixed point is determined on the reference line to serve as a ground hole, the fixed point includes a vertex or end point of the basic figure, and the orthographic projection of the fixed point on the conductor layer wiring diagram is located on the ground line.

[0156] In one embodiment, the ground holes 11 on adjacent ground lines 22 are distributed axially symmetrically about the first symmetry axis L1 .

[0157] In one embodiment, the reference lines 31 include grid lines. In this case, at least some of the ground holes 11 are located at the intersections of the grid lines. For example, the orthographic projections of all ground holes 11 on the reference layer 30 are located at the intersections of the grid lines. In another example, some of the ground holes 11 are located at the intersections of the grid lines, while the remaining ground holes 11 are located at the connecting lines of the grid lines. For example, referring to FIG. 2a , additional ground holes 11 may be provided between adjacent ground holes 11 on the grid lines extending along the first direction x. Such additional ground holes 11 are located on the connecting lines of the grid lines, rather than at the intersections of the grid lines.

[0158] In one embodiment, the reference line includes a reference line, the reference line includes a basic sub-line, and the ground hole 11 is located at an end point of the basic sub-line.

[0159] FIG18 is a schematic diagram of the structure of a display module provided in an embodiment of the present disclosure. As shown in FIG18 , the display module includes: a display panel 50 and a circuit board 60 provided in any of the above embodiments, wherein the circuit board 60 and the display panel 50 are bonded to each other.

[0160] The display panel 50 may be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a quantum dot electroluminescent display panel, or the like.

[0161] The circuit board 60 is used to provide a high-speed video signal to the display panel 50 to drive the display panel 50 to realize a display function.

[0162] The display module provided in this embodiment can be applied to a display device. FIG19 is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. As shown in FIG19 , the display device includes the display module 70 shown in FIG18 .

[0163] The display device can be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0164] In addition, the display device can also have functions such as taking pictures, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device also includes at least one functional module for realizing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, etc.

[0165] The present disclosure also provides a computer device. Figure 20 is a block diagram of the computer device provided in one embodiment of the present disclosure. As shown in Figure 20, computer device 80 includes: memory 81, processor 82, and a computer program stored in memory 81 and executed by processor 82. When processor 82 executes the computer program, it implements the steps of the wiring method provided in any of the above embodiments.

[0166] The memory 81 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory includes random access memory (RAM) and / or cache memory. Non-volatile memory includes read-only memory (ROM), a hard disk, flash memory, etc. The memory 81 may also store a correspondence table between special characters and pronunciation categories.

[0167] The processor 82 may be a processing unit having data processing capability and / or instruction execution capability, such as a central processing unit (CPU).

[0168] The computer program may be written in one or more programming languages. Programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C. The computer program may be executed entirely on the computer device 80, partially on the computer device 80 and partially on a server, or as a standalone software package.

[0169] In one embodiment, computer device 80 further includes an input device 83 and an output device 84, each connected to processor 82. Input device 83 may be a microphone or microphone array for capturing sound signals. Input device 83 may also be a keyboard, mouse, etc. Output device 84 may output various information, including the determined speech category. Output device 84 may be a display, speaker, printer, etc.

[0170] The present disclosure further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the wiring method provided in any of the above embodiments are implemented.

[0171] Computer-readable storage media can be any combination of one or more computer-readable media. Computer-readable storage media can be in any form of electrical, magnetic, optical, electromagnetic, infrared, semiconductor, or any combination thereof. For example, computer-readable storage media include hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, and the like.

[0172] The present disclosure also provides a method for preparing a circuit board. FIG21 is a flow chart of a method for preparing a circuit board provided in one embodiment of the present disclosure. As shown in FIG21 , in combination with the circuit board provided in any of the above embodiments, the preparation method 2100 includes:

[0173] Step S2110: providing an insulating layer.

[0174] Step S2120: preparing a reference layer on one side of the insulating layer.

[0175] The reference layer includes at least one reference line.

[0176] The order of forming the insulating layer and the reference layer is not limited. For example, a metal layer may be prepared first, and then an insulating layer may be formed on one side of the metal layer, and then the metal layer may be patterned.

[0177] Of course, other steps can also be used for the preparation. For example, a metal layer can be first deposited on a substrate, then patterned to form a reference layer; and then an insulating layer can be formed on one side of the reference layer. The insulating layer covers the orthographic projection of at least one reference line on the substrate. The substrate can be removed later, for example, after forming the insulating layer or after forming the conductive line layer.

[0178] The substrate can be either a base substrate or a display substrate. The base substrate can be either a rigid substrate or a flexible substrate. Examples of rigid substrates include glass substrates and silicon substrates. Flexible substrates can include polyimide films. The display substrate includes a base substrate and subpixels formed on the base substrate.

[0179] Step S2130, preparing a conductor layer on the side of the insulating layer away from the reference layer, the conductor layer including an impedance unit and a ground wire both extending along a first direction, and ground wires are respectively provided on both sides of the impedance unit in a second direction, and the second direction intersects with the first direction; in the second direction, the impedance unit is located between adjacent ground wires; the ground wire is connected to the reference wire through a ground hole penetrating the insulating layer; the impedance unit includes multiple impedance wires, and at least two impedance lines have the same arrangement rule at the overlapping position of the orthographic projection of the reference layer and the reference line, and the arrangement rule includes the number of overlapping positions and the position coordinates of the overlapping positions in the first direction.

[0180] Specifically, the same arrangement rule includes having the same number of overlapping positions, and the position coordinates of the overlapping positions in the first direction x are the same.

[0181] Alternatively, the conductor layer in step S2130 includes a single-ended wire and a ground wire extending along a first direction x. In a second direction y, ground wires are provided on both sides of the single-ended wire, and the single-ended wires are arranged at equal intervals at the intersection of the orthographic projection of the reference layer and the reference wire.

[0182] In other embodiments, before executing step S2130, the method further includes etching a ground hole in the insulating layer, wherein the ground hole penetrates the insulating layer in the thickness direction of the insulating layer, and the ground hole exposes the ground wire. Subsequently, the process of executing step S2130 includes first preparing a metal layer on the surface of the insulating layer, the metal layer filling the ground hole, and patterning the metal layer to obtain a conductor layer.

[0183] The order of forming the insulating layer, the reference layer, and the wire layer in this embodiment is not limited and can be adjusted according to actual conditions.

[0184] The preparation method provided in this embodiment is applicable to preparing the circuit board provided in any of the above embodiments. For structural details not described in the preparation method embodiment, please refer to the circuit board embodiment and will not be described in detail here.

[0185] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be construed as necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0186] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A circuit board, comprising: Insulation layer; a conductor layer located on one side surface of the insulating layer, the conductor layer including an impedance unit and a ground wire both extending along a first direction, the ground wires being respectively provided on both sides of the impedance unit in a second direction, the second direction intersecting the first direction; as well as a reference layer, located on a side of the insulating layer facing away from the conductive line layer, the reference layer comprising at least one reference line; The impedance unit includes a plurality of impedance lines, and at least two of the impedance lines have the same arrangement pattern at an overlapping position between the orthographic projection of the reference layer and the reference line.

2. The circuit board according to claim 1, wherein The plurality of impedance lines includes an odd number of impedance lines; Each of the impedance lines has the same arrangement rule at the overlapping position of the orthographic projection of the reference layer and the reference line; The impedance line has a plurality of overlapping positions between the orthographic projection of the reference layer and the reference line, and the intervals between adjacent overlapping positions in the first direction are equal.

3. The circuit board according to claim 1, wherein The plurality of impedance lines include at least one differential line pair, wherein the differential line pair includes two differential lines; Two differential lines in at least one differential line pair have the same arrangement rule at an overlapping position of an orthographic projection of the reference layer and the reference line.

4. The circuit board according to claim 3, wherein: The plurality of impedance lines include a plurality of differential line pairs, and the two differential lines in each differential line pair have the same arrangement rule at an overlapping position of an orthographic projection of the reference layer and the reference line; The plurality of impedance lines include a plurality of differential line pairs, and the differential lines of different differential line pairs have the same arrangement rule at the overlapping position of the orthographic projection of the reference layer and the reference line.

5. The circuit board according to claim 3 or 4, wherein: The differential line has a plurality of overlapping positions between the orthographic projection of the reference layer and the reference line, and the plurality of overlapping positions are arranged at equal intervals in the first direction; or The differential line has multiple overlapping positions where the orthographic projection of the reference layer and the reference line overlap, and the multiple overlapping positions are periodically arranged in the first direction; within the same arrangement period, the spacing between adjacent overlapping positions in the first direction changes gradually. The circuit board according to claim 3 , wherein: The adjacent ground lines are symmetrical about a first symmetry axis, and the differential line pairs between the adjacent ground lines are axially symmetrically distributed about the first symmetry axis.

7. The circuit board according to claim 1, wherein The conductor layer includes a plurality of ground lines and a plurality of impedance units, and the plurality of ground lines and the plurality of impedance units are alternately arranged in the second direction; At least one of the impedance units includes an odd number of impedance lines, and the remaining impedance units include at least one set of differential line pairs.

8. The circuit board according to claim 1, wherein The ground wire is connected to the reference wire through a ground hole penetrating the insulating layer; The adjacent ground lines are symmetrical about a first symmetry axis, and the ground holes on the adjacent ground lines are axially symmetrically distributed about the first symmetry axis.

9. The circuit board according to claim 1, wherein The reference lines include grid lines, the grid lines enclose a plurality of basic grids, and the plurality of basic grids are arranged in an array along the first direction and / or the second direction; The basic grid is an axisymmetric figure; The orthographic projection of the basic grid on the conductor layer is located between adjacent ground wires; The second symmetry axis of the basic grid is parallel to the first direction or the second direction; Adjacent ground lines are symmetrical about a first symmetry axis, and an orthographic projection of the first symmetry axis in the reference layer coincides with the second symmetry axis.

10. The circuit board according to claim 9, wherein In the first direction, adjacent basic grids are symmetrical about a third symmetry axis, and the third symmetry axis is parallel to the second direction; in the second direction, adjacent basic grids are symmetrical about a fourth symmetry axis, and the fourth symmetry axis is parallel to the first direction; the shape of the basic grid includes any one of a polygon, a circle, and an ellipse; The grid lines have uniform line widths; The ground wire is connected to the reference wire through a ground hole penetrating the insulating layer, and at least part of the ground hole is located on the vertex of the basic grid; The first direction is perpendicular to the second direction.

11. The circuit board according to claim 9 or 10, wherein: In the first direction, adjacent vertices or adjacent edges of adjacent basic meshes overlap, and in the second direction, adjacent vertices or adjacent edges of adjacent basic meshes overlap; The grid lines enclose a plurality of reconstructed grids. In the array of the basic grids, adjacent edges of adjacent basic grids enclose each other to form the reconstructed grid.

12. The circuit board according to claim 11, wherein The reconstructed grid and the basic grid have the same shape; The basic grid and the reconstructed grid are both diamond grids, and two diagonal lines of the diamond grid are parallel to the first direction and the second direction respectively.

13. The circuit board according to claim 11, wherein The reconstructed mesh and the base mesh have different shapes; The basic grid includes a hexagonal grid, and the reconstructed grid includes a diamond grid. Two opposite sides of the hexagonal grid are parallel to the first direction, and two diagonals of the diamond grid are parallel to the first direction and the second direction, respectively.

14. The circuit board according to claim 1, wherein The at least one reference line includes a plurality of reference lines, the reference lines are arranged along the first direction, the plurality of reference lines are arranged at intervals along the second direction, and the orthographic projections of the reference lines on the conductor layer are located between adjacent ground lines; The reference line includes a plurality of basic sub-lines, and the basic sub-lines are sequentially connected to form the reference line; In the first direction, adjacent basic sub-lines are symmetrical about a fifth symmetry axis, and the fifth symmetry axis is parallel to the second direction; The ground wire is connected to the reference wire via a ground hole penetrating the insulating layer, and the ground hole at least coincides with an end point of the basic sub-wire; The first direction is perpendicular to the second direction.

15. A circuit board comprising: Insulation layer; a wire layer located on one side surface of the insulating layer, the wire layer including a single-ended wire and a ground wire, both extending along a first direction, the ground wires being provided on both sides of the single-ended wire in a second direction, the second direction intersecting the first direction; as well as a reference layer, located on a side of the insulating layer facing away from the conductive line layer, the reference layer comprising at least one reference line; The single-ended line has a plurality of overlapping positions between the orthographic projection of the reference layer and the reference line, and the plurality of overlapping positions are arranged at equal intervals in the first direction.

16. The circuit board according to claim 15, wherein The invention also includes an impedance unit and a ground line, both extending along a first direction. In a second direction, the ground lines are respectively provided on both sides of the impedance unit, and the second direction intersects the first direction. The impedance unit includes a plurality of impedance lines, and at least two of the impedance lines have the same arrangement pattern at an overlapping position between the orthographic projection of the reference layer and the reference line.

17. The circuit board according to any one of claims 1 to 16, wherein: The material of the insulating layer includes at least one of epoxy resin glass fiber cloth and pure resin glue; The material of the reference line includes at least one of copper, silver, gold, and aluminum.

18. A method for preparing a circuit board, comprising: providing an insulating layer; preparing a reference layer on one side of the insulating layer, wherein the reference layer includes at least one reference line; A conductor layer is prepared on the side of the insulating layer facing away from the reference layer, the conductor layer includes an impedance unit and a ground wire both extending along a first direction, and the ground wires are respectively arranged on both sides of the impedance unit in a second direction, and the second direction intersects with the first direction; the impedance unit includes multiple impedance lines, and at least two of the impedance lines have the same arrangement pattern at the overlapping position of the orthographic projection of the reference layer and the reference line; or the conductor layer includes a single-ended line and a ground wire both extending along the first direction, and the ground wires are respectively arranged on both sides of the single-ended line in a second direction, and the second direction intersects with the first direction, and there are multiple single-ended lines at the overlapping position of the orthographic projection of the reference layer and the reference line, and the multiple overlapping positions are arranged at equal intervals in the first direction.

19. A display module comprising: Display panel; and The circuit board according to any one of claims 1 to 17 or the circuit board prepared by the preparation method according to claim 18, wherein the circuit board is electrically connected to the display panel.

20. A display device comprising the display module according to claim 19.

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