Image sensor and electronic device

Abstract

Disclosed in the present application are an image sensor and an electronic device. The image sensor comprises a pixel array and a reading circuit. The pixel array comprises pixels, wherein the pixels output reset voltages and signal voltages in a first mode and reset voltages and signal voltages in a second mode. The reading circuit comprises mode selection circuits and analog quantization circuits, wherein the mode selection circuits output the reset voltages in the first mode and in the second mode to the analog quantization circuits, so that the analog quantization circuits generate corresponding digital quantization values; the mode selection circuits output the signal voltages in the second mode to the analog quantization circuits, so that the analog quantization circuits generate feedback signals and feed the feedback signals back to the mode selection circuits; and in response to the feedback signals, the mode selection circuits output the signal voltages in the first mode or the second mode to the analog quantization circuits, so as to generate target digital quantization values in the first mode or the second mode. Thus, a quantization process only needs to be performed three times on four voltages outputted by each pixel having a DCG function, thereby shortening the frame period and improving the frame rate.

Description

Image sensor and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on January 31, 2024, with application number 202410144617.4 and application name “An Image Sensor and Electronic Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of image processing technology, and in particular to an image sensor and electronic equipment. Background Art

[0004] Image sensors are widely used in electronic devices such as digital cameras and mobile phones to capture digital images. Traditional image sensors consist of multiple pixels, each of which includes a photodiode (PD) and a pixel circuit. The PD converts light signals into electrical signals, and the pixel circuit outputs a voltage related to the electrical signal to construct the image. Furthermore, the voltage output by the pixel circuit is fed into an analog-to-digital converter (ADC), which quantizes the voltage into a digital value representing the intensity of the incident light. In traditional high dynamic range (HDR) image sensors with dual conversion gain (DCG) functionality, the ADC sequentially quantizes the voltage in high conversion gain (HCG) and low conversion gain (LCG) modes. This results in traditional image sensors requiring sequential quantization in HCG and LCG modes during pixel processing, leading to lengthy quantization times, increased frame periods, and reduced frame rates. Summary of the Invention

[0005] The present application provides an image sensor and an electronic device for reducing the number of quantization times of an image sensor with a DCG function, reducing the frame period, and improving the frame rate.

[0006] In a first aspect, embodiments of the present application provide an image sensor comprising a pixel array and a readout circuit. The pixel array comprises pixels and readout lines connected thereto, the pixels being configured to output a reset voltage and a signal voltage in a first mode, and a reset voltage and a signal voltage in a second mode, to the readout lines. Furthermore, the readout circuit is connected to the readout lines in a one-to-one correspondence and comprises a mode selection circuit and an analog quantization circuit, the analog quantization circuit being connected to the readout lines via the mode selection circuit. The mode selection circuit is configured to output reset voltages in the first and second modes to the analog quantization circuit, causing the analog quantization circuit to generate digital quantized values ​​of the reset voltages in the first and second modes. Furthermore, the mode selection circuit is configured to output a signal voltage in the second mode to the analog quantization circuit, causing the analog quantization circuit to generate a feedback signal, which the analog quantization circuit then feeds back to the mode selection circuit. In response to the feedback signal, the mode selection circuit is configured to output the signal voltage in the first or second mode to the analog quantization circuit, causing the analog quantization circuit to generate a target digital quantized value in the first or second mode, thereby enabling the readout circuit to quantize the signal voltage in the first or second mode output by the pixels, rather than quantizing the signal voltages in both the first and second modes. With this setting, the analog quantization circuit only needs to perform three quantization processes on the four voltages output by each pixel with DCG function to obtain the exposure quantization result of the HCG mode or the exposure quantization result of the LCG mode, which can reduce the number of quantization times, reduce the frame period, and improve the frame rate.

[0007] The target digital quantization value of the first mode includes: the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the first mode, or the difference between the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the first mode. The target digital quantization value of the second mode includes: the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the second mode, or the difference between the digital quantization value of the reset voltage and the digital quantization value of the signal voltage in the second mode.

[0008] Moreover, in the embodiment of the present application, there is no need to set up an additional feedback line between the reading circuit and the pixel, and there is no need to change the various control signals of the pixel. Instead, the various control signals of the pixel in the related technology can be reused, thereby reducing the development cost, cycle and risk of the pixel.

[0009] Furthermore, in the embodiments of the present application, the mode selection circuit in the readout circuit is configured on the readout line, making it applicable to a rolling shutter and compatible with the most commonly used circuit architectures in related technologies, thus having broad application value. Of course, the readout circuit in the embodiments of the present application can also be applied to architectures other than a rolling shutter.

[0010] In some embodiments, the image sensor further includes a data transmitter, and each readout circuit is connected to the image signal processor via the data transmitter. Each readout circuit outputs the target digital quantization value of the first mode or the second mode to the data transmitter, and the data transmitter transmits the target digital quantization value of the first mode or the second mode to the image signal processor.

[0011] In some embodiments, the feedback signal has a first level or a second level, and the mode selection circuit is capable of outputting a first signal voltage or a second signal voltage to the analog quantization circuit in response to the level of the feedback signal. If the level of the feedback signal is the second level, the mode selection circuit, in response to the level of the feedback signal being the second level, outputs a signal voltage of the second mode to the analog quantization circuit, causing the analog quantization circuit to generate a target digital quantization value of the second mode. Alternatively, if the level of the feedback signal is the first level, the mode selection circuit, in response to the level of the feedback signal being the first level, outputs a signal voltage of the first mode to the analog quantization circuit, causing the analog quantization circuit to generate a target digital quantization value of the first mode.

[0012] In some embodiments, the analog quantization circuit is further configured to generate a feedback signal in response to an input signal voltage and a reference voltage.

[0013] In some embodiments, to generate a feedback signal, the analog quantization circuit compares an input signal voltage with a reference voltage. In response to the input signal voltage being less than the reference voltage, the analog quantization circuit feeds back a feedback signal having a first level to the mode selection circuit. In response to the input signal voltage being greater than the reference voltage, the analog quantization circuit feeds back a feedback signal having a second level to the mode selection circuit.

[0014] In some embodiments, the mode selection circuit includes: a first control circuit, a second control circuit, and a third control circuit, wherein the first control circuit is connected to the readout line and the analog quantization circuit, respectively; the second control circuit is connected to the third control circuit and the analog quantization circuit, respectively; and the third control circuit is also connected to the first control circuit. Furthermore, the first control circuit is used to control the connection or disconnection between the readout line and the analog quantization circuit. The second control circuit is used to output the feedback signal generated by the analog quantization circuit to the third control circuit. The third control circuit is used to control the first control circuit to connect the readout line and the analog quantization circuit in response to the readout line transmitting the reset voltage of the first mode and the second mode, so that the analog quantization circuit generates a digital quantization value of the reset voltage. Furthermore, the third control circuit is used to control the first control circuit to connect the readout line and the analog quantization circuit in response to the readout line transmitting the signal voltage of the second mode, so that the analog quantization circuit generates a feedback signal. Furthermore, the third control circuit is further configured to control the first control circuit to disconnect the readout line from the analog quantization circuit in response to the feedback signal having a first level and the readout line transmitting a signal voltage of the second mode, and to control the first control circuit to connect the readout line to the analog quantization circuit in response to the feedback signal having a first level and the readout line transmitting a signal voltage of the first mode. Furthermore, the third control circuit is further configured to control the first control circuit to connect the readout line to the analog quantization circuit in response to the feedback signal having a second level and the readout line transmitting a signal voltage of the second mode, and to disconnect the readout line from the analog quantization circuit in response to the feedback signal having a second level and the readout line transmitting a signal voltage of the first mode.

[0015] In some embodiments, the first control circuit includes a first switch and a storage capacitor, wherein the control terminal of the first switch is connected to the third control circuit, the first terminal of the first switch is connected to the readout line, and the second terminal of the first switch is connected to the analog quantization circuit. Furthermore, the first terminal of the first storage capacitor is connected to the second terminal of the first switch, and the second terminal of the storage capacitor is grounded. This configuration enables the functionality of the first control circuit to be realized.

[0016] In some embodiments, the second control circuit includes a second switch, wherein a control terminal of the second switch is configured to receive a mode control signal, a first terminal of the second switch is connected to the analog quantization circuit, and a second terminal of the second switch is connected to the third control circuit. This configuration enables the function of the second control circuit to be realized.

[0017] In some embodiments, the third control circuit includes a first multiplexer, a second multiplexer, a third switch, a first inverter, a second inverter, and a first memory. The control terminal of the first multiplexer is configured to receive a first selection control signal, the first input terminal of the first multiplexer is configured to receive a first input signal, the second input terminal of the first multiplexer is connected to the output terminal of the second multiplexer, and the output terminal of the first multiplexer is connected to the first control circuit. The input terminal of the first inverter is respectively connected to the second control circuit and the first terminal of the third switch, the output terminal of the first inverter is respectively connected to the input terminal of the second inverter and the first input terminal of the second multiplexer. The output terminal of the second inverter is respectively connected to the second terminal of the third switch and the second input terminal of the second multiplexer. The control terminal of the third switch is configured to receive a latch control signal. The control terminal of the second multiplexer is configured to receive a second selection control signal. The first memory is connected to the output terminal of the second inverter and is configured to store and output a feedback signal. This configuration enables the functions of the third control circuit to be realized.

[0018] In some embodiments, an analog quantization circuit includes a comparator, a counter, and a second memory. The comparator's first input is connected to a mode selection circuit, its second input is configured to receive a comparison signal, and its output is connected to the counter and the mode selection circuit, respectively. The comparator is configured to output a feedback signal in response to a signal voltage of the second mode being input to its first input and the comparison signal being a reference voltage, and to output a comparison result corresponding to the target voltage in response to a target voltage being input to its first input and the comparison signal being a ramp signal. The target voltage may include a reset voltage of the first mode, a reset voltage of the second mode, a signal voltage of the second mode, or a signal voltage of the first mode. The counter is configured to generate a count value related to time. The second memory is configured to store the count value in the counter based on the comparison result of the comparator with respect to the target voltage, where the count value in the counter is a digital quantization value. This configuration enables the functionality of the analog quantization circuit.

[0019] In some embodiments, the mode selection circuit further includes: a fourth control circuit, the fourth control circuit being connected to the second memory and the comparator, respectively. The fourth control circuit is configured to, in response to the feedback signal having a first level, output the digital quantized value of the reset voltage in the first mode stored in the second memory to the counter, such that the count value stored in the second memory is the difference between the digital quantized value of the reset voltage in the first mode and the digital quantized value of the signal voltage. Furthermore, the fourth control circuit is configured to, in response to the feedback signal having a second level, output the digital quantized value of the reset voltage in the second mode stored in the second memory to the counter, such that the count value stored in the second memory is the difference between the digital quantized value of the reset voltage in the second mode and the digital quantized value of the signal voltage.

[0020] In some embodiments, the second memory may be one or two or three or more memories.

[0021] In some embodiments, the fourth control circuit includes a third multiplexer and a fourth switch, wherein a control terminal of the third multiplexer is connected to the third control circuit, a first input terminal and a second input terminal of the third multiplexer are respectively connected to the second memory, and an output terminal of the third multiplexer is connected to a first terminal of the fourth switch. The control terminal of the fourth switch is configured to receive a storage selection signal, and a second terminal of the fourth switch is connected to a counter. This configuration enables the functionality of the fourth control circuit to be realized.

[0022] In a second aspect, an embodiment of the present application further provides an electronic device, comprising an image signal processor and an image sensor, wherein the image sensor is connected to the image signal processor. Furthermore, the image sensor is configured to output a feedback signal and a digital quantization value for each pixel to the image signal processor, and the image signal processor is configured to generate an image based on the feedback signal and the digital quantization value for each pixel. The image sensor is the image sensor described in the first aspect or any possible implementation of the first aspect.

[0023] In addition, the technical effects of the corresponding scheme in the second aspect can refer to the technical effects that can be obtained by the corresponding scheme in the first aspect, and the repeated parts will not be described in detail. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0025] FIG2 is a schematic diagram of the structure of an image sensor provided in an embodiment of the present application;

[0026] FIG3 is a circuit diagram of a pixel provided in an embodiment of the present application;

[0027] FIG4 is a signal timing diagram in a DCG mode provided by an embodiment of the present application;

[0028] FIG5 is a schematic diagram of another structure of an image sensor provided in an embodiment of the present application;

[0029] FIG6 is a schematic diagram of another structure of an image sensor provided in an embodiment of the present application;

[0030] FIG7 is a schematic structural diagram of a reading circuit provided in an embodiment of the present application;

[0031] FIG8 is a schematic diagram of a circuit structure of a reading circuit provided in an embodiment of the present application;

[0032] FIG9 is a schematic diagram of another circuit structure of a reading circuit provided in an embodiment of the present application;

[0033] FIG10 a is a signal timing diagram of a read circuit in LCG mode provided by an embodiment of the present application;

[0034] FIG10 b is a signal timing diagram of a read circuit in HCG mode provided by an embodiment of the present application;

[0035] FIG11 is a schematic diagram of another circuit structure of a reading circuit provided in an embodiment of the present application;

[0036] FIG12 a is another signal timing diagram of the read circuit in the LCG mode provided by an embodiment of the present application;

[0037] FIG12 b is another signal timing diagram of the read circuit in the HCG mode provided by an embodiment of the present application;

[0038] FIG13 is a schematic diagram of another structure of a reading circuit provided in an embodiment of the present application;

[0039] FIG14 is a schematic diagram of another circuit structure of a reading circuit provided in an embodiment of the present application.

[0040] Figure 1: 1-housing; 2-image sensor; 3-mainboard; 100-pixel array; 110-pixel circuit; 200-reading circuit; 210-mode selection circuit; 211-first control circuit; 212-second control circuit; 213-third control circuit; 214-fourth control circuit; 220-analog quantization circuit; 221-comparator; 222-counter; 223-second memory; 2231-first sub-memory; 2232-second sub-memory; 300-image signal processor; 400-data transmitter; PX-pixel; VSL-readout line; M1-reset transistor; M2-conversion gain control transistor; M3-charge transfer transistor; M4-source follower transistor; M5-row selection transistor; CS-capacitor. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0042] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0043] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the following first describes its specific application scenarios. The image sensor provided by the embodiments of the present application can be applied to electronic devices, including but not limited to common devices with camera functions such as digital cameras, mobile phones, tablet computers, and wearable devices. Of course, the image sensor provided by the embodiments of the present application can also be applied to other types of electronic devices with camera functions.

[0044] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Referring to Figure 1 , the electronic device may include: a housing 1, an image sensor 2, and a mainboard 3. The image sensor 2 and mainboard 3 are disposed within the housing 1, and the image sensor 2 is disposed on and electrically connected to the mainboard 3. For example, the mainboard 3 includes, but is not limited to, a printed circuit board (PCB).

[0045] FIG2 is a schematic diagram of the structure of an image sensor provided in an embodiment of the present application. Referring to FIG2 , the image sensor includes a pixel array 100, a readout circuit 200, and an image signal processor (ISP) 300, and each readout circuit 200 is connected to the image signal processor 300. The pixel array 100 includes a plurality of pixels PX and a plurality of readout lines VSL arranged in an array, and each readout line VSL is connected to the readout circuit 200 in a one-to-one correspondence. For example, the plurality of pixels PX can be arranged in the form of multiple rows and multiple columns, and a column of pixels PX can be connected to one or more readout lines VSL. In addition, each pixel PX has a photodiode (PD) and a pixel circuit composed of a transistor, the pixel circuit is connected to the negative electrode of the photodiode, and the pixel circuit is also connected to the readout line VSL. In actual applications, light from a target object enters the PD of the image sensor, where it converts the optical signal into an electrical signal. The pixel circuit then transfers the electrical signal from the PD to the readout line VSL. The readout circuit 200 quantizes the signal on the readout line VSL and outputs it to the image signal processor 300. The image signal processor 300 then performs image synthesis based on the received signal. It is understood that this application uses the example of a column of pixels PX connected to a single readout line VSL for detailed description.

[0046] FIG3 is a circuit diagram of a pixel provided in an embodiment of the present application. Referring to FIG3 , the pixel includes a PD operating at a reverse bias voltage and a pixel circuit. The pixel circuit 110 may include a reset transistor M1, a conversion gain control transistor M2, a charge transfer transistor M3, a source follower transistor M4, a row select transistor M5, and a capacitor CS. The positive electrode of the PD is grounded, and the negative electrode of the PD is connected to the first electrode of the charge transfer transistor M3. Furthermore, the capacitor CS is connected between the first and second electrodes of the reset transistor M1. It is understood that the capacitor CS may be a physical capacitor or a parasitic capacitor. The gate of the reset transistor M1 is connected to the reset signal line RST. The first electrode of the reset transistor M1 is used to receive the voltage VDD. The second electrode of the reset transistor M1 is connected to the first electrode of the conversion gain control transistor M2. The gate of the conversion gain control transistor M2 is connected to the gain control signal line DCGX, and the second electrode of the conversion gain control transistor M2 is connected to the gate of the source follower transistor M4. The gate of the charge transfer transistor M3 is connected to the charge transfer signal line TG, and the second electrode of the charge transfer transistor M3 is connected to the gate of the source follower transistor M4. The first electrode of the source follower transistor M4 is used to receive the voltage VDD, and the second electrode of the source follower transistor M4 is connected to the first electrode of the row selection transistor M5. The gate of the row selection transistor M5 is connected to the row selection signal line RS, and the second electrode of the row selection transistor M5 is connected to the readout line VSL. The signals on the reset signal line RST, the gain control signal line DCGX, the charge transfer signal line TG and the row selection signal line RS are controlled by the row driver. It can be understood that the above is only an example to illustrate the specific structure of the pixel circuit provided in the embodiment of the present application. In specific implementation, the specific structure of the pixel circuit is not limited to the above structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which are not limited here.

[0047] In a specific implementation, the reset transistor M1, the conversion gain control transistor M2, the charge transfer transistor M3, and the row selection transistor M5 can be turned on by a high-level signal and turned off by a low-level signal. It is understood that the first electrode of the above-mentioned transistors can be a source and the second electrode can be a drain, or the first electrode can be a drain and the second electrode can be a source.

[0048] In conjunction with Figure 3, the second electrode of the conversion gain control transistor M2, the gate of the source follower transistor M4, and the second electrode of the charge transfer transistor M3 are connected to a floating diffusion potential (FD) point. In a specific implementation, when light from a target object enters the pixel PX, photoelectric conversion is completed in the PD, generating photogenerated electrons, which are stored in the PD. When the charge transfer transistor M3 is turned on, the photogenerated electrons in the PD are diverted to the FD point, causing the voltage value at the FD point to change. This voltage value controls the source follower transistor M4 to generate a corresponding voltage. The voltage is input to the readout line VSL through the turned-on row select transistor M5, thereby enabling the readout line VSL to transmit the corresponding voltage.

[0049] Moreover, DCG is one of the methods for image sensors to implement HDR. Compared with the technical solution of implementing HDR through multiple exposures, the DCG technical solution only requires a single exposure, so it can effectively avoid the problem of motion artifacts. The pixel PX provided in the embodiment of the present application may have a DCG function. Specifically, the parasitic capacitance of the FD point is recorded as Cpar, and Cpar includes the capacitance of the metal wiring, the coupling capacitance between the gate and the second pole of the charge transfer transistor M3, the coupling capacitance between the gate and the second pole of the conversion gain control transistor M2, etc. Among them, when the conversion gain control transistor M2 and the reset transistor M1 are both in the off state, the FD point capacitance CFD1 includes Cpar. When the conversion gain control transistor M2 is in the on state and the reset transistor M1 is in the off state, the FD point capacitance CFD2 includes both Cpar and Ccs (Ccs represents the capacitance of the capacitor CS). Therefore, CFD2>CFD1. For DCG HDR, when the incident light intensity is low, the number of photogenerated electrons generated in the PD is small, and the high conversion gain (HCG) mode is adopted. In the HCG mode, the conversion gain control transistor M2 is in the off state. Although the CFD1 capacitance value is small, the FD point can fully carry the number of photogenerated electrons derived by the PD. When the incident light intensity is high, the number of photon electrons generated in the PD is large, and the parasitic capacitance Cpar of the FD point itself cannot fully carry the photogenerated electrons derived by the PD, resulting in the voltage change amplitude of the FD point not being able to accurately reflect the number of photogenerated electrons generated in the PD. Therefore, the low conversion gain (LCG) mode is adopted at this time. In the LCG mode, the conversion gain control transistor M2 is in the on state, the CFD2 capacitance value is large, and the FD point can fully carry the number of photogenerated electrons derived by the PD. It can be understood that the conversion gain is defined as the voltage change at the FD point caused by each electron, and the unit is usually μV / e-, which is inversely proportional to the capacitance of the FD point. That is, the smaller the capacitance at point FD, the higher the conversion gain; and the larger the capacitance at point FD, the lower the conversion gain.

[0050] For example, taking the reset transistor M1, the conversion gain control transistor M2, the charge transfer transistor M3, and the row selection transistor M5 as an example, which are turned on under the control of a high-level signal and turned off under the control of a low-level signal, FIG4 is a signal timing diagram under a DCG mode provided by an embodiment of the present application. Referring to FIG4 , rs represents the signal transmitted by the row selection signal line RS, rst represents the signal transmitted by the reset signal line RST, dcgx represents the signal transmitted by the gain control signal line DCGX, tg represents the signal transmitted by the charge transfer signal line TG, and vsl represents the signal transmitted by the readout line VSL. The pixel shown in FIG3 operates under the control of the signal in the signal timing diagram shown in FIG4 , and can output the following to the readout line VSL in sequence: the reset voltage V LR 、HCG mode reset voltage V HR 、HCG mode signal voltage V HS and the signal voltage V in LCG mode LS Furthermore, in a specific implementation, in a column of pixels PX, the previous pixel PX can sequentially output the reset voltage V LR , reset voltage V HR , signal voltage V HS and signal voltage V LS After that, the next pixel PX outputs the reset voltage V to the readout line VSL in turn: LR , reset voltage V HR , signal voltage V HS and signal voltage V LS .

[0051] In the related art, in order to reconstruct the HDR image, it is necessary to reset the voltage V output by each pixel through the reading circuit. LR 、V HR , signal voltage V HS 、V LS All are digitally quantized to obtain the reset voltage V LR The digital quantization value D LR , reset voltage V HR The digital quantization value D HR , signal voltage V HS The digital quantization value D HS and signal voltage V LS The digital quantization value D LS Among them, in LCG mode, the exposure quantization result D in LCG mode is obtained by performing a difference through Correlated Double Sampling (CDS). LCG , and D LCG =D LS -D LRIn HCG mode, the exposure quantification result D in HCG mode is obtained by making a difference through CDS. HCG , and D HCG =D HS -D HR Exposure quantification results D LCG and D HCG The images are synthesized in the image signal processor 300 to obtain an HDR image.

[0052] Generally speaking, the frame period of the image sensor when working in DCG mode is: n×t ADC +t idle , n represents the total number of rows of pixels PX in the image sensor, t ADC Represents the quantized time of the output voltage of each pixel PX after exposure, t idle Represents the idle time between frames. From the formula, we can see that if t ADC If it decreases, the frame period will decrease, that is, t ADC This limits the improvement of the frame rate. Since the above-mentioned related art solution needs to quantize the reset voltage V twice LR 、V HR and twice the signal voltage V HS 、V LS , that is, it is necessary to perform quantization process 4 times on the 4 voltages output by each pixel, which increases the frame period and reduces the frame rate. To this end, the embodiment of the present application provides an image sensor, which reduces the number of quantization times by including a mode selection circuit and an analog quantization circuit in the reading circuit, thereby enabling t ADC Reducing it can reduce the frame period and increase the frame rate.

[0053] It is understandable that the first mode can be the LCG mode and the second mode can be the HCG mode, and the pixels can sequentially output the reset voltage V of the first mode to the readout line. LR , the reset voltage V HR , the signal voltage of the second mode V HS and the first mode signal voltage V LS The following describes the working process of the image sensor provided in the embodiment of the present application in detail by taking the first mode being the LCG mode and the second mode being the HCG mode as an example.

[0054] FIG5 is another structural diagram of an image sensor provided by an embodiment of the present application. Referring to FIG5, the read circuit 200 includes: a mode selection circuit 210 and an analog quantization circuit 220. The analog quantization circuit 220 is connected to the readout line VSL through the mode selection circuit 210. In a specific implementation, the reset voltage V is transmitted on the readout line VSL. LR When the mode selection circuit 210 is able to reset the voltage V LROutput to analog quantization circuit 220, analog quantization circuit 220 reset voltage V LR Quantize and generate reset voltage V LR The digital quantization value D LR After that, the reset voltage V is transmitted on the readout line VSL. HR When the mode selection circuit 210 is able to reset the voltage V HR Output to analog quantization circuit 220, analog quantization circuit 220 reset voltage V HR Quantize and generate reset voltage V HR The digital quantization value D HR After that, the signal voltage V is transmitted on the readout line VSL. HS When the mode selection circuit 210 can set the signal voltage V HS Output to the analog quantization circuit 220, the analog quantization circuit 220 can be based on the first signal voltage V HS Generate a feedback signal and feed the feedback signal back to the mode selection circuit 210. Based on this, the mode selection circuit 210 can respond to the feedback signal and adjust the signal voltage V HS Or signal voltage V LS Output to the analog quantization circuit 220, so that the analog quantization circuit 220 generates a corresponding target digital quantization value, so that the reading circuit 200 outputs a signal voltage V HS Or signal voltage V LS Quantization is performed without the need to HS and signal voltage V LS Therefore, the analog quantization circuit 220 only needs to perform three quantization processes on the four voltages output by each pixel PX with DCG function to obtain the exposure quantization result of the HCG mode or the exposure quantization result of the LCG mode, which can reduce the number of quantization times and reduce t ADC , thereby reducing the frame period and improving the frame rate.

[0055] In the embodiment of the present application, there is no need to set an additional feedback line between the reading circuit 200 and the pixel PX, and there is no need to change the various control signals of the pixel PX. Instead, the various control signals of the pixel PX in the related art can be reused, thereby reducing the development cost, cycle and risk of the pixel PX.

[0056] Furthermore, in the embodiment of the present application, the mode selection circuit 210 in the readout circuit 200 is configured on the readout line VSL, making it applicable to a rolling shutter and compatible with the most commonly used circuit architectures in related technologies, thus having a wide range of applications. Of course, the readout circuit 200 in the embodiment of the present application can also be applied to architectures other than a rolling shutter.

[0057] In some examples, the mode selection circuit 210 responds to the feedback signal and sets the signal voltage V HS Output to the analog quantization circuit 220, the analog quantization circuit 220 can generate the target digital quantization value of the second mode. The target digital quantization value of the second mode can be the reset voltage V HR The digital quantization value D HR and signal voltage V HS The digital quantization value D HS The difference D HS -D HR , then the difference D HS -D HR The exposure quantization result of the HCG mode can be represented, so that the exposure quantization result of the HCG mode can be output to the image signal processor 300 for synthesizing the HDR image. For example, the analog quantization circuit 220 can be based on the reset voltage V HR The digital quantization value D HR and signal voltage V HS The digital quantization value D HS , producing a difference D HS -D HR .

[0058] In some other examples, the mode selection circuit 210 responds to the feedback signal and sets the signal voltage V LS Output to the analog quantization circuit 220, the analog quantization circuit 220 can generate the target digital quantization value of the first mode. The target digital quantization value of the first mode can be the reset voltage V LR The digital quantization value D LR and signal voltage V LS The digital quantization value D LS The difference D LR -D LR , then the difference D LR -D LR The exposure quantization result of the LCG mode can be represented, so that the exposure quantization result of the LCG mode can be output to the image signal processor 300. For example, the analog quantization circuit 220 can be based on the reset voltage V LR The digital quantization value D LR and the second signal voltage V LS The digital quantization value D LS , producing a difference D LR -D LR .

[0059] For example, the feedback signal generated by the analog quantization circuit 220 may have a first level or a second level, and the mode selection circuit 210 may adjust the signal voltage VHS Or signal voltage V LS Output to the analog quantization circuit 220. If the level of the feedback signal is the first level, the mode selection circuit 210 changes the signal voltage V LS Output to the analog quantization circuit 220, so that the analog quantization circuit 220 generates the target digital quantization value of the first mode. If the level of the feedback signal is the second level, the mode selection circuit 210 changes the signal voltage V HS The output is sent to the analog quantization circuit 220 , so that the analog quantization circuit 220 generates a target digital quantization value of the second mode.

[0060] In order to generate the feedback signal, the analog quantization circuit 220 can convert the signal voltage V HS With reference voltage V REF For example, the analog quantization circuit 220 compares the signal voltage V HS With reference voltage V REF For comparison, if V HS <V REF , the analog quantization circuit 220 responds to V HS <V REF , the feedback signal with the first level is fed back to the mode selection circuit 210, so that the mode selection circuit 210 can receive the feedback signal with the first level. HS >V REF , the analog quantization circuit 220 responds to V HS >V REF , the feedback signal with the second level is fed back to the mode selection circuit 210, so that the mode selection circuit 210 can receive the feedback signal with the second level. For example, the first level can be a high level and the second level can be a low level. Alternatively, the first level can also be a low level and the second level can be a high level. It is understandable that the reference voltage V REF The specific value of can be determined according to the application scenario and is not limited here.

[0061] FIG6 is a schematic diagram of another structure of an image sensor provided by an embodiment of the present application. Referring to FIG6 , the image sensor further includes a data transmitter. Each readout circuit 200 is connected to the image signal processor 300 via a data transmitter 400. Each readout circuit 200 outputs a target digital quantization value of the first mode or a target digital quantization value of the second mode to the data transmitter 400. The data transmitter 400 transmits the target digital quantization value of the first mode or the target digital quantization value of the second mode to the image signal processor 300.

[0062] In order to improve the accuracy of constructing the HDR image, the mode selection circuit 210 also outputs the feedback signal of each sub-pixel PX to the data transmitter 400, and the feedback signal of each sub-pixel PX is also sent to the image signal processor 300 through the data transmitter 400, so that the image signal processor 300 constructs the HDR image according to the feedback signal of each sub-pixel PX and the target digital quantization value of the corresponding mode.

[0063] In some embodiments, to improve data synchronization and accuracy, the mode selection circuit 210 may also output a feedback signal for the pixel PX when the analog quantization circuit 220 outputs the target digital quantization value for the pixel PX. For example, the feedback signal for the pixel PX may be directly output to the image signal processor 300, or the feedback signal for the pixel PX may be output to the data transmitter 400, and then output to the image signal processor 300 via the data transmitter 400. This configuration enables the image signal processor 300 to determine, based on the feedback signal, whether the exposure quantization result for the pixel PX was obtained using the HCG mode or the LCG mode.

[0064] FIG7 is a schematic diagram of a readout circuit according to an embodiment of the present application. Referring to FIG7 , the mode selection circuit 210 may include a first control circuit 211, a second control circuit 212, and a third control circuit 213. The first control circuit 211 is connected to the readout line VSL and the analog quantization circuit 220, respectively. The second control circuit 212 is connected to the third control circuit 213 and the analog quantization circuit 220, respectively. The third control circuit 213 is also connected to the first control circuit 211. Furthermore, the analog quantization circuit 220 is connected to the readout line VSL via the first control circuit 211, thereby controlling the connection or disconnection between the readout line VSL and the analog quantization circuit 220 through the first control circuit 211.

[0065] The readout line VSL transmits the reset voltage V LR When the third control circuit 213 transmits the reset voltage V in response to the readout line VSL LR , control the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, and reset the voltage V LR Input analog quantization circuit 220, analog quantization circuit 220 reset voltage V LR Quantize and get the reset voltage V LR The digital quantization value D LR .

[0066] The readout line VSL transmits the reset voltage V HR When the third control circuit 213 is in response to the readout line VSL, the reset voltage V HR, control the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, and reset the voltage V HR Input analog quantization circuit 220, analog quantization circuit 220 reset voltage V HR Quantize and get the reset voltage V HR The digital quantization value D HR .

[0067] The readout line VSL transmits the signal voltage V HS When the third control circuit 213 can also respond to the readout line VSL transmission signal voltage V HS , controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, and turns the signal voltage V HS The analog quantization circuit 220 is inputted so that the analog quantization circuit 220 converts the signal voltage V HS With reference voltage V REF Furthermore, the analog quantization circuit 220 is connected to the third control circuit 213 via the second control circuit 212 , so that the feedback signal generated by the analog quantization circuit 220 is output to the third control circuit 213 via the second control circuit 212 .

[0068] 7, by the signal voltage V HS With reference voltage V REF By comparison, a feedback signal with a first level or a second level can be obtained. Then, the level of the feedback signal received by the third control circuit 213 is the first level or the second level. Therefore, the third control circuit 213 can control when the first control circuit 211 is turned on according to the feedback signal to determine whether to turn on the signal voltage V HS , or the signal voltage V LS Input to the analog quantization circuit 220.

[0069] When the level of the feedback signal is the first level, if the readout line VSL transmits the first signal voltage V HS , the third control circuit 213 can control the first control circuit 211 to disconnect the readout line VSL and the analog quantization circuit 220, thereby avoiding the signal voltage V HS Input analog quantization circuit 220. If the readout line VSL transmits a signal voltage V LS The third control circuit 213 controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, and turns the signal voltage V LS The analog quantization circuit 220 is inputted, so that the analog quantization circuit 220 outputs the target digital quantization value of the first mode (ie, D LS -D LR ).

[0070] When the level of the feedback signal is the second level, if the readout line VSL transmits the first signal voltage V HS The third control circuit 213 controls the first control circuit 211 to turn on the readout line VSL and the analog quantization circuit 220, and turns the signal voltage V HS Input analog quantization circuit 220. If the readout line VSL transmits a signal voltage V LS , the third control circuit 213 controls the first control circuit 211 to disconnect the readout line VSL and the analog quantization circuit 220, thereby avoiding the second signal voltage V LS The analog quantization circuit 220 is inputted, so that the analog quantization circuit 220 outputs the target digital quantization value of the second mode (ie, D HS -D HR ).

[0071] The analog quantization circuit 220 in the present application may be an analog to digital converter (ADC). For example, FIG8 is a schematic diagram of a circuit structure of a reading circuit provided in an embodiment of the present application. Referring to FIG8 , the analog quantization circuit 220 may include: a comparator 221, a counter 222, and a second memory 223. The first input terminal of the comparator 221 is connected to the mode selection circuit 210, and the second input terminal of the comparator 221 is used to receive the comparison signal V RAMP , the output terminal of the comparator 221 is connected to the counter 222 and the mode selection circuit 210 respectively. Then, the comparator 221 can receive the signal voltage V through the first input terminal. HS , receives the comparison signal V through the second input terminal RAMP And the comparison signal V RAMP The voltage is the reference voltage V REF , the comparator 221 converts the signal voltage V HS and reference voltage V REF Comparison is performed and a feedback signal is output. Furthermore, the comparator 221 can also receive a target voltage through a first input terminal and a comparison signal V through a second input terminal. RAMP And the comparison signal V RAMP The comparator 221 compares the target voltage with the ramp signal and outputs a comparison result corresponding to the target voltage. The target voltage includes the reset voltage V LR , the reset voltage V HR , the first signal voltage V HS and the second signal voltage V LSA voltage in the counter 222. The counter 222 can generate a count value related to time. The second memory 223 can store the count value in the counter 222 based on the comparison result of the comparator 221 on the target voltage, and the count value in the counter 222 is a digital quantized value. It is understandable that the first input terminal of the comparator 221 can be a negative input terminal, and the second input terminal of the comparator 221 can be a positive input terminal. In addition, in Figure 8, "-" represents the negative input terminal and "+" represents the positive input terminal.

[0072] For example, the image sensor may further include a ramp generator connected to each comparator in the read circuit. The ramp generator can generate a comparison signal V RAMP , and V RAMP Input to each analog quantization circuit.

[0073] 8, the mode selection circuit 210 may further include a fourth control circuit 214, which is connected to the second memory 223 and the comparator 221. When the feedback signal is at the first level, the fourth control circuit 214 resets the reset voltage V stored in the second memory 223 to LR The digital quantization value D LR Output to the counter 222, so that the count value stored in the second memory 223 is reset voltage V LR The digital quantization value D LR and signal voltage V LS The digital quantization value D LS The difference D LS -D LR Alternatively, when the feedback signal is at the second level, the fourth control circuit 214 sets the reset voltage V stored in the second memory 223 to HR The digital quantization value D HR Output to the counter 222, so that the count value stored in the second memory 223 is reset voltage V HR The digital quantization value D HR and signal voltage V HS The digital quantization value D HS The difference D HS -D HR .

[0074] FIG9 is a schematic diagram of another circuit structure of a read circuit provided in an embodiment of the present application. Referring to FIG9 , the first control circuit 211 may include: a first switch K1 and a storage capacitor CG, wherein the control terminal of the first switch K1 is connected to the third control circuit 213, the first terminal of the first switch K1 is connected to the readout line VSL, the second terminal of the first switch K1 is connected to the analog quantization circuit 220 (e.g., the first input terminal of the comparator 221), the first terminal of the first storage capacitor is connected to the second terminal of the first switch K1, and the second terminal of the storage capacitor CG is grounded.

[0075] 9 , the second control circuit 212 may include: a second switch K2, wherein a control end of the second switch K2 is used to receive a mode control signal Φ1, a first end of the second switch K2 is connected to the analog quantization circuit 220 (e.g., an output end of the comparator 221), and a second end of the second switch K2 is connected to the third control circuit 213.

[0076] 9 , the third control circuit 213 may include: a first multiplexer U1, a second multiplexer U2, a third switch K3, a first inverter D1, a second inverter D2, and a first memory 2131. The control terminal of the first multiplexer U1 is configured to receive a first selection control signal U1_sel, a first input terminal of the first multiplexer U1 is configured to receive a first input signal V4, a second input terminal of the first multiplexer U1 is connected to an output terminal of the second multiplexer U2, and an output terminal of the first multiplexer U1 is connected to the first control circuit 211 (e.g., the control terminal of the first switch K1). The input terminal of the first inverter D1 is respectively connected to the second control circuit 212 (e.g., the second terminal of the second switch K2) and the first terminal of the third switch K3, and the output terminal of the first inverter D1 is respectively connected to the input terminal of the second inverter D2 and the first input terminal of the second multiplexer U2. The output terminal of the second inverter D2 is connected to the second terminal of the third switch K3 and the second input terminal of the second multiplexer U2, respectively. The control terminal of the third switch K3 is configured to receive the latch control signal Φ2. The control terminal of the second multiplexer U2 is configured to receive the second selection control signal U2_sel. Furthermore, the first memory 2131 is connected to the output terminal of the second inverter D2 and is configured to store and output the feedback signal.

[0077] 9 , the fourth control circuit 214 includes a third multiplexer U3 and a fourth switch K4. The control terminal of the third multiplexer U3 is connected to the third control circuit 213 (e.g., the output terminal of the second inverter). The first and second input terminals of the third multiplexer U3 are respectively connected to the second memory 223. The output terminal of the third multiplexer U3 is connected to the first terminal of the fourth switch K4. The control terminal of the fourth switch K4 is configured to receive a storage selection signal Φ3. The second terminal of the fourth switch K4 is connected to the counter 222. By way of example, the second memory 223 can be configured as a single memory.

[0078] The switch in the embodiment of the present application can be one or more of various types of switching devices such as a relay, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a silicon carbide (SiC) MOSFET, etc., which are not listed one by one in the embodiment of the present application. In addition, each switch can include a first end, a second end and a control end, wherein the control end is used to control the closing or opening of the switch. When the switch is closed, current can be transmitted between the first end and the second end of the switch. When the switch is open, current cannot be transmitted between the first end and the second end of the switch. Taking MOSFET as an example, the control end of the switch is the gate, the first end of the switch can be the source, and the second end can be the drain, or the first end can be the drain and the second end can be the source. In addition, the first memory and the second memory in the embodiment of the present application include but are not limited to static random access memory (SRAM).

[0079] It is worth mentioning that the above is only an example to illustrate the specific structure of the reading circuit provided in the embodiment of the present application. In specific implementation, the specific structure of the reading circuit is not limited to the above structure provided in the embodiment of the present application, and can also be other structures known to those skilled in the art, which is not limited here.

[0080] The following describes the working process of the reading circuit in the image sensor provided by the embodiment of the present application in detail, taking the structure of the reading circuit shown in FIG. 9 as an example and combining with the signal timing diagram.

[0081] FIG10a is a signal timing diagram of a read circuit in LCG mode provided by an embodiment of the present application, wherein vsl represents the signal on the readout line VSL, V CMPrepresents the signal at the output of the comparator 221, V1 represents the signal at the output of the first inverter D1, V2 represents the signal at the output of the second inverter D2, V3 represents the signal at the output of the second multiplexer U2, Φ IN represents the signal at the output of the first multiplexer U1. LR and reset voltage V HR When the first multiplexer U1 selects V4 in response to the control of the first selection control signal U1_sel, and the level of V4 is a constant high level, then Φ IN When Φ1 is high, the first switch K1 is turned on; when Φ2 is low, the second switch K2 is turned off.

[0082] At time t1, the readout line VSL transmits the reset voltage V LR , reset voltage V LR The comparison signal V RAMP Set as ramp signal, reset voltage V LR Quantization, generating reset voltage V LR The digital quantization value D LR , and D LR Stored in the second memory 223.

[0083] At time t2, the readout line VSL transmits the reset voltage V HR , reset voltage V HR The comparison signal V RAMP Set as ramp signal, reset voltage V HR Quantization, generating reset voltage V HR The digital quantization value D HR , and D HR Stored in the second memory 223. At the reset voltage V LR and reset voltage V HR After quantization is completed, the comparison signal V RAMP The voltage is set as the reference voltage V REF , used for comparison at time t3.

[0084] During the time period t3' to t3, the readout line VSL transmits a signal voltage V HS The first multiplexer U1 responds to the control of the first selection control signal U1_sel to select V4, the first switch K1 is turned on, and the signal voltage V HS The reference voltage V REF The first signal voltage V HS and reference voltage V REF , judge the current incident light intensity. If VHS <V REF , which means the current incident light intensity is large, so the LCG mode is suitable. The signal V output by the comparator 221 is CMP is high level, the high level signal can be used as a feedback signal.

[0085] During the time period from t3 to t4, Φ1 is at a high level, the second switch K2 is turned on, V1 is at a low level, V2 is at a high level, and the first memory 2131 stores the high-level feedback signal. Furthermore, the second multiplexer U2 selects V1 in response to the control of the second selection control signal U2_sel, and V3 is at a low level. The first multiplexer U1 selects V3 in response to the control of the first selection control signal U1_sel, and Φ IN is low, the first switch K1 is closed, and Φ3 is high, the fourth switch K4 is turned on, and the third multiplexer U3 responds to the control of the high-level feedback signal and stores the reset voltage V LR The digital quantization value D LR Output to counter 222, thereby D LR Reload the counter 222. The counter 222 used in the embodiment of the present application includes but is not limited to an up / down counter 222 (Up / Down Counter), which is used to quantize the reset voltage V LR and reset voltage V HR When the quantized signal voltage V HS and signal voltage V LS When using the Count Up mode of the Up / Down Counter.

[0086] At time t4, Φ1 is at a low level, the second switch K2 is closed, and the feedback signal is latched.

[0087] At time t4-t5, the second multiplexer U2 responds to the control of the second selection control signal U2_sel and selects V1, then V3 is low level, and the first multiplexer U1 responds to the control of the first selection control signal U1_sel and selects V3, then Φ IN is low level, and the first switch K1 is closed.

[0088] At time t5-t6, the second multiplexer U2 responds to the control of the second selection control signal U2_sel and selects V2, then V3 is high level, and the first multiplexer U1 responds to the control of the first selection control signal U1_sel and selects V3, then Φ IN is high, the first switch K1 is turned on, and the signal voltage V LS Stored in storage capacitor CG.

[0089] At time t6, the comparison signal input to the comparator 221 is a ramp signal, and the signal voltage V LS Input comparator 221, starts to compare the signal voltage V LS During the quantization process, the counter 222 combines the reset voltage V LR The digital quantization value D LR , to obtain the reset voltage V LR The digital quantization value D LR and signal voltage V LS The digital quantization value D LS The difference D LS -D LR , and the difference D LS -D LR Stored in the second memory 223.

[0090] Finally, the high level feedback signal stored in the first memory 2131 and the difference D stored in the second memory 223 are combined. LS -D LR The data is sent to the data transmitter 400 and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0091] FIG10 b is a signal timing diagram of the read circuit provided in the HCG mode according to an embodiment of the present application, wherein vsl represents the signal on the readout line VSL, V CMP represents the signal at the output of the comparator 221, V1 represents the signal at the output of the first inverter D1, V2 represents the signal at the output of the second inverter D2, V3 represents the signal at the output of the second multiplexer U2, Φ IN represents the signal at the output of the first multiplexer U1. LR and reset voltage V HR When the first multiplexer U1 selects V4 in response to the control of the first selection control signal U1_sel, and the level of V4 is a constant high level, then Φ IN When Φ1 is high, the first switch K1 is turned on; when Φ2 is low, the second switch K2 is turned off.

[0092] The working process from time t1 to time t2 is substantially the same as the working process from time t1 to time t2 shown in FIG10 a , and will not be described in detail here.

[0093] During the time period t3' to t3, the readout line VSL transmits a signal voltage V HS The first multiplexer U1 responds to the control of the first selection control signal U1_sel to select V4, the first switch K1 is turned on, and the first signal voltage V HSThe reference voltage VREF is also input into the comparator 221 through the first switch K1. The comparator 221 compares the first signal voltage V HS and reference voltage V REF , judge the current incident light intensity. If V HS >V REF , indicating that the current incident light intensity is small, then the HCG mode is suitable, and the signal V output by the comparator 221 is CMP is low level, the low level signal can be used as a feedback signal.

[0094] During the time period from t3 to t4, Φ1 is at a high level, the second switch K2 is turned on, V1 is at a high level, V2 is at a low level, and the first memory 2131 stores the low-level feedback signal. Furthermore, the second multiplexer U2 selects V1 in response to the control of the second selection control signal U2_sel, and V3 is at a high level. The first multiplexer U1 selects V3 in response to the control of the first selection control signal U1_sel, and Φ IN is high, the first switch K1 is turned on, and Φ3 is high, the fourth switch K4 is turned on, and the third multiplexer U3 responds to the control of the low-level feedback signal and stores the reset voltage V HR The digital quantization value D HR Output to counter 222, thereby D HR Reload the counter 222.

[0095] At time t4, Φ1 is at a low level, the second switch K2 is closed, and the feedback signal is latched.

[0096] At time t4-t5, the second multiplexer U2 responds to the second selection control signal U2_sel to select V1, then V3 is high level, and the first multiplexer U1 responds to the first selection control signal U1_sel to select V3, then Φ IN is high, the first switch K1 is turned on, and the signal voltage V HS Stored in storage capacitor CG.

[0097] At time t5-t6, the second multiplexer U2 responds to the control of the second selection control signal U2_sel and selects V2, then V3 is low level, and the first multiplexer U1 responds to the control of the first selection control signal U1_sel and selects V3, then Φ IN is low level, the first switch K1 is closed, and the signal voltage V transmitted by the readout line VSL is LS The storage capacitor CG still stores the signal voltage V HS .

[0098] At time t6, the comparison signal input to the comparator 221 is a ramp signal, and the signal voltage V HS Input comparator 221, starts to compare the signal voltage V HS During the quantization process, the counter 222 combines the reset voltage V HR The digital quantization value D HR , to obtain the reset voltage V HR The digital quantization value D HR and signal voltage V HS The digital quantization value D HS The difference D HS -D HR , and the difference D HS- D HR Stored in the second memory 223.

[0099] Finally, the low-level feedback signal stored in the first memory 2131 and the difference D stored in the second memory 223 are combined. HS- D HR The data is sent to the data transmitter 400 and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0100] In some embodiments, a row of pixels in a pixel array may include multiple pixels, and the multiple pixels in the row may include a first target pixel and a second target pixel, i.e., some pixels in the row are first target pixels, and some pixels are second target pixels. The analog quantization circuit connected to the first target pixel may generate a feedback signal having a first level in response to a signal voltage in the second mode being less than a reference voltage. Furthermore, the mode selection circuit connected to the first target pixel may output the signal voltage in the first mode to the analog quantization circuit in response to the feedback signal having the first level, causing the analog quantization circuit to output a target digital quantization value in the first mode. Furthermore, the analog quantization circuit connected to the second target pixel may generate a feedback signal having a second level in response to a signal voltage in the second mode being greater than the reference voltage. Furthermore, the mode selection circuit connected to the second target pixel may output the signal voltage in the second mode to the analog quantization circuit in response to the feedback signal having the second level, causing the analog quantization circuit to output a target digital quantization value in the second mode. Specifically, the operation process of the readout circuit connected to the first target pixel may refer to the operation process of the readout circuit shown in FIG. 9 in combination with the signal timing diagram shown in FIG. 10a. The operation process of the readout circuit connected to the second target pixel may refer to the operation process of the readout circuit shown in FIG. 9 in combination with the signal timing diagram shown in FIG. 10b. Based on this, the reading circuit connected to the first target pixel and the reading circuit connected to the second target pixel both perform the signal voltage quantization process at time t6. In some other embodiments, the multiple pixels in the row can also be the first target pixels or the second target pixels, which is not limited here.

[0101] It is understood that since each readout circuit 200 is connected to a column of pixels PX via a readout line VSL, each readout circuit 200 can output digital quantization values ​​corresponding to a column of pixels PX. The image signal processor 300 can then receive the digital quantization values ​​corresponding to all pixels PX, thereby constructing an HDR image based on the digital quantization values ​​corresponding to all pixels PX. It is understood that the digital quantization values ​​corresponding to a column of pixels PX output by each readout circuit 200 can all be target digital quantization values ​​of the first mode, or all be target digital quantization values ​​of the second mode, or some be target digital quantization values ​​of the first mode and some be target digital quantization values ​​of the second mode. The digital quantization values ​​corresponding to all pixels PX received by the image signal processor 300 can all be target digital quantization values ​​of the first mode, or all be target digital quantization values ​​of the second mode, or some be target digital quantization values ​​of the first mode and some be target digital quantization values ​​of the second mode.

[0102] It is understandable that the image sensor may further include a clock generator, which is respectively connected to the mode selection circuit in each reading circuit, so as to input signals V4, U1_sel, U2_sel, Φ1, Φ2, and Φ3 to the mode selection circuit through the clock generator.

[0103] FIG11 is another circuit structure diagram of a reading circuit provided in an embodiment of the present application. Referring to FIG11 , the reading circuit in this embodiment is modified with respect to the reading circuit in the above embodiment. The similarities are not repeated here. The difference is that the second memory 223 can be set as two memories: a first sub-memory 2231 and a second sub-memory 2232. The first sub-memory 2231 is used to store the reset voltage V LR The digital quantization value D LR The second sub-memory 2232 is used to store the reset voltage V HR The digital quantization value D HR , and store the difference D LS -D LR , and output the difference D LS -D LR , or store the difference D HS -D HR , and output the difference D HS -D HR. It is understandable that the second memory 223 may also include three or more memories. In addition, the signal timing diagram corresponding to Figure 11 can refer to Figures 12a and 12b, Figure 12a is another signal timing diagram of the reading circuit provided in the embodiment of the present application in the LCG mode, and Figure 12b is another signal timing diagram of the reading circuit provided in the embodiment of the present application in the HCG mode. Among them, S_sel represents the storage selection signal, and the remaining signals refer to the description in the above embodiments. It is understandable that the clock generator is also connected to the analog quantization circuit in each reading circuit respectively to input the signal S_sel to the analog quantization circuit through the clock generator.

[0104] The following describes the operation of the readout circuit in the image sensor provided by the present invention in conjunction with Figures 11 and 12a. The operation of the readout circuit shown in Figure 11 in conjunction with the signal timing diagram shown in Figure 12a is largely identical to the operation of the readout circuit shown in Figure 9 in conjunction with the signal timing diagram shown in Figure 10a. The differences are described below.

[0105] At time t1, the reset voltage V LR The digital quantization value D LR Stored in the first sub-memory 2231.

[0106] At time t2, the reset voltage V HR The digital quantization value D HR Stored in the second sub-memory 2232.

[0107] During the time period t3 to t4, the third multiplexer U3 switches the reset voltage V stored in the first sub-memory 2231 to LR The digital quantization value D LR Output to counter 222.

[0108] At time t6, the difference D LS -D LR Stored in the second sub-memory 2232.

[0109] Finally, the high-level feedback signal stored in the first memory 2131 and the difference D stored in the second sub-memory 2232 are combined. LS -D LR The data is sent to the data transmitter 400 and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0110] The following describes the operation of the readout circuit in the image sensor provided by the present invention in conjunction with Figures 11 and 12b. The operation of the readout circuit shown in Figure 11 in conjunction with the signal timing diagram shown in Figure 12b is largely identical to the operation of the readout circuit shown in Figure 9 in conjunction with the signal timing diagram shown in Figure 10b. The differences are described below.

[0111] At time t1, the reset voltage V LR The digital quantization value D LR Stored in the first sub-memory 2231.

[0112] At time t2, the reset voltage V HR The digital quantization value D HR Stored in the second sub-memory 2232.

[0113] During the time period t3 to t4, the third multiplexer U3 switches the reset voltage V stored in the second sub-memory 2232 to HR The digital quantization value D HR Output to counter 222.

[0114] At time t6, the difference D HS -D HR Stored in the second sub-memory 2232.

[0115] Finally, the high-level feedback signal stored in the first memory 2131 and the difference D stored in the second sub-memory 2232 are combined. HS -D HR The data is sent to the data transmitter 400 and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0116] FIG13 is another structural diagram of a read circuit provided in an embodiment of the present application. Referring to FIG13 , the read circuit in this embodiment is modified from the read circuit in the embodiment shown in FIG8 . The similarities are not described here. The difference is that the mode selection circuit 210 includes a first control circuit 211, a second control circuit 212, and a third control circuit 213, but does not include a fourth control circuit 214. Then, the target digital quantization value of the second mode output by the analog quantization circuit 220 includes the reset voltage V HR The digital quantization value D HR and signal voltage V HS The digital quantization value D HS , the image signal processor 300 receives the reset voltage V HR The digital quantization value D HR and signal voltage V HS The digital quantization value D HS After that, the reset voltage V HRThe digital quantization value D HR and signal voltage V HS The digital quantization value D HS Do the difference and get the difference D HS -D HR , and then according to the difference D HS -D HR Reconstruct HDR image.

[0117] Alternatively, the target digital quantization value of the first mode output by the analog quantization circuit 220 includes a reset voltage V LR The digital quantization value D LR and signal voltage V LS The digital quantization value D LS , the image signal processor 300 receives the reset voltage V LR The digital quantization value D LR and signal voltage V LS The digital quantization value D LS After that, the reset voltage V LR The digital quantization value D LR and signal voltage V LS The digital quantization value D LS Do the difference and get the difference D LS -D LR , and then according to the difference D LS -D LR Reconstruct HDR image.

[0118] A circuit structure diagram corresponding to FIG13 is shown in FIG14 , and FIG14 differs from FIG9 in that the fourth control circuit is not provided. The remaining structure can be referred to FIG9 , and the details are not repeated here. In addition, the signal timing diagram corresponding to FIG13 can be referred to FIG10a and FIG10b .

[0119] The following describes the operation of the readout circuit in the image sensor provided by the present invention in conjunction with Figures 13 and 10a. The operation of the readout circuit shown in Figure 13 in conjunction with the signal timing diagram shown in Figure 10a is largely identical to the operation of the readout circuit shown in Figure 9 in conjunction with the signal timing diagram shown in Figure 10a. The differences are described below.

[0120] During the time period t3 to t4, the reset voltage V stored in the second memory 223 is LR The digital quantization value D LR It does not need to be output to the counter 222.

[0121] At time t6, the counter 222 calculates the signal voltage V according to the ramp signal. LS Quantize and get the signal voltage V LS The digital quantization value D LSand the signal voltage V LS The digital quantization value D LS Stored in the second memory 223.

[0122] Finally, the high-level feedback signal stored in the first memory 2131 is combined with the digital quantization value D stored in the second memory 223. LR and D LS The data is sent to the data transmitter 400 and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0123] The following describes the operation of the readout circuit in the image sensor provided by the present invention in conjunction with Figures 13 and 10b. The operation of the readout circuit shown in Figure 13 in conjunction with the signal timing diagram shown in Figure 10b is largely identical to the operation of the readout circuit shown in Figure 9 in conjunction with the signal timing diagram shown in Figure 10b. The differences are described below.

[0124] During the time period t3 to t4, the reset voltage V stored in the second memory 223 is HR The digital quantization value D HR It does not need to be output to the counter 222.

[0125] At time t6, the counter 222 calculates the signal voltage V according to the ramp signal. HS Quantize and get the signal voltage V HS The digital quantization value D HS and the signal voltage V HS The digital quantization value D HS Stored in the second memory 223.

[0126] Finally, the high-level feedback signal stored in the first memory 2131 is combined with the digital quantization value D stored in the second memory 223. HR and D HS The data is sent to the data transmitter 400 and output to the image signal processor 300 through the data transmitter 400 for HDR image reconstruction.

[0127] It is understandable that the second memory 223 may include one memory or two memories or more memories.

[0128] It is worth mentioning that in FIG10a, FIG10b, FIG12a and FIG12b, since some signals have no effect on the working process of the circuit in some time periods, the signals are not divided into high level or low level in these time periods. Therefore, FIG10a, FIG10b, FIG12a and FIG12b adopt To express.

[0129] The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, and they should all be covered by the protection scope of the present application.

Claims

1. An image sensor, characterized in that: include: pixel array and readout circuitry; The pixel array includes: pixels and readout lines connected to the pixels, the pixels being configured to output a reset voltage and a signal voltage of a first mode and a reset voltage and a signal voltage of a second mode to the readout lines; The readout circuit is connected to the readout line in a one-to-one correspondence, and the readout circuit includes: a mode selection circuit and an analog quantization circuit, and the analog quantization circuit is connected to the readout line through the mode selection circuit; The mode selection circuit is configured to output the reset voltages of the first mode and the second mode to the analog quantization circuit, so that the analog quantization circuit generates digital quantized values of the reset voltages of the first mode and the second mode; and output the signal voltage of the second mode to the analog quantization circuit, so that the analog quantization circuit generates a feedback signal, and the analog quantization circuit further feeds the feedback signal back to the mode selection circuit; The mode selection circuit is also used to output the signal voltage of the first mode or the second mode to the analog quantization circuit in response to the feedback signal, so that the analog quantization circuit generates a target digital quantization value of the first mode or the second mode; wherein the target digital quantization value includes: the digital quantization value of the reset voltage and the digital quantization value of the signal voltage, or the difference between the digital quantization value of the reset voltage and the digital quantization value of the signal voltage.

2. The image sensor according to claim 1, wherein The mode selection circuit is further configured to: In response to the feedback signal having a first level, outputting the signal voltage of the first mode to the analog quantization circuit; In response to the feedback signal having a second level, the signal voltage of the second mode is output to the analog quantization circuit.

3. The image sensor according to claim 1 or 2, wherein: The analog quantization circuit is further configured to generate the feedback signal in response to an input signal voltage and a reference voltage.

4. The image sensor according to claim 3, wherein The analog quantization circuit is further configured to: In response to the input signal voltage being less than the reference voltage, feeding back a feedback signal having a first level to the mode selection circuit; In response to the input signal voltage being greater than the reference voltage, a feedback signal having a second level is fed back to the mode selection circuit.

5. The image sensor according to any one of claims 1 to 4, wherein: The mode selection circuit includes: a first control circuit, a second control circuit and a third control circuit; The first control circuit is connected to the readout line and the analog quantization circuit respectively, and is used to control the connection or disconnection between the readout line and the analog quantization circuit; The second control circuit is connected to the third control circuit and the analog quantization circuit respectively, and is used to: output the feedback signal generated by the analog quantization circuit to the third control circuit; The third control circuit is further connected to the first control circuit, and is configured to: In response to the readout line transmitting the reset voltages of the first mode and the second mode, controlling the first control circuit to conduct the readout line and the analog quantization circuit so that the analog quantization circuit generates a digital quantization value of the reset voltage; and, in response to the readout line transmitting the signal voltage of the second mode, controlling the first control circuit to conduct the readout line and the analog quantization circuit, so that the analog quantization circuit generates a feedback signal; and, in response to the feedback signal having the first level and the readout line transmitting the signal voltage of the first mode, controlling the first control circuit to conduct the readout line and the analog quantization circuit; And, in response to the feedback signal having a second level and the readout line transmitting the second mode signal voltage, controlling the first control circuit to conduct the readout line and the analog quantization circuit.

6. The image sensor according to claim 5, wherein: The first control circuit includes: a first switch and a storage capacitor; The control end of the first switch is connected to the third control circuit, the first end of the first switch is connected to the readout line, and the second end of the first switch is connected to the analog quantization circuit; A first end of the first storage capacitor is connected to a second end of the first switch, and a second end of the storage capacitor is grounded.

7. The image sensor according to claim 5 or 6, wherein: The second control circuit includes: a second switch, a control end of the second switch is used to receive a mode control signal, a first end of the second switch is connected to the analog quantization circuit, and a second end of the second switch is connected to the third control circuit.

8. The image sensor according to any one of claims 5 to 7, wherein: The third control circuit includes: a first multiplexer, a second multiplexer, a third switch, a first inverter, a second inverter and a first memory; The control terminal of the first multiplexer is used to receive a first selection control signal, the first input terminal of the first multiplexer is used to receive a first input signal, the second input terminal of the first multiplexer is connected to the output terminal of the second multiplexer, and the output terminal of the first multiplexer is connected to the first control circuit; The input end of the first inverter is connected to the second control circuit and the first end of the third switch respectively, and the output end of the first inverter is connected to the input end of the second inverter and the first input end of the second multiplexer respectively; The output terminal of the second inverter is connected to the second terminal of the third switch and the second input terminal of the second multiplexer respectively; The control terminal of the third switch is used to receive a latch control signal; The control terminal of the second multiplexer is used to receive a second selection control signal; The first memory is connected to the output end of the second inverter, and is configured to store the feedback signal and output the feedback signal.

9. The image sensor according to any one of claims 1 to 8, wherein: The analog quantization circuit includes: a comparator, a counter and a second memory; The first input terminal of the comparator is connected to the mode selection circuit, the second input terminal of the comparator is used to receive a comparison signal, and the output terminal of the comparator is connected to the counter and the mode selection circuit respectively. The comparator is configured to output a feedback signal in response to a signal voltage of the second mode being input to the first input terminal and the voltage of the comparison signal being a reference voltage, and to output a comparison result corresponding to the target voltage in response to a target voltage being input to the first input terminal and the comparison signal being a ramp signal; the target voltage includes one of a reset voltage and a signal voltage of the first mode and the second mode; The counter is used to: generate a count value related to time; The second memory is used to store the count value in the counter based on the comparison result of the comparator on the target voltage, where the count value in the counter is a digital quantized value.

10. The image sensor according to claim 9, wherein The mode selection circuit further includes: a fourth control circuit, wherein the fourth control circuit is connected to the second memory and the comparator respectively; The fourth control circuit is used for: In response to the feedback signal having a first level, outputting the digital quantized value of the reset voltage of the first mode stored in the second memory to the counter, so that the count value stored in the second memory is the difference between the digital quantized value of the reset voltage of the first mode and the digital quantized value of the signal voltage; In response to the level of the feedback signal being the second level, the digital quantized value of the reset voltage of the second mode stored in the second memory is output to the counter, so that the count value stored in the second memory is the difference between the digital quantized value of the reset voltage of the second mode and the digital quantized value of the signal voltage.

11. The image sensor according to claim 10, wherein: The fourth control circuit includes: a third multiplexer and a fourth switch; The control terminal of the third multiplexer is connected to the third control circuit, the first input terminal and the second input terminal of the third multiplexer are respectively connected to the second memory, and the output terminal of the third multiplexer is connected to the first terminal of the fourth switch; The control end of the fourth switch is used to receive a storage selection signal, and the second end of the fourth switch is connected to the counter.

12. An electronic device, characterized in that: comprising an image signal processor and an image sensor according to any one of claims 1 to 11, The image sensor is connected to the image signal processor, and is used to output a feedback signal and a digital quantization value of each pixel to the image signal processor; The image signal processor is used to generate an image according to the feedback signal and the digital quantization value of each pixel.

Images