Storage expansion device and computing device

Abstract

Provided in the embodiments of the present application are a storage expansion device and a computing device. The storage expansion device comprises a cable interface, a PCIE interface, a first CXL controller, a second CXL controller and DIMMs, wherein the first CXL controller is connected to a first part of DIMMs, and the second CXL controller is connected to a second part of DIMMs; a first part of CXL interfaces of the first CXL controller is connected to the cable interface, and a second part of CXL interfaces thereof is connected to the PCIE interface; both the first part of CXL interfaces and the second part of CXL interfaces of the first CXL controller can access all the DIMMs connected to the first CXL controller; a first part of CXL interfaces of the second CXL controller is connected to the cable interface, and a second part of CXL interfaces thereof is connected to the PCIE interface; and both the first part of CXL interfaces and the second part of CXL interfaces of the second CXL controller can access all the DIMMs connected to the second CXL controller. Therefore, an access space of a single memory access port of the storage expansion device can be increased.

Description

Storage expansion device and computing device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on January 29, 2024, with application number 202410129849.2 and application name “A storage expansion device and computing device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of servers, and in particular to a storage expansion device and a computing device. Background Art

[0003] With the development of computer technology, the number of CPU cores has increased rapidly and computing density has continued to grow. However, due to the limitations of the physical space and design costs of computing devices, the growth rate of memory performance has lagged behind the growth of computing density. The average memory performance per core has continued to decline, limiting the computing power of computing devices.

[0004] Compute Express Link (CXL), an open industry standard, provides high-bandwidth, low-latency connections between dedicated compute, memory, I / O, and storage elements in data centers. Expanding memory on computing devices via the CXL bus effectively addresses bottlenecks such as memory and I / O walls. Currently, various hardware cards utilize the CXL bus for memory expansion, including add-in cards (AICs), E3.S form factors, and custom, custom-designed cards.

[0005] Currently, a single AIC card supports two Double Data Rate (DDR) channels. A single DDR channel can support dual-rank DIMMs per channel (DPC). Therefore, a single AIC card can connect to four Dual-Inline-Memory-Modules (DIMMs).

[0006] Therefore, in the prior art, only a portion of the DIMMs connected to the CXL controller can be accessed through the memory access port of a single AIC card, and the access space is limited. Summary of the Invention

[0007] Embodiments of the present invention provide a storage expansion device and a computing device, which can increase the access space of a single memory access port of the storage expansion device.

[0008] An embodiment of the present application provides a storage expansion device, comprising: a baseboard and a cable interface, a PCIE interface, a first CXL controller, a second CXL controller, and a plurality of dual in-line memory modules (DIMMs) arranged on the baseboard; the first CXL controller is connected to a first portion of the plurality of DIMMs, and the second CXL controller is connected to a second portion of the plurality of DIMMs; the CXL interface of the first CXL controller is divided into a first portion of CXL interfaces and a second portion of CXL interfaces, the first portion of the CXL interface of the first CXL controller being used to connect to the cable interface, and the second portion of the CXL interface of the first CXL controller being used to connect to the PCIE interface; the first portion of the CXL interface of the first CXL controller and the second portion of the CXL interface of the first CXL controller being used to connect to the PCIE interface; Both interfaces can access the memory space of all DIMMs connected to the first CXL controller; the CXL interface of the second CXL controller is divided into a first CXL interface and a second CXL interface. The first CXL interface of the second CXL controller is used to connect to the cable interface, and the second CXL interface of the second CXL controller is used to connect to the PCIE interface; the first CXL interface and the second CXL interface of the second CXL controller can both access the memory space of all DIMMs connected to the second CXL controller; the cable interface is used to access all memory space connected to the first CXL controller and the second CXL controller; the PCIE interface is used to access all memory space connected to the first CXL controller and the second CXL controller.

[0009] The storage expansion device provided in the embodiment of the present application includes at least two CXL controllers, and the CXL interface of each CXL controller is divided into two parts, and each part of the CXL interface can access all the memory spaces of the DIMMs connected to the CXL controller. In this way, any CXL interface of the server connected to the CXL controller can access all the DIMMs extended by the CXL controller. For example, the memory access port may include a PCIE interface and a cable interface, and the memory space of all DIMMs connected to the CXL controller can be accessed through the PCIE interface or the cable interface. The CXL controller supports a bifurcation function, and bifurcation means that the CXL interface of the CXL controller can be divided into multiple parts, for example, into two parts, or into more parts, or into four parts. Of course, the CXL interface can be divided into multiple parts in an equal manner, and the number of pins of each part is the same, or it can be divided into multiple parts in a non-equal manner, and the number of pins of any two parts in the multiple parts can be different.

[0010] The storage expansion device in this embodiment can be connected to two different computing devices through a cable interface and a PCIE interface respectively, so that the two computing devices can share the memory space of the storage expansion device.

[0011] In one possible implementation, the CXL interface of the first CXL controller is an X16 interface, and the first portion of the CXL interface and the second portion of the CXL interface of the first CXL controller are both X8 interfaces; the first portion of the CXL interface of the first CXL controller is connected to the first X8 interface of the cable interface, and the first portion of the CXL interface of the second CXL controller is connected to the second X8 interface of the cable interface; the cable interface is used to access all memory space of the first portion of DIMMs and all memory space of the second portion of DIMMs.

[0012] The present embodiment does not specifically limit the number of CXL interfaces included in the first and second CXL controllers. The above example illustrates a splitting of an X16 CXL interface into two equal parts, i.e., the first and second CXL controllers each include two X8 interfaces. The storage expansion device provided in the present embodiment can access the memory space of all DIMMs connected to the first CXL controller via the cable interface, and can also access the memory space of all DIMMs connected to the second CXL controller via the cable interface.

[0013] In one possible implementation, the CXL interface of the second CXL controller is an X16 interface, and the first and second CXL interfaces of the second CXL controller are both X8 interfaces. The PCIE interface is divided into a first X8 interface and a second X8 interface. The second CXL interface of the first CXL controller is connected to the first X8 interface of the PCIE interface, and the second CXL interface of the second CXL controller is connected to the second X8 interface of the PCIE interface. The PCIE interface is used to access all memory spaces of the first and second DIMMs.

[0014] The storage expansion device provided in the embodiment of the present application can access the memory space of all DIMMs connected to the first CXL controller through the PCIE interface, and can also access the memory space of all DIMMs connected to the second CXL controller through the PCIE interface.

[0015] In one possible implementation, a first CXL controller stores a first mapping table and a second mapping table. The first mapping table corresponds to a first portion of CXL interfaces of the first CXL controller, and the second mapping table corresponds to a second portion of CXL interfaces of the first CXL controller. The first mapping table implements mapping and conversion of memory physical addresses of servers connected to the first portion of CXL interfaces of the first CXL controller to memory physical addresses of all DIMMs of the first CXL controller; the second mapping table implements mapping and conversion of memory physical addresses of servers connected to the second portion of CXL interfaces of the first CXL controller to memory physical addresses of all DIMMs of the first CXL controller.

[0016] The storage expansion device provided in an embodiment of the present application has two mapping tables set up inside the first CXL controller, corresponding to the two parts of CXL interfaces respectively, so that the memory access interface connected to the two parts of CXL interfaces can access the memory space of all DIMMs connected to the first CXL controller through the corresponding mapping tables.

[0017] In one possible implementation, the second CXL controller stores a third mapping table and a fourth mapping table. The third mapping table corresponds to the first portion of the CXL interface of the second CXL controller, and the third mapping table corresponds to the second portion of the CXL interface of the first CXL controller. The third mapping table implements mapping and conversion of the memory physical addresses of the server connected to the first portion of the CXL interface of the second CXL controller to the memory physical addresses of all DIMMs of the second CXL controller; and the fourth mapping table implements mapping and conversion of the memory physical addresses of the server connected to the second portion of the CXL interface of the second CXL controller to the memory physical addresses of all DIMMs of the second CXL controller.

[0018] The storage expansion device provided in an embodiment of the present application has two mapping tables set inside the second CXL controller, corresponding to the two parts of the CXL interface respectively, so that the memory access interface connected to the two parts of the CXL interface can access the memory space of all DIMMs connected to the first CXL controller through the corresponding mapping tables.

[0019] A possible implementation method also includes a sensor and a system management bus (SMbus) switch interface provided on the substrate; the sensor is used to detect the temperature of the storage expansion device; a first end of the SMbus switch interface is connected to the first CXL controller and the second CXL controller; a second end of the SMbus switch interface is connected to the sensor; and a third end of the SMbus switch interface is used for a cable interface or a PCIE interface.

[0020] The server connects to the SMbus switch interface and accesses at least one of the sensor, the first CXL controller, and the second CXL controller through the SMbus switch interface. Furthermore, the server can simultaneously access the sensor, the first CXL controller, and the second CXL controller through the SMbus switch interface. By accessing the first and second CXL controllers, the server can access data in the DIMMs expanded by the first and second CXL controllers.

[0021] In one possible implementation, both the cable interface and the PCIE interface provide a clock pin, a reset pin, an SMbus pin, an in-position pin, and a power pin, and the third end of the SMbus switch interface is connected to the SMbus pins of the cable interface and the PCIE interface.

[0022] One possible implementation method is that the storage expansion device is in the form of a PCIE standard card, and the PCIE interface is located on the long side of the substrate for vertical insertion into the backplane of the computing device; or, the storage expansion device is in the form of a plug-in card, and the PCIE interface is located on the short side of the substrate for horizontal insertion into the backplane of the computing device.

[0023] The storage expansion device provided in the embodiment of the present application does not specifically limit the location of the PCIE interface setting and can be freely designed according to needs to facilitate connection to the backplane in the computing device.

[0024] In one possible implementation, the storage expansion device provided in an embodiment of the present application further includes a first full-duplex synchronous serial bus SPI flash memory and a second SPI flash memory arranged on a substrate; the first CXL controller is connected to the first SPI flash memory; and the second CXL controller is connected to the second SPI flash memory.

[0025] The first SPI flash memory C and the second SPI flash memory D are both in the form of electronically erasable programmable read-only memory, allowing multiple erasing or writing of SPI data.

[0026] In a possible implementation, the computing device provided in the embodiment of the present application further includes: a debug interface; and the first CXL controller and the second CXL controller are both connected to the debug interface.

[0027] The debug interface can be connected to an external device to test or debug the first CXL controller and the second CXL controller of the storage expansion device.

[0028] In one possible implementation, the storage expansion device provided in an embodiment of the present application further includes a support structure.

[0029] The support structure can secure the storage expansion device to the support plate relative to each other. For example, the support plate can be a metal plate, and the storage expansion device is fixed to the metal plate through the fixed support structure, providing strength support. The present application does not specifically limit the type of support structure, and can be, for example, screws or rivets. The number of support structures is also not specifically limited, and can be set according to actual needs.

[0030] In a second aspect, an embodiment of the present application further provides a storage expansion device, comprising: a substrate and a cable interface, a PCIE interface, a CXL controller, and multiple dual in-line memory modules (DIMMs) arranged on the substrate; the CXL controller is connected to the multiple DIMMs, and the CXL interface of the CXL controller is divided into a first CXL interface and a second CXL interface, the first CXL interface is connected to the cable interface, and the second CXL interface is connected to the PCIE interface; both the first CXL interface and the second CXL interface can access the memory space of all DIMMs connected to the CXL controller; the cable interface is used to access all memory space of the CXL controller; and the PCIE interface is used to access all memory space of the CXL controller.

[0031] In a third aspect, an embodiment of the present application further provides a computing device, comprising: a backplane and the storage expansion device introduced above; the storage expansion device is connected to the backplane.

[0032] The computing device provided in the embodiment of the present application can access all memories through the PCIE interface, i.e., the gold finger, and can also access all memories through the cable interface, thereby realizing the need to access high-density memory with fewer CXL bus interface resources. For example, the memory density of 8 DIMMs can be expanded using the X16 interface, so that more memory can be accessed using fewer interfaces, thereby saving the number of interfaces and improving the memory density of a single storage expansion device, thereby improving the memory density of the computing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic diagram of a storage expansion device provided in an embodiment of the present application;

[0034] FIG2 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0035] FIG3 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0036] FIG4A is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0037] FIG4B is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0038] FIG5 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0039] FIG6 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0040] FIG7 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0041] FIG8 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0042] FIG9 is a schematic diagram of another storage expansion device provided in an embodiment of the present application;

[0043] FIG10 is a schematic diagram of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The computing devices provided in the embodiments of this application are not specifically limited to specific application scenarios. For example, the computing device is described using a server as an example, and the server type is not specifically limited. For example, the computing device can be a rack server or an edge server. The server can be located in a data center or other areas, and this is not specifically limited in the embodiments of this application.

[0045] A server is a type of computing device that runs faster and handles higher loads than regular computers. It provides computing or application services to other clients on a network. Examples include personal computers (PCs) and smartphones. Servers feature high-speed CPU computing power, long-term reliable operation, strong external data throughput, and excellent scalability. Servers are categorized by their physical form factor into rack-mount, blade, tower, and cabinet types.

[0046] A server generally includes a motherboard and a power supply, which is used to supply power to various loads on the motherboard. The embodiment of the present application does not specifically limit the voltage level provided by the power supply to the motherboard, for example, DC 12V is used as an example for description.

[0047] The motherboard is a key circuit board in a server. It includes a baseboard and components such as a baseboard management controller (BMC), a central processing unit (CPU), controllers, memory, and connectors. A motherboard can include one or more CPUs. The controller has limited interfaces, so connectors can be used to expand these interfaces to connect peripheral devices. For example, USB ports can be added to connect devices like mice and keyboards, and serial data ports can be added to connect devices like graphics cards. The controller can be one or more of a microcontroller unit (MCU), a complex programmable logic device (CPLD), or a field programmable gate array (FPGA).

[0048] The embodiments of the present application do not specifically limit the specific type of memory. For example, the memory includes but is not limited to the following types: dual-inline-memory-modules (DIMMs), hard disk drives (HDDs), etc.

[0049] High-speed serial computer expansion bus standard Peripheral Component Interconnect Express (PCIE) cards connect to server connectors, facilitating the expansion of peripheral devices such as graphics cards or memory cards for the server controller. PCIE cards utilize high-speed serial point-to-point dual-channel, high-bandwidth transmission, typically using differential signaling channels. These cards allocate dedicated channel bandwidth to connected devices, eliminating bus bandwidth sharing. They primarily support active power management, error reporting, end-to-end reliable transmission, hot swapping, and quality of service features.

[0050] Serial Peripheral Interface (SPI), SPI is a high-speed, full-duplex, synchronous communication bus that only occupies four lines on the chip pins.

[0051] The System Management Bus (SMBus) was introduced by Intel in 1995 for low-speed communication in mobile and desktop PC systems. The SMBus is a powerful bus that uses two lines to control devices on the motherboard and collect information.

[0052] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, a detailed description is given below with reference to the accompanying drawings.

[0053] See Figure 1, which is a schematic diagram of a storage expansion device provided in an embodiment of the present application.

[0054] The storage expansion device provided in an embodiment of the present application includes: a baseboard 1000, at least one of a cable interface 200 or a PCIE interface 100 provided on the baseboard 1000, and at least one CXL controller. FIG1 illustrates an example of a baseboard of the storage expansion device including a first CXL controller A and a second CXL controller B. The first CXL controller A is configured to connect a first group of four DIMMs. The second CXL controller B is configured to connect a second group of four DIMMs.

[0055] For example, a plurality of PCIe slots are provided on the substrate, and the DIMMs are inserted into corresponding PCIe slots.

[0056] It should be understood that the CXL controller includes a CXL interface, which may include an X8 interface or an X16 interface. The X8 interface includes 8 pairs of differential signal pins, and the X16 interface includes 16 pairs of differential signal pins.

[0057] It should be noted that the memory access port of the storage expansion device in this embodiment can be provided with both a cable interface 200 and a PCIE interface 100. Alternatively, the storage expansion device may be provided with only a cable interface 200 or only a PCIE interface 100. A device or component connected to the line interface of the storage expansion device can access all DIMMs on the storage expansion device via the cable interface 200. A device or component connected to the PCIE interface of the storage expansion device can also access all DIMMs on the storage expansion device via the PCIE interface 100. This embodiment is described below assuming that the storage expansion device includes both a cable interface 200 and a PCIE interface 100.

[0058] The embodiment of the present application does not specifically limit the number of CXL controllers provided on the storage expansion device, which can be one or more. However, each CXL controller on the storage expansion device provided by the embodiment of the present application can connect to four DIMMs.

[0059] The first CXL controller A supports bifurcation. Bifurcation means that the CXL interface of the CXL controller can be divided into multiple parts, for example, into two parts, or into more parts, such as four parts. Of course, the CXL interface can be divided into multiple parts in an equal manner, with each part having the same number of pins, or it can be divided into multiple parts in an unequal manner, with any two parts having different numbers of pins. In the embodiments of the present application, the CXL interface of the CXL controller is divided into two parts as an example.

[0060] For example, the CXL interface of the CXL controller includes an X16 interface. The X16 interface is divided into two X8 interfaces. Correspondingly, the cable interface 200 includes an X16 interface, that is, includes two X8 interfaces. Similarly, the PCIE interface 100 also includes two X8 interfaces.

[0061] The CXL interface of the first CXL controller A includes a first CXL interface and a second CXL interface. The first CXL interface of the first CXL controller A is connected to the first X8 interface of the cable interface 200, and the second CXL interface of the first CXL controller A is connected to the first X8 interface of the PCIE interface 100. For example, if the CXL interface of the first CXL controller A is an X16 interface, the X16 interface is divided into two X8 interfaces. For example, one X8 interface is used to connect to the cable interface 200, and the other X8 interface is used to connect to the PCIE interface 100. It should be understood that the PCIE interface 100 is a gold finger interface. For example, a storage expansion device connects to the backplane of a server through a gold finger, providing memory access to the server.

[0062] In the embodiment of the present application, the X16 interface is divided into two X8 interfaces as an example. In other implementations, the X16 interface can also be divided into four X4 interfaces, etc., which is not specifically limited in the embodiment of the present application.

[0063] The X16 interface is divided into two X8 interfaces, which can be understood as follows: the X16 interface is a physical interface, half of the X16 interface pins are divided into a virtual X8 interface, and the other half of the X16 interface pins are divided into another virtual X8 interface. In other words, the two X8 interfaces are obtained by dividing the pins of a single X16 interface. Of course, in other embodiments, the CXL controller may also include two physical X8 interfaces.

[0064] The second CXL controller B supports a bifurcation function. The CXL interface of the second CXL controller B includes a first CXL interface and a second CXL interface. The first CXL interface of the second CXL controller B is connected to the second x8 interface of the cable interface 200, and the second CXL interface of the second CXL controller B is connected to the second x8 interface of the PCIE interface 100. For example, if the CXL interface of the second CXL controller B is an x16 interface, the x16 interface is bifurcated into two x8 interfaces. One x8 interface is used to connect to the cable interface 200, and the other x8 interface is used to connect to the PCIE interface 100.

[0065] The server can access all memory spaces of the corresponding first CXL controller A expansion and all memory spaces of the corresponding second CXL controller B expansion through cable interface 200. Specifically, when the storage expansion device includes two CXL controllers, the server can access the first set of four DIMMs of the first CXL controller A expansion and the second set of four DIMMs of the second CXL controller B expansion through cable interface 200. This means that the server can access all eight DIMMs on the storage expansion device through cable interface 200.

[0066] For example, the X8 interface of the first CXL controller is connected to cable interface 200, and the X8 interface of the second CXL controller is also connected to cable interface 200. Cable interface 200 includes an X16 interface. The server can access all DIMMs expanded by the first CXL controller through the X8 interface of cable interface 200, and the server can access all DIMMs expanded by the second CXL controller through another X8 interface of cable interface 200. It should be understood that if the first CXL controller is connected to four DIMMs and the second CXL controller is connected to four DIMMs, the server can access a total of eight DIMMs on the storage expansion device through cable interface 200.

[0067] The PCIE interface 100 in Figure 1 is located on the long side of the substrate, and the cable interface 200 in Figure 1 is located on the short side of the substrate. Furthermore, the four DIMMs connected to each CXL controller are arranged parallel to the long side of the substrate. It should be understood that the positional relationship of the various components in Figure 1 is merely illustrative and is not specifically limited in the embodiments of this application.

[0068] The embodiment of the present application does not specifically limit the specific implementation form of the cable interface. For example, the storage expansion device may include one 16-Lane CXL cable interface 200 or two 8-Lane CXL cable interfaces 200.

[0069] The present embodiment does not specifically limit the specific type of cable interface 200. For example, it may be an optical-to-electrical conversion interface, which converts electrical signals from the CXL controller into optical signals for external transmission, or converts external optical signals into electrical signals for transmission to the CXL controller. The CXL controller can access data in the DIMM, both reading and writing data.

[0070] The server can access all memory spaces expanded by the corresponding first CXL controller A through PCIE interface 100. Specifically, when the storage expansion device includes two CXL controllers, the server can access the four DIMMs expanded by the first CXL controller A and the four DIMMs expanded by the second CXL controller B through PCIE interface 100. In other words, the server can access all eight DIMMs on the storage expansion device through PCIE interface 100.

[0071] For example, the X8 interface of a first CXL controller is connected to PCIE interface 100, and the X8 interface of a second CXL controller is also connected to PCIE interface 100. PCIE interface 100 includes an X16 interface. The server can access all DIMMs connected to the first CXL controller via the X8 interface of PCIE interface 100, and can access all DIMMs connected to the second CXL controller via another X8 interface of PCIE interface 100. It should be understood that if four DIMMs are connected to the first CXL controller and four DIMMs are connected to the second CXL controller, the server can access a total of eight DIMMs on the storage expansion device via PCIE interface 100.

[0072] It is understandable that the two X8 interfaces of the PCIE interface correspond to half of the pins of the PCIE interface, that is, the two X8 interfaces are obtained by dividing the pins of the PCIE interface. Of course, in other embodiments, the storage expansion device may include two physical X8 PCIE interfaces.

[0073] The storage expansion device provided in the embodiments of the present application includes a CXL controller that supports bifurcation functionality. The CXL controller supports at least two DDR channels, with each channel supporting at least two DDR PCIe slots (DPCs). This means a single CXL controller can support four DDR DIMMs. Half of the CXL controller's CXL interfaces are connected to cable interfaces, while the other half are connected to gold fingers for external data exchange. The gold fingers can be externally configured as standard PCIE cards, meaning they can be plugged vertically into the backplane.

[0074] The storage expansion device in this embodiment can be connected to two different computing devices through a cable interface and a PCIE interface respectively, so that the two computing devices can share the memory space of the storage expansion device.

[0075] The storage expansion device provided in the embodiment of the present application enables the server to access the memory of all DIMMs connected to the CXL controller through the PCIE interface, i.e., the gold finger, and can also access all the memory of all DIMMs connected to the CXL controller through the cable interface. This meets the requirement of accessing high-density memory with fewer interface resources. For example, the memory density of 8 DIMMs can be expanded using the X16 interface, so that more memory can be accessed using fewer interfaces, thereby saving the number of interfaces and improving the memory density of a single storage expansion device.

[0076] Figure 1 uses a storage expansion device including two CXL controllers as an example. It should be understood that the storage expansion device can also include only one CXL controller. One CXL controller connects to four DIMMs, which can be accessed through a gold finger or cable interface. The gold finger or cable interface only requires an X8 interface to access the four DIMMs. Compared with traditional technology, the number of interface pins can be reduced by half to access the same number of DIMMs.

[0077] In one possible implementation, the CXL controller of this embodiment enables external devices (e.g., servers) to access all memory spaces expanded by the CXL controller through cable interfaces or cheat sheets through address mapping. Specifically, the CXL controller maps the addresses of all expanded memory spaces to the first and second CXL interfaces.

[0078] In one possible implementation, an address mapping table is provided in the CXL controller. The address mapping table can map all memory spaces of the CXL controller extension. The address mapping table can include two offsets. For example, when accessing all memory spaces of the CXL controller extension through the first CXL interface, the first offset is used to calculate the address mapping relationship. When accessing all memory spaces of the CXL controller extension through the second CXL interface, the second offset is used to calculate the address mapping relationship.

[0079] The CXL controller can complete the address mapping between all expanded memory spaces and the CPU of the server (computing device). The CXL controller is responsible for mapping the physical address of the computing device to the physical address of the storage expansion device. For example, if the computing device is a server, the physical address of the computing device here can be the physical address of the motherboard CPU. For example, if the storage space of the storage expansion device is 64G, then the physical address read by the CPU corresponding to the storage expansion device is the address corresponding to 201G-264G. That is, the physical address is offset internally by the CXL controller, so that the server CPU performs the physical address offset when reading the storage expansion device.

[0080] For example, a first CXL controller stores a first mapping table and a second mapping table. The first mapping table corresponds to a first portion of the CXL interface of the first CXL controller, and the second mapping table corresponds to a second portion of the CXL interface of the first CXL controller. The first mapping table can implement mapping conversion of the memory physical address of a first server (e.g., a server connected to a cable interface) received by the first portion of the CXL interface to the memory physical addresses of all DIMMs (e.g., DIMMs 1-4) of the first CXL controller. This mapping conversion of the memory physical addresses can comply with the CXL specification or a customized method, for example, by calculation using address offsets.

[0081] The second mapping table can implement the mapping conversion of the memory physical address of the second server (for example, the server connected to the PCIE interface) received by the second part CXL interface to the memory physical addresses of all DIMMs (for example, DIMMs 1-4) of the first CXL controller. The mapping conversion of the memory physical address can follow the CXL protocol or a customized method, for example: calculation through address offset.

[0082] Since the first and second CXL interfaces may connect to different servers with different system address spaces, the physical memory addresses received by the first and second CXL interfaces may differ, but the physical addresses they translate to must be the same. Furthermore, the CXL controller ensures that the addresses translated from the two mapping tables can access all DIMMs connected to the CXL controller, and the CXL controller ensures the correct access order.

[0083] Similarly, the second CXL controller stores a third mapping table and a fourth mapping table. The third mapping table corresponds to the first part of the CXL interface of the second CXL controller, and the fourth mapping table corresponds to the second part of the CXL interface of the second CXL controller. The third mapping table can implement mapping conversion of the memory physical address of the first server (for example, the server connected to the cable interface) received by the first part of the CXL interface to the memory physical addresses of all DIMMs (for example, DIMMs 5-8) on the second CXL controller. The mapping conversion of the memory physical address can comply with the CXL specification or a customized method, for example: calculation through address offset.

[0084] The fourth mapping table can implement the mapping conversion of the memory physical address of the second server (for example, a server connected to the PCIE interface) received by the second part CXL interface to the memory physical addresses of all DIMMs (for example, DIMMs 5-8) on the second CXL controller. The mapping conversion of the memory physical address can follow the CXL protocol or a custom method, for example: calculation by address offset.

[0085] Given that the first and second CXL interfaces may be connected to different servers, each with a different system address space, the memory physical addresses received by the first and second CXL interfaces may differ, but the physical addresses to be converted are the same. At the same time, the CXL controller ensures that the addresses converted from the two mapping tables can access all addresses connected to the CXL controller, and the CXL controller ensures the correct access order. It should be noted that when the first server sends a read or write operation instruction to the first CXL controller via the first CXL interface of the first CXL controller, the first CXL controller confirms the destination address included in the read or write operation instruction based on the first mapping table and performs the corresponding read or write operation on the destination address. When the first server sends a read or write operation instruction to the second CXL controller via the first CXL interface of the second CXL controller, the second CXL controller confirms the destination address included in the read or write operation instruction based on the third mapping table and performs the corresponding read or write operation on the destination address.

[0086] When the second server sends a read / write operation instruction to the first CXL controller via the second partial CXL interface of the first CXL controller, the first CXL controller identifies the destination address included in the read / write operation instruction based on the second mapping table and performs the corresponding read / write operation on the destination address. When the second server sends a read / write operation instruction to the second CXL controller via the second partial CXL interface of the second CXL controller, the second CXL controller identifies the destination address included in the read / write operation instruction based on the fourth mapping table and performs the corresponding read / write operation on the destination address.

[0087] Since the CXL interface of the CXL controller includes a first part of the CXL interface and a second part of the CXL interface, each CXL interface can access all memories connected to the CXL controller, and each interface can access all memory spaces connected to the CXL controller through the corresponding address mapping table. This is because the address mapping in the CXL controller can map all extended memory to any part of the CXL interface of the CXL controller, that is, each part of the CXL interface can access all CXL memory spaces, that is, all DIMMs. Therefore, a server connected to the cable interface can access all memory spaces of the storage expansion device through a part of the interface of the first CXL controller and a part of the interface of the second CXL controller, and a server connected to the PCIE interface can access all memory spaces of the storage expansion device through another part of the interface of the first CXL controller and another part of the interface of the second CXL controller.

[0088] The CXL interface is an X16 interface; the X16 interface of the CXL controller is equally divided into a first CXL interface and a second CXL interface, and both the first CXL interface and the second CXL interface are X8 interfaces.

[0089] The first portion of the CXL interface is connected to the cable interface.

[0090] The second part CXL interface is connected to the PCIE interface.

[0091] FIG1 shows a storage expansion device including a cable interface and a PCIE interface. The following describes a case where the storage expansion device only includes a PCIE interface.

[0092] See Figure 2, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0093] The storage expansion device shown in Figure 2 is similar to the storage expansion device shown in Figure 1 in that both include two CXL controllers, each connected to four DIMMs. Furthermore, the PCIE interface 100 in both Figures 1 and 2 is located on the long side of the substrate, and similar parts are not repeated here.

[0094] The storage expansion device shown in FIG2 differs from the storage expansion device shown in FIG1 in that it only includes a PCIE interface 100 and may not include a cable interface. Furthermore, the PCIE interface 100 of the storage expansion device shown in FIG2 is configured in a standard PCIE AIC form factor, meaning that the gold finger may be externally provided in the form of a standard PCIE card and vertically plugged into the backplane of the computing device.

[0095] See Figure 3, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0096] The storage expansion device shown in Figure 3 is similar to the storage expansion device shown in Figure 1 in that both include two CXL controllers, each connected to four DIMMs. Furthermore, the cable interface 200 in Figures 1 and 3 is located on the short side of the baseboard, and the common parts are not repeated here.

[0097] The storage expansion device shown in FIG3 differs from the storage expansion device shown in FIG1 in that the storage expansion device shown in FIG3 only includes a cable interface 200 and may not include a PCIE interface. The cable interface 200 of the storage expansion device shown in FIG3 can be connected to a server via an external cable, for example, the cable interface 200 of the storage expansion device can be connected to the server via an optical fiber.

[0098] The PCIE interface of the storage expansion device provided in the embodiment of the present application can also be configured as a plug-in card, that is, the entire storage expansion device can be pulled out and pushed in like a drawer, for example, it can be inserted into the backplane of a server. The following is a detailed description with reference to the accompanying drawings.

[0099] See Figure 4A, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0100] The storage expansion device shown in FIG4A is the same as the storage expansion device shown in FIG1 in that both include two CXL controllers, each CXL controller is connected to four corresponding DIMMs, and both include a cable interface 200 and a PCIE interface 100 , and the same parts are not repeated here.

[0101] The storage expansion device shown in FIG4A differs from the storage expansion device shown in FIG1 in that the storage expansion device in FIG4A is configured as a plug-in card. This is primarily due to the PCIE interface 100 being configured as a plug-in card that can be plugged into the server backplane. Furthermore, the PCIE interface 100 in FIG1 is located on the long side of the baseboard, while the PCIE interface 100 in FIG4A is located on the short side of the baseboard.

[0102] The four DIMMs connected to each CXL controller are arranged parallel to the long side of the substrate. It should be understood that the positional relationship of the various components in Figure 4A is only for illustration and is not specifically limited in the embodiments of the present application.

[0103] Because the PCIE interface 100 is located on the short side of the substrate, when the storage expansion device is configured as a plug-in card, the storage expansion device may wobble and become unstable. Therefore, a fixed support structure is provided on the storage expansion device to stabilize its state and prevent wobble. For example, the storage expansion device may be provided with multiple fixed structures, distributed at different locations on the storage expansion device. For example, a possible implementation method is shown in FIG4B , which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0104] The computing device provided in the embodiment of the present application also includes a support plate M, on which three fixed structures are provided. The three fixed structures of the memory expansion device are arranged to form the three vertices of a triangle. The three fixed positions are respectively O, P, and Q. For example, in a specific implementation, the storage expansion device and the support plate can be fixed together using screws or rivets. The support plate can be located on the side of the substrate facing away from the DIMM so that the support plate can fix and support the storage expansion device. For example, the support plate is a metal plate, and the substrate of the storage expansion device is fixed to the metal plate by a fixed support structure to provide strength support. The embodiment of the present application does not specifically limit the number of fixed structures, and can be set according to actual needs.

[0105] See Figure 5, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0106] The storage expansion device shown in Figure 5 is similar to the storage expansion device shown in Figure 4A in that both include two CXL controllers, each connected to four corresponding DIMMs. The PCIE interface 100 is provided on the short side of the substrate, and the same parts are not repeated here.

[0107] The storage expansion device shown in FIG5 is different from the storage expansion device shown in FIG4A in that the storage expansion device shown in FIG5 only includes a PCIE interface 100, and the PCIE interface 100 is configured as a plug-in card, that is, the gold finger can be horizontally plugged into the backplane of the server in the form of a plug-in card.

[0108] The following describes in detail the implementation of the storage expansion device provided in the embodiments of the present application with reference to the accompanying drawings.

[0109] See Figure 6, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0110] The storage expansion device provided in this embodiment of the present application is in the form of a standard PCIE card, full height and full length. This storage expansion device provides a DC 12V power interface. Similar to Figure 1 , this storage expansion device includes a first CXL controller A and a second CXL controller B. The first CXL controller A is connected to four corresponding DIMMs, and the second CXL controller B is connected to four corresponding DIMMs. The entire storage expansion device can expand up to eight DIMMs, and the same parts are not repeated here.

[0111] A gold finger interface is provided on the side of the baseboard of the storage expansion device. The gold finger interface is an X16 interface and complies with the PCIE standard specification.

[0112] The storage expansion device provided in this embodiment of the present application includes two X8 cable interfaces, namely, first cable interface 201 is an X8 interface, and second cable interface 202 is an X8 interface. First cable interface 201 is connected to first CXL controller A, and second cable interface 202 is connected to second CXL controller B. First cable interface 201 accesses the four DIMMs connected to first CXL controller A, and second cable interface 202 accesses the four DIMMs connected to second CXL controller B. It should be understood that FIG6 may also include only one cable interface, which is an X16 interface.

[0113] The storage expansion device provided in an embodiment of the present application further includes a first SPI flash memory C and a second SPI flash memory D arranged on the substrate.

[0114] The first CXL controller A is connected to the first SPI flash memory C.

[0115] The second CXL controller B is connected to the second SPI flash memory D.

[0116] The first SPI flash memory C and the second SPI flash memory D are both in the form of electronically erasable programmable read-only memory, which allows multiple erasing or writing of SPI data. Since they can be erased and written, they can be reused.

[0117] The storage expansion device provided in an embodiment of the present application further includes a debug interface provided on the substrate; both the first CXL controller A and the second CXL controller B are connected to the debug interface. The debug interface can be connected to an external device to enable testing or debugging of the first CXL controller A and the second CXL controller B of the storage expansion device. It should be understood that both the first CXL controller A and the second CXL controller B can be connected to the debug interface via a Joint Test Action Group (JTAG) interface or a Universal Asynchronous Receiver / Transmitter (UART) interface.

[0118] The storage expansion device provided in the embodiment of the present application further includes a system management bus (SMbus) switch interface F and a sensor E provided on the substrate. The sensor E is used to detect the temperature of the storage expansion device.

[0119] A first end of the SMbus switch interface F is connected to the first CXL controller A and the second CXL controller B;

[0120] The second end of SMbus switch interface F is connected to sensor E. The third end of SMbus switch interface F is used to connect to a server. For example, SMbus switch interface F can be used to connect to a server. The server can manage the CXL controller on the storage expansion device through SMbus switch interface F.

[0121] In one possible implementation, the server connects to an SMbus switch interface and accesses at least one of the sensor E, the first CXL controller A, and the second CXL controller B through the SMbus switch interface F. Furthermore, the server can simultaneously access the sensor E, the first CXL controller A, and the second CXL controller B through the SMbus switch interface F. By accessing the first CXL controller A and the second CXL controller B, the server can access data in DIMMs expanded by the first CXL controller A and the second CXL controller B.

[0122] In addition to the CXL data read and write pins, the interfaces provided by the first cable interface 201, the second cable interface 202, and the PCIE interface 100 also include a clock pin CLK, a reset pin RST, an SMbus pin, a position pin PRSNT, and a power pin. In other words, the third terminal of the SMbus switch interface F can be connected to a cable interface or a PCIE interface. In this embodiment, the power pin voltage is 3.3V.

[0123] The first CXL controller A connects to the corresponding four DIMMs via a DDR controller and obtains Serial Presence Detect (SPD) information for the four DIMMs via an Inter-Integrated Circuit (I2C) or an Improved Inter Integrated Circuit (I3C) bus interface. SPD information includes information such as the DIMM's memory size and bandwidth, facilitating physical address mapping based on memory size. Similarly, the second CXL controller B connects to the corresponding four DIMMs via a DDR controller and obtains SPD information for the four DIMMs via I2C / I3C.

[0124] The storage expansion device provided in the embodiments of the present application can refresh the firmware of the first CXL controller A and the firmware of the second CXL controller B through a server, modifying their internal address mapping units. This allows all interfaces of the first CXL controller A and the second CXL controller B, which are divided equally, to access all memory spaces connected to the corresponding CXL controllers. As a result, the entire CXL memory space of the storage expansion device, that is, all DIMMs, can be accessed through both the cable interface and the PCIe interface.

[0125] The storage expansion device shown in Figure 6 is provided with a first cable interface 201, a second cable interface 202, and a PCIE interface 100. The PCIE interface 100 is provided on the long side of the baseboard, and the first cable interface 201 and the second cable interface 202 are provided on the short side of the baseboard. Each CXL controller is connected to four corresponding DIMMs.

[0126] In another implementation, the storage expansion device provided in the embodiment of the present application may only include a PCIE interface and does not include a cable interface, which will be described in detail below with reference to the accompanying drawings.

[0127] See Figure 7, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0128] The storage expansion device shown in Figure 7 is similar to the storage expansion device shown in Figure 6 in that both include two CXL controllers, each connected to four corresponding DIMMs. The PCIE interface 100 is provided on the long side of the substrate, and the same parts are not repeated here.

[0129] The storage expansion device shown in FIG7 differs from the storage expansion device shown in FIG6 in that the storage expansion device provided in the embodiment of the present application includes a PCIE interface 100, but does not include a cable interface. The PCIE interface 100 is in the form of a standard PCIE card and can be vertically plugged into the backplane of the server.

[0130] The 8Lane CXL bus of the first CXL controller A is connected to the PCIE interface 100, and the 8Lane CXL bus of the second CXL controller B is connected to the PCIE interface 100. Therefore, the four DIMMs expanded by the first CXL controller A and the four DIMMs expanded by the second CXL controller B can be accessed through the PCIE interface 100.

[0131] The storage expansion device shown in Figure 7 includes a PCIE interface. In addition, the storage expansion device provided in the embodiment of the present application may only include a cable interface without a PCIE interface, which will not be repeated here.

[0132] The following describes in detail with reference to the accompanying drawings how the storage expansion device includes a PCIE interface, but how the PCIE interface is implemented as a plug-in card.

[0133] See Figure 8, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0134] The storage expansion device shown in FIG8 is the same as the storage expansion device shown in FIG6 in that both include two CXL controllers, each CXL controller is connected to corresponding four DIMMs, and the same parts are not repeated here.

[0135] Comparing Figure 8 with Figure 6, the difference between the two is that the PCIE interface 100 in Figure 8 is set on the short side of the substrate. The PCIE interface 100 in Figure 8 is configured as a plug-in card, that is, the gold finger can be horizontally plugged into the backplane of the server in the form of a plug-in card.

[0136] Meanwhile, the storage expansion device provided in FIG8 includes a first cable interface 201 and a second cable interface 202 . For detailed descriptions, please refer to the corresponding descriptions in FIG6 , which will not be repeated here.

[0137] The storage expansion device shown in Figure 8 includes a cable interface and a PCIE interface. In addition, the storage expansion device provided in the embodiment of the present application may only include a PCIE interface without a cable interface. The following will continue to introduce it in detail with reference to the accompanying drawings.

[0138] See Figure 9, which is a schematic diagram of another storage expansion device provided in an embodiment of the present application.

[0139] The difference between the storage expansion device provided in FIG. 9 and the storage expansion device provided in FIG. 8 is that the storage expansion device provided in FIG. 9 does not include a cable interface but only includes a PCIE interface 100 .

[0140] The storage expansion device provided in the embodiment of the present application includes a PCIE interface 100, which is configured as a plug-in card. That is, the gold finger can be horizontally plugged into the backplane of the server in the form of a plug-in card.

[0141] The X8 interface of the first CXL controller A is connected to the PCIE interface 100, and the X8 interface of the second CXL controller B is connected to the PCIE interface 100. Therefore, the four DIMMs expanded by the first CXL controller A and the four DIMMs expanded by the second CXL controller B can be accessed through the PCIE interface 100.

[0142] The CXL controller on the storage expansion device provided in the embodiments of the present application supports bifurcation and, through an address mapping unit, enables access to all memory spaces on the storage expansion device via a cable interface or PCIE interface. For example, an X16 interface can be connected to eight DIMMs for increased memory density. Furthermore, supporting a gold finger or cable interface allows the server to access all memory spaces by simply connecting to one of the gold finger or cable interfaces.

[0143] Furthermore, the storage expansion device provided in the embodiment of the present application can be plugged in and out of the chassis of the computing device, making the CXL memory card easy to maintain and allowing manufacturers to not be restricted to the supply of E3.S-type memory particles.

[0144] The above embodiment is based on the example of connecting a CXL controller to four DIMMs. It should be understood that a CXL controller can also expand a larger number of DIMMs. Regardless of the number of DIMMs expanded by a CXL controller, using the technical solution provided in the embodiment of the present application, a cable interface or PCIE interface can access all DIMMs expanded by each CXL controller. This allows access to all CXL memories on the storage expansion device through a single interface of the storage expansion device, thereby improving memory density and saving costs.

[0145] Furthermore, the embodiments of the present application do not specifically limit the number of CXL controllers that can be installed on a storage expansion device. While the above embodiments utilize two CXL controllers as an example, it should be understood that in other embodiments, a larger number of CXL controllers can be integrated on a storage expansion device, thereby enabling the expansion of a larger number of DIMMs. For example, integrating four CXL controllers can integrate 16 DIMMs, and the memory space of all 16 DIMMs can be accessed via a cable interface or PCIE interface. The above is merely an example, and it should be understood that an odd number of CXL controllers can be installed on a storage expansion device, and this is not specifically limited here.

[0146] Based on the storage expansion device provided in the above embodiment, the present application also provides a computing device, which is described in detail below with reference to the accompanying drawings. The present application does not specifically limit the specific type of computing device, for example, the computing device can be a server.

[0147] See Figure 10, which is a schematic diagram of a computing device provided in an embodiment of the present application.

[0148] The computing device provided in the embodiment of the present application includes: a backplane 2000 and a storage expansion device 3000 described in any one of the above embodiments;

[0149] The storage expansion device 3000 is connected to the backplane 2000 .

[0150] It should be understood that the embodiment of the present application does not specifically limit the number of storage expansion devices 3000 included in the computing device. It can be one or more, and can be set according to the actual scenario.

[0151] Furthermore, the computing device provided in the embodiments of the present application does not specifically limit the connection method between the storage expansion device 3000 and the backplane 2000. As described in the above embodiments, the PCIE interface included in the storage expansion device 3000 can be configured as a PCIE standard card form, and the storage expansion device can be vertically plugged into the backplane 2000. Alternatively, the PCIE interface included in the storage expansion device 3000 can also be configured as a plug-in card form, and the storage expansion device 3000 can be horizontally plugged into the backplane 2000.

[0152] It should be understood that the PCIE interface in Figure 10 is in the form of a PCIE standard card, and the storage expansion device 3000 shown in Figure 10 is a schematic diagram. If it is vertically plugged into the backplane 2000, that is, the storage expansion device 3000 and the backplane 2000 are perpendicular to each other, there will be an obstruction between the storage expansion device 3000 and the backplane 2000 after vertical plugging. In order to understand the connection relationship between the backplane 2000 and the storage expansion device 3000, Figure 10 is only a schematic diagram and does not represent the actual physical form and layout.

[0153] The computing device provided in the embodiment of the present application can access all memories through the PCIE interface, i.e., the gold finger, and can also access all memories through the cable interface, thereby realizing the demand for accessing high-density memory with fewer interface resources. For example, the memory density of 8 DIMMs can be expanded using the X16 interface, so that more memory can be accessed using fewer interfaces, thereby saving the number of interfaces and improving the memory density of a single storage expansion device, thereby improving the memory density of the computing device.

[0154] The above description is only a preferred embodiment of the present application and does not constitute any formal limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A storage expansion device, characterized in that: include: A baseboard and a cable interface, a PCIE interface, a first CXL controller, a second CXL controller, and a plurality of dual in-line memory modules (DIMMs) arranged on the baseboard; The first CXL controller is connected to a first portion of the plurality of DIMMs, and the second CXL controller is connected to a second portion of the plurality of DIMMs; The CXL interface of the first CXL controller is divided into a first CXL interface and a second CXL interface. The first CXL interface of the first CXL controller is used to connect to the cable interface, and the second CXL interface of the first CXL controller is used to connect to the PCIE interface. Both the first CXL interface and the second CXL interface of the first CXL controller can access the memory space of all DIMMs connected to the first CXL controller. The CXL interface of the second CXL controller is divided into a first CXL interface and a second CXL interface. The first CXL interface of the second CXL controller is used to connect to the cable interface, and the second CXL interface of the second CXL controller is used to connect to the PCIE interface. Both the first CXL interface and the second CXL interface of the second CXL controller can access the memory space of all DIMMs connected to the second CXL controller. The cable interface is configured to access all memory spaces connected to the first CXL controller and the second CXL controller; The PCIE interface is used to access all memory spaces connected to the first CXL controller and the second CXL controller.

2. The storage expansion device according to claim 1, wherein: The CXL interface of the first CXL controller is an X16 interface, and the first and second CXL interfaces of the first CXL controller are both X8 interfaces; the first CXL interface of the first CXL controller is connected to the first X8 interface of the cable interface, and the first CXL interface of the second CXL controller is connected to the second X8 interface of the cable interface; The cable interface is used to access all memory spaces of the first part of DIMMs and to access all memory spaces of the second part of DIMMs.

3. The storage expansion device according to claim 1 or 2, wherein: The CXL interface of the second CXL controller is an X16 interface, and the first and second CXL interfaces of the second CXL controller are both X8 interfaces; the PCIE interface is divided into a first X8 interface and a second X8 interface; the second CXL interface of the first CXL controller is connected to the first X8 interface of the PCIE interface, and the second CXL interface of the second CXL controller is connected to the second X8 interface of the PCIE interface; The PCIE interface is used to access all memory spaces of the first part of DIMMs and to access all memory spaces of the second part of DIMMs.

4. The storage expansion device according to any one of claims 1 to 3, wherein: The first CXL controller stores a first mapping table and a second mapping table. The first mapping table corresponds to the first portion of the CXL interfaces of the first CXL controller, and the second mapping table corresponds to the second portion of the CXL interfaces of the first CXL controller. The first mapping table implements mapping and conversion of memory physical addresses of servers connected to the first portion of the CXL interfaces of the first CXL controller to memory physical addresses of all DIMMs of the first CXL controller. The second mapping table implements mapping and conversion of memory physical addresses of servers connected to the second portion of the CXL interfaces of the first CXL controller to memory physical addresses of all DIMMs of the first CXL controller.

5. The storage expansion device according to any one of claims 1 to 3, wherein: The second CXL controller stores a third mapping table and a fourth mapping table. The third mapping table corresponds to the first portion of the CXL interfaces of the second CXL controller, and the fourth mapping table corresponds to the second portion of the CXL interfaces of the first CXL controller. The third mapping table implements mapping and conversion of memory physical addresses of servers connected to the first portion of the CXL interfaces of the second CXL controller to memory physical addresses of all DIMMs of the second CXL controller. The fourth mapping table implements mapping and conversion of memory physical addresses of servers connected to the second portion of the CXL interfaces of the second CXL controller to memory physical addresses of all DIMMs of the second CXL controller.

6. The storage expansion device according to claim 2, wherein: Also included are a sensor and a system management bus SMbus switch interface provided on the substrate; The sensor is used to detect the temperature of the storage expansion device; A first end of the SMbus switch interface is connected to the first CXL controller and the second CXL controller; The second end of the SMbus switch interface is connected to the sensor; the third end of the SMbus switch interface is used for a cable interface or a PCIE interface.

7. The storage expansion device according to any one of claims 1 to 6, wherein: The cable interface and the PCIE interface both provide a clock pin, a reset pin, an SMbus pin, an in-position pin and a power pin, and the third end of the SMbus switch interface is connected to the SMbus pins of the cable interface and the PCIE interface.

8. The storage expansion device according to any one of claims 1 to 6, wherein: The storage expansion device is in the form of a PCIE standard card, and the PCIE interface is arranged on the long side of the substrate, which is used to be vertically plugged into the backplane of the computing device. Alternatively, the storage expansion device is in the form of a plug-in card, and the PCIE interface is arranged on the short side of the substrate, which is used to be horizontally plugged into the backplane of the computing device.

9. A storage expansion device, characterized in that: include: A baseboard and a cable interface, a PCIE interface, a CXL controller, and a plurality of dual in-line memory modules (DIMMs) disposed on the baseboard; The CXL controller is connected to the plurality of DIMMs; The CXL interface of the CXL controller is divided into a first CXL interface and a second CXL interface, the first CXL interface is connected to the cable interface, and the second CXL interface is connected to the PCIE interface; the first CXL interface and the second CXL interface can both access the memory space of all DIMMs connected to the CXL controller; The cable interface is used to access all memory spaces of the CXL controller; The PCIE interface is used to access all memory spaces of the CXL controller.

10. A computing device, characterized in that include: A backplane and a storage expansion device according to any one of claims 1 to 9; The storage expansion device is connected to the backplane.

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