High power density low parasitic inductance sic half bridge module

Abstract

A high power density power module comprising a substrate, a first set of semiconductor dies positioned on the substrate and a second set of semiconductor dies positioned on the substrate. First, second and third power terminals are positioned on the substrate between the first and second sets of semiconductor dies, wherein the second power terminal is positioned between the first and third power terminals such that the second and third power terminal overlap. The first power terminal is electrically connected to a drain terminal of the first set of semiconductor dies and a source terminal of the second set of semiconductor dies. The second power terminal is electrically connected to a source terminal of the first set of semiconductor dies. The third power terminal is electrically connected to a drain terminal of the second set of semiconductor dies.

Description

[0001] High Power Density Low Parasitic Inductance SiC Half Bridge Module

[0002] Field of Disclosure

[0003] The present application relates to high power density power modules, and in particular but not limited to high power density SiC power modules.

[0004] Background

[0005] Silicon Carbide (SiC) power semiconductors are an increasingly used for advanced power conversion systems due to the fast switching frequency and improved efficiency of SiC wide bandgap (WBG) technology compared to that of Silicon (Si). SiC power modules are suitable for a variety of applications including automotive, renewable energy, industrial and battery charging.

[0006] For industry application, such as the automotive industry, half bridge SiC modules are generally provided in a module structure where power chips are attached onto a substrate and interconnected by ultrasonic wire bonds; the power substrate then attached to a baseplate for mechanical support and housing. While automotive industry half bridge inverter modules can be produced in a number of packaging outlines, each outline is typically designed to tackle the primary automotive concerns of efficiency (e.g. in terms of reduction of losses and of removal of heat generated through those losses).

[0007] The Applicant has recognised a need for high power density semiconductor module designs, and in particular but not exclusively a high power density SiC power module design, that provides a compact package with a high reliability across a large temperature range and low power loop inductances.

[0008] Summary

[0009] Aspects and preferred features are outlined in the accompanying claims.

[0010] The present disclosure generally relates to a compact power module design with a symmetrical die layout, which may optionally utilise advanced integrated metal baseplate (IMB) technology, pressureless Cu sintering and clip interconnect technology. According to a first aspect of the present disclosure, there is provided a high power density power module comprising: a substrate, for example an insulated metal baseplate (IMB) substrate; a first set of semiconductor dies positioned on the substrate; a second set of semiconductor dies positioned on the substrate; first, second and third power terminals positioned on the substrate between the first and second sets of semiconductor dies, wherein the second power terminal is positioned between the first and third power terminals such that the second and third power terminal overlap or can be overlapped; and wherein the first power terminal is electrically connected to a drain terminal of the first set of semiconductor dies and a source terminal of the second set of semiconductor dies; the second power terminal is electrically connected to a source terminal of the first set of semiconductor dies; and the third power terminal is electrically connected to a drain terminal of the second set of semiconductor dies.

[0011] The positioning (e.g. overlap) of the second and third (e.g. DC+ and DC-) power terminals or busbars facilitates a reduction in parasitic inductances of the power module. The second and third power terminals may further have a relatively small separation, to further reduce the parasitic inductances. For example, the second and third power terminals may have a separation of 20mm or less, 15mm or less, 10mm or less, 5mm or less, 2mm or less, 1mm or less between them. The separation of the power terminals may be selected to provide adequate insulation at the desired power rating. For example, a 1200V 600A SiC power module according to the present disclosure may have power terminals with a clearance of 5.5mm and a creepage of 11mm.

[0012] In implementations, an insulating layer or film may be provided between the second and third power terminals to facilitate a smaller separation. The insulating layer may comprise any suitable electrically insulating material. The insulating layer may be a thin insulating layer, for example with a thickness of e.g. 1 mm or less.

[0013] Additionally, the central location of the power terminals, i.e. between the sets of semiconductor dies, facilitates a symmetrical die layout to thereby provide a shortened power communication loop. The semiconductor dies may be silicon carbide (SiC) based dies. Alternatively, other suitable semiconductor dies such as silicon (Si) based dies may also be used, and for example may be attached to the substrate via pressure assisted copper (Cu) sintering. The symmetric layout of the power module may be maintained through the positioning of further electrical components. For example, in implementations the power module may comprise first and second sets of (gate) resistors. Each of the resistors of the first set of resistors may be electrically connected to a gate terminal of a respective die of the first set of semiconductor dies, and each of the resistors of the second set of resistors may be electrically connected to a gate terminal of a respective die of the second set of semiconductor dies. The first and second set of resistors may be positioned on the substrate geometrically parallel to the first and second sets of semiconductor dies, such that the first set of resistors are positioned on the substrate between the first set of semiconductor dies and a first edge of the substrate, and the second set of resistors are positioned on the substrate between the second set of semiconductor dies and a second edge of the substrate.

[0014] As such, the power terminals and semiconductor dies may maintain a central position on the substrate, providing a symmetrical layout across the power module. Power modules according to the present disclosure may therefore comprise a compact layout with short power communication loops. Additionally, the communication loops may be symmetrical to further facilitate balancing of high and low side parasitic inductances, and reduced gate / control loop and common source inductances.

[0015] In implementations, the first set of semiconductor dies and the second set of semiconductor dies are each arranged geometrically in a line in a first dimension, and wherein the first and second sets of semiconductor dies are separated from one another in a second dimension that is perpendicular to the first dimension. Optionally, the second and third power terminals may overlap in the second dimension.

[0016] The power module may be arranged in a half bridge configuration, with e.g. 6 dies paralleled in a line as a switch. However, customized power solutions can be realised by increasing or decreasing the number of dies (such as SiC MOSFETs) for each switch. Advantageously therefore, by providing the dies adjacent to (or with small separations) one another in a line, the overall module (e.g. half-bridge) structure may be easily preserved while altering the number of parallel dies.

[0017] In implementations, the first and second sets of semiconductor dies are attached to the substrate via copper (Cu) sintering techniques, and optionally via pressureless copper sintering. The use of copper sintering for die attachment facilitates a die connection with a high reliability at relatively high operational temperatures. Additionally or alternatively, the power module may comprise one or more first copper clips and one or more second copper clips, each first copper clip providing an electrical connection between the second power terminal and a plurality of dies of the first set of semiconductor dies, and each second copper clip providing an electrical connection between the third power terminal and a plurality of dies of the second set of semiconductor dies. The use of clip interconnects (for example Copper clips) for topside connections between the semiconductor dies and the power terminals may similarly facilitate high electrical and / or thermal performance when compared to other interconnect technologies.

[0018] To further assist in measuring or detecting thermal performance, the power module may comprise one or more temperature sensors for monitoring a temperature of the power module. For example, the power module may comprise a temperature sensor corresponding to the high side switch and a temperature sensor comprising to the low side switch of a half-bridge configuration. Optionally, the temperature sensor(s) may be a Negative Temperature Coefficient (NTC) thermistor.

[0019] The power module may comprise one or more auxiliary terminals positioned towards an edge of the substrate, the one or more auxiliary terminals electrically connected to the substrate, for example via ultrasonic bonds such as Aluminium ultrasonic bonds. Optionally, the one or more auxiliary terminals comprise a press-fit connection, e.g. to facilitate easy connections to the gate drive board for an end user. The auxiliary terminals may provide various functionality for the power module, for example acting as external source, gate or drain terminals for the semiconductor dies, and / or acting as external connection terminals for other components such as a temperature sensor.

[0020] High temperature lead-free solder interconnections or other suitable means may be used for connecting various electrical components to the substrate, such as the power terminals and / or any clips, resistors and temperature sensors provided in the power module.

[0021] In implementations, the power module may comprise a frame perpendicular to the substrate, wherein the frame surrounds at least the first and second set of semiconductor dies and first, second and third power terminals. The frame may house all of the components provided on the substrate. The frame may provide additional mechanical stability to the power module. Optionally, the power terminals may be bent such that they comprise a first section perpendicular to the substrate and a second section parallel to the substrate. In implementations comprising a frame, the second section of the power terminals may be level with or approximately level with a top of the frame. The frame may therefore define an internal volume of the power module to provide a compact, low volume power module design with a high mechanical stability.

[0022] In implementations, an encapsulation layer may be provided above the substrate. The encapsulation layer may at least partially surround the first and second set of semiconductor dies and first, second and third power terminals, and / or any other electrical components provided on the substrate. In particular, the power terminals and / or auxiliary terminals may extend at least partially beyond the encapsulation layer, to facilitate external connections. The encapsulation layer may be provided within a frame or other housing of the power module, to enhance an isolation of the components of the power module by (e.g. epoxy) encapsulation materials.

[0023] The encapsulation layer may comprise an epoxy moulding compound, provide isolation for the components of the power module and / or to further enhance the reliability of the module at high temperatures. In implementations, the encapsulation layer material may be selected such that the substrate (e.g. an insulated metal baseplate) and the encapsulation layer have the same or similar coefficients of thermal expansion (CTE), to further enhance the operational lifetime of the power module.

[0024] In implementations, the power module comprises only a single substrate. For example, the power module may not comprise any auxiliary substrates or other PCB, with all components instead being attached to the (only) substrate. The substrate may be an insulated metal substrate or baseplate (IMB). The use of a single substrate may both facilitate compact module designs, and further improve the thermal cycling capability due to the lack of substrate attach e.g. between the substrate and any secondary substrates.

[0025] In implementations, additional structures, such as ribbon bond structures or pinfin structures, can be added to the bottom surface of the (IMB) substrate, to thereby facilitate further improvements to the thermal performance of the power module via e.g. direct liquid cooling or other cooling techniques.

[0026] Implementations of the present disclosure may provide an Integrated Power Module (IPM) packaging for inverter applications, such as automotive inverter applications. However, it may also be utilized for other industrial applications, in particular for applications in which similar power ratings, high power densities, low inductances and high reliability requirements are emphasized. According to a second aspect of the invention, there is provided a method of making a high power density power module, comprising: attaching, to a substrate, a first set of semiconductor dies; attaching, to the substrate, a second set of semiconductor dies; attaching first, second and third power terminals to the substrate and positioned between the first and second sets of semiconductor dies, wherein the second power terminal is positioned between the first and third power terminals such that the second and third power terminal overlap; electrically connecting the first power terminal to a drain terminal of the first set of semiconductor dies and a source terminal of the second set of semiconductor dies; electrically connecting the second power terminal to a source terminal of the first set of semiconductor dies; and electrically connecting the third power terminal to a drain terminal of the second set of semiconductor dies.

[0027] The method may comprise geometrically positioning each of the first set of semiconductor dies and the second set of semiconductor dies in a line in a first dimension, and wherein the first and second sets of semiconductor dies are separated from one another in a second dimension that is perpendicular to the first dimension. Optionally, the method may comprise positioning the second and third power terminals such that they overlap in the second dimension.

[0028] In implementations, the steps of attaching the first and second sets of semiconductor dies to the substrate comprises attaching the first and second sets of semiconductor dies to the substrate via pressureless copper sintering techniques.

[0029] In implementations, the method may comprise forming an encapsulation layer above the substrate, the encapsulation layer at least partially surrounding the first and second set of semiconductor dies and first, second and third power terminals, and optionally wherein the encapsulation layer comprises an epoxy moulding compound.

[0030] The method may further comprise one or more steps of: connecting other components or electrical components (e.g. resistors, auxiliary terminals, temperature sensors, clip interconnects etc.) to the substrate. Optionally these components may be attached to the substrate via soldering; attaching a frame to the substrate, for example via glue or soldering; bending the power terminals such that they comprise a first section approximately perpendicular to the substrate and a second section approximately parallel to the substrate; and electrically connecting any auxiliary terminals to the other components of the power module, e.g. via wire bonding techniques.

[0031] Brief Description of the Figures

[0032] Some preferred embodiments of the invention will now be described, by way of example only and with reference to the accompanying drawings, in which:

[0033] Figure 1 illustrates an example power module design according to implementations of the present disclosure.

[0034] Figure 2 illustrates a further view of an example power module design according to implementations of the present disclosure.

[0035] Figure 3 illustrates an example circuit schematic according to implementations of the present disclosure.

[0036] Figures 4, 5a, 5b, 6 illustrate an example power module according to implementations of the present disclosure at various stages of a packaging process.

[0037] Figure 7 illustrates a flow diagram depicting a method of making a power module according to implementations of the present disclosure.

[0038] Detailed Description of the Preferred Embodiments

[0039] Figures 1 and 2 illustrate respectively top and side view of an example power module 100 in a half bridge configuration. The power module 100 comprises a substrate 107, such as an insulated metal substrate (IMS). The substrate 107 may optional be attached or connected to a baseplate, for example an insulated metal baseplate (IMB). Advantageously, power module designs according to the present disclosure may be provided on only a single substrate, i.e. without the use of any auxiliary substrate structures.

[0040] Each switch of the power module 100 comprises sets of parallel connected semiconductor dies 112 arranged geometrically in a line on the substrate 107. Each die 112 may comprise a resistor. Power module 100 comprises six high side dies 112b forming a “high side switch”, as well as six low side dies 112a forming a “low side switch”. As depicted in Figure 1 , each of the high side and low side dies 112 may be provided adjacent to one another or separated from one another in a first dimension, while the sets of high and low side dies may be separated in a second (perpendicular) dimension.

[0041] The dies 112 may be or comprise any suitable transistor, for example SiC MOSFETs or other field effect transistors.

[0042] While six dies 112 are provided for each switch in this example, it will be understood that any number of dies 112 may instead be provided for each switch. For example, in a half-bridge configuration 1 , 2, 3, 4 or more dies 112 may be provided for each switch, such that each of the high and low side switches is provided with the same number of dies 112. Generally speaking, different power ratings for the power module may be provided by paralleling different number of dies per switch, and the geometrically linear lay out of the dies facilitates easy adjustment to the number of parallel dies to enable the power level of the power module 100 according to the needs for the intended use. As such, the number of dies 112 provided for each switch may be determined by the desired power rating of the device. Power module 100 may be, for example, a 1200V 600A SiC power module.

[0043] The dies 112 may be attached to the substrate via any suitable means, for example by silver (Ag) or copper (Cu) sintering, soldering etc. In one implementation, the dies 112 are attached to the substrate via pressureless copper sintering techniques.

[0044] The power module 100 comprises busbars or power terminals 101 , 102, 103 positioned centrally on the substrate between the lines of high and low side dies 112a,b. A first, AC, power terminal 101 is positioned near to the low side switch, and a third, DC+, power terminal 103 is positioned near the high side switch. A second, DC-, power terminal 102 is positioned between the first and third terminals 101 , 103. The positioning of the DC+ and DC- power terminals 102, 103 (e.g. such that they overlap and are in close proximity) may increase mutual coupling to thereby facilitate a reduction in parasitic inductances, as well as facilitating a compact module design with a high power density.

[0045] The power terminals 102, 103 may be positioned with an air gap (e.g. of 10mm or less, 5mm or less, 2mm or less, 1mm or less, etc.) between them, or may otherwise be separated by an insulating layer or film. The insulating layer may comprise any suitable electrically insulating material. The insulating layer may be a thin insulating layer, for example with a thickness of e.g. 1 mm or less. Additionally or alternatively, the power module may be provided with housing, such as a frame and / or lid, and the housing may comprise shielding features to further enhance an isolation of the power terminals.

[0046] Power terminals 101 , 102 and 103 may be “bent” such that they each comprise a first section perpendicular to the substrate 107 and a second section parallel to the substrate 107, as depicted in Figure 2. In Figure 1 , by contrast, power terminals 101 , 102 and 103 are depicted “straight” or “unbent”, such that they are perpendicular to the substrate 107 and do not comprise an upper parallel section as depicted in Figure 2. It will be understood that the power terminals 101 , 102, 103 may be provided bent as in Figure 2 or unbent as in Figure 1 , depending on the intended use of the device in question. Advantageously however, the “bent” power terminals as depicted in Figure 2 may facilitate a more compact power module package without reducing an external connection area of the power terminals.

[0047] Integrated gate resistors 108 may be provided for each die 112 such that the resistors are electrically connected to gate terminals of the respective dies 112. For example, each (e.g. SiC) semiconductor die 112 may be integrated with one corresponding gate resistor 108. Optionally, and as depicted in Figure 1 , the resistors 108 may be positioned on substrate 107 geometrically parallel to the respective line of dies 112. The resistors 108 may be provided between the dies 112 and the respective edges of substrate 107. Advantageously, the symmetric design of the power module 100 may facilitate a symmetric and low profile current communication loop with uniform current balancing. This in turn may further reduce a parasitic inductance of the power module 100.

[0048] Two clips 104, 105 are provided for each switch, with each clip interconnecting three dies 112 and a respective power terminal. Clips 104b, 105b provide an electrical connection between the high side dies 112b and the third power terminal 103, while clips 104a, 105a provide an electrical connection between the low side dies 112a and the second power terminal 102. The clips 104, 105 may comprise any suitable material, such as copper, and may advantageously provide improved electrical and / or thermal performances relative to other connection methods. Alternatively, electrical connections between the dies and the power terminals may be provided via e.g. wire bonds or any other suitable method. An even number of dies 112 may be provided for each switch, such that each of the two clips 104, 105 may be connected to the same number of dies 112.

[0049] Integrated temperature sensors 109 such as Negative Temperature Coefficient (NTC) sensors may be provided on the substrate for temperature monitoring. Auxiliary terminals 106 may be provided at the edge of the substrate 107, e.g. between the dies 112 and / or resistors 108 and the respective edges of the substrate 107. Auxiliary terminals 106 may be electrically connected to components of the power module 100 via any suitable means, for example wire bonds 110. The wire bonds 110 may be connected via e.g. ultrasonic Aluminium (Al) wire bonding techniques, or by other suitable means such as soldering.

[0050] Each auxiliary terminal may comprise e.g. a press-fit pin, for easy connection to external components. Power module 100 may comprise any or all of auxiliary terminals 106a,b,f,g connected to respective temperature sensors 109 for detecting a temperature of the module, source auxiliary terminals 106c, h, gate auxiliary terminals 106d,i, middle point (MP) auxiliary terminal 106e, and DC+ auxiliary terminal 106j. Auxiliary terminal 106j may, for example, be used in test and characterisation processes.

[0051] It will be understood that the number and / or function of the auxiliary terminals may be varied depending on the application and desired functionality of the power module. By way of example, a power module without temperature sensors 109 may not comprise one or more of auxiliary terminals 106a,b,f,g. As a further example, an alternative power module implementation may not include a DC+ auxiliary terminal 106j.

[0052] Figure 3 depicts an example circuit schematic corresponding to a power module according to implementations of the present disclosure, such as power module 100. The schematic depicts the respective electrical connections of the high switch MOSFETs M7-M12 and low switch MOSFETs M1-M6, such as the dies 112 of power module 100.

[0053] Figures 4, 5a, 5b, 6 depict an example power module according to implementations of the present disclosure at various stages of a packaging process. Power module 400 of Figure 4 corresponds to power module 100 of Figure 1 , comprising terminals 402, 403 and 404 positioned centrally on substrate 401.

[0054] Figures 5a and 5b illustrate various views of a power module 500 at a later step of a packaging process. Relative to power module 400, a frame 501 is provided about an edge of the substrate 401 such that external connections 502 for the auxiliary terminals are integrated into respective ends of the frame, to thereby further reduce a profile of the package. The external connections 502 may be pressfit pins that integrated with the frame 501. The press fit pins may be connected to one or more auxiliary terminals provided on the substrate, for example via wire bonds such as ultrasonic aluminium wire bonds. As discussed above, terminals 402, 403 and 404 may optionally be “bent” to further reduce the profile of the power module and provide a more compact package. Optionally the frame may include other housing components, such as a lid.

[0055] Figure 6 illustrates a power module 600 at a later step of a packaging process. Relative to power module 500, an encapsulation layer 601 over substrate 401 and within frame 501 may be provided to enhance a mechanical and thermal stability of the power module. The encapsulation layer 601 may be e.g. an epoxy based encapsulation layer. For example, the encapsulation layer may comprise an epoxy moulding compound (EMC). In implementations, the encapsulation layer 601 and substrate 401 may have a similar or same coefficient of thermal expansion (CTE) to further enhance the reliability of the power module 600 across its operational temperature range. Any suitable method may be used for encapsulating the power module. For example, a liquid epoxy or other encapsulation material may be potted into the area housed by frame in a vacuum to cover all of the components assembled on the substrate 401. The epoxy material is then cured to form a solid encapsulation layer.

[0056] Implementations of the present disclosure may therefore provide a power module arranged on a single substrate with high mechanical and thermal reliability, and low parasitic inductances.

[0057] Figure 7 illustrates a flow diagram 700 of a method for manufacturing a power module according to implementations of the present disclosure.

[0058] In step S701 , high and low side dies are attached to a substrate. The high and low side dies may be positioned on the substrate geometrically in respective lines corresponding to the high and low side switches of the power module. The dies may be placed using a die bonder and bonded via any suitable method, such as pressureless copper sintering.

[0059] In step S702, various other components may be attached to the substrate. For example, clips, busbars or power terminals, resistors & temperature (NTC) sensors may be attached to the substrate. The components may be electrically connected by any suitable means, for example by reflowing of high temperature lead-free (e.g. Sn-Sb) solder.

[0060] In step S703, a frame may be attached to the substrate. The frame may be attached via any suitable means, such as gluing. The frame may be positioned around a perimeter of the substrate or else such that it surrounds the components of the power module. Optionally, the frame may integrate one or more auxiliary terminals.

[0061] In step S704, one or more auxiliary terminals together with the gate resistor connection are electrically connected to the respective components of the power module, for example via wire bonding. In one example, the substrate may be provided with conductive regions for receiving electrical components, and some or each of the conductive regions (i.e. the available component positions) may be connected to the auxiliary terminals.

[0062] In step S705, the power terminals or busbars may be bent such that they comprise a first section approximately perpendicular to the substrate and a second section approximately parallel to the substrate. The power module may be encapsulated e.g. via an epoxy encapsulation layer formed above the substrate.

[0063] It will be understood that the ordering of steps S701-S705 may be altered and / or one or more steps may be omitted entirely. For example, wire bonding of components to respective auxiliary terminals may occur prior to the attachment of a frame to the substrate, or all wire bonding may occur in a single step after the frame is bonded to the substrate.

[0064] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘above’, ‘top’, ‘side’, etc. are made with reference to conceptual illustrations of an apparatus, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a device when in an orientation as shown in the accompanying drawings.

[0065] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure, which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:1 . A high power density power module comprising: a substrate; a first set of semiconductor dies positioned on the substrate; a second set of semiconductor dies positioned on the substrate; first, second and third power terminals positioned on the substrate between the first and second sets of semiconductor dies, wherein the second power terminal is positioned between the first and third power terminals such that the second and third power terminal overlap; and wherein the first power terminal is electrically connected to a drain terminal of the first set of semiconductor dies and a source terminal of the second set of semiconductor dies; the second power terminal is electrically connected to a source terminal of the first set of semiconductor dies; and the third power terminal is electrically connected to a drain terminal of the second set of semiconductor dies.

2. The power module of claim 1 , wherein the first set of semiconductor dies and the second set of semiconductor dies are each arranged geometrically in a line in a first dimension, and wherein the first and second sets of semiconductor dies are separated from one another in a second dimension that is perpendicular to the first dimension.

3. The power module of claim 2, wherein the second and third power terminals overlap in the second dimension.

4. The power module of any preceding claim, comprising first and second sets of resistors; wherein each of the resistors of the first set of resistors is electrically connected to a gate terminal of a respective die of the first set of semiconductor dies; and each of the resistors of the second set of resistors is electrically connected to a gate terminal of a respective die of the second set of semiconductor dies.

5. The power module of claim 4, wherein the first and second set of resistors are positioned on the substrate geometrically parallel to the first and second sets of semiconductor dies.

6. The power module of claim 4 or 5, wherein the first set of resistors are positioned on the substrate between the first set of semiconductor dies and a first edge of the substrate; and the second set of resistors are positioned on the substrate between the second set of semiconductor dies and a second edge of the substrate.

7. The power module of any preceding claim, comprising a frame perpendicular to the substrate, wherein the frame surrounds at least the first and second set of semiconductor dies and first, second and third power terminals.

8. The power module of any preceding claim, comprising an encapsulation layer above the substrate, the encapsulation layer at least partially surrounding the first and second set of semiconductor dies and first, second and third power terminals, optionally wherein the encapsulation layer comprises an epoxy moulding compound.

9. The power module of claim 8, wherein the substrate and encapsulation layer have approximately the same coefficient of thermal expansion.

10. The power module of any preceding claim, wherein at least one of: the power module comprises only a single substrate; and / or the substrate comprises an insulated metal substrate.

11. The power module of any preceding claim, wherein the first and second sets of semiconductor dies are attached to the substrate via copper sintering, optionally wherein the first and second sets of semiconductor dies are attached to the substrate via pressureless copper sintering.

12. The power module of any preceding claim, comprising one or more first copper clips and one or more second copper clips, each first copper clip providing an electrical connection between the second power terminal and a plurality of dies of the first set of semiconductor dies, and each second copper clip providing an electrical connection between the third power terminal and a plurality of dies of the second set of semiconductor dies.

13. The power module of any preceding claim, comprising a temperature sensor for detecting a temperature of the power module, optionally wherein the temperature sensor is a Negative Temperature Coefficient thermistor.

14. The power module of any preceding claim, comprising one or more auxiliary terminals positioned towards an edge of the substrate.

15. The power module of claim 14, wherein the one or more auxiliary terminals comprise a press-fit connection.

16. A method of packaging a high power density power module according to any one of claim 1 to 15, comprising: attaching, to a substrate, a first set of semiconductor dies; attaching, to the substrate, a second set of semiconductor dies; attaching first, second and third power terminals to the substrate and positioned between the first and second sets of semiconductor dies, wherein the second power terminal is positioned between the first and third power terminals such that the second and third power terminal overlap; connecting the first power terminal to a drain terminal of the first set of semiconductor dies and a source terminal of the second set of semiconductor dies; connecting the second power terminal to a source terminal of the first set of semiconductor dies; and connecting the third power terminal to a drain terminal of the second set of semiconductor dies.

17. The method of claim 16, comprising geometrically positioning each of the first set of semiconductor dies and the second set of semiconductor dies in a line in a first dimension, and wherein the first and second sets of semiconductor dies are separated from one another in a second dimension that is perpendicular to the first dimension.

18. The method of claim 17, comprising positioning the second and third power terminals such that they overlap in the second dimension.

19. The method of any one of claims 16-18, wherein the steps of attaching the first and second sets of semiconductor dies to the substrate comprises attaching the first and second sets of semiconductor dies to the substrate via pressureless copper sintering techniques.

20. The method of any one of claims 16-19, comprising forming an encapsulation layer above the substrate, the encapsulation layer at least partially surrounding the first and second set of semiconductor dies and first, second and third power terminals, and optionally wherein the encapsulation layer comprises an epoxy moulding compound.

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