Device for storing information about an overvoltage event, and read-out device

Abstract

The invention relates to a device for storing information about an overvoltage event (5) and to a read-out device, wherein the device has: a monitoring element (10), at least a first memory cell (20) and a second memory cell (22), and at least one delay element (30), wherein the monitoring element (10) is designed to be electrically connected to a connection (42) of an electrical circuit (40) and to output an overvoltage signal (S) for a duration corresponding to an overvoltage event (5) when an overvoltage event (5) occurs. The device is designed to write to the first memory cell (20) and to activate the delay element (30) when the overvoltage signal (S) is applied and to write to the second memory cell (22) when the overvoltage signal (S) is applied and a defined delay time implemented by the delay element (30) has elapsed, and the memory cells (20, 22) are designed to be read separately.

Description

[0001] Description

[0002] title

[0003] Device for storing information about an overvoltage event and readout device

[0004] State of the art

[0005] The present invention relates to a device for storing information about an overvoltage event and a readout device for reading this information.

[0006] Modern integrated circuits (e.g., ASICs, etc.) typically have a large number of connection pins that require protection, particularly against electrostatic discharge (ESD). Most of the protective measures provided for this purpose are intended for unpowered integrated circuits (e.g., during integrated circuit manufacturing), where ESD events can lead to damage and / or degradation of the integrated circuit even before the integrated circuits are actually used.

[0007] ESD protection measures also exist for connection pins (e.g., input / output pins) of integrated circuits intended for active operation of the integrated circuits. Diodes, for example, are used to divert the respective pins to positive supply voltages (VDD) or negative supply voltages (VSS) if VDD is exceeded or VSS is undershot.

[0008] Since ESD discharges usually involve voltages of several kV, each of these discharges poses a potential risk to the integrated circuit or a counterpart of the respective pin. As long as the ESD protection is functioning and the discharges remain within a specified voltage range, the risk of damage to the integrated circuit is minimized. However, if this specified voltage range is exceeded, it is possible that the overvoltage is no longer sufficiently clamped and critical values ​​are exceeded. This can lead to damage to individual elements of the integrated circuit, such as gate oxides.

[0009] In addition, circuits are known from the prior art which detect such ESD events and, in response, output signals which represent an existing ESD event.

[0010] I. -H. Wu and M. -D. Ker, "Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control," 2022 International Symposium on VLSI Design, Automation and Test, (VLSI-DAT), 2022, pp. 1 -4, doi: 10.1109 / VLSI- DAT54769.2022.9768083, discloses, among other things, a detection of an EDS event, which is classified as an ESD or EOS ("electrical overstress") event using a time discriminator.

[0011] Disclosure of the invention

[0012] According to a first aspect of the present invention, a device for storing information about an overvoltage event is proposed, wherein the overvoltage event can be, for example, an ESD (electrostatic discharge) event and / or an EOS (electrical overstress) event.

[0013] The device according to the invention comprises a monitoring element, at least one first memory cell and one second memory cell, which can be configured for volatile or non-volatile storage of information, and at least one delay element. The monitoring element is configured to be electrically connected to a terminal of an electrical circuit and to output an overvoltage signal for a duration corresponding to an overvoltage event when an overvoltage event occurs. The overvoltage signal is accordingly a control signal generated by the monitoring element, which is preferably not influenced by the overvoltage event.

[0014] Furthermore, it is advantageously possible for the device according to the invention to additionally comprise a protective element, which is also configured to be connected to the terminal of the electrical circuit in order to protect the electrical circuit from a (positive and / or negative) overvoltage occurring at the terminal due to an overvoltage event. Furthermore, it is possible for the protective element and the monitoring element to be integrated into a circuit unit.

[0015] The protective element can, for example, be designed as an ESD clamp known from the prior art for the low-resistance discharge of overvoltages.

[0016] The electrical circuit can also be an integrated circuit or similar device, with the electrical connection being, for example, an externally contactable connection pin of the electrical circuit. Furthermore, the electrical circuit can be, for example, any semiconductor chip such as an ASIC or a different chip.

[0017] The overvoltage signal may, for example, be a signal which assumes a digital “high” level during an existing overvoltage event and assumes a digital “low” level outside of the overvoltage event, without thereby imposing a restriction on the design of the overvoltage signal.

[0018] The device is configured to write to the first memory cell and activate the delay element when the overvoltage signal is present. Writing to the memory cell is understood to mean programming the memory cell, in which the memory cell is changed from a state representing an unregistered overvoltage event (e.g., a bit set to "0") to a state representing a registered overvoltage event (e.g., a bit set to "1").

[0019] Furthermore, the device is configured to write to the second memory cell when the overvoltage signal is present and a predefined delay time implemented by the delay element, which is a delay time greater than zero, has elapsed. The memory cells are configured to be read separately, so that, based on an evaluation of the respective memory states of the respective memory cells, it is possible to determine whether an overvoltage event occurred and, if so, whether it was shorter than the delay time or longer than the delay time.Accordingly, based on the read memory cells, the level of stress caused by the overvoltage event can be determined, allowing, for example, an assessment to be made as to whether the electrical circuit monitored by the device according to the invention has suffered long-term damage following an overvoltage event, which prevents the use of the electrical circuit in general or at least in certain areas of application. Such areas of application can include, for example, areas of application in safety-critical environments, such as use in a vehicle, etc.

[0020] It should be noted in general that preferably additional memory cells can be used in conjunction with corresponding additional delay elements in order to increase a temporal resolution in the detection of the overvoltage event and / or a monitoring period.

[0021] Monitoring for occurring overvoltages can preferably be carried out during active operation of the electrical circuit, in which a supply voltage is provided for the device according to the invention and the electrical circuit. This does not preclude the device according to the invention from also being used in a passive state, for example in a non-supplied state during manufacture and / or handling of the electrical circuit and / or the device. This can be achieved, for example, by the components of the device themselves being supplied with electrical energy from an overvoltage event, wherein the electrical energy of the overvoltage event can preferably be buffered by means of one or more capacitors in order to be able to provide the device according to the invention with a voltage supply for a required minimum duration for programming.

[0022] The subclaims show preferred developments of the invention. More preferably, the at least one delay element is implemented on the basis of non-gates (inverters) with an RC element connected in between and / or on the basis of a shift register. The latter can be used advantageously in particular if, for reasons of space, the use of RC elements is not possible, but digital logic is present, for example. This can be present or provided, for example, in the electrical circuit to be protected and monitored, which can be designed, for example, as an ASIC. In this case, for example, a cleared shift register (i.e., reset to a basic state) is written to with each clock pulse of a clock signal with a value of 1 for the duration of the overvoltage event.Based on a number of memory positions in the register described with 1, the duration of the overvoltage event can be determined accordingly after the overvoltage event has expired.

[0023] In an advantageous embodiment of the present invention, the delay element is a first delay element, while the predefined delay time of the first delay element is a first predefined delay time. Furthermore, the device advantageously comprises at least one second delay element (and preferably further delay elements) that implement a second predefined delay time. In this way, an overvoltage event can be evaluated with greater accuracy.

[0024] The second delay element can be arranged upstream of the first delay element in a processing chain and configured to delay the writing to the first memory cell and the activation, i.e., the starting of the first delay element, after the occurrence of the overvoltage event by the second delay time. In this way, it is possible to ensure that an overvoltage event whose duration is shorter than the second delay time is not registered in any of the memory cells. This can be useful, for example, if the second delay time is selected to be so short that no, or no relevant, damage and / or impairment to the electrical circuit is to be expected within this short period.In general, it should be noted that when using a plurality of delay elements, these are preferably arranged one after the other in a chain, so that the plurality of delay elements are each activated one after the other by the respective preceding delay element.

[0025] Alternatively, it is possible for the second delay element to be arranged downstream of the first delay element in a processing chain and to be activated immediately after the first delay element has expired. Furthermore, the device is configured to write to a third memory cell when the overvoltage signal is present and the second delay time has expired. In this way, further delay elements and corresponding memory cells can be arranged consecutively in the processing chain to increase the temporal resolution and / or the total duration for detecting overvoltage events.

[0026] In a further advantageous embodiment of the present invention, the first delay time and the second delay time are different delay times. Alternatively or additionally, the respective delay times of the delay elements along the processing chain are defined as a function of the expected temporal progression of an overvoltage event. Further alternatively or additionally, the respective delay times of the delay elements along a processing chain comprising the delay elements increase the further away the respective delay element is from a start of the processing chain. This increase can, for example, be an exponential increase or an increase which deviates therefrom. The increasing delay times offer the advantage that an early phase of the respective overvoltage events, in which usuallyA particularly precise temporal resolution can be recorded when a maximum voltage load is expected, while a temporal resolution during the decay phase of the overvoltage event may be less precise without losing essential information regarding the load on the electrical circuit caused by the overvoltage event. This allows for a reduction in the number of required delay elements and memory cells, thus reducing costs and the space required for these.

[0027] Preferably, the device is further configured to reset the memory cells in response to receiving a reset signal and / or to increment an overvoltage counter each time an overvoltage event occurs and to store the current value of the overvoltage counter in counter memory cells provided for this purpose. Resetting the memory cells enables repeated use of the device according to the invention, which can be advantageously used in particular in conjunction with a respective incrementation of a counter value in the said counter memory cells. In this way, a history, i.e., a number of overvoltage events that have already occurred, can be recorded, while the temporal progression of the most recent overvoltage event can be specifically evaluated using the plurality of memory cells.In this context, it is particularly advantageous to imagine that only those overvoltage events lead to an incrementation of the counter value whose duration exceeds a predefined threshold, which can potentially be accompanied by a critical impairment of the electrical circuit.

[0028] According to a second aspect of the present invention, a readout device for reading memory cells of the device according to the first aspect of the invention is proposed, wherein the readout device is configured to read the memory cells individually and, based on a memory state of the respective memory cells, to determine a duration of the overvoltage event and / or a number of overvoltage events (for example, based on the aforementioned counter memory cells). Preferably, the readout device is further configured to perform a readout process based on a readout voltage that lies below a threshold voltage for writing to the memory cell, so that the information about the overvoltage events stored in the memory cell is not inadvertently overwritten or corrupted during a readout process.

[0029] Further advantageously, the readout device is configured to determine a state of an electrical circuit monitored by the device based on the readout memory cells and / or to provide the device with a reset signal in order to erase the memory cells. The readout device is, for example, a device formed separately from the device, which is connected to the device during a manufacturing process, in particular at the end of a manufacturing process of the device and the electrical circuit. In a case in which the determined overvoltage load of the electrical circuit exceeds a predefined threshold, for example, it is possible to classify the electrical circuit as faulty or insufficiently reliable.Furthermore, it is particularly advantageous for the reading device to be housed together with the device and / or the electrical circuit in a unit, for example in a housing, and / or to be integrated therewith in order to carry out an evaluation of the overvoltage load internally (e.g. while a supply voltage is applied to such a unit) and to output information about the overvoltage load state of the unit to the outside via a signal.

[0030] Short description of the drawings

[0031] Embodiments of the invention are described in detail below with reference to the accompanying drawings. In the drawing:

[0032] Figure 1 is a block diagram of an exemplary first embodiment of a device according to the invention in conjunction with an electrical circuit and a readout device according to the invention;

[0033] Figure 2 shows an exemplary embodiment of an inventive

[0034] delay element;

[0035] Figure 3 is a block diagram of an exemplary second

[0036] Embodiment of a device according to the invention; and

[0037] Figure 4 exemplary signal curves during storage of

[0038] Overvoltage information in a device according to the invention.

[0039] Embodiments of the invention Figure 1 shows a block diagram of an exemplary first embodiment of a device according to the invention for storing information about an overvoltage event in conjunction with an electrical circuit 40, which is designed here as an ASIC, and a readout device 50 according to the invention.

[0040] The device comprises a monitoring element 10, first to fifth memory cells 20, 22, 23, 24, 25 and first to fourth delay elements 30, 32, 33, 34.

[0041] The monitoring element 10 is electrically connected to a connection pin 42 of the electrical circuit 40 and, on this basis, is configured to output an overvoltage signal S (which can also be considered a control signal and / or trigger signal) for a duration corresponding to the overvoltage event when an overvoltage event occurs. Specifically, the signal S has a digital "high" level when the overvoltage event occurs and a digital "low" level otherwise.

[0042] The device is configured to write to the first memory cell 20 and to activate the first delay element 30 (ie, to start a time measurement in the first delay element 30) when the overvoltage signal S is present, specifically when the overvoltage signal performs a state change from a "low" level to a "high" level.

[0043] The device is further configured to write to the second memory cell 22 when the overvoltage signal S is present and a predefined first delay time implemented by the first delay element 30 has elapsed. For this purpose, the first delay element 30 outputs a "high" level to an AND gate immediately after the first delay time has elapsed, which logically combines the output of the first delay element 30 with the overvoltage signal S. Accordingly, the second memory cell 22 is programmed when the first delay element 30 and the overvoltage signal simultaneously have a "high" level.The delay elements 32, 33 and 34 following in the processing chain are configured corresponding to the first delay element 30 and the second memory element 22 to program the respective memory cells 22, 23, 24, 25 sequentially after respective delay times until the overvoltage signal S is no longer present, ie has an "Iow" level.

[0044] The memory cells 20, 22, 23, 24, 25 are also configured to be read separately via a readout device 50. It should be noted that the readout device 50 here is a readout device 50 integrated into the electrical circuit 40, i.e., the ASIC, which is configured to determine the duration of an overvoltage event based on the respective memory states of the memory cells 20, 22, 23, 24, 25. The respective IT connections of the readout device 50 to the memory cells 20, 22, 23, 24, 25 are not shown here for reasons of clarity.

[0045] Advantageously, the delay times of the delay elements 30, 32, 33, 34 increase the further the delay elements 30, 32, 33, 34 are arranged from a start of the processing chain.

[0046] Figure 2 shows an exemplary embodiment of a delay element 30 according to the invention. The delay element 30 is formed here on the basis of two inverters 60 and an RC element consisting of a resistor R and a capacitor C.

[0047] Figure 3 shows a block diagram of an exemplary second embodiment of a device according to the invention, wherein storage of information about an overvoltage event is implemented here on the basis of a shift register 80, which is clocked by a clock generator 70 and stores values ​​of "1" with each clock pulse of the clock generator 70 and shifts them internally in the register as long as an overvoltage signal S with a "high" level is present, which is provided by a monitoring element 10 when an overvoltage event is actively present. Figure 4 shows exemplary signal curves during storage of overvoltage information in a device according to the invention over time t.

[0048] In the event of an overvoltage event 5 occurring, an overvoltage signal S is generated by a monitoring element 10 (see Figure 1 or Figure 3) until a voltage of the overvoltage event falls below a predefined voltage threshold value TH.

[0049] After a first delay time of a first delay element 30 (see Figure 1) of the device has elapsed, a first storage operation 90 takes place in a first memory cell 20 (see Figure 1). After a delay time of a second delay element 32 (see Figure 1), a second storage operation 92 takes place in a second memory cell 20 (see Figure 1). Subsequently, a third storage operation 93 and a fourth storage operation 94 take place in a third memory cell 33 (see Figure 1) and a fourth memory cell 34 (see Figure 1), respectively.

[0050] Further memory cells are not subsequently written because the overvoltage signal S drops to a “low” level after the fourth storage operation 94, since the voltage of the overvoltage event has already fallen below the voltage threshold TH at this time.

Claims

Claims 1 . Device for storing information about an overvoltage event (5) comprising: - a monitoring element (10), - at least one first memory cell (20) and one second memory cell (22), and - at least one delay element (30), wherein - the monitoring element (10) is set up, - to be electrically connected to a terminal (42) of an electrical circuit (40), and - to output an overvoltage signal (S) for a duration corresponding to an overvoltage event (5) when an overvoltage event (5) occurs at the terminal (42), the device is arranged, - to write to the first memory cell (20) and to activate the delay element (30) when the overvoltage signal (S) is present, - to write to the second memory cell (22) when the overvoltage signal (S) is present and a predefined delay time implemented by the delay element (30) has elapsed, and - the memory cells (20, 22) are arranged to be read out separately.

2. Device according to claim 1, wherein the delay element (30) is based on - of non-gates with an RC element in between, and / or - a shift register is implemented.

3. Device according to one of the preceding claims, wherein - the delay element is a first delay element (30), - the predefined delay time of the first delay element (30) is a first predefined delay time, and - the device has at least one second delay element (32) which realizes a second predefined delay time.

4. The device according to claim 3, wherein the second delay element (32) is arranged in a processing chain upstream of the first delay element (30) and is configured to delay the writing of the first memory cell (20) and the activation of the first delay element (30) after the occurrence of the overvoltage event (5) by the second delay time.

5. Device according to claim 3, wherein - the second delay element (32) is arranged in a processing chain after the first delay element (30) and is designed to be activated immediately after the expiration of the first delay element (30), and - the device is arranged to write to a third memory cell (23) when the overvoltage signal is present and the second delay time has elapsed.

6. Device according to one of claims 3 to 5, wherein - the first delay time and the second delay time are different delay times, and / or - respective delay times of the delay elements (30, 32) along the processing chain are determined as a function of an expected temporal course of an overvoltage event (5), and / or - respective delay times of the delay elements (30, 32) along a processing chain comprising the delay elements (30, 32) increase the further away the respective delay element (30, 32) is arranged from a start of the processing chain.

7. Device according to one of the preceding claims, wherein the device is arranged - to reset the memory cells (20, 22) in response to receiving a reset signal, and / or - to increment an overvoltage counter each time an overvoltage event (5) occurs and to store the current value of the overvoltage counter in counter memory cells provided for this purpose.

8. Read-out device (50) for reading out memory cells (20, 22) of a device according to one of the preceding claims, wherein the read-out device (50) is configured to read out the memory cells (20, 22) individually and to determine a duration of the overvoltage event (5) and / or a number of overvoltage events (5) based on a memory state of the respective memory cells (20, 22).

9. Reading device (50) according to claim 8, wherein the reading device (50) is arranged - to determine a state of an electrical circuit (40) monitored by the device on the basis of the read memory cells (20, 22), and / or - providing a reset signal to the device to erase the memory cells (20, 22).

10. Reading device (50) according to claim 8 or 9, wherein the reading device (50) - is a separate unit connectable to the device, or - is a jointly formed unit with the device.

Images