Semiconductor device

Abstract

The present invention provides a semiconductor device that is easily scaled down. The present invention also provides a semiconductor device that enables a higher level of integration. The semiconductor device comprises a first conductive layer, a pair of second conductive layers, a pair of third conductive layers, a pair of semiconductor layers, a first insulating layer having an opening, and a pair of second insulating layers. Each of the pair of semiconductor layers includes a first metal oxide. Each of the pair of semiconductor layers has a first region and a second region, and the second region has higher resistivity than the first region. The first conductive layer extends in a first direction. The pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the opening extend in a second direction intersecting the first direction. The first region and the second region are alternately arranged in the second direction. The first insulating layer is provided on the first conductive layer. Each of the pair of semiconductor layers has a vertical portion in contact with a side wall of the opening and a horizontal portion in contact with an upper surface of the first conductive layer. Each of the pair of semiconductor layers is in contact with the upper surface of the first conductive layer in the first region, and each of the pair of second conductive layers is in contact with the vertical portion. Each of the pair of second insulating layers covers the vertical portion and the horizontal portion, and each of the pair of third conductive layers covers the vertical portion and the horizontal portion with the second insulating layer interposed therebetween.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In recent years, along with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a need for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0008] Also, Patent Document 5 discloses a semiconductor memory device having a channel pattern having a vertical channel portion on a bit line, and a word line provided on the channel pattern so as to cross the bit line.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A U.S. Patent Application Publication No. 2023 / 0055499

[0010] An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device in which a wiring load is reduced. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention provides a semiconductor device including a first conductive layer, a pair of second conductive layers, a pair of third conductive layers, a pair of semiconductor layers, a first insulating layer having an opening, and a pair of second insulating layers, each of the pair of semiconductor layers including a first metal oxide, each of the pair of semiconductor layers having a first region and a second region, at least a part of the first region functions as a channel formation region, the second region has a higher resistivity than the first region, the first conductive layer extends in a first direction, the pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the opening extend in a second direction intersecting the first direction, and the pair of third conductive layers, the pair of semiconductor layers, and the pair of second insulating layers are a first insulating layer provided on the first conductive layer, the opening reaching an upper surface of the first conductive layer; each of the pair of semiconductor layers having a vertical portion in contact with a sidewall of the opening and a horizontal portion in contact with an upper surface of the first conductive layer; each of the pair of semiconductor layers in contact with the upper surface of the first conductive layer in the first region; each of the pair of second conductive layers having a portion located above the first insulating layer and in contact with the vertical portion; each of the pair of second insulating layers covering the vertical portion and the horizontal portion; and each of the pair of third conductive layers covering the vertical portion and the horizontal portion via the second insulating layer.

[0014] In the above, the second region preferably contains either or both of aluminum and hafnium.

[0015] In the above, the second region preferably has a higher concentration of either or both of aluminum and hafnium than the first region.

[0016] In the above, it is preferable that the first conductive layer has a first conductive film and a second conductive film over the first conductive film, the pair of semiconductor layers are each in contact with the second conductive film, the second conductive film contains a second metal oxide, and the first conductive film contains a metal.

[0017] In the above, the first metal oxide and the second metal oxide preferably contain one or more of the same elements selected from In, Sn, Zn, Ga, and Ti.

[0018] In the above, it is preferable that the second conductive film has a recess, and the pair of semiconductor layers have portions located in the recess and contact the side and upper surfaces of the second conductive film in the recess.

[0019] Furthermore, in the above, it is preferable that the semiconductor device has a pair of third insulating layers, each of which covers the vertical and horizontal portions via the second insulating layer and the third conductive layer, and the third insulating layer has the function of capturing or fixing hydrogen.

[0020] In addition, in the above, it is preferable that a capacitance element is provided on the second conductive layer, and the capacitance element has a fourth conductive layer in contact with the second conductive layer, a fifth conductive layer, and a fourth insulating layer between them.

[0021] Furthermore, in the above, it is preferable that the fourth conductive layer has a recess, the fourth insulating layer has a portion that is provided along the recess, and the fifth conductive layer has a portion that is located within the recess via the fourth insulating layer and contacts the side and top surfaces of the fourth insulating layer within the recess.

[0022] Furthermore, in the above, it is preferable that the fourth conductive layer has a columnar shape, the fourth insulating layer covers the fourth conductive layer, and the fifth conductive layer is provided to cover the top and side surfaces of the fourth conductive layer via the fourth insulating layer.

[0023] In the above, it is preferable that a transistor is provided below the first conductive layer, the transistor contains silicon as a semiconductor in which a channel is formed, and one of a source electrode and a drain electrode of the transistor is connected to the first conductive layer.

[0024] According to one embodiment of the present invention, a semiconductor device that can be easily miniaturized, a semiconductor device that enables high integration, a semiconductor device in which the load on wiring is reduced, a highly reliable semiconductor device, a semiconductor device that exhibits favorable electrical characteristics, or a semiconductor device that operates at a high speed can be provided.

[0025] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0027] FIGS. 1A and 1B are structural examples of a semiconductor device. FIGS. 2A and 2B are structural examples of a semiconductor device. FIGS. 3A and 3B are structural examples of a semiconductor device. FIGS. 4A and 4B are structural examples of a semiconductor device. FIG. 5 is a structural example of a semiconductor device. FIG. 6 is a structural example of a semiconductor device. FIGS. 7A and 7B are structural examples of a semiconductor device. FIGS. 8A and 8B are structural examples of a semiconductor device. FIGS. 9A to 9D are structural examples of a semiconductor device. FIGS. 10A to 10D are structural examples of a semiconductor device. FIGS. 11A to 11D are structural examples of a semiconductor device. FIGS. 12A to 12C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13A and 13B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14A and 14B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15A and 15B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16A and 16B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17A to 17C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18A to 18C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19A to 19C are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20A and 20B are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIG. 21 is a diagram illustrating an example of a method for manufacturing a semiconductor device. FIG. 22 is a block diagram illustrating an example of a configuration of a semiconductor device. FIGS. 23A to 23H are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 24A and 24B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 25 is a block diagram illustrating a CPU. FIGS. 26A and 26B are perspective views of a semiconductor device. FIGS. 27A and 27B are perspective views of a semiconductor device. FIGS. 28A and 28B are an example of a configuration of an electronic component. FIGS. 29A to 29C are an example of a configuration of a mainframe computer. FIG. 30A is an example of a configuration of space equipment. FIG. 30B is an example of a configuration of a storage system.

[0028] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0030] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0031] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0034] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A and B represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0035] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0036] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0037] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0038] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0039] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0040] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0041] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0042] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0043] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0044] Embodiment 1 In this embodiment, a structural example of a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device exemplified below can be applied to a memory device.

[0045] A semiconductor device according to one embodiment of the present invention includes a plurality of memory cells. Each memory cell includes one transistor and one memory element. Various elements capable of retaining stored data, such as a capacitor, a variable resistance element, a ferroelectric element, a charge trap element, or a floating gate element, can be used as the memory element. An example in which a capacitor is used as the memory element will be described below.

[0046] In a transistor included in a memory cell, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in a height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0047] More specifically, a first insulating layer having an opening and functioning as a spacer is provided on a lower electrode (first conductive layer) that is one of a source electrode and a drain electrode, and an upper electrode (second conductive layer) that is the other of the source electrode and the drain electrode is provided so as to have a portion located above the first insulating layer. The opening in the first insulating layer has a sidewall that is approximately perpendicular to the top surface of the lower electrode, and a portion of the sidewall overlaps with the lower electrode. The semiconductor layer has a vertical portion (also referred to as a vertical portion) along the sidewall, a portion in contact with the upper electrode, and a portion in contact with the lower electrode. The portion of the semiconductor layer in contact with the lower electrode may have a portion (also referred to as a horizontal portion or lateral portion) parallel to the top surface of the lower electrode. Furthermore, a gate insulating layer (second insulating layer) is provided to cover the vertical and horizontal portions of the semiconductor layer, and a gate electrode (third conductive layer) is provided to cover the vertical and horizontal portions via the gate insulating layer. Furthermore, a third insulating layer is provided covering the vertical and horizontal portions via the gate insulating layer and the gate electrode.

[0048] The two transistors of two adjacent memory cells are preferably arranged symmetrically within the opening. That is, a pair of semiconductor layers, a pair of gate insulating layers, a pair of gate electrodes, a pair of third insulating layers, a pair of upper electrodes, etc. can be arranged along a pair of side surfaces of the opening. This allows for even higher density arrangement of transistors.

[0049] The semiconductor layer is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor properties. Along the opening in the semiconductor layer, first regions that function as channel formation regions and second regions that function as element isolation regions are alternately arranged. The second regions are metal oxides to which a metal element (such as aluminum or hafnium) has been added, and have a higher resistivity than the first regions.

[0050] For example, when a semiconductor layer is patterned into islands to perform element isolation, the etching process may not be sufficient at the bottom of the opening, which may result in electrical conduction between adjacent first regions. In response to this problem, the semiconductor layer can be formed to cover the opening, and the first and second regions can be alternately formed to achieve sufficient element isolation. This allows transistors with a three-dimensional structure to be manufactured with a high yield.

[0051] Furthermore, the second region may have lower crystallinity and more oxygen vacancies than the first region. This allows the second region to capture or fix hydrogen and excess oxygen contained in the first region. Therefore, it is possible to reduce the hydrogen and excess oxygen in the first region, which functions as a channel formation region. By reducing the hydrogen concentration in the first region, it is possible to suppress a negative shift in the initial characteristics of the transistor and achieve normally-off characteristics. Furthermore, it is possible to suppress negative drift degradation in a +GBT (Gate Bias-Temperature) stress test. Furthermore, by reducing the concentration of excess oxygen in the first region, it is possible to suppress an excessive positive shift in the initial characteristics of the transistor. Furthermore, it is possible to suppress excessive positive drift degradation in a +GBT stress test.

[0052] A more specific example will be described below with reference to the drawings.

[0053] [Configuration Example] Fig. 1A shows a schematic top view of the semiconductor device 10. Figs. 2A and 2B show perspective views of the semiconductor device 10. Figs. 3A, 3B, 4A, and 4B show schematic cross-sectional views taken along the cutting lines A1-A2, B1-B2, C1-C2, and D1-D2 shown in Fig. 1A, respectively. Each figure also shows arrows indicating the X, Y, and Z directions (hereinafter sometimes referred to as the X direction, Y direction, and Z direction). The X direction, Y direction, and Z direction intersect with each other. For example, it is preferable that the X direction, Y direction, and Z direction are perpendicular to each other.

[0054] The semiconductor device 10 has a configuration in which a plurality of memory cells 15 are arranged in the X and Y directions (this can also be referred to as a matrix arrangement or a row and column arrangement). In the semiconductor device 10, conductive layers 24 functioning as bit lines extend in the X direction, and conductive layers 23 functioning as word lines extend in the Y direction. As shown in FIG. 3A , the memory cell 15 has a transistor 20 and a capacitance element 30 thereon.

[0055] 1B shows a circuit diagram corresponding to the semiconductor device 10. In FIG. 1B, a plurality of bit lines BL, a plurality of word lines WL orthogonal to each bit line, and wiring CL are shown. While FIG. 1B shows an example in which the wiring CL is parallel to the bit lines BL, the wiring CL may also be parallel to the word lines WL or may be arranged in a grid pattern. Alternatively, the wiring CL may be a flat conductive film.

[0056] The memory cell 15 includes one transistor 20 and one capacitor 30. The transistor 20 has a gate connected to a word line WL, one of a source and a drain connected to a bit line BL, and the other connected to one electrode of the capacitor 30. The other electrode of the capacitor 30 is connected to a wiring CL.

[0057] 1A and 1B, the memory cells 15 arranged along the X direction are arranged so that the orientations of the transistors 20 are staggered. That is, two transistors 20 adjacent along the X direction are arranged symmetrically with respect to the Y-Z plane.

[0058] The bit line BL functions as a wiring for writing and reading data. The word line WL functions as a wiring for controlling the on / off (conducting state or non-conducting state) of the transistor 20 functioning as a switch. The wiring CL functions as a constant potential line connected to the capacitor 30.

[0059] It is also possible to configure the structure such that a conductive layer to which a constant potential is applied is disposed between each conductive layer 24. By disposing such a conductive layer, it is possible to block signal transmission between two adjacent bit lines.

[0060] 3A and other drawings, the transistor 20 and the capacitor 30 are provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0061] 7A shows an enlarged view of the transistor 20 and its vicinity in FIG. 3A. The transistor 20 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other electrode. Here, an example is shown in which the conductive layer 24 includes a conductive film 24a and a conductive film 24b located thereon.

[0062] An insulating layer 41 is provided on the insulating layer 11, and a conductive layer 24 and an insulating layer 42 are provided on the insulating layer 41. The conductive layer 24 is provided to extend in the X direction and is embedded in the insulating layer 42. It is preferable that the heights of the upper surfaces of the conductive layer 24 and the insulating layer 42 (heights from the upper surface of the insulating layer 11) are approximately the same.

[0063] The insulating layer 41 functions as a protective insulating layer and has the function of preventing impurities such as hydrogen from diffusing from the insulating layer 11 side into the semiconductor layer 21. For example, a film through which hydrogen is less likely to diffuse than a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. In particular, it is preferable to use a silicon nitride film or a silicon nitride oxide film. Note that the insulating layer 41 does not have to be provided if it is not necessary.

[0064] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0065] The conductive layer 24 includes a conductive film 24a and a conductive film 24b located thereon. The conductive film 24a is preferably made of a conductive material having a lower resistance than the conductive film 24b. In particular, it is preferable for the conductive film 24a to contain a metal material. The conductive film 24b is preferably made of a conductive metal oxide (oxide conductor).

[0066] Using a conductive metal oxide for the conductive film 24b in contact with the semiconductor layer 21 containing a metal oxide reduces the contact resistance between them, thereby reducing the load on the wiring, which is preferable. In particular, a configuration in which the conductive film 24b contains the same metal element as the metal element contained in the semiconductor layer 21 is preferable because this further reduces the contact resistance. Specifically, it is preferable that both the semiconductor layer 21 and the conductive film 24b contain the same one or more elements selected from In, Sn, Zn, Ga, and Ti. Furthermore, using a metal material with a lower resistance than the conductive film 24b for the conductive film 24a reduces both the contact resistance and the wiring resistance, thereby further reducing the load on the wiring.

[0067] An insulating layer 43 is provided on the conductive layer 24 and the insulating layer 42. The insulating layer 43 has an opening 47 extending in the Y direction. The opening 47 may be shaped like a groove, trench, slit, or the like. The opening 47 reaches the upper surface of the conductive film 24b and the upper surface of the insulating layer 42. The side surface of the opening 47 in the insulating layer 43 (which may also be referred to as the sidewall of the opening 47) is preferably approximately perpendicular to the surface on which it is to be formed (the upper surface of the conductive layer 24 or the insulating layer 42). Furthermore, the depth of the opening 47 is preferably greater than the width between adjacent openings 47 in the insulating layer 43.

[0068] Although the above describes an example in which the insulating layer 43 has the opening 47, the present invention is not limited to this. For example, the insulating layer 43 may be a structure having a strip-shaped upper surface extending in the Y direction. In this case, the insulating layer 43 has a pair of side surfaces perpendicular to the X direction, and a portion of the side surfaces overlaps the conductive layer 24. It is also preferable that the side surfaces of the insulating layer 43 are approximately perpendicular to the surface on which the insulating layer 43 is to be formed. It is also preferable that the height of the insulating layer 43 is greater than the width in the X direction.

[0069] In this specification, "two surfaces are perpendicular" refers to a state in which the interior angle between them is 80 degrees or more and 100 degrees or less. "Two surfaces are approximately perpendicular" refers to a state in which the interior angle between them is 60 degrees or more and 120 degrees or less. "Two surfaces are parallel" refers to a state in which the interior angle between them is -10 degrees or more and 10 degrees or less (including parallel). "Two surfaces are approximately parallel" refers to a state in which the interior angle between them is -30 degrees or more and 30 degrees or less (including parallel).

[0070] Here, it is preferable that the bottom edge of the opening 47 has a curved shape (which can also be called a rounded shape) with an arbitrary curvature as shown in FIG. 7A . By using such a structure, the edges of the recesses of the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 can also be similarly curved. This makes it possible to alleviate electric field concentration at the edges of the recesses of the conductive layer 23. Therefore, it is possible to suppress the occurrence of dielectric breakdown in the transistor 20.

[0071] The semiconductor layer 21 extends in the Y direction. The semiconductor layer 21 has a vertical portion in contact with the sidewall of the opening 47 and a horizontal portion in contact with the top surface of the conductive layer 24. Note that the vertical portion is not necessarily vertical in the strict sense; if the sidewall of the opening 47 is inclined with respect to the Z direction, the vertical portion of the semiconductor layer 21 is also inclined along the sidewall. Similarly, if the top surface of the conductive layer 24 is inclined with respect to the X-Y plane (e.g., the substrate surface), the horizontal portion of the semiconductor layer 21 is also inclined along the top surface.

[0072] More specifically, the vertical portion of the semiconductor layer 21 refers to a portion that is provided along the sidewall of the opening 47 and whose surface (either or both of the surface of the semiconductor layer 21 on the insulating layer 43 side or the surface of the insulating layer 22 side) is perpendicular or approximately perpendicular to the upper surface of the conductive layer 24 or the insulating layer 42. Furthermore, the horizontal portion of the semiconductor layer 21 refers to a portion that is provided along the upper surface of the conductive layer 24 or the insulating layer 42 and whose surface (the surface of the semiconductor layer 21 on the conductive layer 24 side or the surface of the insulating layer 22 side) is parallel or approximately parallel to the upper surface of the conductive layer 24 or the insulating layer 42.

[0073] The semiconductor layer 21 is also provided across the two transistors 20 provided in the opening 47. That is, the semiconductor layer 21 has a pair of vertical portions along the two opposing side walls of the opening 47, and one horizontal portion connected to the vertical portions and in contact with the top surface of the conductive layer 24.

[0074] In the transistor 20, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 20 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (Lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0075] Furthermore, the channel length of the transistor 20 can be precisely controlled by the thickness of the insulating layer 43 (which can also be referred to as the depth of the opening 47) that functions as a spacer. This allows for extremely small variations in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 43, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using extremely expensive exposure equipment used in cutting-edge LSI technology.

[0076] The semiconductor layer 21 has at least a portion thereof that exhibits semiconductivity. As shown in FIGS. 1A, 2A, and 2B, the semiconductor layer 21 has a plurality of regions 21a and a plurality of regions 21b. Here, FIG. 2B shows the structure above the regions 21a and 21b removed from FIG. 2A to make the regions 21a and 21b easier to see. The regions 21a are semiconductive, and the regions 21b are insulating. In the semiconductor layer 21 provided in the opening 47, the plurality of regions 21a and the plurality of regions 21b are alternately arranged in the Y direction. That is, among the plurality of transistors 20 arranged in the opening 47, the transistors 20 including the regions 21a are each isolated by the regions 21b. For this reason, the regions 21b can also be called isolation regions.

[0077] At least a portion of region 21a functions as a channel formation region. As shown in Figure 7A, a portion of the vertical portion of region 21a functions as the channel formation region. The upper end of the vertical portion of region 21a contacts the lower end of conductive layer 25 and functions as either a source region or a drain region. The lower surface of the horizontal portion of region 21a contacts the upper surface of conductive film 24b and functions as the other of the source region or the drain region.

[0078] Region 21b has a higher resistivity than region 21a. For example, the resistivity of region 21b is preferably 10 times or more that of region 21a. Region 21b contains either or both of aluminum and hafnium. Region 21b has a higher concentration of either or both of aluminum and hafnium than region 21a. One or more of aluminum oxide, hafnium oxide, and hafnium aluminate are formed in region 21b. Region 21b has lower crystallinity than region 21a and preferably has an amorphous structure.

[0079] 8A , like region 21a, region 21b also has a vertical portion and a horizontal portion. The upper end of the vertical portion of region 21b contacts the lower end of insulating layer 44. The lower surface of the horizontal portion of region 21b contacts the upper surface of insulating layer 42.

[0080] For example, when element isolation is performed by patterning the semiconductor layer into islands, the etching process may not be sufficient at the bottom of the opening 47, etc. This may result in electrical conduction between adjacent regions 21a. In response to this, the semiconductor layer 21 is formed to cover the opening 47, and regions 21a and 21b are alternately formed, thereby achieving sufficient element isolation. This improves the yield of semiconductor devices.

[0081] The insulating layer 22 is provided to cover the vertical and horizontal portions of the semiconductor layer 21. The conductive layer 23 is located on the insulating layer 22 and is provided to cover the vertical and horizontal portions of the semiconductor layer 21 via the insulating layer 22. An insulating layer 31 is provided on the conductive layer 23. The insulating layer 31 is provided to cover the vertical and horizontal portions of the semiconductor layer 21 via the insulating layer 22 and the conductive layer 23. The insulating layer 22, the conductive layer 23, and the insulating layer 31 are provided to extend in the Y direction within the opening 47.

[0082] It is preferable to use an insulating film having a function of capturing or fixing hydrogen for the insulating layer 31. This allows hydrogen that may diffuse into the semiconductor layer 21 due to heat or the like applied during the manufacturing process of the transistor 20 or the memory cell 15 to be captured or fixed by the insulating layer 31, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to realize a transistor 20 or a semiconductor device 10 with good electrical characteristics and high reliability. As an insulating film that can be used for the insulating layer 31 and that can capture or fix hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like is preferably used.

[0083] Slits are provided in the insulating layer 31, the conductive layer 23, and the insulating layer 22, reaching the semiconductor layer 21, and the insulating layer 31, the conductive layer 23, and the insulating layer 22 are separated by the slits. Inside the slits, insulating layers 32 are provided along and in contact with the side surfaces of the insulating layer 31, the side surfaces of the conductive layer 23, the side surfaces of the insulating layer 22, and the top surface of the semiconductor layer 21. Furthermore, insulating layers 33 are provided on the insulating layer 32 so as to fill the slits. The insulating layers 32 and 33 are provided within the opening 47, extending in the Y direction.

[0084] As with the insulating layer 41, it is preferable to use an insulating film having a barrier property against hydrogen for the insulating layer 32. This can prevent hydrogen contained in the insulating layer 33 and the like from diffusing toward the semiconductor layer 21. It is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like for the insulating layer 32. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

[0085] It is preferable to use an insulating material with a low dielectric constant for the insulating layer 33. This can reduce the parasitic capacitance between the pair of conductive layers 23 sandwiching the insulating layer 33. For the insulating layer 33, an inorganic insulating material such as silicon oxide or silicon oxynitride can be used.

[0086] An insulating layer 34 is provided in contact with the upper surfaces of the conductive layer 23, the insulating layer 31, the insulating layer 32, and the insulating layer 33. The insulating layer 34 can also be provided in contact with the side surface of the insulating layer 22 (the side surface on the insulating layer 33 side). The insulating layer 34 is provided in the opening 47 and extends in the Y direction.

[0087] As the insulating layer 34, it is preferable to use an insulating film having a barrier property against hydrogen, similar to the insulating layer 32 and the insulating layer 41. This makes it possible to prevent hydrogen from diffusing from above the insulating layer 34 toward the semiconductor layer 21. It is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like for the insulating layer 34. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

[0088] Furthermore, it is preferable to use an insulating film having a function of capturing or fixing hydrogen, similar to the insulating layer 31, for the insulating layer 34. This allows hydrogen that may diffuse into the semiconductor layer 21 due to heat or the like applied during the manufacturing process of the transistor 20 or the memory cell 15 to be captured or fixed by the insulating layer 34, thereby reducing the concentration of hydrogen contained in the semiconductor layer 21. This makes it possible to realize a highly reliable transistor 20 or semiconductor device 10 with good electrical characteristics. As an insulating film that can capture or fix hydrogen and that can be used for the insulating layer 34, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like.

[0089] An insulating layer 44 is provided to cover the insulating layer 43, the insulating layer 22, and the insulating layer 34. The insulating layer 44 functions as an interlayer insulating film. The insulating layer 44 can be made of an inorganic insulating material such as silicon oxide or silicon oxynitride.

[0090] Furthermore, a conductive layer 25 is provided on the insulating layer 34, the insulating layer 22, and the semiconductor layer 21. Here, the upper surface of the vertical portion of the semiconductor layer 21 may be located below the upper surface of the insulating layer 22, and a portion of the conductive layer 25 may be provided in the gap surrounded by the insulating layer 43, the insulating layer 22, and the semiconductor layer 21. In this case, the upper surface of the semiconductor layer 21 is preferably located below the upper surface of the conductive layer 23. If the upper surface of the semiconductor layer 21 is located above the upper surface of the conductive layer 23, a so-called offset region may be formed, in which a gate electric field is not applied. Therefore, by processing the upper surface of the semiconductor layer 21 so that it is located below the upper surface of the conductive layer 23, the formation of an offset region in the semiconductor layer 21 can be prevented, and the current that the transistor 20 can pass can be increased. This allows for a semiconductor device 10 with high operating speed.

[0091] 7A and other figures show a case where the side wall of opening 47 and the side surface of insulating layer 44 are flush with each other, but in a plan view, the side surface of insulating layer 44 can be positioned outside the side wall of opening 47. In this case, part of conductive layer 25 has a portion that contacts the upper surface of insulating layer 43.

[0092] 8A , in a region where the conductive layer 25 is not provided, a portion of the insulating layer 44 is provided in a gap surrounded by the insulating layer 43, the insulating layer 22, and the semiconductor layer 21. In the cross section shown in FIG. 7A , the region 21 a of the semiconductor layer 21 contacts the conductive layer 25, and in the cross section shown in FIG. 8B , the region 21 b of the semiconductor layer 21 contacts the insulating layer 44. In this manner, at least a portion of the region 21 a contacts the conductive layer 25, and at least a portion of the region 21 b contacts the insulating layer 44. However, there are cases where another portion of the region 21 a contacts the insulating layer 44. There are also cases where another portion of the region 21 b contacts the conductive layer 25.

[0093] Here, two transistors 20 are provided symmetrically in the Y-direction cross section of opening 47. More specifically, a semiconductor layer 21, a pair of conductive layers 25, a pair of conductive layers 23, a pair of insulating layers 22, a pair of insulating layers 31, etc. are provided symmetrically with respect to the Y-Z plane in opening 47. Providing transistors 20 along each of two opposing sidewalls of opening 47 in this manner is preferable because it increases the integration density of transistors 20.

[0094] An insulating layer 45 is provided to cover the conductive layer 25 and the insulating layer 44. As the insulating layer 45, it is preferable to use an insulating film having barrier properties against hydrogen, similar to the insulating layers 34, 32, and 41. This makes it possible to prevent hydrogen from diffusing from above the insulating layer 45 toward the semiconductor layer 21. It is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, or the like for the insulating layer 45. It is particularly preferable to use a silicon nitride film or a silicon nitride oxide film.

[0095] An insulating layer 46 is provided on the insulating layer 45. The insulating layer 46 functions as an interlayer insulating layer. As with the insulating layer 44, the insulating layer 46 can be made of an inorganic insulating material such as silicon oxide or silicon oxynitride.

[0096] 3A , the insulating layers 45 and 46 have openings that reach the conductive layer 25. The capacitive element 30 is provided in the openings provided in the insulating layers 45 and 46. Here, the openings in the insulating layers 45 and 46 are vertical holes, and unlike the opening 47, preferably do not extend in the X direction or the Y direction.

[0097] The capacitor 30 includes a conductive layer 51 functioning as a lower electrode, a conductive layer 53 functioning as an upper electrode, and an insulating layer 52 disposed therebetween and functioning as a dielectric. The conductive layer 51 has a vertical portion provided along the side surfaces of the openings in the insulating layers 45 and 46 and a horizontal portion contacting the upper surface of the conductive layer 25. In other words, the conductive layer 51 has a cylindrical (also called cup-shaped) shape with a bottom and a recess. The insulating layer 52 has a portion provided along the recess of the conductive layer 51, a portion contacting the upper surface of the conductive layer 51, and a portion contacting the upper surface of the insulating layer 46. The conductive layer 53 is provided so as to fill the recess of the conductive layer 51 via the insulating layer 52. The conductive layer 53 also has a portion provided on the insulating layer 46 via the insulating layer 52. The conductive layer 51 is provided individually for each memory cell, whereas the conductive layer 53 is provided in common to multiple memory cells. Here, the upper part of the conductive layer 53 also serves as the wiring CL.

[0098] 7A, the bottom edges of the openings in the insulating layer 45 and the insulating layer 46 preferably have a curved shape with a given curvature. The curved shape may be formed only in the insulating layer 45, or may be formed across the insulating layer 45 and the insulating layer 46. By using such a structure, the edges of the recesses in the insulating layer 52 and the edges of the protrusions in the conductive layer 53 can also be similarly curved. This makes it possible to alleviate electric field concentration at the edges of the protrusions in the conductive layer 53. This makes it possible to suppress dielectric breakdown in the capacitance element 30.

[0099] 7A, the upper end of the conductive layer 51 can be configured to be lower than the upper surface of the insulating layer 46. The upper end of the conductive layer 51 can also be tapered. Here, the upper end of the conductive layer 51 and the upper end of the insulating layer 46 preferably have a curved shape with a given curvature, as shown in FIG. 7A. By using such a structure, the insulating layer 52 can also be similarly curved. This can alleviate the electric field concentration at the upper end of the conductive layer 51. Therefore, the occurrence of dielectric breakdown in the capacitance element 30 can be suppressed.

[0100] 1A shows an example in which the outline of the conductive layer 51 in a plan view is circular, but this is not limiting. For example, the shape of the outline of the conductive layer 51 in a plan view is not limited to a circle, and can be an ellipse, a rectangle with rounded corners, or the like. It may also be a regular polygon such as an equilateral triangle, a square, or a regular pentagon, or a polygon other than a regular polygon. Furthermore, a concave polygon, such as a star-shaped polygon, in which at least one interior angle exceeds 180 degrees, can increase the capacitance of the capacitive element 30. Other shapes include a polygon with rounded corners and a closed curve that combines straight lines and curves.

[0101] 1A, the horizontal cross-sectional shape of the conductive layer 51 can also be considered to be a circular ring shape. However, the horizontal cross-sectional shape of the conductive layer 51 is not limited to a circular ring shape and may be any ring shape. For example, the horizontal cross-sectional shape of the conductive layer 51 may be a ring shape, an ellipse, a regular polygon, a polygon other than a regular polygon, a concave polygon, a polygon with rounded corners, or the like.

[0102] The capacitance element 30 illustrated in Fig. 3A and other figures is a so-called cylinder-type or trench-type capacitance element. The configuration of the capacitance element 30 is not limited to this, and a pillar-type capacitance element, for example, may also be applied. Fig. 5 shows an example in which a pillar-type capacitance element 30a is applied.

[0103] 5 , a columnar conductive layer 51 is provided on a conductive layer 25, and an insulating layer 52 is provided to cover the top and side surfaces of the conductive layer 51. Furthermore, a conductive layer 53 is provided to cover the top and side surfaces of the conductive layer 51 with the insulating layer 52 interposed therebetween. The contour shape of the conductive layer 51 in a plan view can typically be circular, but can also be any of the various shapes described above.

[0104] Here, it is preferable that the semiconductor device 10 has a layer in which the memory cells 15 are provided stacked on a layer in which the functional circuits are provided. The functional circuits may include, for example, a driver circuit for driving the memory cells 15, an arithmetic circuit, a power supply circuit, etc. The driver circuit may include, for example, one or more of a row decoder, a column decoder, a row driver, a column driver, an input circuit, an output circuit, a sense amplifier, etc. This not only reduces the footprint of the semiconductor chip including the semiconductor device 10, but also shortens the wiring length compared to when the functional circuits and the memory cells 15 are arranged side by side, thereby achieving high-speed operation and low power consumption.

[0105] 6 shows an example in which a transistor 90 constituting a functional circuit is arranged below the insulating layer 11. In this example, one of a source electrode and a drain electrode of the transistor 90 is connected to a conductive layer 24 functioning as a bit line.

[0106] The transistor 90 is a transistor in which a channel is formed in a part of a substrate 91, which is a single-crystal semiconductor substrate. The substrate 91 can typically be made of single-crystal silicon. The substrate 91 can be made of a semiconductor made of a single element such as germanium, or a compound semiconductor made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or gallium nitride. Alternatively, the substrate 91 can be a semiconductor substrate having an insulator region therein, such as an SOI (Silicon On Insulator) substrate.

[0107] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95a and 95b functioning as source and drain regions. The transistor 90 may be either a p-channel type or an n-channel type. An element isolation layer 98 is provided on the substrate 91 between two adjacent transistors 90.

[0108] The transistor 90 has a semiconductor region 92 in which a channel is formed that has a convex shape (fin shape). Although not shown in Fig. 6, a conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 in the X direction via an insulating layer 93. Such a transistor 90 is also called a FIN-type transistor.

[0109] An insulating layer 85 is provided covering the transistor 90, an insulating layer 86 is provided on the insulating layer 85, and an insulating layer 87 is provided on the insulating layer 86. A conductive layer 81 is provided so as to be embedded in the insulating layer 87. An insulating layer 11 is provided covering the conductive layer 81 and the insulating layer 87. A plug 82 is provided inside an opening provided in the insulating layer 85 and the insulating layer 86, and the plug 82 connects the conductive layer 81 to the low-resistance region 95b. A plug 83 is provided inside an opening provided in the insulating layer 41 and the insulating layer 11, and the plug 83 connects the conductive layer 24 (specifically, the conductive film 24a) and the conductive layer 81.

[0110] Note that although an example of providing a conductive layer 81 as a wiring layer has been shown here, a structure in which interlayer insulating layers and wiring layers are alternately stacked (also called a multilayer wiring layer) can be used between the layer in which the transistor 90 is provided and the layer in which the memory cell 15 is provided.

[0111] The above is a description of an example of the configuration of the semiconductor device.

[0112] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0113] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0114] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0115] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0116] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0117] The semiconductor layer 21 can be made of, for example, In oxide, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, or the like. Ga—Zn oxide may also be used. A material that does not contain Zn, such as indium oxide, is preferred because it enhances compatibility with the LSI manufacturing process. On the other hand, a material that contains Zn is preferred because it facilitates high crystallinity.

[0118] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0119] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0120] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0121] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0122] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0123] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0124] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0125] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0126] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0127] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0128] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0129] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is contained, or the content of that element, also affects the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn=4:3:2 [atomic ratio] and materials in the vicinity thereof, In:Zn=1:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=2:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=4:1 [atomic ratio] and materials in the vicinity thereof, and In:Sn:Zn=40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X=1) and materials in the vicinity thereof. On the other hand, examples of materials having lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn=1:3:2 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:3:4 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=2:2:1 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:1:1 [atomic ratio] and materials in the vicinity thereof, and In:Ga:Zn=1:1:2 [atomic ratio] and materials in the vicinity thereof.

[0130] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0131] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0132] Region 21a of semiconductor layer 21 preferably has the above-described configuration. Meanwhile, region 21b of semiconductor layer 21 is a metal oxide obtained by adding a metal element (either aluminum or hafnium, or both) to the above-described metal oxide. By adding either aluminum or hafnium, or both, to a metal oxide such as In—Ga—Zn oxide to improve insulation, region 21b can function as an element isolation region. The resistivity of region 21b is preferably 10 times or more the resistivity of region 21a.

[0133] The region 21b has a higher concentration of either aluminum or hafnium or both than the region 21a. The compositions of the metal oxides in the region 21b and the region 21a are analyzed by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), Auger electron spectroscopy (AES), and inductively coupled plasma mass spectrometry (ICP-MS). For example, an inductively coupled plasma atomic emission spectrometry (ICP-AES) or an inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these techniques may be used for the analysis.

[0134] Either or both of the aluminum and hafnium added to region 21b may combine with oxygen and exist in region 21b as aluminum oxide, hafnium oxide, or hafnium aluminate. While aluminum and hafnium have been described above as elements to be added to region 21b, the present invention is not limited to this. The element to be added to region 21b may be any element that at least increases the resistivity of region 21b. For example, silicon or gallium may be added to region 21b. In this case, the concentration of silicon or gallium in region 21b will be higher than that in region 21a.

[0135] The crystallinity of region 21b may decrease due to the addition of the metal element. In this case, the crystallinity of region 21b becomes lower than that of region 21a. For example, region 21a may have a CAAC structure, while region 21b may have an amorphous structure. The crystallinity of the metal oxides in region 21b and region 21a can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED).

[0136] Region 21b has low crystallinity and contains more oxygen vacancies than region 21a, and therefore has the function of capturing or fixing (this can also be called gettering) the hydrogen and excess oxygen contained in region 21a. For example, by performing a heat treatment, the hydrogen and excess oxygen contained in region 21a can be captured or fixed in region 21b. In this case, when measuring the oxygen or hydrogen profile by SIMS, the oxygen or hydrogen concentration is higher in region 21b than in region 21a. Note that in this specification, excess oxygen refers to oxygen in an amount greater than the amount that satisfies the stoichiometric composition.

[0137] By gettering hydrogen contained in the region 21a in the region 21b, the hydrogen concentration in the region 21a, which functions as a channel formation region, can be reduced, thereby suppressing a negative shift in the initial characteristics of the transistor 20 and achieving normally-off characteristics. In addition, negative drift degradation during a +GBT stress test can be suppressed.

[0138] Furthermore, gettering the excess oxygen contained in the region 21a in the region 21b reduces the excess oxygen in the region 21a, which functions as a channel formation region, and suppresses the formation of electron traps due to the excess oxygen. This suppresses excessive positive shifts in the initial characteristics of the transistor 20 due to the electron traps. Furthermore, excessive positive drift degradation in a +GBT stress test can be suppressed. As described above, gettering the hydrogen and excess oxygen contained in the region 21a to the region 21b improves the electrical characteristics and reliability of the transistor 20.

[0139] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0140] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0141] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0142] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0143] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0144] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0145] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0146] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0147] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0148] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0149] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0150] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials, and preferably by using a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0151] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ｘ (X is a real number greater than 0) may also be used as a metal oxide with Y (yttrium) added. Ｘ(X is a real number greater than 0) and adding Y (yttrium) to the compound can enhance the ferroelectricity.

[0152] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0153] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0154] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0155] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material with a lower dielectric constant than the other films for the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen for the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen for the film located between them. Silicon oxide or silicon oxynitride can be used as the material with a low dielectric constant. With this configuration, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0156] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0157] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, an insulating film made of a material with a lower dielectric constant than the other films for the film next closest to the semiconductor layer 21, an insulating film having the function of capturing or fixing hydrogen for the film next closest to the semiconductor layer 21, and an insulating film having a barrier property against hydrogen and oxygen for the film closest to the conductive layer 23. That is, in addition to the above-described three-layer structure, a configuration can be adopted in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, oxygen desorption from the semiconductor layer 21 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 21.

[0158] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0159] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0160] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0161] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0162] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0163] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0164] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0165] For example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used for the conductive film 24b and conductive layer 25 in contact with the semiconductor layer 21. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferred.

[0166] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0167] For example, the conductive layer 24 and the conductive layer 25 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0168] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0169] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 .

[0170] Since the conductive layer 23, the conductive film 24a, and the conductive layer 25 also function as wiring, it is preferable to use a laminate of low-resistance conductive materials. For example, the low-resistance conductive material that can be used for the conductive layer 23 described above can also be used for the upper layer of the conductive film 24a and the conductive layer 25.

[0171] <Insulating Layer> The insulating layer 43 can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, by forming the insulating layer 43 by a sputtering method without using hydrogen gas as a film formation gas, a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 20 can be stabilized.

[0172] The insulating layer 43 is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The insulating layer 43 can be an oxide insulating film that can be used for the gate insulating layer.

[0173] Furthermore, since the insulating layer 43 functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 43 can be formed by a plasma CVD method. When forming the insulating layer 43 by the plasma CVD method, TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ ) is preferably used, which can improve productivity.

[0174] The insulating layer 11, the insulating layer 42, the insulating layer 44, and the insulating layer 46 each function as an interlayer insulating layer. The insulating layer 11, the insulating layer 42, the insulating layer 44, and the insulating layer 46 can be made of the same insulating material as can be used for the insulating layer 43.

[0175] The insulating layer 52 functions as a dielectric for the capacitance element 30. The insulating layer 52 can be made of the same insulating material as the insulating layer 22. Furthermore, by using the above-mentioned ferroelectric material for the insulating layer 52, the capacitance element 30 can be made into a ferroelectric capacitor, thereby realizing a nonvolatile memory device. Note that the capacitance element 30 can also be a resistance change type memory element that utilizes the electric field induced giant resistance change (CER: Colossal Electro-Resistance) effect.

[0176] This concludes the description of the components.

[0177] [Modification] The following describes an example in which the configuration is partially different from the above-described configuration example. Note that the same reference numerals are used to designate the same parts as those described above, and descriptions thereof will be omitted.

[0178] [Modification 1] The configuration shown in FIG. 8B differs from the above-described configuration examples mainly in that the shape of the conductive layer 24 is different.

[0179] A recess is formed in the conductive film 24b of the conductive layer 24. More specifically, the thickness of the conductive film 24b is processed so that the thickness of the non-overlapping region is thinner than the thickness of the region of the conductive film 24b that overlaps with the insulating layer 43. Furthermore, the semiconductor layer 21 contacts not only the top surface of the recess of the conductive film 24b but also the side surface. With this configuration, the contact area between the semiconductor layer 21 and the conductive film 24b can be increased, thereby further reducing the contact resistance between them.

[0180] Here, the end of the recess in the conductive film 24b preferably has a curved shape (which can also be called a rounded shape) with an arbitrary curvature, as shown in FIG. 8B . By using such a structure, the end of the recess in the insulating layer 22 and the conductive layer 23 can also be similarly curved. This makes it possible to alleviate electric field concentration at the end of the recess in the conductive layer 23. Therefore, it is possible to suppress the occurrence of dielectric breakdown in the transistor 20.

[0181] 7B, the conductive layer 25 can have a laminated structure of a conductive film 25a and a conductive film 25b on the conductive film 25a. In this case, a recess can be formed in the conductive film 25b, similar to the conductive film 24b shown in FIG. 8B. Here, the conductive layer 51 contacts not only the top surface of the recess in the conductive film 25b but also the side surface. This configuration increases the contact area between the conductive layer 51 and the conductive film 25b, thereby further reducing the contact resistance between them.

[0182] 7B , by forming the end of the recess of the conductive film 25b into a curved shape with an arbitrary curvature, the end of the recess of the insulating layer 52 and the end of the protrusion of the conductive layer 53 can also be formed into a similarly curved shape. This makes it possible to alleviate electric field concentration at the end of the protrusion of the conductive layer 53. Therefore, it is possible to suppress the occurrence of dielectric breakdown in the capacitance element 30.

[0183] [Modification 2] The configuration shown in FIG. 9A differs from the above-described configuration example mainly in that the insulating layer 31 is not provided.

[0184] 9A , the insulating layer 32 is provided in contact with the surface of the conductive layer 23 on the insulating layer 33 side. A part of the insulating layer 32 covers the horizontal portion of the semiconductor layer 21 via the conductive layer 23 and the insulating layer 22. The insulating layer 33 also covers the horizontal portion of the semiconductor layer 21 via the insulating layer 32, the conductive layer 23, and the insulating layer 22. Not providing the insulating layer 31 is preferable because the step of forming the insulating layer 31 can be omitted and the manufacturing process can be simplified.

[0185] FIG. 9B shows an example in which the conductive film 24b having the recesses illustrated in the first modification is applied to this configuration.

[0186] 9A and 9B, an insulating film having a function of capturing or fixing hydrogen is preferably used for insulating layer 32 or insulating layer 33 instead of insulating layer 31. As an insulating film that can be used for insulating layer 32 or insulating layer 33 and that can capture or fix hydrogen, a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like is preferably used.

[0187] [Modification 3] The configuration shown in FIG. 9C differs from Modification 2 above mainly in that it does not have the insulating layer 33 and that the shape of the insulating layer 32 is different.

[0188] The insulating layer 32 is provided to fill a region surrounded by the conductive layer 23, the insulating layer 22, the semiconductor layer 21, and the insulating layer 34. With this structure, the steps of forming the insulating layers 31 and 33 can be omitted, thereby simplifying the manufacturing process.

[0189] FIG. 9D shows an example in which the conductive film 24b having the recesses illustrated in the first modification is applied to this configuration.

[0190] 9C and 9D, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as insulating layer 32 instead of insulating layer 31. As an insulating film that can be used for insulating layer 32 and that can capture or fix hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, or the like.

[0191] [Modification 4] The configuration shown in FIG. 10A differs from the above-described configuration examples mainly in that an insulating layer 22 is provided between the insulating layer 32 and the semiconductor layer 21 .

[0192] With this configuration, the upper surface of the semiconductor layer 21 is not exposed during the process of forming the insulating layer 32, and is covered by the insulating layer 22, thereby suppressing damage to the semiconductor layer 21 and improving reliability.

[0193] 10B shows an example in which the conductive film 24b having the recesses illustrated in the above-described Modification 1 is applied to this configuration. Also, Figures 10C and 10D show an example in which the insulating layer 31 is not provided, as in the above-described Modification 2. Although not shown here, a configuration in which the insulating layer 31 and the insulating layer 33 are not provided may also be used, as in the above-described Modification 3.

[0194] [Modification 5] The configuration shown in FIG. 11A differs from the above-described configuration examples mainly in that a region 21b is disposed between a pair of regions 21a in a cross section of the semiconductor layer 21 in the Y direction.

[0195] A pair of regions 21a separated by region 21b is formed between two transistors 20 provided in opening 47. In addition, insulating layer 32 is provided in contact with the upper surface of region 21b. In this case, it is preferable that the boundary between region 21a and region 21b is approximately flush with the side surfaces of insulating layer 22, conductive layer 23, and insulating layer 31. In other words, it is preferable that region 21b is provided so as to overlap with the region between the pair of insulating layers 22, the region between the pair of conductive layers 23, and the region between the pair of insulating layers 31.

[0196] 11B shows an example in which the conductive film 24b having the recesses illustrated in the above-described Modification 1 is applied to this configuration. Also, Figures 11C and 11D show an example in which the insulating layer 31 is not provided, as in the above-described Modification 2. Although not shown here, a configuration in which the insulating layer 31 and the insulating layer 33 are not provided may also be used, as in the above-described Modification 3.

[0197] The above is a description of the modified example.

[0198] [Manufacturing Method Example] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking the semiconductor device 10 including the memory cell 15 exemplified in the above structure example as an example.

[0199] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. CVD methods include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0200] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0201] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming films using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0202] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. They can also be further classified into metal CVD (MCVD) and MOCVD, depending on the source gas used.

[0203] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0204] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0205] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0206] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0207] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0208] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0209] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0210] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0211] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0212] 12A to 21 are schematic cross-sectional views corresponding to each step in the exemplary fabrication method described below. Figures 12A to 12C, 13A, 14A, 15A, 16A, and 17A to 21 correspond to cross sections taken along the line O-P-Q in Figure 1A. Figures 13B, 14B, 15B, and 16B correspond to cross sections taken along the line R-S in Figure 1A.

[0213] First, a substrate (not shown) is prepared, an insulating layer 11 is formed on the substrate, and an insulating layer 41 is formed on the insulating layer 11 .

[0214] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0215] The insulating layer 11 may be an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film. The insulating layer 41 may be an inorganic insulating film such as a silicon nitride film or a silicon nitride oxide film. The insulating layer 11 and the insulating layer 41 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0216] Next, a conductive film that will become conductive film 24a and a conductive film that will become conductive film 24b are formed in this order on insulating layer 41. Each conductive film can be formed by a film formation method such as sputtering, ALD, or CVD. Next, a resist mask is formed on the conductive film that will become conductive film 24b, and unnecessary portions of each conductive film are removed by etching, thereby forming conductive layer 24 including conductive film 24a and conductive film 24b. Here, conductive layer 24 is formed to extend in the X direction.

[0217] Next, an insulating film that will become the insulating layer 42 is formed to cover the conductive layer 24, and then planarization is performed until the upper surface of the conductive film 24b is exposed, thereby forming the insulating layer 42 (FIG. 12A). The insulating film that will become the insulating layer 42 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0218] Although the example shown here is one in which the insulating layer 42 is formed after the conductive layer 24 is formed, the conductive layer 24 may be formed after the insulating layer 42 is formed. In this case, an insulating film that will become the insulating layer 42 is formed, and then an opening (or a recess) for burying the conductive layer 24 is formed, thereby forming the insulating layer 42. Thereafter, two conductive films that will become the conductive films 24a and 24b, respectively, are formed in this order, and then a planarization process is performed until the top surface of the insulating layer 42 is exposed, thereby forming the conductive layer 24.

[0219] Next, an insulating layer 43 is formed on the conductive layer 24 and the insulating layer 42 ( FIG. 12B ). First, an insulating film that will become the insulating layer 43 is formed. Next, the insulating film is etched by photolithography to form an opening 47 extending in the Y direction. The opening 47 is formed so as to reach the conductive film 25b and the insulating layer 42. In this manner, the insulating layer 43 having the opening 47 can be formed. After the insulating layer 43 is formed, the upper surfaces of the conductive film 24b and the insulating layer 42 are exposed in the opening 47. Here, it is preferable that the edge of the bottom surface of the opening 47 has a curved shape with an arbitrary curvature, as shown in FIG. 7A , etc.

[0220] It should be noted that there is a risk that the insulating layer 42 may be etched and thinned during processing of the insulating layer 43. In such a case, an insulating layer that functions as an etching stop film may be provided under the insulating film that will become the insulating layer 43, and after the insulating layer 43 is formed by etching, the etching stop film may be subsequently etched, thereby exposing the top surfaces of the insulating layer 42 and the like.

[0221] Here, since the thickness of the insulating layer 43 affects the channel length of the transistor, it is important to prevent the insulating layer 43 from varying in thickness.

[0222] When processing the insulating layer 43, it is preferable to process it by anisotropic dry etching so that the side surfaces are approximately vertical. Depending on the processing conditions, the side surfaces of the insulating layer 43 may be inclined with respect to the direction perpendicular to the surface on which they are formed, resulting in a tapered shape.

[0223] Furthermore, when processing the insulating layer 43, a portion of the upper part of the conductive film 24b can be etched to reduce the thickness of the region that does not overlap with the insulating layer 43. This allows the conductive film 24b having a recess as shown in FIG. 8B and other figures to be formed. In this case, it is preferable to determine the etching conditions so that the conductive film 24b does not disappear, or to form the conductive film 24b thick in advance. Here, it is preferable that the end of the recess in the conductive film 24b has a curved shape with a given curvature as shown in FIG. 8B.

[0224] The insulating film to be the insulating layer 43 is preferably an oxide film that contains a large amount of oxygen to such an extent that oxygen is released by heating and that contains a small amount of hydrogen. The insulating film to be the insulating layer 43 can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is particularly preferably formed by a sputtering method. In particular, by forming the insulating film using a gas containing oxygen and not a gas containing hydrogen as a film formation gas, an insulating film with an extremely small amount of hydrogen and an excess amount of oxygen can be formed. By forming the insulating film to be the insulating layer 43 in this manner, oxygen can be supplied from the insulating layer 43 to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0225] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen after the heat treatment in the nitrogen gas or inert gas atmosphere. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 43 or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0226] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 43 and the like as much as possible.

[0227] A process for supplying oxygen may be performed after the insulating film that becomes the insulating layer 43 is formed or after processing into the insulating layer 43. This allows oxygen to be supplied from the insulating layer 43 to the semiconductor film 21f by heat or the like applied after the semiconductor film 21f is formed.

[0228] Examples of treatments for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Here, microwave plasma treatment may refer to treatment using, for example, an apparatus having a power source for generating high-density plasma using microwaves. Alternatively, oxygen may be supplied to the insulating layer by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0229] Subsequently, a semiconductor film 21f, which will later become the semiconductor layer 21, is formed to cover the insulating layer 43, the conductive film 24b, and the insulating layer 42 (FIG. 12C).

[0230] The semiconductor film 21f may be a metal oxide (oxide semiconductor) film having semiconductor properties. The metal oxide film may be formed by a suitable method such as sputtering, CVD, MBE, PLD, or ALD. The metal oxide film is preferably formed in contact with the substantially vertical side surface of the insulating layer 43. Therefore, the metal oxide film is preferably formed by a method with good coverage, and more preferably by ALD.

[0231] The metal oxide film preferably has crystallinity. In particular, the metal oxide film of one embodiment of the present invention preferably contains a metal oxide having a CAAC structure.

[0232] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0233] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0234] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering may be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0235] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0236] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0237] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (substrate temperature) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0238] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0239] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0240] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0241] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0242] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0243] The deposition conditions for the metal oxide film are such that the substrate temperature is from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferred because productivity is increased. Furthermore, by depositing the metal oxide film at room temperature or without intentionally heating the substrate, the crystallinity can be reduced.

[0244] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0245] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0246] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0247] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0248] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0249] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0250] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0251] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0252] After the metal oxide film is formed, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, such as 250° C. to 650° C., preferably 400° C. to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0253] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for the heat treatment, it is possible to prevent moisture and the like from being incorporated into the metal oxide film as much as possible.

[0254] Although the semiconductor film 21f is shown as a single layer in the drawings, it may have a laminated structure. For example, it may have a two-layer structure formed by the ALD method, a three-layer structure formed by the ALD method, a two-layer structure in which the first layer is formed by the ALD method and the second layer is formed by the sputtering method, or a three-layer structure in which the first layer is formed by the ALD method, the second layer is formed by the sputtering method, and the third layer is formed by the ALD method or the sputtering method. Forming the first layer by the ALD method is preferable because it can suppress mixing, but it can also be formed by the sputtering method. Note that the semiconductor film 21f may have a laminated structure of four or more layers.

[0255] Next, a sacrificial layer 61 and a resist mask 65 are formed (FIGS. 13A and 13B). The resist mask 65 and the sacrificial layer 61 function as masks for forming the above-described region 21b in the semiconductor film 21f. Therefore, the openings in the resist mask 65 are formed so as to overlap the region 21b of the semiconductor layer 21, which will be formed in a later step. Therefore, as shown in FIGS. 13A and 13B, the conductive layer 24, in other words, the portion where the region 21a will be formed in a later step, is covered with the resist mask 65.

[0256] The sacrificial layer 61 can be made of an organic or inorganic material formed by a coating method. More specifically, a coating-type insulating film such as an SOC (Spin On Carbon) film or an SOG (Spin On Glass) film can be used. Alternatively, the sacrificial layer 61 can be formed by a film formation method such as a sputtering method or a CVD method. It is preferable that the material used for the sacrificial layer 61 satisfy the following conditions: it can be formed thick, it can be formed or processed vertically, and it can be easily removed (no residue is left behind, and damage to the surface on which it is formed is minimal). The sacrificial layer 61 need not be provided if it is not necessary.

[0257] Next, the portion of the sacrificial layer 61 that is not covered by the resist mask 65 is removed by etching to form an opening (FIGS. 14A and 14B). That is, the opening of the sacrificial layer 61 is formed so as to overlap with the region 21b of the semiconductor layer 21 that will be formed in a later step.

[0258] Next, it is preferable to remove the resist mask 65. The resist mask 65 can be removed by wet etching or dry etching. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0259] Next, a sacrificial layer 67 is formed to cover the semiconductor film 21f and the sacrificial layer 61 (FIGS. 15A and 15B). The sacrificial layer 67 functions as a layer for adding a metal element to the semiconductor film 21f in a later process. As described above, the metal element is preferably either aluminum or hafnium, or both. Therefore, the sacrificial layer 67 is preferably an oxide film containing either aluminum or hafnium, or both. For example, aluminum oxide, hafnium oxide, or hafnium aluminate can be used as the sacrificial layer 67. Here, to prevent excessive oxygen from being added to the semiconductor film 21f in a later process, the amount of oxygen contained in the sacrificial layer 67 is preferably less than the amount that satisfies the stoichiometric composition.

[0260] 15A and 15B, the sacrificial layer 67 is formed so as to contact the semiconductor film 21f located at the bottom of the opening in the sacrificial layer 61. For this reason, it is preferable to use a film formation method with good coverage for forming the sacrificial layer 67. It is also preferable that the sacrificial layer 67 has a thin film thickness. For example, it is preferable that the film thickness is thinner than that of the semiconductor film 21f, and specifically, the film thickness can be set to 0.5 nm or more and 1.0 nm or less. Therefore, it is preferable to form the sacrificial layer 67 using the ALD method, which has good coverage and can form an ultra-thin film with a precise thickness.

[0261] Subsequently, plasma treatment is performed to add the metal elements contained in the sacrificial layer 67 to the semiconductor film 21f, forming regions 21fa and 21fb (FIGS. 16A and 16B). By performing plasma treatment on the thin sacrificial layer 67, the metal elements contained in the sacrificial layer 67 are impacted, allowing the metal elements to be added to the semiconductor film 21f in the region where the sacrificial layer 67 and the semiconductor film 21f contact each other. The region of the semiconductor film 21f in contact with the sacrificial layer 67 is doped with the metal elements, forming region 21fb, while the region of the semiconductor film 21f covered by the sacrificial layer 61 is not doped with the metal elements, forming region 21fa. Thus, region 21fb contains either or both of aluminum and hafnium. Furthermore, region 21fb has a higher concentration of either or both of aluminum and hafnium than region 21fa. Here, one or more of aluminum oxide, hafnium oxide, and hafnium aluminate are formed in region 21fb.

[0262] Furthermore, by adding the metal element as described above, oxygen vacancies are formed in region 21fb, resulting in a decrease in crystallinity. In this way, region 21fb has an amorphous structure. Therefore, region 21fb has a larger amount of oxygen vacancies and lower crystallinity than region 21fa. Such region 21fb has a higher resistivity than region 21fa. Preferably, the resistivity of region 21fb is 10 times or more the resistivity of region 21fa. In this manner, region 21fb, which functions as an element isolation region, can be formed.

[0263] As the plasma treatment, for example, reverse sputtering is preferably performed. Here, reverse sputtering refers to a method of modifying a surface by bombarding ions onto a surface to be treated, in contrast to the normal sputtering method of bombarding a sputter target with ions. One method of bombarding ions onto the surface to be treated is to apply a high frequency voltage to the surface to be treated in an argon atmosphere to generate plasma near the substrate. When reverse sputtering is used, argon is added to region 21fb in addition to the metal elements. In this case, the argon concentration in region 21b becomes higher than the argon concentration in region 21a. In addition to argon gas, other gases such as helium gas, nitrous oxide (N ２ O) gas, nitrogen gas, oxygen gas, or the like can also be used.

[0264] The plasma treatment is not limited to reverse sputtering. For example, the microwave plasma treatment described above may be performed. Furthermore, the plasma treatment may be performed without applying a bias voltage to the surface to be treated. For the above treatment, a sputtering device, a CVD device, a dry etching device, a CVD device using a high-density plasma source, or a dry etching device using a high-density plasma source may be used.

[0265] Alternatively, heat treatment may be performed instead of the plasma treatment, during the plasma treatment, before the plasma treatment, or after the plasma treatment. The conditions for the heat treatment may refer to the heat treatment for gettering described later.

[0266] The method of adding the metal element to the semiconductor film 21f is not limited to the above. For example, the metal element may be added by ion implantation or ion doping without providing the sacrificial layer 67.

[0267] Next, a heat treatment is performed to capture or fix (this can also be called gettering) the hydrogen and excess oxygen contained in region 21fa to region 21fb. As described above, region 21fb contains more oxygen vacancies than region 21fa. Therefore, by performing the heat treatment, the hydrogen and excess oxygen contained in the adjacent region 21fa can be captured or fixed.

[0268] This reduces the hydrogen concentration in the region 21fa that functions as a channel formation region in the transistor 20, thereby suppressing a negative shift in the initial characteristics of the transistor 20 and enabling the transistor 20 to have normally-off characteristics. Furthermore, negative drift degradation in a +GBT stress test can be suppressed.

[0269] Furthermore, in the transistor 20, excess oxygen in the region 21fa, which functions as a channel formation region, can be reduced, thereby suppressing the formation of electron traps due to the excess oxygen. This can suppress an excessive positive shift in the initial characteristics of the transistor 20 due to the electron traps. Furthermore, excessive positive drift degradation in a +GBT stress test can be suppressed. As described above, by capturing or fixing the hydrogen and excess oxygen contained in the region 21fa in the region 21fb, the electrical characteristics and reliability of the transistor 20 can be improved.

[0270] The heat treatment is preferably performed at a substrate temperature of 200° C. to 500° C., preferably 400° C. to 450° C. The heat treatment is preferably performed for a treatment time of 1 hour to 8 hours. The heat treatment is preferably performed in an atmosphere that does not contain oxygen gas or has a low oxygen gas content. For example, the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. The gas used in the heat treatment is preferably highly purified. For example, the moisture content of the gas used in the heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.

[0271] Next, the sacrificial layers 67 and 61 are removed ( FIG. 17A ). The sacrificial layers 67 and 61 can be removed by wet etching or dry etching. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed. The sacrificial layer 67 may remain near the region 21fb. The plasma treatment and heat treatment may result in an unclear interface between the sacrificial layer 67 and the semiconductor film 21f. In this case, the sacrificial layer 67 may remain near the region 21fb.

[0272] Next, a new sacrificial layer 62 is formed (FIG. 17B). The sacrificial layer 62 can be formed by the same method as the sacrificial layer 61.

[0273] Next, a planarization process is performed until the top surface of the insulating layer 43 is exposed ( FIG. 17C ). As a result, the portion of the semiconductor film 21f located above the insulating layer 43 is removed, and the portion located within the opening 47 remains. In this manner, the semiconductor layer 21 arranged along the inside of the opening 47 can be formed. Furthermore, the remaining portion of the region 21fa becomes the region 21a, and the remaining portion of the region 21fb becomes the region 21b. As shown in FIG. 17C , the regions 21a and 21b are arranged alternately within the opening 47.

[0274] The planarization process can be performed by, for example, a chemical mechanical polishing (CMP) method, dry etching, etc. After the semiconductor layer 21 is formed, the sacrificial layer 62 is removed. The sacrificial layer 62 can be removed by the same method as the sacrificial layer 61 described above.

[0275] Subsequently, an insulating film 22f, which will later become the insulating layer 22, is formed to cover the semiconductor layer 21, the insulating layer 43, the insulating layer 42, the conductive layer 24, and the like.

[0276] The insulating film 22f can be formed by a film formation method such as sputtering, ALD, or CVD. It is preferable that the insulating film 22f be provided on the surface of the vertical portion of the semiconductor layer 21 with as uniform a thickness as possible. Therefore, it is particularly preferable to form the insulating film 22f by the ALD method, which is a film formation method with extremely excellent coverage. Note that when the sidewalls of the insulating layer 43 have a tapered shape, the insulating film 22f can be formed by a film formation method such as sputtering or CVD.

[0277] Subsequently, a conductive film 23f is formed to cover the insulating film 22f, and the conductive film 23f will later become the conductive layer 23. The conductive film 23f can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, the CVD method is particularly preferable.

[0278] Subsequently, an insulating film 31f is formed to cover the conductive film 23f (FIG. 18A), which will later become the insulating layer 31. The insulating film 31f can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0279] Next, insulating film 31f is anisotropically etched to form a pair of insulating layers 31 that are disposed along the vertical portions of conductive film 23f and are symmetrically arranged with respect to the Y-Z plane within opening 47. Next, conductive film 23f is anisotropically etched using insulating layer 31 as a mask to form a pair of conductive layers 23 that are symmetrically arranged with respect to the Y-Z plane within opening 47. Next, insulating film 22f is anisotropically etched to form a pair of insulating layers 22 that are symmetrically arranged with respect to the Y-Z plane within opening 47, with insulating layer 43 sandwiched between them ( FIG. 18B ). In this manner, a pair of insulating layers 31, a pair of conductive layers 23, and a pair of insulating layers 22 that are disposed along the interior of opening 47 can be formed.

[0280] The insulating film 31f, the conductive film 23f, and the insulating film 22f may be etched in order using different etching methods, or two or more films may be etched simultaneously in one etching step. For example, in the etching step of the conductive film 23f, the insulating film 22f may be etched successively under the same conditions after the conductive film 23f.

[0281] 11A and other figures, a region 21b can be formed in a region overlapping with a region between a pair of conductive layers 23. In this case, after the step shown in FIG. 18B, a method similar to the method shown in FIGS. 13 to 16 may be used.

[0282] Next, an insulating film that will become insulating layer 32 is formed. Next, an insulating film that will become insulating layer 33 is formed so as to fill the recesses in the insulating film. These insulating films can be formed independently by a film formation method such as a sputtering method, an ALD method, or a CVD method. For example, the insulating film that will become insulating layer 32 can be formed by an ALD method, and the insulating film that will become insulating layer 33 can be formed by a CVD method. Next, the insulating film that will become insulating layer 33 and the insulating film that will become insulating layer 32 are anisotropically etched in order to expose the upper surfaces of semiconductor layer 21, insulating layer 22, conductive layer 23, and insulating layer 31.

[0283] Next, an insulating film that will become the insulating layer 34 is formed, and planarization is performed until the top surface of the insulating layer 43 is exposed, thereby forming the insulating layer 34 that contacts the top surfaces of the conductive layer 23, the insulating layer 31, the insulating layer 32, and the insulating layer 33 ( FIG. 18C ). The insulating film that will become the insulating layer 34 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0284] Next, semiconductor layer 21 is etched so that the upper surface of semiconductor layer 21 is lower than the upper surface of conductive layer 23 ( FIG. 19A ). At this time, a recess is formed that is surrounded by the side surfaces of insulating layer 43, insulating layer 22, and the upper surface of semiconductor layer 21. Next, a conductive film is formed so as to fill the recess, and unnecessary portions of the conductive film are etched and removed by photolithography, thereby forming conductive layer 25 ( FIG. 19B ).

[0285] 7B, a laminated structure of conductive films 25a and 25b may be used. In this case, a laminated conductive film similar to the above-described conductive films 24b and 24a may be formed, and the laminated conductive film may be processed to form the conductive layer 25.

[0286] At this point, transistor 20 can be formed.

[0287] Thereafter, an insulating film that will become insulating layer 44 is formed and planarized until the top surface of conductive layer 25 is exposed, thereby forming insulating layer 44 ( FIG. 19C ). The insulating film that will become insulating layer 44 can be formed by a film formation method such as sputtering, ALD, or CVD. In addition, in the region where conductive layer 25 is not provided, as shown in FIG. 3B , part of insulating layer 44 is embedded in a recess surrounded by the side surfaces of insulating layer 43, insulating layer 22, and the top surface of semiconductor layer 21 (e.g., region 21 b).

[0288] Subsequently, the insulating layer 45 is formed, and the insulating layer 46 is formed on the insulating layer 45. The insulating layer 45 and the insulating layer 46 can be formed independently by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0289] Next, openings are formed in the insulating layer 46 and the insulating layer 45, reaching the conductive layer 25 ( FIG. 20A ). Here, the bottom edge of the opening preferably has a curved shape with a given curvature, as shown in FIG. 7A . Note that a portion of the top surface of the conductive layer 25 may be etched. To prevent this, the insulating layer 45 can be used as an etching stop film when etching the insulating layer 46.

[0290] Furthermore, when the conductive layer 25 has a laminated structure of conductive films 25a and 25b, a portion of the upper part of the conductive film 25b can be etched to reduce the thickness of the central part of the conductive film 25b. This allows the conductive film 25b having a recess, as shown in FIG. 7B and other figures. In this case, it is preferable to determine the etching conditions so that the conductive film 25b does not disappear, or to form the conductive film 25b thick in advance. Here, it is preferable that the edge of the recess in the conductive film 25b has a curved shape with a given curvature, as shown in FIG. 7B.

[0291] Subsequently, a conductive film that will become the conductive layer 51 is formed to cover the upper surface of the insulating layer 46, the side surfaces of the insulating layer 46 in the opening, the side surfaces of the insulating layer 45, and the upper surface of the conductive layer 25. The conductive film can be formed by a method such as CVD, ALD, or sputtering. From the viewpoint of coverage, it is particularly preferable to form the conductive film by CVD.

[0292] Next, a sacrificial layer is formed on the conductive film so as to cover the recess of the opening, and a planarization process is performed until the upper surface of the insulating layer 46 is exposed. The sacrificial layer is then removed, thereby forming a conductive layer 51 that is located only inside the opening (Figure 20B).

[0293] Here, the conductive film can also be etched to form the conductive layer 51. In this case, as shown in FIG. 7A , the upper end of the conductive layer 51 can be configured to be lower than the upper surface of the insulating layer 46. The upper end of the conductive layer 51 can also be tapered. Here, the upper end of the conductive layer 51 and the upper end of the insulating layer 46 preferably have a curved shape with a given curvature as shown in FIG. 7A .

[0294] Next, an insulating layer 52 is formed along the surfaces of the insulating layer 46 and the conductive layer 51. The insulating layer 52 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method, but the ALD method is preferable from the viewpoint of coverage. Next, a conductive layer 53 is formed on the insulating layer 52 so as to fill the recesses in the openings of the insulating layer 46 ( FIG. 21 ). Thereafter, the upper surface of the conductive layer 53 may be planarized as necessary.

[0295] Through the above steps, a semiconductor device including the transistor 20 and the capacitor 30 can be manufactured.

[0296] The above is a description of an example of the manufacturing method.

[0297] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0298] Embodiment 2 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiment, will be described. The semiconductor device 900 can function as a memory device.

[0299] Fig. 22 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 22 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 22 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0300] The memory cell 15 exemplified in the above embodiment can be applied to the memory cell 950 .

[0301] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0302] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0303] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0304] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0305] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0306] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0307] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0308] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0309] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 22, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0310] 23A to 23H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0311] 23A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0312] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0313] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0314] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0315] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0316] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 may have the configuration of a memory cell 952 as shown in FIG. 23B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0317] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0318] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0319] 23C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0320] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0321] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0322] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0323] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0324] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in FIG. 23D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0325] 23E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 23F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0326] Note that it is preferable to use an OS transistor for at least the transistor M2, and particularly for the transistors M2 and M3.

[0327] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0328] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0329] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0330] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0331] 23G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0332] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0333] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0334] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0335] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0336] Note that at least the transistor M4 is preferably an OS transistor.

[0337] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0338] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0339] 23H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 23H is a memory cell of an SRAM capable of backing up data.

[0340] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0341] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0342] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0343] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0344] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0345] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0346] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0347] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0348] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0349] When reading data, the wirings BIL and BILB are precharged to a predetermined potential, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL. As a result, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The wirings BIL and BILB change from their precharged potentials to the potentials of the first terminals of the capacitor CD2 and CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0350] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0351] Note that Si transistors may be used as the transistors MS1 to MS4.

[0352] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 24A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 24B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0353] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0354] 25 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 25 can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0355] The arithmetic device 960 shown in FIG. 25 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0356] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0357] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0358] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0359] The arithmetic device 960 shown in FIG. 25 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 25 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0360] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0361] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0362] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0363] 25, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0364] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 26A and 26B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 26B.

[0365] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0366] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0367] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0368] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0369] 26B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0370] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0371] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0372] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0373] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0374] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 27A shows a perspective view of a semiconductor device 970B.

[0375] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 27A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0376] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0377] A plurality of memory arrays may be stacked. Figure 27B shows a perspective view of a semiconductor device 970C.

[0378] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0379] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0380] Embodiment 3 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0381] [Electronic Component] FIG. 28A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 28A has a semiconductor device 710 inside a mold 711. FIG. 28A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0382] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0383] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0384] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0385] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0386] 28B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0387] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a field programmable gate array (FPGA).

[0388] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0389] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0390] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0391] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0392] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0393] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0394] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 28B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0395] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0396] 29A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0397] 29B shows a perspective view of an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0398] Fig. 29C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629 mounted on the board 5622. Note that Fig. 29C illustrates components other than electronic components 5626, 5627, and 5628.

[0399] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0400] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0401] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0402] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0403] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0404] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0405] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0406] Fig. 30A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 30A shows a planet 6804 in space as an example.

[0407] 30A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0408] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0409] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0410] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0411] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0412] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0413] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0414] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0415] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0416] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0417] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0418] Fig. 30B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 30B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0419] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0420] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0421] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0422] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0423] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0424] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0425] 10: semiconductor device, 11: insulating layer, 15: memory cell, 20: transistor, 21: semiconductor layer, 21a: region, 21b: region, 21f: semiconductor film, 21fa: region, 21fb: region, 22: insulating layer, 22f: insulating film, 23: conductive layer, 23f: conductive film, 24: conductive layer, 24a: conductive film, 24b: conductive film, 25: conductive layer, 25a: conductive film, 25b: conductive film, 30: capacitance element, 30a: capacitance element, 31: insulating layer, 31f: insulating film, 32: insulating layer, 33: insulating layer, 34: insulating layer, 41: insulating layer, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: Insulating layer, 47: opening, 51: conductive layer, 52: insulating layer, 53: conductive layer, 61: sacrificial layer, 62: sacrificial layer, 65: resist mask, 67: sacrificial layer, 81: conductive layer, 82: plug, 83: plug, 85: insulating layer, 86: insulating layer, 87: insulating layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 98: element isolation layer, 700: electronic component, 702: printed circuit board, 704: mounting substrate, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 7 15: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell , 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface,999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 5627: electronic component, 5628: electronic component, 5629: connection terminal, 5630: motherboard, 5631: slot, 6000: storage system, 6001: host, 6001sb: server, 6002: storage control circuit, 6003: storage, 6003md: storage device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device,

Claims

a first conductive layer, a pair of second conductive layers, a pair of third conductive layers, a pair of semiconductor layers, a first insulating layer having an opening, and a pair of second insulating layers; each of the pair of semiconductor layers includes a first metal oxide; each of the pair of semiconductor layers has a first region and a second region; at least a portion of the first region functions as a channel formation region; the second region has a higher resistivity than the first region; the first conductive layer extends in a first direction; the pair of third conductive layers, the pair of semiconductor layers, the pair of second insulating layers, and the opening extend in a second direction intersecting the first direction; the pair of third conductive layers, the pair of semiconductor layers, and the pair of second insulating layers are respectively provided symmetrically within the opening; the first regions and the second regions are alternately arranged in the second direction, the first insulating layer is provided on the first conductive layer; the opening reaches the top surface of the first conductive layer; each of the pair of semiconductor layers has a vertical portion in contact with a sidewall of the opening and a horizontal portion in contact with an upper surface of the first conductive layer; each of the pair of semiconductor layers contacting an upper surface of the first conductive layer in the first region; each of the pair of second conductive layers has a portion located above the first insulating layer and in contact with the vertical portion; the pair of second insulating layers respectively covering the vertical portion and the horizontal portion; the pair of third conductive layers respectively cover the vertical portion and the horizontal portion via the second insulating layer; Semiconductor device. 　 In claim 1, the second region includes either or both of aluminum and hafnium; Semiconductor device. 　 In claim 2, the second region has a higher concentration of either or both of aluminum and hafnium than the first region; Semiconductor device. 　 In claim 1, the first conductive layer includes a first conductive film and a second conductive film on the first conductive film; the pair of semiconductor layers are each in contact with the second conductive film; the second conductive film includes a second metal oxide; the first conductive film contains a metal; Semiconductor device. 　 In claim 4, the first metal oxide and the second metal oxide contain one or more of the same elements selected from In, Sn, Zn, Ga, and Ti; Semiconductor device. 　 In claim 4, the second conductive film has a recess; the pair of semiconductor layers have portions located within the recess and in contact with the side surface and the top surface of the second conductive film within the recess; Semiconductor device. 　 In claim 1, a pair of third insulating layers; the pair of third insulating layers respectively cover the vertical portion and the horizontal portion via the second insulating layer and the third conductive layer; the third insulating layer has a function of capturing or fixing hydrogen; Semiconductor device. 　 In any one of claims 1 to 7, a capacitance element on the second conductive layer; the capacitive element includes a fourth conductive layer in contact with the second conductive layer, a fifth conductive layer, and a fourth insulating layer therebetween; Semiconductor device. 　 In claim 8, the fourth conductive layer has a recess; the fourth insulating layer has a portion provided along the recess, the fifth conductive layer has a portion located within the recess with the fourth insulating layer interposed therebetween, and is in contact with a side surface and an upper surface of the fourth insulating layer within the recess; Semiconductor device. 　 In claim 8, the fourth conductive layer has a columnar shape, the fourth insulating layer covers the fourth conductive layer; the fifth conductive layer is provided to cover an upper surface and side surfaces of the fourth conductive layer via the fourth insulating layer; Semiconductor device. 　 In any one of claims 1 to 7, a transistor below the first conductive layer; The transistor includes silicon as a semiconductor in which a channel is formed, one of a source electrode and a drain electrode of the transistor is connected to the first conductive layer; Semiconductor device.

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