Multilayer ceramic capacitor

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor capable of improving moisture resistance without increasing the thickness of an outer layer part.　This multilayer ceramic capacitor 1 includes: a laminate 10 including an inner layer part 100 including a plurality of inner layer dielectric layers 20i and a plurality of internal electrode layers 30 laminated in a first direction D1, and a pair of outer layer parts 200 arranged so as to sandwich the inner layer part 100 from the first direction D1; and a pair of external electrodes 40 arranged at both ends in a second direction D2 of the laminate 10 and connected to the internal electrode layer 30. The plurality of internal electrode layers 30 contain Ni as a main component, and include a region of MnNi oxide in at least a part of the plurality of internal electrode layers 30.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Conventionally, multilayer ceramic capacitors mounted in electronic devices generally have inner layer sections in which internal electrodes and dielectric layers are alternately laminated, and outer layer sections made up of dielectric layers. The inner layer sections contribute to capacitance generation, while the outer layer sections contribute to reliability.

[0003] On the other hand, as electronic devices become smaller and thinner, there is a demand for smaller and thinner multilayer ceramic capacitors as well. However, if the dielectric layers constituting the inner or outer layers are made thinner to accommodate the smaller and thinner multilayer ceramic capacitors, there is a risk that the reliability of the multilayer ceramic capacitor will decrease.

[0004] Japanese Patent Application Laid-Open No. 2023-113923

[0005] In order to maintain the reliability of a multilayer ceramic capacitor, for example, if an insulating layer is arranged to cover the surface of the capacitor body as described in Patent Document 1, a process for arranging the insulating layer is required, and the thickness of the insulating layer increases, making it difficult to reduce the size and thickness of the multilayer ceramic capacitor.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that can improve moisture resistance without increasing the thickness of the outer layer portions.

[0007] The present inventors have found that the reliability of a multilayer ceramic capacitor can be improved by using Ni as the main component of a plurality of internal electrode layers and including an MnNi oxide region in at least a portion of the plurality of internal electrode layers, and have completed the present invention.

[0008] That is, the present invention provides a multilayer ceramic capacitor comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers stacked in a first direction; and a pair of outer layer portions formed by arranging outer dielectric layers so as to sandwich the inner layer portion from the first direction, the laminate forming a first face and a second face opposing each other in the first direction, a third face and a fourth face opposing each other in a second direction perpendicular to the first direction, and a fifth face and a sixth face opposing each other in a third direction perpendicular to the first and second directions; and a pair of external electrodes disposed at both ends of the laminate in the second direction or the third direction and connected to the internal electrode layers, wherein the internal electrode layers are mainly composed of Ni, and at least a portion of the internal electrode layers includes a region of MnNi oxide.

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can improve moisture resistance without increasing the thickness of the outer layer portions.

[0010] 1 is a perspective view showing a multilayer ceramic capacitor according to a first embodiment; FIG. 2 is a cross-sectional view (D12 cross-sectional view) of the multilayer ceramic capacitor shown in FIG. 1 taken along line II-II; FIG. 3 is a cross-sectional view (D13 cross-sectional view) of the multilayer ceramic capacitor shown in FIG. 1 taken along line III-III; FIG. 4 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in FIG. 1; FIG. 5 is a perspective view showing a multilayer ceramic capacitor according to a second embodiment; FIG. 6 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in FIG. 7; FIG. 8 is a partially enlarged view of the D12 cross-section of the multilayer ceramic capacitor showing the presence of regions A of MnNi oxide;

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (Multilayer Ceramic Capacitor) Fig. 1 is a perspective view showing a multilayer ceramic capacitor (first embodiment), Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. Fig. 4 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in Fig. 1. The multilayer ceramic capacitor 1 shown in Figs. 1 to 4 includes a laminate 10 and external electrodes 40. The external electrodes 40 include a first external electrode 41 and a second external electrode 42.

[0013] 1 to 3 show an orthogonal coordinate system. A first direction D1 is the direction in which inner dielectric layers and internal electrode layers, which will be described later, are stacked. A second direction D2, which is orthogonal to the first direction D1, corresponds to the length direction of the multilayer ceramic capacitor 1 and the laminate 10, and a third direction D3, which is orthogonal to the first direction D1 and the second direction, corresponds to the width direction of the multilayer ceramic capacitor 1 and the laminate 10. The cross section shown in FIG. 2 is also referred to as a D12 cross section, and the cross section shown in FIG. 3 is also referred to as a D13 cross section.

[0014] The first direction D1, the second direction D2, and the third direction D3 do not necessarily have to be perpendicular to each other, and may intersect each other.

[0015] The laminate 10 has a substantially rectangular parallelepiped shape and includes a first surface P1 and a second surface P2 facing the first direction D1, a third surface P3 and a fourth surface P4 facing the second direction D2, and a fifth surface P5 and a sixth surface P6 facing the third direction D3. The surfaces of the respective surfaces may be uneven or may be roughened.

[0016] It is preferable that the corners and ridges of the laminate 10 are rounded. A corner is a portion where three surfaces of the laminate 10 intersect, and a ridge is a portion where two surfaces of the laminate 10 intersect.

[0017] 2 and 3, the laminate 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in a first direction D1. The laminate 10 also has, in the first direction D1, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100.

[0018] The inner dielectric layer 20i constituting the inner layer portion 100 and the outer dielectric layer 20o constituting the outer layer portion 200 may have different component compositions because the inner layer portion 100 and the outer layer portion 200 are required to have different functions. For example, the inner dielectric layer 20i is required to have a high dielectric constant, while the outer dielectric layer 20o is required to have high moisture resistance, facing property, and strength. For this reason, the dielectric layer constituting the inner layer portion 100 will be referred to as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 will be referred to as the outer dielectric layer 20o. However, when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be collectively referred to as the dielectric layer 20.

[0019] (Inner Layer Portion) The inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged opposite each other with the inner dielectric layers 20i interposed therebetween. The inner layer portion 100 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0020] The material of the dielectric layer 20 is, for example, BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ A dielectric ceramic containing, as a main component, a Mn compound, an Fe compound, a Cr compound, a Co compound, a Ni compound, or the like may be added as a secondary component to the material of the dielectric layer 20.

[0021] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably 0.2 μm to 2.0 μm, more preferably 0.2 μm to 0.5 μm, for example. By forming the inner dielectric layer 20i to such a thickness, it is possible to improve the capacitance while maintaining the insulating properties.

[0022] (Outer layer portion) The first outer layer portion 201 is arranged on the first surface P1 side of the laminate 10, and the second outer layer portion 202 is arranged on the second surface P2 side of the laminate 10. More specifically, the first outer layer portion 201 is arranged between the first surface P1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first surface P1, and the second outer layer portion 202 is arranged between the second surface P2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second surface P2. The first outer layer portion 201 and the second outer layer portion 202 do not include the internal electrode layer 30.

[0023] The outer layer portion 200 is formed of an insulating material. The first outer layer portion 201 and the second outer layer portion 202 can each be composed of a plurality of outer dielectric layers 20o, or may be composed of a single outer dielectric layer 20o. The outer dielectric layer 20o can be composed of the same type of dielectric material as the inner dielectric layer 20i, but may contain a different component from that of the inner dielectric layer 20i depending on the desired function.

[0024] The outer layer portion 200 preferably contains Mn. By adding a Mn compound to the outer dielectric layer 20o constituting the outer layer portion 200, it is possible to adjust the grain growth of the dielectric ceramic and form a dense outer layer portion 200. This makes it possible to improve the moisture resistance of the multilayer ceramic capacitor 1.

[0025] The content of Mn is determined by the following formula: ３ or SrTiO ３ In this case, it is preferable that Mn is present in an amount of 0.5 mol % or more and 0.7 mol % or less relative to 100 mol of Ti. The 100 mol of Ti mentioned here means that the dielectric ceramic material constituting the outer layer portion 200 has a perovskite structure (ABO ３ The amount of rare earth elements present per 100 moles of Ti was determined on the premise that the main component was a compound having the structure shown in (where B=Ti). The amount of Mn present can be confirmed by TEM-EDX.

[0026] (Internal Electrode Layers) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the first direction D1 of the laminate 10.

[0027] The first internal electrode layer 31 includes a first opposing electrode portion 311 and a first lead electrode portion 312 , and the second internal electrode layer 32 includes a second opposing electrode portion 321 and a second lead electrode portion 322 .

[0028] The first opposing electrode portion 311 and the second opposing electrode portion 321 face each other via the inner dielectric layer 20i in the first direction D1 of the laminate 10. The shapes of the first opposing electrode portion 311 and the second opposing electrode portion 321 are not particularly limited and may be, for example, approximately rectangular. The first opposing electrode portion 311 and the second opposing electrode portion 321 are portions that generate electrostatic capacitance and essentially function as a capacitor.

[0029] The first extraction electrode portion 312 extends from the first opposing electrode portion 311 toward the third surface P3 of the laminate 10 and is exposed at the third surface P3. The second extraction electrode portion 322 extends from the second opposing electrode portion 321 toward the fourth surface P4 of the laminate 10 and is exposed at the fourth surface P4. The lengths of the first opposing electrode portion 311 and the first extraction electrode portion 312 in the third direction D3 may be the same or different. Furthermore, the lengths of these portions in the third direction D3 may gradually change toward the exposed third surface P3. The lengths of the second opposing electrode portion 321 and the second extraction electrode portion 322 in the third direction D3 may be the same or different. Furthermore, the lengths of these portions in the third direction D3 may gradually change toward the exposed fourth surface P4.

[0030] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the fourth surface P4 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the third surface P3 of the laminate 10, i.e., the first external electrode 41.

[0031] The first internal electrode layer 31 and the second internal electrode layer 32 contain Ni as a primary component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd, Sn, or Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy, as a component, or may contain other components. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the primary component, particles of a dielectric material having the same composition as the ceramic contained in the internal dielectric layer 20i. In this specification, the term "primary metal" refers to the metal component with the highest weight percentage. Furthermore, the inclusion of Sn in the first internal electrode layer 31 and the second internal electrode layer 32 can mitigate electric field concentration at the interface, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is contained in only one of the internal electrode layers 30, the first internal electrode layer 31 or the second internal electrode layer 32.

[0032] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.2 μm or more and 2.0 μm or less, and more preferably 0.2 μm or more and 0.5 μm or less, for example. This makes it possible to reduce the thickness while maintaining the capacitance. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited.

[0033] The thicknesses of the inner dielectric layers 20i and the inner electrode layers 30 may be measured by, for example, observing a D12 cross section near the center in the third direction D3 of the laminate exposed by polishing with a scanning electron microscope. Each value may be an average value of measurements taken at multiple points in the second direction D2, or may be an average value of measurements taken at multiple points in the first direction D1.

[0034] 3 , the laminate 10 has, in the third direction D3, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap WG1 and a second side gap WG2 arranged to sandwich the electrode facing portion W30. The first side gap WG1 is located between the electrode facing portion W30 and the fifth plane P5, and the second side gap WG2 is located between the electrode facing portion W30 and the sixth plane P6. More specifically, the first side gap WG1 is located between the end of the internal electrode layer 30 on the fifth plane P5 side and the fifth plane P5, and the second side gap WG2 is located between the end of the internal electrode layer 30 on the sixth plane P6 side and the sixth plane P6. The first side gap WG1 and the second side gap WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap WG1 and the second side gap WG2 are also called W gaps.

[0035] The first side gap WG1 and the second side gap WG2 may have Si segregation, which can improve the flexural strength of the multilayer ceramic capacitor.

[0036] 2 , the laminate 10 has, in the second direction D2, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the third plane P3, and the second end gap LG2 is located between the electrode facing portion L30 and the fourth plane P4. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the third plane P3 side and the third plane P3, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the fourth plane P4 side and the fourth plane P4. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the inner dielectric layer 20i, while the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap LG1 is a portion that functions as an extraction electrode portion for the first internal electrode layer 31 to the third surface P3, and the second end gap LG2 is a portion that functions as an extraction electrode portion for the second internal electrode layer 32 to the fourth surface P4. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0037] The electrode opposing portion L30 is located with the first opposing electrode portion 311 of the first internal electrode layer 31 and the second opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located with the first lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located with the second lead-out electrode portion 322 of the second internal electrode layer 32.

[0038] An example of a method for measuring the length of the laminate 10 in the first direction D1 is to use a scanning electron microscope to observe, for example, a D12 cross section near the center in the third direction D3 of the laminate exposed by polishing, or a D13 cross section near the center in the second direction D2 of the laminate exposed by polishing. Each value may be an average of measurements taken at multiple locations in the second direction D2 or the third direction D3. Similarly, an example of a method for measuring the length of the laminate 10 in the second direction is to use a scanning electron microscope to observe, for example, a D12 cross section near the center in the third direction D3 of the laminate exposed by polishing. Each value may be an average of measurements taken at multiple locations in the first direction D1. Similarly, an example of a method for measuring the length of the laminate 10 in the third direction is to use a scanning electron microscope to observe, for example, a D13 cross section near the center in the second direction D2 of the laminate exposed by polishing. Each value may be an average of measurements taken at multiple locations in the first direction D1.

[0039] It is preferable that the dimension of the laminate in the first direction D1 be 0.1 mm or more and 1.0 mm or less, the dimension in the second direction D2 be 0.2 mm or more and 1.8 mm or less, and the dimension in the third direction D3 be 0.1 mm or more and 1.0 mm or less.

[0040] (External Electrodes) The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0041] The first external electrode 41 is disposed on the third surface P3 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the third surface P3 to a portion of the first surface P1 and a portion of the second surface P2. The first external electrode 41 may also extend from the third surface P3 to a portion of the fifth surface P5 and a portion of the sixth surface P6.

[0042] The second external electrode 42 is disposed on the fourth surface P4 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the fourth surface P4 to a portion of the first surface P1 and a portion of the second surface P2. The second external electrode 42 may also extend from the fourth surface P4 to a portion of the fifth surface P5 and a portion of the sixth surface P6.

[0043] The first external electrode 41 has a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 has a second base electrode layer 425 and a second plating layer 426. The first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0044] The first base electrode layer 415 and the second base electrode layer 425 may be fired layers containing a metal and glass. The glass may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may contain Cu as a main component. The metal may contain at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0045] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0046] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layers may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0047] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0048] The thickness of each of the first base electrode layer 415 and the second base electrode layer 425 as a fired layer or a resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0049] Alternatively, the first base electrode layer 415 and the second base electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0050] First plating layer 416 covers at least a portion of first base electrode layer 415, and second plating layer 426 covers at least a portion of second base electrode layer 425. First plating layer 416 and second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag—Pd alloys.

[0051] The first plating layer 416 and the second plating layer 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The first plating layer 416 and the second plating layer 426 may each have a three-layer structure, for example, by stacking Sn plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0052] The thickness of each of first plating layer 416 and second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0053] (MnNi oxide region) The plurality of internal electrode layers 30 included in the internal layer portion 100 are mainly composed of Ni, and a region A of MnNi oxide is present in at least a part of the plurality of internal electrode layers 30. That is, the region A of MnNi oxide may be present in a part of all the internal electrode layers 30 included in the internal layer portion 100, or the region A of MnNi oxide may be present in a part of some of the plurality of internal electrode layers 30 included in the internal layer portion 100. In this way, by forming the region A of MnNi oxide in at least a part of the plurality of internal electrode layers 30, the moisture resistance of the internal electrode layers 30 can be improved.

[0054] <Method for identifying various elements> A multilayer ceramic capacitor is polished in the third direction D3 until it is reduced to half its original size, and a cross section (D12 cross section) parallel to the first direction D1 and the second direction D2 is exposed. Elements can be identified by TEM-EDX measurement using a JEOL JEM-2200FS or JEM-F200.

[0055] When the inner layer portion 100 is divided into three equal regions in the first direction D1, the regions are defined as a first surface side region R1, a central region RC, and a second surface side region R2, in that order from the first surface P1 side, the internal electrode layer 30 in the first surface side region R1 and the second surface side region R2 preferably has a higher proportion of MnNi oxide regions A than the internal electrode layer in the central region RC. The presence of a higher proportion of MnNi oxide regions A in the internal electrode layer 30 in the first surface side region R1 and the second surface side region R2 makes it possible to prevent moisture penetration from the first direction D1, thereby improving the moisture resistance of the multilayer ceramic capacitor 1. Furthermore, in order to increase the proportion of MnNi oxide regions A in the internal electrode layer 30 in the first surface side region R1 or the second surface side region R2, it is preferable that the outer dielectric layer 20o contains Mn.

[0056] In the inner layer portion 100, the ratio of the area of ​​the MnNi oxide region to the total area of ​​the internal electrode layer 30 located within 20 μm in the first direction D1 from the internal electrode layer 30 closest to the first surface P1 among the plurality of internal electrode layers 30, or the internal electrode layer 30 located within 20 μm in the first direction from the internal electrode layer 30 closest to the second surface P2 among the plurality of internal electrode layers 30, is preferably 170 ppm or more and 300 ppm or less. If the area ratio of the MnNi oxide region is less than 170 ppm, the densification of the outer layer portion becomes insufficient, and if it is more than 300 ppm, the abundance ratio of the MnNi oxide region becomes so high that structural defects may occur. Therefore, in order to prevent the penetration of moisture from the outside and improve moisture resistance, it is preferable that the area ratio of the MnNi oxide region be 170 ppm or more and 300 ppm or less. In order to adjust the area ratio of the MnNi oxide region in the internal electrode layer 30 within a region of 20 μm in the first direction D1 from the internal electrode layer 30 closest to the first surface P1, or in the internal electrode layer 30 within a region of 20 μm in the first direction from the internal electrode layer 30 closest to the second surface P2, it is preferable that the outer dielectric layer 20o contains Mn.

[0057] <Method for measuring the proportion of MnNi oxide regions> A multilayer ceramic capacitor was polished in the third direction D3 to half its original size, and a cross section (D12 cross section) parallel to the first direction D1 and the second direction D2 was exposed. The proportion of the MnNi oxide regions was measured by measuring the length of the MnNi oxide regions relative to each internal electrode in each region using a Keyence VHX-8000 at a magnification of 150x in bright field.

[0058] The inner dielectric layer 20i in the first surface region R1 or the second surface region R2 preferably has a higher proportion of Dy dissolved in the solid solution near the MnNi oxide region A than the inner dielectric layer 20i in the central region RC. This reduces the dimension of the inner dielectric layer in the first direction D1, and increases the proportion of Dy dissolved in the solid solution near the outer layer portion where insulation degradation is likely to occur, thereby improving insulation reliability.

[0059] (Manufacturing Method) Next, an example of a manufacturing method for the above-mentioned multilayer ceramic capacitor 1 will be described. A dielectric sheet for the dielectric layers 20 and a conductive paste for the internal electrode layers 30 are prepared. The dielectric sheet and the conductive paste contain a binder and a solvent. Known materials can be used as the binder and the solvent.

[0060] The main components of the dielectric sheet for the inner dielectric layer 20i are BaTiO3, CaTiO ３ or SrTiO ３ It is preferable that Dy is present in an amount of 0.97 mol % or more and 1.07 mol % or less relative to 100 mol of Ti. The term "100 mol of Ti" used here means that the dielectric ceramic material constituting the inner dielectric layer 20i has a perovskite structure (ABO ３ The amount of Dy present is determined based on the premise that the main component is a compound having the structure shown in

[0061] The main components of the dielectric sheet for the outer dielectric layer 20o are BaTiO3, CaTiO ３ or SrTiO ３ It is preferable that Mn is present in an amount of 0.5 mol % or more and 0.7 mol % or less relative to 100 mol of Ti. The 100 mol of Ti mentioned here means that the dielectric ceramic material constituting the inner dielectric layer 20i has a perovskite structure (ABO ３ The amount of rare earth elements present per 100 moles of Ti was determined on the premise that the main component was a compound having the structure shown in (where B=Ti). The amount of Mn present can be confirmed by TEM-EDX.

[0062] Next, a conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. The internal electrode pattern can be formed by screen printing, gravure printing, or the like.

[0063] Next, a predetermined number of dielectric sheets for the second outer layer portion 202, on which no internal electrode pattern is printed, are stacked. Dielectric sheets for the inner layer portion 100, on which internal electrode patterns are printed, are stacked in sequence on top of these. A predetermined number of dielectric sheets for the first outer layer portion 201, on which no internal electrode pattern is printed, are stacked on top of these. In this way, a laminated sheet is produced.

[0064] Next, the laminate sheet is pressed in the first direction D1 using a means such as a hydrostatic press to produce a laminate block. Next, the laminate block is cut to a predetermined size, and laminate chips are cut out. At this time, the corners and ridges of the laminate chip are rounded by barrel polishing or the like. Note that the laminate chip may be cut so that the internal electrode patterns are exposed on both side surfaces in the third direction D3, and a covering dielectric sheet that becomes the first side gap WG1 and the second side gap WG2 may be attached to cover both side surfaces.

[0065] Next, the laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric and the internal electrodes, but is preferably 900° C. or higher and 1400° C. or lower.

[0066] During firing of the laminate, the MnNi oxide region present in the region 20 μm inward in the first direction D1 from the internal electrode closest to the outer layer is fired to 170 ppm to 300 ppm, thereby densifying the outer layer and improving moisture resistance. Note that a re-oxidation treatment can then be performed to control the solid solution of Dy in the MnNi oxide region nearby, thereby suppressing insulation degradation.

[0067] Next, using a dipping method, the third surface P3 of the laminate 10 is immersed in a conductive paste that is an electrode material for the base electrode layer, thereby applying a conductive paste for the first base electrode layer 415 to the third surface P3. Similarly, using a dipping method, the fourth surface P4 of the laminate 10 is immersed in a conductive paste that is an electrode material for the base electrode layer, thereby applying a conductive paste for the second base electrode layer 425 to the fourth surface P4. These conductive pastes are then fired to form the first base electrode layer 415 and the second base electrode layer 425, which are fired layers. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0068] As described above, the first base electrode layer 415 and the second base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and then firing it, or the first base electrode layer 415 and the second base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0069] Thereafter, a first plating layer 416 is formed on the surface of the first base electrode layer 415 to form the first external electrode 41, and a second plating layer 426 is formed on the surface of the second base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 is obtained.

[0070] The present invention is not limited to the shape of the multilayer ceramic capacitor 1, and can be widely used as long as it has an inner layer portion 100 formed by laminating inner dielectric layers 20i and internal electrode layers 30.

[0071] For example, as shown in FIG. 5, there is a multilayer ceramic capacitor 1A having external electrodes 40a and 40b on the fifth surface P5 and the sixth surface P6 of the laminate 10, respectively, and having external electrodes 40c and 40d on the third surface P3 and the fourth surface P4 of the laminate 10, respectively.

[0072] 6, the inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. The inner layer portion 100 includes, in the first direction D1, the internal electrode layer 30 located closest to the first surface P1 to the internal electrode layer 30 located closest to the second surface P2. In the inner layer portion 100, the multiple internal electrode layers 30 are arranged opposite each other with the inner dielectric layer 20i interposed therebetween.

[0073] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 are arranged on the multiple inner dielectric layers 20i. The multiple second internal electrode layers 32 are arranged on the multiple inner dielectric layers 20i. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the first direction D1 of the laminate 10, with the inner dielectric layers 20i interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the inner dielectric layers 20i therebetween.

[0074] The first internal electrode layer 31 is connected to the external electrodes 40a, 40b on the fifth surface P5 and the sixth surface P6 of the laminate 10, and the second internal electrode layer 32 is connected to the external electrodes 40c, 40d on the third surface P3 and the fourth surface P4 of the laminate 10.

[0075] The multilayer ceramic capacitor 1A can be used as a three-terminal capacitor by dividing the power supply line or signal line in the circuit, connecting the external electrode 40c to one end of the divided line, connecting the external electrode 40d to the other end of the divided line, and connecting the external electrodes 40a and 40b to ground. In this case, the second internal electrode layer 32 serves as a through electrode, and the first internal electrode layer 31 serves as a ground electrode.

[0076] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention.

[0077] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 First opposing electrode portion 312 First lead electrode portion 32 Second internal electrode layer 321 Second opposing electrode portion 322 Second lead electrode portion 40 External electrode 41 First external electrode 415 First base electrode layer 416 First plating layer 42 Second external electrode 425 Second base electrode layer 426 Second plating layer 100 Internal layer portion 200 External layer portion 201 First external layer portion 202 Second external layer portion L30 Electrode opposing portion LG1 First end gap portion LG2 Second end gap portion W30 Electrode opposing portion WG1 First side gap portion WG2 Second side gap portion D1 First direction D2 Second direction D3 Third direction P1 First surface P2 Second surface P3 Third surface P4 Fourth surface P5 Fifth surface P6 Sixth surface A MnNi oxide region R1 First surface side region RC Central region R2 Second surface side region

Claims

1. A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers stacked in a first direction; and a pair of outer layer portions formed by arranging outer dielectric layers so as to sandwich the inner layer portion from the first direction, the laminate forming a first face and a second face opposing each other in the first direction, a third face and a fourth face opposing each other in a second direction perpendicular to the first direction, and a fifth face and a sixth face opposing each other in a third direction perpendicular to the first direction and the second direction; and a pair of external electrodes disposed at both ends of the laminate in the second direction or the third direction and connected to the internal electrode layers, wherein the internal electrode layers are mainly composed of Ni, and at least a portion of the internal electrode layers includes a region of MnNi oxide.

2. The multilayer ceramic capacitor according to claim 1, wherein the outer dielectric layers contain Mn, and when the inner layer portion is divided into three equal parts in the first direction, the regions are defined as a first surface side region, a central region, and a second surface side region in order from the first surface side, the internal electrode layers in the first surface side region and the second surface side region have a higher proportion of MnNi oxide regions than the internal electrode layers in the central region.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the outer dielectric layer contains Mn, and in the inner layer portion, a ratio of an area of the MnNi oxide region to a total area of the internal electrode layer located within a region of 20 μm in the first direction from the internal electrode layer of the plurality of internal electrode layers that is closest to the first surface, or of the internal electrode layer located within a region of 20 μm in the first direction from the internal electrode layer of the plurality of internal electrode layers that is closest to the second surface, is 170 ppm or more and 300 ppm or less.

4. The multilayer ceramic capacitor according to claim 2, wherein the inner dielectric layer in the first surface region or the second surface region has a higher proportion of Dy dissolved in a solid solution near the MnNi oxide region than the inner dielectric layer in the central region.

5. A multilayer ceramic capacitor comprising: an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers stacked in a first direction; and a pair of outer layer portions formed by arranging outer dielectric layers so as to sandwich the inner layer portion from the first direction, the laminate forming a first face and a second face opposing each other in the first direction, a third face and a fourth face opposing each other in a second direction perpendicular to the first direction, and a fifth face and a sixth face opposing each other in a third direction perpendicular to the first direction and the second direction; and external electrodes disposed at both ends of the laminate in the second direction and at both ends in the third direction, and connected to the internal electrode layers, wherein the internal electrode layers are mainly composed of Ni, and at least a portion of the internal electrode layers includes a region of MnNi oxide.

6. The multilayer ceramic capacitor according to claim 5, wherein the outer dielectric layers contain Mn, and when the inner layer portion is divided into three equal parts in the first direction, the regions are defined as a first surface side region, a central region, and a second surface side region in order from the first surface side, the internal electrode layers in the first surface side region and the second surface side region have a higher proportion of MnNi oxide regions than the internal electrode layers in the central region.

7. The multilayer ceramic capacitor according to claim 5 or 6, wherein the outer dielectric layer contains Mn, and in the inner layer portion, the ratio of the area of the MnNi oxide region to the internal electrode layer located within a region of 20 μm in the first direction from the internal electrode layer closest to the first surface among the internal electrode layers and the internal electrode layer located within a region of 20 μm in the first direction from the internal electrode layer closest to the second surface among the internal electrode layers is 170 ppm or more and 300 ppm or less.

8. The multilayer ceramic capacitor according to claim 6, wherein the inner dielectric layer contains Dy, and the inner dielectric layer near the MnNi oxide region in the first surface region and the second surface region has a higher proportion of Dy dissolved therein than the inner dielectric layer near the MnNi oxide region in the central region.

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