Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor.　A multilayer ceramic capacitor 1 includes: a laminate 2; a first external electrode 3A provided on a first end surface CA and connected to an internal electrode 15; and a second external electrode 3B provided on a second end surface BB and connected to the internal electrode. The first external electrode 3A including: a first base electrode layer 31A connected to the internal electrode 15 and having a conductive metal and a glass 52; and a first plating layer 32A disposed on the first base electrode layer 31A. The first plating layer 32A is provided, on its surface, with: a plurality of recesses 55 that are recessed from the surface of the first plating layer 32A toward the laminate 2; and a recess region 58 that is a region comprising adjacent recesses 55.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors (see, for example, Patent Document 1) exist that include a laminate in which internal electrodes and dielectric layers are alternately stacked, and external electrodes connected to the internal electrodes. Multilayer ceramic capacitors are one of the important electronic components.

[0003] Japanese Patent Application Laid-Open No. 2003-243249

[0004] In recent years, with the spread of electric vehicles and smartphones, there has been a growing demand for highly reliable multilayer ceramic capacitors that can operate stably.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor with excellent reliability.

[0006] In order to solve the above-mentioned problems, the multilayer ceramic capacitor of the present invention comprises a laminate having a plurality of stacked dielectric layers and a plurality of internal electrodes, the laminate having first and second main surfaces opposing each other in a stacking direction, first side surfaces opposing each other in a width direction perpendicular to the stacking direction, and first end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode provided on the first end surface and connected to the internal electrode; and a second external electrode provided on the second end surface and connected to the internal electrode, the first external electrode having a first base electrode layer connected to the internal electrode and including a conductive metal and glass; and a first plating layer disposed on the first base electrode layer, the surface of the first plating layer having a plurality of recessed portions recessed from the surface of the first plating layer toward the laminate, and a recessed region which is an area consisting of adjacent recessed portions.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor with excellent reliability.

[0008] 1. A schematic perspective view of the multilayer ceramic capacitor 1 in accordance with the first embodiment. A cross-sectional view taken along II-II in FIG. 1. A cross-sectional view taken along III-III in FIG. 1. A cross-sectional view taken along IV-IV in FIG. 1. A schematic perspective view of the multilayer ceramic capacitor 1 in accordance with a second embodiment. A cross-sectional view taken along VI-VI in FIG. 5. A view of the first external electrode 3A in accordance with the second embodiment as seen in the length direction L. An enlarged view of part VIII in FIG. 6. An enlarged view of part IX in FIG. 8.

[0009] A multilayer ceramic capacitor 1 according to an embodiment of the present invention will now be described with reference to FIGS.

[0010] (Multilayer Ceramic Capacitor 1) As shown in Fig. 1, the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a so-called two-terminal structure. The multilayer ceramic capacitor 1 includes a laminate 2, a first external electrode 3A, and a second external electrode 3B. The laminate 2 is substantially rectangular and has six outer surfaces. The laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are stacked. The first external electrode 3A and the second external electrode 3B may be collectively referred to as the "external electrodes 3."

[0011] In this specification, the direction in which the dielectric layers 14 and the internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 is referred to as the stacking direction T. One of the directions perpendicular to the stacking direction T is referred to as the length direction L. The direction perpendicular to both the length direction L and the stacking direction T is referred to as the width direction W.

[0012] Of the six outer surfaces of the laminate 2, a pair of outer surfaces on both sides in the stacking direction T are referred to as the first main surface AA and the second main surface AB, a pair of outer surfaces extending in the stacking direction T and on both sides in the width direction W are referred to as the first side surface BA and the second side surface BB, and a pair of outer surfaces extending in the stacking direction T and on both sides in the length direction L are referred to as the first end surface CA and the second end surface CB. The first main surface AA and the second main surface AB may be collectively referred to as "each main surface A." The first side surface BA and the second side surface BB may be collectively referred to as "each side surface B." The first end surface CA and the second end surface CB may be collectively referred to as "each end surface C."

[0013] A cross section parallel to the stacking direction T and the length direction L is referred to as an "LT cross section." A cross section parallel to the stacking direction T and the width direction W is referred to as a "WT cross section." The cross section in FIG. 2 is an LT cross section passing through the center in the width direction W of the multilayer ceramic capacitor 1. The cross section in FIG. 3 is a WT cross section passing through the center in the length direction L of the multilayer ceramic capacitor 1. The cross section in FIG. 4 is a WT cross section passing through the center in the length direction L of a portion of the first external electrode 3A that overlaps with the first main surface AA when viewed in the stacking direction T.

[0014] (Laminate 2) The laminate 2 has an inner layer portion 11 and a pair of outer layer portions 12 arranged on either side of the inner layer portion 11 in the stacking direction T. The laminate 2 preferably has rounded corners and ridges. Note that the corners are portions where three surfaces of the laminate 2 intersect. The ridges are portions where two surfaces of the laminate 2 intersect.

[0015] The outer dimensions of the laminate are, for example, 0.2 mm to 5.7 mm in the length direction L and 0.1 mm to 5.0 mm in the width direction W. The outer dimensions of the multilayer ceramic capacitor 1 can be measured using a micrometer.

[0016] 2 and 3, the inner layer portion 11 has a plurality of dielectric layers 14 and a plurality of internal electrodes 15. The dielectric layers 14 and the internal electrodes 15 are alternately stacked.

[0017] The dielectric layer 14 is made of a perovskite-type compound containing Ba or Ti. Dielectric ceramics containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like as a main component can be used as the material for the dielectric layer 14. Furthermore, materials containing these main components and added with a secondary component such as a Mn compound, Mg compound, Si compound, Fe compound, Cr compound, Co compound, Ni compound, Al compound, V compound, or rare earth compound can also be used.

[0018] The internal electrodes 15 are formed by sintering a conductive paste containing a metal powder that serves as a conductor, an organic solvent, a binder, and a dispersant on the dielectric layer 14. As the metal powder that serves as a conductor, for example, metals such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, and Au can be used. These metals may also be compounds containing these metal elements or alloys with other metals.

[0019] The internal electrode 15 includes a plurality of first internal electrodes 15A and a plurality of second internal electrodes 15B. The first internal electrodes 15A are exposed only at the first end face CA. The second internal electrodes 15B are exposed only at the second end face CB. The first internal electrodes 15A and the second internal electrodes 15B are arranged alternately.

[0020] The first internal electrode 15A has a first opposing portion 15Aa and a first lead portion 15Ab. The first opposing portion 15Aa is a portion of the first internal electrode 15A that faces the second internal electrode 15B adjacent to it in the stacking direction T. The first opposing portion 15Aa is located in the center between the end faces C. The first lead portion 15Ab is a portion of the first internal electrode 15A that is led out from the first opposing portion 15Aa toward the first end face CA.

[0021] The second internal electrode 15B has a second opposing portion 15Ba and a second lead portion 15Bb. The second opposing portion 15Ba is a portion of the second internal electrode 15B that faces the adjacent first internal electrode 15A (first opposing portion 15Aa). The second opposing portion 15Ba is located in the center between the end faces C. The second lead portion 15Bb is a portion of the second internal electrode 15B that is led out from the second opposing portion 15Ba toward the second end face CB.

[0022] The first internal electrode 15A and the second internal electrode 15B may be collectively referred to as "internal electrodes 15." The first opposing portion 15Aa and the second opposing portion 15Ba may be collectively referred to as "opposing portion 15a."

[0023] (Outer Layer Portion 12) The outer layer portion 12 is formed of the same material as the dielectric layer 14 of the inner layer portion 11. Note that no inner electrode 15 is disposed in the outer layer portion 12.

[0024] (External electrode 3) The first external electrode 3A is provided on the first end face CA. The first external electrode 3A covers not only the first end face CA but also part of the main face A and part of the side face B. The first external electrode 3A is connected to the first internal electrode 15A. The first external electrode 3A includes a first base electrode layer 31A formed in contact with the surface of the laminate 2 and a first plating layer 32A disposed on the first base electrode layer 31A. The first plating layer 32A includes a first lower plating layer 33A disposed on the first base electrode layer 31A and a first upper plating layer 34A disposed on the first lower plating layer 33A.

[0025] The second external electrode 3B is provided on the second end face CB. The second external electrode 3B covers not only the second end face CB but also a portion of the main face A and a portion of the side face B. The second external electrode 3B is connected to the second internal electrode 15B. The second external electrode 3B includes a second base electrode layer 31B formed in contact with the surface of the laminate 2 and a second plating layer 32B disposed on the second base electrode layer 31B. The second plating layer 32B includes a second lower plating layer 33B disposed on the second base electrode layer 31B and a second upper plating layer 34B disposed on the second lower plating layer 33B.

[0026] The first base electrode layer 31A and the second base electrode layer 31B may be collectively referred to as the "base electrode layer 31." The first plating layer 32A and the second plating layer 32B may be collectively referred to as the "plating layer 32." The first lower plating layer 33A and the second lower plating layer 33B may be collectively referred to as the "lower plating layer 33." The first upper plating layer 34A and the second upper plating layer 34B may be collectively referred to as the "upper plating layer 34."

[0027] The base electrode layer 31 includes a conductive metal, glass 52, and voids 53. The base electrode layer 31 is, for example, a baked layer. The conductive metal is, for example, a suitable metal such as Ni (nickel), Cu (copper), Ag (silver), Pd (palladium), Au (gold), or an Ag-Pd alloy, and is preferably Cu. The metal contained in the base electrode layer 31 can be confirmed using a wavelength dispersive X-ray analyzer (WDX) after polishing the multilayer ceramic capacitor 1. The maximum thickness of the base electrode layer 31 is preferably 10 μm or more and 200 μm or less. The thickness of the base electrode layer 31 is thinner at the corners of the laminate 2. The glass 52 is particulate. The glass 42 and voids 53 can be confirmed using a scanning electron microscope (SEM) after polishing the multilayer ceramic capacitor 1.

[0028] The plating layer 32 is made of, for example, one metal selected from the group consisting of Ni, Cu, Ag, Pd, Au, and Sn, or an alloy containing this metal.

[0029] The lower plating layer 33 is, for example, a Ni plating layer. The upper plating layer 34 is, for example, a Sn (tin) plating layer. The thickness of each plating layer is preferably 1.5 μm or more and 15.0 μm or less. The plating layer may be a single layer, or may be a Cu plating layer or an Au plating layer.

[0030] The external electrodes 3 are connected to the substrate by solder when the multilayer ceramic capacitor 1 is mounted on the substrate with the first main surface AA facing the substrate.

[0031] Here, the first base electrode layer 31 A will be described in detail. Note that the configuration of the second base electrode layer 31 B is similar to that of the first base electrode layer 31 A, and therefore a description thereof will be omitted.

[0032] As shown in Figures 2 and 4, the first external electrode 3A has a first external electrode end surface region 3Ac, which is a region that overlaps with the first end face CA when viewed in the longitudinal direction L, a first external electrode main surface region 3Aa, which is a region that overlaps with the first main surface AA when viewed in the stacking direction T, and a first external electrode corner region 3Ad, which is a region that connects at least one of the first external electrode side surface region 3Ab and the first external electrode main surface region 3Aa to the first external electrode end surface region 3Ac.

[0033] The first base electrode layer 31A has a first base electrode end surface region 31Ac which is a region overlapping with the first end surface CA when viewed in the longitudinal direction L, a first base electrode main surface region 31Aa which is a region overlapping with the first main surface AA when viewed in the stacking direction T, and a first base electrode corner region 31Ad which is a region connecting at least one of the first base electrode side surface region 31Ab and the first base electrode main surface region 31Aa to the first base electrode end surface region 31Ac.

[0034] The first plating layer 32A has a first plating end surface region 32Ac which is a region overlapping with the first end surface CA when viewed in the longitudinal direction L, a first plating main surface region 32Aa which is a region overlapping with the first main surface AA when viewed in the stacking direction T, and a first plating corner region 32Ad which is a region connecting at least one of the first plating side surface region 32Ab and the first plating main surface region 32Aa to the first plating end surface region 32Ac.

[0035] The first lower plating layer 33A has a first lower plating end surface region 33Ac which is a region overlapping with the first end surface CA when viewed in the longitudinal direction L, a first lower plating main surface region 33Aa which is a region overlapping with the first main surface AA when viewed in the stacking direction T, and a first lower plating corner region 33Ad which is a region connecting at least one of the first lower plating side surface region 33Ab and the first lower plating main surface region 33Aa to the first lower plating end surface region 33Ac.

[0036] The first lower plating layer 33A covers the entire outer surface of the first base electrode layer 31A, so that the entire outer surface of the first base electrode end surface region 31Ac corresponds to the region of the outer surface of the first base electrode end surface region 31Ac that faces the first plating layer 32A.

[0037] The first upper plating layer 34A covers the entire outer surface of the first lower plating layer 33A. The outer surface of the first upper plating layer 34A forms the outer surface of the first external electrode 3A and also the outer surface of the first plating layer 32A.

[0038] (Surface Smoothness) The outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode main surface region 31Aa, and for example, has a smaller surface roughness.

[0039] The outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode side surface region 31Ab, and for example, has a smaller surface roughness.

[0040] The region of the outer surface of the first base electrode end surface region 31Ac that faces the first plating layer 32A is smoother than both the region of the outer surface of the first base electrode main surface region 31Aa that faces the first plating layer 32A and the region of the outer surface of the first base electrode side surface region 31Ab that faces the first plating layer 32A, and has, for example, smaller surface roughness.

[0041] The outer surface of the first lower plated end surface region 33Ac is smoother than the outer surface of the first lower plated main surface region 33Aa, and for example, has a smaller surface roughness.

[0042] The outer surface of the first lower plated end surface region 33Ac is smoother than the outer surface of the first lower plated side surface region 33Ab, and for example, has a smaller surface roughness.

[0043] The surface roughness of the outer surface of the first lower plated end surface region 33Ac is 0 μm or more and 0.1 μm or less. The surface roughness of the outer surface of the first lower plated main surface region 33Aa and the surface roughness of the outer surface of the first lower plated side surface region 33Ab are each greater than 0.1 μm and less than 0.4 μm. It is more preferable that the surface roughness of the outer surface of the first lower plated main surface region 33Aa and the surface roughness of the outer surface of the first lower plated side surface region 33Ab are each greater than 0.1 μm and less than 0.4 μm.

[0044] The outer surface of the first base electrode corner region 31Ad is smoother than both the outer surface of the first base electrode main surface region 31Aa and the outer surface of the first base electrode side surface region 31Ab, and for example, has smaller surface roughness.

[0045] The outer surface of the first lower plated corner region 33Ad is smoother than both the outer surface of the first lower plated main surface region 33Aa and the outer surface of the first lower plated side surface region 33Ab, and for example, has smaller surface roughness.

[0046] The value obtained by dividing the surface roughness of the outer surface of the first lower plated end surface region 33Ac by the average value of the surface roughness of the outer surface of the first lower plated main surface region 33Aa and the surface roughness of the outer surface of the first lower plated side surface region 33Ab is greater than 0 and not more than 0.7. This allows the solder to sufficiently wet and rise onto the first external electrode end surface region 3Ac.

[0047] The surface roughness of the first base electrode layer 31A, the first lower plating layer 33A, and the first upper plating layer 34A is measured by acquiring images of the measurement object using a laser microscope and analyzing the acquired images using analysis software. The surface roughness is defined as the arithmetic mean height Sa. The dimensions of the acquired images are, for example, 280 μm × 210 μm.

[0048] Prior to measuring the surface roughness of the first lower plating layer 33A, the first upper plating layer 34A is stripped. The first upper plating layer 34A is stripped by immersing the first external electrode 3A in a metal stripping solution for a predetermined period of time. The metal stripping solution is stirred as appropriate. When the plating layer is a Sn plating layer, the metal stripping solution is, for example, Enstrip TL-105. The immersion time is, for example, 1.5 to 9 minutes. Because the thickness of the lower plating layer is approximately uniform, if the surface roughness of the lower plating layer can be measured, the surface roughness of the base electrode layer can also be measured.

[0049] In the LT cross section passing through the center of the width direction W of the laminate 2, the ratio of the length of the line along the outer surface of the first base electrode end surface region 31Ac to the length of the line along the first end surface CA is smaller than the ratio of the length of the line along the outer surface of the first base electrode main surface region 31Aa to the length of the line along the portion of the first main surface AA where the first base electrode layer 31A is located.

[0050] In the LT cross section passing through the center of the width direction W of the laminate 2, if the ratio of the length of the line along the outer surface of the first base electrode end surface region 31Ac to the length of the line along the first end surface CA is A1, and the ratio of the length along the outer surface of the first base electrode main surface region 31Aa to the length of the line along the portion of the first main surface AA that contacts the first base electrode main surface region 31Aa is B1, the relationship between A1 and B1 satisfies 0.5 <= A1 / B1 < 1.

[0051] In the LT cross section passing through the center of the laminate 2 in the width direction W, a rectangular region having sides extending parallel to the first principal surface AA and sides extending parallel to the first end surface CA, and having dimensions of 75 μm × 55 μm, is defined as the “reference region.” The lengths of lines along the first end surface CA, the length of lines along the outer surface of the first base electrode end surface region 31Ac, the length of lines along a portion of the first principal surface AA that contacts the first base electrode principal surface region 31Aa, and the length along the outer surface of the first base electrode principal surface region 31Aa are each defined as the lengths of the portions located in the reference region.

[0052] When obtaining the length of a line along the first end face CA and the length of a line along the outer surface of the first base electrode end face region 31Ac, the position of the reference region is defined as a position where the center of the reference region in the stacking direction T overlaps with the center of the first base electrode end face region 31Ac in the stacking direction T. When obtaining the length of a line along a portion of the first main surface AA that contacts the first base electrode main face region 31Aa and the length along the outer surface of the first base electrode main face region 31Aa, the position of the reference region is defined as a position where the center of the reference region in the length direction overlaps with the center of the first base electrode main face region 31Aa in the width direction W.

[0053] An image of the reference area is acquired using an optical microscope. The lengths of various lines are measured in the acquired image. The cross section of the multilayer ceramic capacitor 1 to be measured is exposed by polishing the multilayer ceramic capacitor 1.

[0054] (Hardness of First Base Electrode Layer 31A) The hardness Hv of the first base electrode end surface region 31Ac is higher than both the hardness Hv of the first base electrode main surface region 31Aa and the hardness Hv of the first base electrode side surface region 31Ab.

[0055] The hardness Hv of the first base electrode end surface region 31Ac is 100 or more and 200 or less.

[0056] The hardness Hv of the first base electrode corner region 31Ad is higher than both the hardness Hv of the first base electrode main surface region 31Aa and the hardness Hv of the first base electrode side surface region 31Ab.

[0057] The hardness Hv of each portion of the first base electrode layer 31A is measured using a microhardness tester on the multilayer ceramic capacitor 1 from which the first upper plating layer 34A has been removed. The hardness Hv of each portion of the first base electrode layer 31A is the hardness Hv of the outer surface of each portion of the first base electrode layer 31A. The hardness Hv of the outer surface of the first base electrode layer 31A is measured from above the first lower plating layer 33A while the first lower plating layer 33A is attached to the first base electrode layer 31A. Because the thickness of the first lower plating layer 33A is extremely small, the impact of the first lower plating layer 33A on the measured hardness Hv of the outer surface of the first base electrode layer 31A is small. However, the first upper plating layer 34A is previously removed using a metal stripping solution as described above.

[0058] (Method for Manufacturing Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the embodiment will be described.

[0059] (Internal electrode pattern forming process) First, a ceramic green sheet is prepared by forming a ceramic slurry into a sheet shape. A pattern of the internal electrodes 15 is printed on the ceramic green sheet using a conductive paste. This results in a laminated ceramic green sheet for an inner layer portion on which the internal electrodes 15 are arranged. The pattern of the internal electrodes 15 is formed by printing, for example, by screen printing, gravure printing, letterpress printing, or the like.

[0060] (Laminating Process) Next, the ceramic green sheets for the inner layer portions are laminated. The ceramic green sheets for the inner layer portions are laminated so that the internal electrode patterns are shifted by half a pitch between adjacent sheets in the length direction L. Next, ceramic green sheets for the outer layer portions, which will become the outer layer portions 12, are laminated on both sides of the laminated ceramic green sheets in the lamination direction T. The ceramic green sheets for the outer layer portions are thermocompression bonded to the ceramic green sheets for lamination. This produces a mother block.

[0061] Each outer layer portion 12 may be formed by laminating a plurality of ceramic green sheets or by a single ceramic green sheet. The ceramic green sheets for the inner layer portion and the ceramic green sheets for the outer layer portion may contain different components.

[0062] (Mother Block Cutting Process) Next, the mother block is divided along cutting lines corresponding to the dimensions of the laminate 2. The mother block is cut, for example, in the length direction L and the width direction W. This results in a plurality of rectangular parallelepiped blocks (referred to as "laminated chips"). It is preferable that the corners and ridges of the laminated chips are rounded, for example, by barrel polishing.

[0063] (Laminate Firing Step) Next, the laminated chip is heated at a predetermined firing temperature in a nitrogen atmosphere for a predetermined time, thereby obtaining the laminate 2.

[0064] (Base electrode layer forming process) Next, a base electrode layer 31 is formed on each end face C of the laminate 2. A conductive paste containing glass and metal is applied onto the laminate 2. Each base electrode layer 31 is formed, for example, so as to cover each end face C, each main face A, each side face B, and a part of each ridge 5 on the end face C side. However, this is not limited to this, and each base electrode layer 31 may be disposed only on each end face C.

[0065] (Base electrode layer baking process) Next, the laminate 2 on which the base electrode layer 31 has been formed is heated in a nitrogen atmosphere at a predetermined baking temperature for a predetermined time. This bakes the base electrode layer 31 onto the laminate 2. The laminate baking process and the base electrode layer baking process may be performed simultaneously after the material for the base electrode layer 31 has been placed on the laminate chip. Note that voids 53 are formed in the base electrode layer 31 as the solvent and the like in the conductive paste disappear during baking.

[0066] (Pressing Process) Here, the outer surface of the first base electrode layer 31A is pressed by a pressing member. The pressing member is, for example, a metal plate. The pressing member is formed of a material harder than the first base electrode layer 31A, preferably harder than Cu. This smooths the outer surface of the first base electrode layer 31A. The first base electrode end surface region 31Ac is pressed by the pressing member more intensively than the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab. The first base electrode corner region 31Ad is pressed by the pressing member more intensively than the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab.

[0067] This allows the outer surfaces of the first base electrode end surface region 31Ac and the first base electrode corner region 31Ad to be smoother than the outer surfaces of the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab, and the hardness of the outer surfaces of the first base electrode end surface region 31Ac and the first base electrode corner region 31Ad can be made higher than the hardness of the outer surfaces of the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab.

[0068] (Plating Process) Next, a first lower plating layer 33A is formed on the outer surface of the first base electrode layer 31A. Next, a first upper plating layer 34A is formed on the outer surface of the first lower plating layer 33A. The first lower plating layer 33A is formed, for example, by Ni plating. The first upper plating layer 34A is formed, for example, by Sn plating. The first lower plating layer 33A and the first upper plating layer 34A are formed sequentially, for example, by electrolytic plating. As a result, first external electrodes 3A are formed on the first end faces CA, respectively.

[0069] The thickness of the first lower plating layer 33A is relatively small. Therefore, the shape of the outer surface of the first lower plating layer 33A is substantially the same as the shape of the outer surface of the first base electrode layer 31A. Therefore, the outer surfaces of the first lower plating end face region 33Ac and the first lower plating corner region 33Ad are smoother than the outer surfaces of the first lower plating main surface region 33Aa and the first lower plating side surface region 33Ab.

[0070] The thickness of the first upper plating layer 34A is relatively small. Therefore, the shape of the outer surface of the first upper plating layer 34A is substantially the same as the shapes of the outer surfaces of the first base electrode layer 31A and the first lower plating layer 33A. Therefore, the outer surfaces of the first external electrode end surface region 3Ac and the first external electrode corner region 3Ad are smoother than the outer surfaces of the first external electrode main surface region 3Aa and the first external electrode side surface region 3Ab.

[0071] The pressing step and plating step are also performed on the second base electrode layer 31B in the same manner.

[0072] As a result of the above, the multilayer ceramic capacitor 1 shown in FIG. 1 is obtained.

[0073] (Effects of First Embodiment) According to this embodiment, the following effects can be obtained.

[0074] According to this embodiment, the outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode main surface region 31Aa.

[0075] According to this configuration, the outer surface of the region on the end face of the first external electrode 3A can be made smooth, thereby enabling the solder to wet and rise smoothly onto the region on the end face of the first external electrode 3A.

[0076] Furthermore, the outer surface of the region on the first main surface AA of the first external electrode 3A can be roughened, which creates an anchor effect between the solder and the portion of the first external electrode 3A facing the substrate, thereby improving the bond between the solder and the multilayer ceramic capacitor 1.

[0077] Therefore, it is possible to provide a highly reliable multilayer ceramic capacitor.

[0078] According to this embodiment, the outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode side surface region 31Ab.

[0079] With this configuration, the outer surface of the region on the first side face BA of the first external electrode 3A can be made relatively rough, which can generate an anchor effect between the region on the first side face BA of the first external electrode 3A and the solder, thereby improving the bond between the solder and the multilayer ceramic capacitor 1.

[0080] According to this embodiment, the region of the outer surface of the first base electrode end surface region 31Ac that faces the first plating layer 32A is smoother than both the region of the outer surface of the first base electrode main surface region 31Aa that faces the first plating layer 32A and the region of the outer surface of the first base electrode side surface region 31Ab that faces the first plating layer 32A.

[0081] With this configuration, the shape of the outer surface of the first base electrode layer 31A is reflected on the outer surface of the first plating layer 32A. Therefore, in a configuration in which the first plating layer 32A is provided on the first base electrode layer 31A, it is possible to improve the wetting of the solder onto the region on the first end face CA of the first external electrode 3A and to generate an anchor effect between the first external electrode 3A and the solder.

[0082] According to this embodiment, the outer surface of the first lower plated end surface region 33Ac is smoother than the outer surface of the first lower plated main surface region 33Aa.

[0083] With this configuration, the shapes of the outer surfaces of the first base electrode layer 31A and the first lower plating layer 33A are reflected in the outer surface of the first upper plating layer 34A. Therefore, in a configuration in which the first lower plating layer 33A and the first upper plating layer 34A are provided on the first base electrode layer 31A, it is possible to improve the wetting of the solder onto the region on the first end face CA of the first external electrode 3A and to generate an anchor effect between the first external electrode 3A and the solder.

[0084] According to this embodiment, the outer surface of the first lower plated end surface region 33Ac is smoother than the outer surface of the first lower plated side surface region 33Ab.

[0085] With this configuration, the shapes of the outer surfaces of the first base electrode layer 31A and the first lower plating layer 33A are reflected in the outer surface of the first upper plating layer 34A. Therefore, in a configuration in which the first lower plating layer 33A and the first upper plating layer 34A are provided on the first base electrode layer 31A, the solder can be smoothly wetted onto the region on the first end face CA of the first external electrode 3A, and the anchor effect between the first external electrode 3A and the solder can be generated over a wider range.

[0086] According to this embodiment, the surface roughness of the outer surface of the first lower plated end surface region 33Ac is greater than 0 μm and less than 0.1 μm, and the surface roughness of the outer surface of the first lower plated main surface region 33Aa and the surface roughness of the outer surface of the first lower plated side surface region 33Ab are each greater than 0.1 μm and less than 0.4 μm.

[0087] This configuration more reliably improves the wetting of the solder onto the area on the first end face CA of the first external electrode 3A, and also generates an anchor effect between the first external electrode 3A and the solder.

[0088] According to this embodiment, the outer surface of the first base electrode corner region 31Ad is smoother than both the outer surface of the first base electrode main surface region 31Aa and the outer surface of the first base electrode side surface region 31Ab.

[0089] This configuration makes it possible to smooth the outer surface of the region of the first external electrode 3A between the region facing the substrate and the region on the first end face CA, thereby improving the wetting of the solder onto the region on the first end face CA of the first external electrode 3A.

[0090] Furthermore, the outer surface of the region on the first main surface AA of the first external electrode 3A can be roughened, which creates an anchor effect between the solder and the portion of the first external electrode 3A facing the substrate, thereby improving the bond between the solder and the multilayer ceramic capacitor 1.

[0091] According to this embodiment, the outer surface of the first lower plated corner region 33Ad is smoother than both the outer surface of the first lower plated main surface region 33Aa and the outer surface of the first lower plated side surface region 33Ab.

[0092] With this configuration, the shape of the outer surface of the first base electrode layer 31A is reflected on the outer surface of the first plating layer 32A. Therefore, in a configuration in which the first plating layer 32A is provided on the first base electrode layer 31A, it is possible to improve the wetting of the solder onto the region on the first end face CA of the first external electrode 3A and to generate an anchor effect between the first external electrode 3A and the solder.

[0093] According to this embodiment, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, the ratio of the length of the line along the outer surface of the first base electrode end surface region 31Ac to the length of the line along the first end surface CA is smaller than the ratio of the length of the line along the outer surface of the first base electrode main surface region 31Aa to the length of the line along the portion of the first main surface AA where the first base electrode layer 31A is arranged.

[0094] This configuration improves the wetting of the solder onto the region on the first end face CA of the first external electrode 3A, and also generates an anchor effect between the first external electrode 3A and the solder, thereby providing a highly reliable multilayer ceramic capacitor 1.

[0095] According to this embodiment, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, if the ratio of the length of the line along the surface of the first base electrode end surface region 31Ac to the length of the line along the first end surface CA is A1, and the ratio of the length along the outer surface of the first base electrode main surface region 31Aa to the length of the line along the portion of the first main surface AA that contacts the first base electrode main surface region 31Aa is B1, the relationship between A1 and B1 satisfies 0.5 <= A1 / B1 < 1.

[0096] This configuration more reliably improves the wetting of the solder onto the area on the first end face CA of the first external electrode 3A, and also generates an anchor effect between the first external electrode 3A and the solder.

[0097] According to this embodiment, the hardness Hv of the first base electrode end surface region 31Ac is higher than both the hardness Hv of the first base electrode main surface region 31Aa and the hardness Hv of the first base electrode side surface region 31Ab.

[0098] The higher the hardness of the first base electrode layer 31A, the denser the first base electrode layer 31A can be, and therefore, the more effectively water permeation into the first base electrode layer 31A can be suppressed. With this configuration, the hardness Hv of the first base electrode end surface region 31Ac can be increased, and therefore, water can be suppressed from penetrating into the stack 2 through the first end surface CA.

[0099] Furthermore, the lower the hardness Hv of the first base electrode layer 31A, the more the clamping of the laminate 2 can be suppressed, and therefore the occurrence of cracks in the laminate 2 can be suppressed.

[0100] Therefore, it is possible to provide a multilayer ceramic capacitor 1 with excellent reliability.

[0101] According to this embodiment, the hardness Hv of the first base electrode end surface region 31Ac is 100 or more and 200 or less.

[0102] According to this configuration, the first base electrode layer 31A can be made dense, and therefore, the intrusion of water into the first end face CA can be more reliably suppressed.

[0103] According to this configuration, the lower the hardness of the base electrode layer 31, the weaker the clamping force of the base electrode layer 31 on the laminate 2. This makes it possible to suppress the clamping force of the first base electrode main surface region 31Aa on the laminate 2, thereby suppressing the occurrence of cracks in the laminate 2 due to stress.

[0104] According to this embodiment, the hardness Hv of the corner regions of the first base electrode is higher than both the hardness Hv of the main surface region of the first base electrode and the hardness Hv of the side region of the first base electrode.

[0105] According to this configuration, by increasing the hardness and density of the first base electrode corner regions 31Ad, it is possible to suppress the penetration of water into the laminate 2 through the ridge portions of the laminate 2. Furthermore, since the hardness of the first base electrode main surface regions 31Aa and the first base electrode side surface regions 31Ab can be reduced, it is possible to suppress the clamping of the laminate 2 by the first base electrode main surface regions 31Aa and the first base electrode side surface regions 31Ab.

[0106] Second Embodiment Next, a multilayer ceramic capacitor 1 according to a second embodiment of the present invention will be described with reference to Figures 5 to 9. The following description will focus on differences from the first embodiment, and the same components as those in the first embodiment will be given the same reference numerals and description thereof will be omitted. The cross section in Figure 6 is an LT cross section passing through the center of the multilayer ceramic capacitor 1 in the width direction W.

[0107] 5 to 9 , in the second embodiment, the surface of the first plating layer 32A (more specifically, the surface of the first upper plating layer 34A) is provided with a plurality of recessed portions 55 recessed from the surface of the first plating layer 32A toward the laminate 2, and a recessed region 58 which is an area consisting of adjacent recessed portions 55. The surface of the first base electrode layer 31A is provided with a plurality of recessed portions 54 and a recessed region 58 which is an area consisting of adjacent recessed portions 54. The recessed portions 55 and recessed regions 58 of the first plating layer 32A are formed by recessing the first plating layer 32A (more specifically, the first lower plating layer 33A and the first upper plating layer 34A) to match the shapes of the recessed portions 54 and recessed regions 58 of the first base electrode layer 31A.

[0108] The first plated end surface region 32Ac has a plurality of recessed portions 55 and recessed regions 58. The first plated main surface region 32Aa does not have any recessed portions 55 or recessed regions 58. The second plated side surface region Ab does not have any recessed portions 55 or recessed regions 58.

[0109] The total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating end surface region 32Ac is greater than both the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating main surface region 32Aa and the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating side surface region 32Ab. The number of recessed portions 55 provided in the first plating end surface region 32Ac is greater than both the number of recessed portions 55 provided in the first plating main surface region 32Aa and the number of recessed portions 55 provided in the first plating side surface region 32Ab.

[0110] The first plating corner region 32Ad is provided with a plurality of recessed portions 55 and recessed regions 58 .

[0111] The total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating corner region 32Ad is greater than both the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating main surface region 32Aa and the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating side surface region 32Ab. The number of recessed portions 55 provided in the first plating corner region 32Ad is greater than both the number of recessed portions 55 provided in the first plating main surface region 32Aa and the number of recessed portions 55 provided in the first plating side surface region 32Ab.

[0112] The areas of the recessed portions 55 and the recessed regions 58 are measured by acquiring images of the object to be measured using a laser microscope and analyzing the acquired images using analysis software. Next, the areas of the recessed portions 55 are summed for the first plated end surface region 32Ac, the first plated main surface region 32Aa, the first plated side surface region 32Ab, and the first plated corner region 32Ad. The image capturing direction of the first plated end surface region 32Ac is the length direction L. The image capturing direction of the first plated main surface region 32Aa is the stacking direction T. The image capturing direction of the first plated side surface region 32Ab is the width direction W. The photographing direction of the first plating corner region 32Ad is the direction in which a straight line passing through the intersection of the tangent to the first end face CA parallel to the stacking direction T and the tangent to the first main face AA parallel to the length direction L, and the intersection of the tangent to the second end face CB parallel to the stacking direction T and the tangent to the second main face AB parallel to the length direction L extends.

[0113] When viewed in the recessed direction of the recessed portion 55 (more specifically, in the length direction L), the recessed portion 55 has, for example, a circular shape or a partially missing circular shape. A portion of the opening periphery of the recessed portion 55 has an arc shape. The opening periphery of the recessed portion 55 has, for example, an annular shape. The radius of the annulus including the arc formed by the opening periphery of the recessed portion 55 (in other words, the radius of curvature of the arc) is 5 μm or more, and preferably 5 μm or more and 100 μm or less. The radius of the annulus formed by the opening periphery of the recessed portion 55 is 5 μm or more, and preferably 5 μm or more and 100 μm or less.

[0114] The shape of the inner circumferential surface of the recessed portion 55 in a cross section extending in the recessed direction of the recessed portion 55 is arc-shaped.

[0115] In addition, the "cross section of the recessed portion 55 extending in the direction in which the recessed portion 55 is recessed" is, for example, an LT cross section when the recessed portion 55 is formed in the first base electrode end surface region 31Ac, and is, for example, a WT cross section when the recessed portion 55 is formed in any of the first base electrode main surface region 31Aa, the first base electrode side surface region 31Ab, and the first base electrode corner region 31Ad.

[0116] The first plating corner region 32Ad is provided with a plurality of recessed portions 55 and recessed regions 58 .

[0117] (Glass 52 Coated with Metal Thin Film 56) As shown in Figure 9, the first base electrode layer 31A includes a plurality of glass particles 52 in the form of particles. The first base electrode layer 31A has a metal thin film 56, which is a region containing a conductive metal and has a thickness of 1 µm or less, located between the glass 52 and the first plating layer 32A (more specifically, the first lower plating layer 33A). In other words, the portion of the glass 52 facing the first plating layer 32A is coated with the metal thin film 56, which contains a metal and is formed in a thin film shape. The thickness of the metal thin film 56 refers to the shortest distance between the portion of the metal thin film 56 in contact with the glass 52 and the portion in contact with the first plating layer 32A.

[0118] The conductive metal with the highest content rate among the conductive metals contained in the first base electrode layer 31A is, for example, Cu. The metal thin film 56 contains the conductive metal with the highest content rate among the conductive metals contained in the first base electrode layer 31A, specifically, Cu.

[0119] The glass 52 covered with the metal thin film 56 is exposed on the outer surface of the first base electrode layer 31A. The glass 52 covered with the metal thin film 56 is in contact with the first lower plating layer 33A.

[0120] The first base electrode end surface region 31Ac includes glass 52 covered with a metal thin film 56. The glass 52 covered with the metal thin film 56 is exposed on the outer surface of the first base electrode end surface region 31Ac. The glass 52 covered with the metal thin film 56 is in contact with the first lower plating end surface region 33Ac.

[0121] The first base electrode corner region 31Ad includes glass 52 coated with a metal thin film 56. The glass 52 coated with the metal thin film 56 is exposed on the outer surface of the first base electrode corner region 31Ad. The glass 52 coated with the metal thin film 56 is in contact with the first lower plating corner region 33Ad.

[0122] (Method for Manufacturing Multilayer Ceramic Capacitor 1) Next, a method for manufacturing the multilayer ceramic capacitor 1 of the second embodiment will be described. Differences from the method for manufacturing the multilayer ceramic capacitor 1 of the first embodiment will be described.

[0123] In the second embodiment, in the pressing step, the pressing member has a curved surface. When the outer surface of the first base electrode layer 31A is pressed by the pressing member, a substantially hemispherical depression is formed in the outer surface of the first base electrode layer 31A. As a result, a depression portion 54 is formed in the outer surface of the first base electrode layer 31A. When a position of the first base electrode layer 31A overlapping with the depression portion 54 is pressed by the pressing member, a depression region is formed in the first base electrode layer 31A. The first base electrode end surface region 31Ac is pressed by a larger number of pressing members than the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab. The first base electrode corner region 31Ad is pressed by a larger number of pressing members than the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab. As a result, a larger number of recesses 54 are formed on the outer surface of the first base electrode end surface region 31Ac and the outer surface of the first base electrode corner region 31Ad than on the outer surface of the first base electrode main surface region 31Aa and the outer surface of the first base electrode side surface region 31Ab.

[0124] The first base electrode layer 31A is pressed and compacted by a pressing member, so that the hardness of the first base electrode end surface region 31Ac is higher than the hardness of the first base electrode main surface region 31Aa.

[0125] Furthermore, when the first base electrode layer 31A is pressed by the pressing member, the first base electrode layer 31A is compressed. As a result, the region of the first base electrode layer 31A between the glass 52 and the first plating layer 32A is formed into a thin film. When the first base electrode layer 31A is pressed by the pressing member, the conductive metal in the first base electrode layer 31A is rolled, so that the conductive metal present near the glass 52 extends into the region between the glass 52 and the first plating layer 32A. Therefore, the mass ratio of the conductive metal to the dielectric component in the metal thin film 56 is greater than the mass ratio of the conductive metal to the dielectric component in the metal thin film 56 in the portion of the first base electrode layer 31A excluding the metal thin film 56. As a result, the metal thin film 56 is formed between the glass 52 and the first plating layer 32A.

[0126] When the first base electrode layer 31A is pressed by the pressing member, there is a risk that the glass 52 will be exposed on the outer surface of the first base electrode layer 31A. However, by forming the metal thin film 56 between the glass 52 and the first plating layer 32A, it is possible to prevent the glass 52 from being exposed.

[0127] Next, when the plating step is performed, the outer surfaces of the first lower plating layer 33A and the first upper plating layer 34A each reflect the shape of the outer surface of the first base electrode layer 31A. A recessed portion 55 and a recessed region 58 are formed on the outer surface of the first plating layer 32A (more specifically, the outer surface of the first upper plating layer 34A).

[0128] (Effects of Second Embodiment) According to this embodiment, the following effects can be obtained.

[0129] According to this embodiment, the surface of the first plating layer 32A is provided with a plurality of recesses 54 that are recessed from the surface of the first plating layer 32A toward the laminate 2, and recess regions 58 that are regions consisting of adjacent recesses 54.

[0130] With this configuration, it is possible to form the recessed portion 55 and recessed region 58 on the outer surface of the first external electrode 3A. The recessed portion 55 and recessed region 58 on the first external electrode 3A can trap the solder, thereby increasing the adhesive strength between the first external electrode 3A and the solder during mounting.

[0131] Therefore, it is possible to provide a multilayer ceramic capacitor 1 with excellent reliability.

[0132] According to this embodiment, the sum of the areas of the recessed portions 55 and the recessed regions 58 in the first plated end surface region 32Ac is larger than both the sum of the areas of the recessed portions 55 and the recessed regions 58 in the first plated main surface region 32Aa and the sum of the areas of the recessed portions 55 and the recessed regions 58 in the first plated side surface region 32Ab.

[0133] With this configuration, the recessed portion 55 and the recessed region 58 can be formed over a wider area in the first plated end surface region 32Ac, thereby increasing the adhesive strength between the first plated end surface region 32Ac and the solder during mounting.

[0134] The recessed portion 55 is formed by pressing the first external electrode 3A with a pressing member. As a result, the recessed portion 55 in the first base electrode layer 31A and the region between the recessed portion 55 and the laminate 2 are compacted and densified. When the first base electrode layer 31A is densely formed, water is less likely to permeate through the first base electrode layer 31A.

[0135] With this configuration, the recessed portions 55 and recessed regions 58 can be provided over a wider area in the first plating end surface region 32Ac, which allows the first base electrode layer 31A to be compacted over a wider area, thereby more reliably preventing water from penetrating into the stack 2 through the first end surface CA.

[0136] According to this configuration, the area in which the recessed portions 55 and recessed regions 58 are formed in the first plating main surface region 32Aa and the area in which the recessed portions 55 and recessed regions 58 are formed in the first plating side surface region 32Ab can be reduced. This reduces the compacted area in the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab. This prevents the laminate 2 from being clamped by the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab. This prevents cracks from occurring in the laminate 2 due to stress.

[0137] According to this embodiment, in the first plating end surface region 32Ac, a portion of the opening periphery of the recessed portion 55 is arc-shaped.

[0138] According to this configuration, the recessed portion 55 can suitably trap the solder, thereby improving the adhesive strength between the first external electrode 3A and the solder during mounting.

[0139] According to this embodiment, in the first plated end surface region 32Ac, the radius of curvature of the arc formed by the opening periphery of the recess 55 is 5 μm or more, and preferably 5 μm or more and 100 μm or less.

[0140] With this configuration, the recessed portion 55 can trap the solder more effectively, and the adhesive strength between the first external electrode 3A and the solder during mounting can be further improved.

[0141] According to this embodiment, the first plating corner region 32Ad is provided with a recessed portion 55 and a recessed region 58 .

[0142] This configuration can increase the adhesive strength between the first plated corner region 32Ad and the solder during mounting.

[0143] Furthermore, the portions of the first base electrode layer 31A that overlap with the first plated principal surface region 32Aa and the first plated side surface region 32Ab can prevent the laminate 2 from being tightened, thereby preventing cracks from occurring in the laminate 2 due to stress.

[0144] According to this embodiment, the first plating layer 32A has a first lower plating layer 33A in contact with the first base electrode layer 31A, and the first lower plating layer 33A is a Ni plating layer.

[0145] This configuration can prevent the multilayer ceramic capacitor 1 from being corroded by solder during mounting. The provision of the recessed portion 55 on the outer surface of the first base electrode layer 31A allows the Ni plating layer to adhere more reliably to the first base electrode layer 31A, thereby more reliably preventing the multilayer ceramic capacitor 1 from being corroded by solder.

[0146] According to this embodiment, the first base electrode layer 31A has a metal thin film 56, which is a region between the glass 52 and the first plating layer 32A and contains the conductive metal and has a thickness of 1 μm or less. The first base electrode layer 31A contains a conductive metal and glass 52, and the glass 52 is coated with the metal thin film 56, which is a thin film of metal.

[0147] The glass 52 included in the first base electrode layer 31A may be exposed on the surface of the first base electrode layer 31A. In such cases, plating is difficult to form on the glass 52, and when attempting to form a plating layer on the first base electrode layer 31A, the plating may not adhere well to the first base electrode layer 31A. According to this configuration, the glass 52 is coated with a thin metal film 56, which is a thin metal film. The thin metal film 56 contains a metal component, allowing plating to adhere well. Therefore, plating can be adhered well to the glass 52 coated with the thin metal film 56. This makes it easier to form a continuous plating layer on the first base electrode layer 31A. Therefore, corrosion of the multilayer ceramic capacitor 1 by solder during mounting and penetration of water into the laminate 2 can be effectively suppressed.

[0148] According to this embodiment, the metal thin film 56 contains the conductive metal with the highest content of the conductive metals contained in the first base electrode layer 31A.

[0149] With this configuration, the glass 52 coated with the metal thin film 56 can be easily obtained.

[0150] According to this embodiment, the first base electrode end surface region 31Ac includes the glass 52 covered with the metal thin film 56.

[0151] This configuration makes it easier to form a continuous plating layer on the first base electrode end surface region 31Ac, thereby effectively preventing the multilayer ceramic capacitor 1 from being corroded by solder during mounting, and preventing water from entering the laminate 2.

[0152] According to this embodiment, the first base electrode corner region 31Ad includes glass 52 covered with a metal thin film 56.

[0153] The first base electrode corner region 31Ad is difficult to plate because the thickness of the first base electrode layer 31A is relatively thin. With this configuration, it is possible to easily form a continuous plating layer on the first base electrode corner region 31Ad.

[0154] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0155] The configuration of the multilayer ceramic capacitor 1 is not limited to the configuration shown in FIGS. 1 to 12 . For example, the multilayer ceramic capacitor may be a three-terminal type having a pair of external electrodes arranged on each end face and a pair of external electrodes arranged on each side face. In this case, the external electrodes arranged on each side face extend, for example, not only on each side face but also on each main face. The external electrodes arranged on each side face have a base electrode layer and a plating layer (e.g., a lower plating layer and an upper plating layer), similar to the external electrode 3 of the above embodiment.

[0156] In a three-terminal multilayer ceramic capacitor, the external electrodes arranged in pairs on each end face have the same configuration as the external electrodes 3 in each of the above embodiments, thereby achieving the desired effect.

[0157] Furthermore, by configuring the external electrodes arranged on each side surface to correspond to the configuration of the external electrodes arranged on the end faces in the above-described embodiments, the external electrodes arranged on each side surface can achieve the same effects as those of the above-described embodiments. For example, by smoothing the surface roughness or increasing the number of depressions in the portions of the base electrode layer or plating layer arranged on each side surface that overlap with the side surface in the width direction, it is possible to improve solder wetting. By increasing the hardness in the portions of the base electrode layer arranged on each side surface that overlap with the side surface in the width direction, it is possible to improve moisture resistance reliability. By decreasing the hardness in the portions of the base electrode layer or plating layer arranged on each side surface that overlap with the main surface in the stacking direction, it is possible to suppress clamping of the laminate.

[0158] In the pressing step, it is not essential that the external electrodes arranged on each side surface are pressed by the pressing member.

[0159] In the second embodiment, the recessed portion 55 and the recessed region 58 are provided only in the first plated end surface region 32Ac and the first plated corner region 32Ad, but this is not limiting. The recessed portion 55 and the recessed region 58 may be provided in the first plated main surface region 32Aa or the second plated side surface region Ab.

[0160] However, the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating end surface region 32Ac is preferably greater than both the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating main surface region 32Aa and the total area of ​​the recessed portions 55 and the recessed regions 58 in the first plating side surface region 32Ab. The number of recessed portions 55 provided in the first plating end surface region 32Ac is preferably greater than both the number of recessed portions 55 provided in the first plating main surface region 32Aa and the number of recessed portions 55 provided in the first plating side surface region 32Ab.

[0161] In addition, within the scope of the spirit of the present invention, it is possible to replace the components in each of the above embodiments with well-known components as appropriate, and the above embodiments may be combined as appropriate.

[0162] For example, the multilayer ceramic capacitor 1 of the first embodiment may further have the configuration of the multilayer ceramic capacitor 1 of the second embodiment. The multilayer ceramic capacitor 1 of the second embodiment may further have the configuration of the multilayer ceramic capacitor 1 of the first embodiment. The multilayer ceramic capacitor may include at least a portion of the configuration of the multilayer ceramic capacitor 1 of the first embodiment and at least a portion of the configuration of the multilayer ceramic capacitor 1 of the second embodiment. For example, in the multilayer ceramic capacitor 1 of the first embodiment, recesses 55 may be provided in the external electrodes 3, and a metal thin film 56 may be provided between the glass 52 and the first plating layer 32A.

[0163] More specifically, in the multilayer ceramic capacitor 1, the outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode main surface region 31Aa, and in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, the ratio of the length of a line along the outer surface of the first base electrode end surface region 31Ac to the length of a line along the first end surface CA is smaller than the ratio of the length of a line along the outer surface of the first base electrode main surface region 31Aa to the length of a line along the portion of the first main surface AA where the first base electrode layer 31A is arranged. The hardness Hv of the first base electrode end surface region 31Ac is higher than the hardness Hv of both the first base electrode main surface region 31Aa and the first base electrode side surface region 31Ab, the surface of the first plating layer 32A is provided with a plurality of recesses 54 recessed from the surface of the first plating layer 32A toward the laminate 2 and recess regions 58 each consisting of adjacent recesses 54, and the first base electrode layer 31A has a metal thin film 56 between the glass 52 and the first plating layer 32A, the metal thin film 56 being a region containing the conductive metal and having a thickness of 1 μm or less. The first base electrode layer 31A includes a conductive metal and glass 52, and the glass 52 may be covered with the metal thin film 56, which is a thin film of metal.

[0164] The multilayer ceramic capacitor 1 is configured such that the outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode main surface region 31Aa, and in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, the ratio of the length of a line along the outer surface of the first base electrode end surface region 31Ac to the length of a line along the first end surface CA is smaller than the ratio of the length of a line along the outer surface of the first base electrode main surface region 31Aa to the length of a line along the portion of the first main surface AA where the first base electrode layer 31A is arranged, and the hardness Hv of region 31Ac is higher than the hardness Hv of both first base electrode main surface region 31Aa and first base electrode side surface region 31Ab, and the surface of first plating layer 32A is provided with a plurality of recesses 54 recessed from the surface of first plating layer 32A toward laminate 2, and recessed regions 58 each consisting of adjacent recesses 54; and first base electrode layer 31A has metal thin film 56, which is a region between glass 52 and first plating layer 32A and contains the conductive metal and has a thickness of 1 μm or less. First base electrode layer 31A includes conductive metal and glass 52, and glass 52 is covered with metal thin film 56, which is a thin film of metal.

[0165] Furthermore, in the multilayer ceramic capacitor 1, the outer surface of the first base electrode end surface region 31Ac may be smoother than the outer surface of the first base electrode main surface region 31Aa, and the hardness Hv of the first base electrode end surface region 31Ac may be higher than both the hardness Hv of the first base electrode main surface region 31Aa and the hardness Hv of the first base electrode side surface region 31Ab.

[0166] In the multilayer ceramic capacitor 1, the outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode main surface region 31Aa, and the surface of the first plating layer 32A may be provided with a plurality of recesses 54 that are recessed from the surface of the first plating layer 32A toward the laminate 2, and a recess region 58 that is a region consisting of adjacent recesses 54.

[0167] In the multilayer ceramic capacitor 1, the outer surface of the first base electrode end surface region 31Ac is smoother than the outer surface of the first base electrode main surface region 31Aa, and the first base electrode layer 31A has a metal thin film 56 that is a region between the glass 52 and the first plating layer 32A and contains the conductive metal and has a thickness of 1 μm or less. The first base electrode layer 31A includes a conductive metal and glass 52, and the glass 52 may be covered with the metal thin film 56 that is a thin film of metal.

[0168] In the multilayer ceramic capacitor 1, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, the ratio of the length of a line along the outer surface of the first base electrode end surface region 31Ac to the length of a line along the first end face CA is smaller than the ratio of the length of a line along the outer surface of the first base electrode main surface region 31Aa to the length of a line along the portion of the first main surface AA where the first base electrode layer 31A is arranged, and the hardness Hv of the first base electrode end surface region 31Ac may be higher than both the hardness Hv of the first base electrode main surface region 31Aa and the hardness Hv of the first base electrode side surface region 31Ab.

[0169] In the multilayer ceramic capacitor 1, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, the ratio of the length of a line along the outer surface of the first base electrode end face region 31Ac to the length of a line along the first end face CA is smaller than the ratio of the length of a line along the outer surface of the first base electrode main face region 31Aa to the length of a line along the portion of the first main face AA where the first base electrode layer 31A is arranged, and the surface of the first plating layer 32A may be provided with a plurality of recesses 54 that are recessed from the surface of the first plating layer 32A toward the laminate 2, and a recess region 58 that is a region consisting of adjacent recesses 54.

[0170] In the multilayer ceramic capacitor 1, in a cross section extending parallel to the stacking direction T and the length direction L and passing through the center of the width direction W of the laminate 2, the ratio of the length of a line along the outer surface of the first base electrode end face region 31Ac to the length of a line along the first end face CA is smaller than the ratio of the length of a line along the outer surface of the first base electrode main face region 31Aa to the length of a line along the portion of the first main face AA where the first base electrode layer 31A is arranged, and the first base electrode layer 31A has a metal thin film 56 that is a region between the glass 52 and the first plating layer 32A and contains the conductive metal and has a thickness of 1 μm or less. The first base electrode layer 31A includes a conductive metal and glass 52, and the glass 52 may be covered with the metal thin film 56, which is a thin metal film.

[0171] The present invention also includes the following combinations:

[0172] <1> A multilayer ceramic capacitor comprising: a laminate having a plurality of stacked dielectric layers and a plurality of internal electrodes, the laminate having first and second main surfaces opposing each other in a stacking direction, first and second side surfaces opposing each other in a width direction perpendicular to the stacking direction, and first and second end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first external electrode provided on the first end surface and connected to the internal electrode; and a second external electrode provided on the second end surface and connected to the internal electrode, wherein the first external electrode has a first base electrode layer connected to the internal electrode and including a conductive metal and glass, and a first plating layer disposed on the first base electrode layer, and the surface of the first plating layer is provided with a plurality of recessed portions recessed from the surface of the first plating layer toward the laminate, and a recessed region which is a region consisting of adjacent recessed portions.

[0173] <2> The multilayer ceramic capacitor according to <1>, having an end surface region, a first plated main surface region that is a region overlapping with the first main surface when viewed in the stacking direction, and a first plated side surface region that is a region overlapping with the first side surface when viewed in the width direction, wherein the sum of the area of ​​the recessed portion and the area of ​​the recessed region in the first plated end surface region is larger than both the sum of the area of ​​the recessed portion and the area of ​​the recessed region in the first plated main surface region and the sum of the area of ​​the recessed portion and the area of ​​the recessed region in the first plated side surface region.

[0174] <3> The multilayer ceramic capacitor according to <1> or <2>, wherein in the first plated end face region, a portion of the periphery of the opening of the recess is arc-shaped.

[0175] <4> The multilayer ceramic capacitor according to <3>, wherein in the first plated end face region, the radius of curvature of the arc formed by the opening periphery of the recess is 5 μm or more and 100 μm or less.

[0176] <5> The multilayer ceramic capacitor according to any one of <1> to <4>, wherein the first plating layer has a first plating end surface region that is a region overlapping with the first end surface when viewed in the length direction, a first plating main surface region that is a region overlapping with the first main surface when viewed in the stacking direction, a first plating side surface region that is a region overlapping with the first side surface when viewed in the width direction, and a first plating corner region that is a region connecting at least one of the first plating side surface region and the first plating main surface region to the first plating end surface region, and the first plating corner region is provided with the recessed portion and the recessed region.

[0177] <6> The multilayer ceramic capacitor according to <5>, wherein a total value of an area of ​​the recessed portion and an area of ​​the recessed region in the first plating corner region is larger than both a total value of an area of ​​the recessed portion and an area of ​​the recessed region in the first plating main surface region and a total value of an area of ​​the recessed portion and an area of ​​the recessed region in the first plating side surface region.

[0178] <7> The multilayer ceramic capacitor according to any one of <1> to <6>, wherein the first plating layer has a first lower plating layer in contact with the first base electrode layer, and the first lower plating layer is a Ni plating layer.

[0179] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 2 Laminate 3A First external electrode 3B Second external electrode 14 Dielectric layer 15 Internal electrode 15a Opposing portion 15b Lead portion 31A First base electrode layer 31Aa First base electrode main surface region 31Ab First base electrode side region 31Ac First base electrode end surface region 31Ad First base electrode corner region 32A First plating layer 32Aa First plating main surface region 32Ab First plating side region 32Ac First plating end surface region 32Ad First plating corner region 33A Lower plating layer 33Aa First lower plating main surface region 33Ab First lower plating side region 33Ac First lower plating end surface region 33Ad First lower plating corner region 34A First upper plating layer 52 Glass 55 Recessed portion 56 Metal thin film (conductive metal) 57 Recessed region AA First main surface AB Second main surface BA First side surface BB Second side surface CA First end surface CB Second end surface

Claims

1. A multilayer ceramic capacitor comprising: a laminate having a plurality of laminated dielectric layers and a plurality of internal electrodes, the laminate having first and second main surfaces opposing each other in the lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; a first external electrode provided on the first end surface and connected to the internal electrode; and a second external electrode provided on the second end surface and connected to the internal electrode; wherein the first external electrode has a first base electrode layer connected to the internal electrode and including a conductive metal and glass, and a first plating layer disposed on the first base electrode layer; and the surface of the first plating layer is provided with a plurality of recesses recessed from the surface of the first plating layer toward the laminate, and a recess region which is an area consisting of adjacent recesses.

2. The multilayer ceramic capacitor according to claim 1, wherein the first plating layer has a first plating end face region that is a region overlapping with the first end face when viewed in the length direction, a first plating main face region that is a region overlapping with the first main face when viewed in the stacking direction, and a first plating side face region that is a region overlapping with the first side face when viewed in the width direction, and the sum of the area of ​​the recessed portion and the area of ​​the recessed region in the first plating end face region is larger than both the sum of the area of ​​the recessed portion and the area of ​​the recessed region in the first plating main face region and the sum of the area of ​​the recessed portion and the area of ​​the recessed region in the first plating side face region.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein a portion of the periphery of the opening of the recess in the first plated end face region is arc-shaped.

4. The multilayer ceramic capacitor according to claim 3, wherein the radius of curvature of the arc formed by the opening periphery of the recess in the first plated end face region is 5 μm or more and 100 μm or less.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein the first plating layer has a first plating end face region that is a region overlapping with the first end face when viewed in the length direction, a first plating main face region that is a region overlapping with the first main face when viewed in the stacking direction, a first plating side face region that is a region overlapping with the first side face when viewed in the width direction, and a first plating corner region that is a region connecting at least one of the first plating side face region and the first plating main face region to the first plating end face region, and the first plating corner region is provided with the recessed portion and the recessed region.

6. The multilayer ceramic capacitor according to claim 5, wherein the sum of the areas of the recessed portions and the recessed regions in the first plating corner region is greater than both the sum of the areas of the recessed portions and the recessed regions in the first plating main surface region and the sum of the areas of the recessed portions and the recessed regions in the first plating side surface region.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein the first plating layer has a first lower plating layer in contact with the first base electrode layer, and the first lower plating layer is a Ni plating layer.

Images