Semiconductor device

Abstract

This semiconductor device comprises: a first insulating layer 26 provided on a nitride semiconductor layer 10b; a source electrode 12 and a drain electrode 14 provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode 16 provided between the source electrode and the drain electrode on the nitride semiconductor layer. The drain electrode has a first portion close to the gate electrode and the source electrode has a second portion close to the gate electrode, and of these portions, only the first portion of the drain electrode, which is close to the gate electrode is provided on the first insulating layer.　

Description

Semiconductor Devices

[0001] This application claims priority to Japanese Patent Application No. 2024-013076, filed on January 31, 2024, and incorporates by reference all of the contents of said Japanese application.

[0002] Transistors using nitride semiconductors, such as GaN-HEMTs (Gallium Nitride High Electron Mobility Transistors), are known (see, for example, Patent Document 1).It is also known that a portion of a gate electrode close to a drain electrode is elevated onto an insulating layer on a semiconductor layer (see, for example, Patent Document 2).

[0003] Japanese Patent Laid-Open No. 10-335637 Japanese Patent Laid-Open No. 2002-100642

[0004] One embodiment of the present disclosure is a semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; a source electrode and a drain electrode provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source electrode and the drain electrode, wherein of a first portion of the drain electrode close to the gate electrode and a second portion of the source electrode close to the gate electrode, only the first portion of the drain electrode close to the gate electrode is provided on the first insulating layer.

[0005] One embodiment of the present disclosure is a semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; a source electrode and a drain electrode provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source electrode and the drain electrode, wherein a length of a first portion of the drain electrode that is close to the gate electrode and provided on the first insulating layer is 0.1 to 0.6 times the distance between a region where the gate electrode is in contact with the nitride semiconductor layer and a region where the drain electrode is in contact with the nitride semiconductor layer.

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; source and drain electrodes provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source and drain electrodes, wherein a first length of a first portion of the drain electrode that is close to the gate electrode and provided on the first insulating layer is greater than a second length of a second portion of the source electrode that is close to the gate electrode and provided on the first insulating layer.

[0007] FIG. 1 is a plan view of a semiconductor device in Example 1. FIG. 2 is a cross-sectional view taken along the line A-A in FIG. 1. FIG. 3A is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 3B is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 4A is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 4B is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 5A is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 5B is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 6A is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 6B is a cross-sectional view showing a manufacturing method of a semiconductor device in Example 1. FIG. 7 is a graph showing the collapse rate versus L1 / Lgd in an experiment. FIG. 8 is a cross-sectional view of Comparative Example 1 for which a simulation was performed. FIG. 9 is a cross-sectional view of Example 1 for which a simulation was performed. FIG. 10 is a graph showing the electric field intensity versus position X in the simulation. FIG. 11 is a cross-sectional view of a semiconductor device in Variation 1 of Example 1. FIG. 12 is a cross-sectional view of a semiconductor device in Example 2. FIG. 13 is a cross-sectional view of a semiconductor device in Example 1. FIG. 14 is a cross-sectional view of a semiconductor device in Example 2. FIG. 15 is a cross-sectional view of a semiconductor device according to a first modification of the second embodiment.

[0008] [Problem to be Solved by the Present Disclosure] It is known that a current transient phenomenon called a collapse phenomenon or a drain current drift phenomenon occurs in a transistor using a nitride semiconductor.

[0009] The present disclosure has been made in consideration of the above-mentioned problems, and aims to suppress current transient phenomena.

[0010] [Advantages of the Present Disclosure] According to the present disclosure, current transient phenomena can be suppressed.

[0011] [Description of Embodiments of the Present Disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including a first insulating layer provided on a nitride semiconductor layer, source and drain electrodes provided on the nitride semiconductor layer and making ohmic contact with the nitride semiconductor layer, and a gate electrode provided on the nitride semiconductor layer between the source and drain electrodes, wherein of a first portion of the drain electrode close to the gate electrode and a second portion of the source electrode close to the gate electrode, only the first portion of the drain electrode close to the gate electrode is provided on the first insulating layer. This makes it possible to suppress current transients and gate-source parasitic capacitance. (2) One embodiment of the present disclosure is a semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; source and drain electrodes provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source and drain electrodes, wherein a length of a first portion of the drain electrode near the gate electrode and provided on the first insulating layer is 0.1 to 0.6 times the distance between a region where the gate electrode contacts the nitride semiconductor layer and a region where the drain electrode contacts the nitride semiconductor layer. This suppresses current transients and gate-drain parasitic capacitance. (3) In the above (2), a second portion of the source electrode near the gate electrode may be provided on the first insulating layer. (4) One embodiment of the present disclosure is a semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; a source electrode and a drain electrode provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source electrode and the drain electrode, wherein a first length of a first portion of the drain electrode near the gate electrode and provided on the first insulating layer is greater than a second length of a second portion of the source electrode near the gate electrode and provided on the first insulating layer. This makes it possible to suppress current transients and gate-source parasitic capacitance.(5) In (4) above, the first length may be 1.5 times or more the second length. This further reduces gate-source parasitic capacitance. (6) In any of (1) to (5) above, a second insulating layer may be provided on the first insulating layer and the drain electrode, and a metal layer may be provided on the drain electrode and in contact with the drain electrode. The second insulating layer may be provided between at least a portion of the first portion close to the gate electrode and the metal layer. This further reduces the penetration of moisture and the like into the drain electrode. (7) In any of (1) to (6) above, the thickness of the first insulating layer may be ½ or less the length of the first portion provided on the first insulating layer. This further reduces current transients. (8) In any of (1), (2), (5), and (6) above, the length of the first portion provided on the first insulating layer may be 0.1 to 0.6 times the length of the contact between the drain electrode and the nitride semiconductor layer. This makes it possible to suppress current transients and gate-drain parasitic capacitance.

[0012] [Details of the embodiments of the present disclosure] Specific examples of semiconductor devices according to the embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] [Example 1] Fig. 1 is a plan view of a semiconductor device in Example 1. Fig. 2 is a cross-sectional view taken along line A-A in Fig. 1. The thickness direction of the substrate 10 is defined as the Z direction, the direction in which the source electrode 12, the drain electrode 14, and the gate electrode 16 are arranged is defined as the X direction, and the direction in which the source electrode 12, the drain electrode 14, and the gate electrode 16 extend is defined as the Y direction.

[0014] 1 and 2 , in the semiconductor device 100 of Example 1, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The semiconductor layer 10b is a nitride semiconductor layer and includes a transit layer 10c and a barrier layer 10d. In an XY plane parallel to the X and Y directions, a region of the semiconductor layer 10b that has been inactivated by ion implantation or the like is an inactive region 13. A region of the semiconductor layer 10b that is activated but not inactivated is an active region 11.

[0015] An insulating layer 26 is provided on the substrate 10. The insulating layer 26 has openings 26a to 26c extending in the Y direction. A source electrode 12, a drain electrode 14, and a gate electrode 16 are provided on the semiconductor layer 10b. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14. The source electrode 12, the drain electrode 14, and the gate electrode 16 are in contact with the semiconductor layer 10b via the openings 26a, 26b, and 26c, respectively.

[0016] The length L26a of the opening 26a in the X direction is approximately the same as the length L12 of the source electrode 12 in the X direction. Therefore, the source electrode 12 barely extends over the insulating layer 26. For example, a second portion of the source electrode 12 close to the gate electrode 16 does not extend over the insulating layer 26. The length L26b of the opening 26b in the X direction is greater than the length L14 of the drain electrode 14 in the X direction. Therefore, the drain electrode 14 extends over the insulating layer 26. The length L1 in the X direction of the first portion 14a of the drain electrode 14 close to the gate electrode 16 and provided on the insulating layer 26 is, for example, (L14-L26b) / 2. The length L26c of the opening 26c in the X direction is greater than the length L16 of the gate electrode 16 in the X direction. Therefore, both ends of the gate electrode 16 extend over the insulating layer 26. The lengths L26c and L16 may be approximately equal.

[0017] The length L26c corresponds to the gate length. The distance in the X direction between the openings 26a and 26c corresponds to the source-gate distance Lsg. The distance in the X direction between the openings 26c and 26b corresponds to the gate-drain distance Lgd.

[0018] An insulating layer 28 is provided on the insulating layer 26 so as to cover the gate electrode 16. A field plate 18 is provided on the insulating layer 28. At least a portion of the field plate 18 is provided above the semiconductor layer 10b between the gate electrode 16 and the drain electrode 14. The field plate 18 is electrically connected to the source electrode 12, and the field plate 18 and the source electrode 12 are at the same potential. A portion of the field plate 18 is provided above the gate electrode 16. The field plate 18 does not have to be provided above the gate electrode 16.

[0019] Metal layers 22 and 24 are provided on the source electrode 12 and the drain electrode 14, respectively. The metal layers 22 and 24 are in electrical contact with the source electrode 12 and the drain electrode 14. An insulating layer 30 is provided on the insulating layer 28 to cover the source electrode 12, the drain electrode 14, and the field plate 18. An insulating layer 32 is provided on the insulating layer 30.

[0020] The substrate 10a is, for example, a silicon carbide (SiC) substrate, a silicon substrate, a gallium nitride (GaN) substrate, or a sapphire substrate, and one example is a silicon carbide substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a gallium nitride layer, an aluminum gallium nitride (AlGaN) layer, and / or an indium gallium nitride (InGaN) layer. In the case of a GaN-HEMT, the running layer 10c is a gallium nitride layer, and the barrier layer 10d is an aluminum gallium nitride layer.

[0021] The source electrode 12 and the drain electrode 14 are metal layers that make ohmic contact with the semiconductor layer 10b, and are, for example, a titanium film and an aluminum film from the substrate 10 side. The gate electrode 16 is a metal layer that forms a Schottky junction with the semiconductor layer 10b, and are, for example, a nickel film and a gold film from the substrate 10 side. The field plate 18 is a low-resistance metal layer, for example, a gold film. The metal layers 22 and 24 are metal layers that are lower in resistance than the source electrode 12 and the drain electrode 14, and are, for example, a gold layer. The insulating layers 26, 28, and 30 are inorganic insulating layers, for example, a silicon nitride layer or a silicon oxide layer. The insulating layer 30 is an organic insulating layer, for example, a polyimide layer or a BCB (benzocyclobutene) layer.

[0022] The thickness T12 of the source electrode 12 and the thickness T14 of the drain electrode 14 are, for example, 300 nm. The thickness T22 of the metal layer 22 and the thickness T24 of the metal layer 24 are, for example, 5 μm.

[0023] The length L26c corresponding to the gate length is, for example, 0.5 μm. Lsg is, for example, 1 μm. Lgd is, for example, 3 μm. The thickness T26 of the insulating layer 26 is, for example, 100 nm.

[0024] 3A to 6B are cross-sectional views showing a manufacturing method of a semiconductor device according to Example 1. As shown in FIG. 3A, a substrate 10 is prepared, which includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. An inactive region 13 is formed in the semiconductor layer 10b by ion implantation. The region other than the inactive region 13 is the active region 11. An insulating layer 26 is formed on the substrate 10 by, for example, a chemical vapor deposition (CVD) method. As shown in FIG. 3B, openings 26a and 26b are formed in the insulating layer 26 by, for example, photolithography and etching.

[0025] As shown in Fig. 4A, the source electrode 12 and the drain electrode 14 are formed in the openings 26a and 26b, respectively, using vacuum deposition and lift-off. Both ends of the drain electrode 14 in the X direction extend onto the insulating layer 26. As shown in Fig. 4B, an opening 26c is formed in the insulating layer 26 using, for example, photolithography and etching. The opening 26c is sandwiched between the source electrode 12 and the drain electrode 14.

[0026] 5A, a gate electrode 16 is formed in the opening 26c by, for example, vacuum deposition and lift-off. Both ends of the gate electrode 16 in the X direction extend onto the insulating layer 26. As shown in FIG. 5B, metal layers 22 and 24 are formed on the source electrode 12 and the drain electrode 14, respectively, by, for example, plating.

[0027] As shown in Fig. 6A, an insulating layer 28 is formed on insulating layer 26 using, for example, a CVD method so as to cover gate electrode 16 and metal layers 22 and 24. Note that insulating layer 28 may cover metal layers 22 and 24 as in Fig. 6A, or may not cover metal layers 22 and 24 as in Fig. 2. As shown in Fig. 6B, a field plate 18 is formed on insulating layer 28 using, for example, a vacuum deposition method and a lift-off method. Thereafter, an insulating layer 32 is formed on insulating layer 30, which in turn forms insulating layer 30 on insulating layer 28, using, for example, a CVD method.

[0028] [Experiment] Transistors with different lengths L1 were fabricated, and the collapse rate was measured as a transient response. The fabricated transistors were GaN-HEMTs, with the substrate 10a being a silicon carbide substrate, the running layer 10c being a gallium nitride layer, and the barrier layer 10d being an aluminum gallium nitride layer. Lsg = 1 μm, Lgd = 3 μm, T26 = 100 nm, and the total thickness of the drain electrode 14 and metal layer 24 was 10 μm. The insulating layer 26 was a silicon nitride layer.

[0029] The collapse phenomenon is a phenomenon in which electrons are trapped in crystal defects or layer interfaces within a transistor when high-voltage stress is applied to the transistor, resulting in an instantaneous decrease in current. A small collapse rate indicates a large transient response, and a collapse rate of 100% indicates that almost no transient current occurs.

[0030] FIG. 7 is a graph showing the collapse rate versus L1 / Lgd in an experiment. In FIG. 7, the horizontal axis represents the ratio of the distance L1 by which the drain electrode 14 extends over the insulating layer 26 to the gate-drain distance Lgd. The vertical axis represents the collapse rate. The dots represent measurement points, and the solid lines connect the dots. When L1 / Lgd is 0.05, the collapse rate is 76%. As L1 / Lgd increases, the collapse rate increases. When L1 / Lgd is 0.47, the collapse rate is 79%. When L1 / Lgd is 0.63, the collapse rate decreases to 78%. Thus, increasing L1 increases the collapse rate. In other words, the current transient phenomenon is improved.

[0031] From the viewpoint of suppressing transient phenomena, L1 / Lgd can be set to 0.1 or more, 0.15 or more, or 0.2 or more. As L1 / Lgd increases, the distance between the gate electrode 16 and the drain electrode 14 and the metal layer 24 decreases, and the gate-drain parasitic capacitance sandwiching the insulating layers 26, 28 to 30 and 32 increases. From this viewpoint, L1 / Ldg can be set to 0.6 or less, or 0.5 or less.

[0032] [Simulation] A simulation was performed to confirm why increasing L1 / Ldg improves transient phenomena. Fig. 8 is a cross-sectional view of Comparative Example 1 on which the simulation was performed. Fig. 9 is a cross-sectional view of Example 1 on which the simulation was performed. The horizontal and vertical directions in Figs. 8 and 9 correspond to the X and Z directions in Figs. 1 and 2, respectively. A two-dimensional device simulation was used for the simulation.

[0033] As shown in Figures 8 and 9, the semiconductor layer 10b is formed by stacking a traveling layer 10c, a barrier layer 10d, and a cap layer 10e in this order. The traveling layer 10c is a gallium nitride layer, the barrier layer 10d is an aluminum gallium nitride layer, and the cap layer 10e is a gallium nitride layer. The insulating layer 26 is a silicon nitride layer, and the insulating layer 32 is a polyimide layer. Openings 26b are provided in the insulating layer 26 and the cap layer 10e. In the simulation, the electric field strength in the channel 15 near the interface of the traveling layer 10c and the barrier layer 10d was calculated. The channel 15 is a two-dimensional electron gas.

[0034] 8, in Comparative Example 1, the drain electrode 14 does not extend over the insulating layer 26. The end of the drain electrode 14 close to the gate electrode 16 and the end of the opening 26b close to the gate electrode 16 coincide with each other, and the position X of the end is X1.

[0035] 9, in Example 1, the drain electrode 14 rides up onto the insulating layer 26. The position X of the end of the drain electrode 14 closest to the gate electrode 16 is X2, and the position X of the end of the opening 26b closest to the gate electrode 16 is X1. Lgd is 4 μm, and L1 / Lgd is 0.125.

[0036] FIG. 10 is a diagram showing the electric field strength relative to position X in the simulation. The horizontal axis in FIG. 10 corresponds to the horizontal position X in FIGS. 8 and 9. The vertical axis represents the electric field strength in the channel 15 in FIGS. 8 and 9. The gate voltage was −5 V and the drain voltage was 100 V. As shown in FIG. 10, in Comparative Example 1, the electric field strength peaks when position X is X1. In this way, the electric field in the channel 15 is concentrated and maximized at the drain electrode 14 and the edge of the opening 26b.

[0037] In Example 1, the electric field has a maximum when position X is X1 and when position X2. The electric field at position X2 is greater than the electric field at position X1. Thus, in Example 1, the electric field is concentrated at two locations: the end of drain electrode 14 and the end of opening 26b. Therefore, the electric field is dispersed to both positions X1 and X2, and the maximum value of the electric field is smaller than in Comparative Example 1.

[0038] The transient phenomenon occurs as follows: Electrons become highly energetic due to the high electric field between the gate electrode 16 and the drain electrode 14, and are captured in traps in the semiconductor layer 10b. This reduces the drain current. The trapped electrons are released over time. Therefore, when the electric field between the gate electrode 16 and the drain electrode 14 decreases, the drain current recovers over time. As shown in FIG. 10, in Example 1, the maximum value of the electric field in the channel 15 is small, making the transient phenomenon less likely to occur. This is thought to result in a large collapse rate, as shown in FIG. 7.

[0039] Therefore, as shown in FIG. 2 , the first portion 14 a of the drain electrode 14 near the gate electrode 16 is provided on the insulating layer 26 (first insulating layer). This reduces electric field concentration near the drain electrode 14, as shown in FIG. 10 , thereby suppressing current transients. On the other hand, if the second portion of the source electrode 12 near the gate electrode 16 is provided on the insulating layer 26, the distance between the source electrode 12 and the gate electrode 16 becomes shorter than when the second portion is not provided on the insulating layer 26, resulting in a larger gate-source parasitic capacitance. The potential difference between the source electrode 12 and the gate electrode 16 is smaller than the potential difference between the gate electrode 16 and the drain electrode 14, so the electric field between the source electrode 12 and the gate electrode 16 is not a significant problem. Therefore, of the first portion 14 a and the second portion 12 a, only the first portion 14 a is provided on the insulating layer 26. This suppresses current transients and gate-source parasitic capacitance.

[0040] To suppress electric field concentration between the gate electrode 16 and the drain electrode 14, Comparative Example 1 can be considered, in which a gate structure such as that described in Patent Document 2 is applied to a nitride semiconductor transistor. In Comparative Example 1, a third portion of the gate electrode 16, which is close to the drain electrode 14, is provided on the insulating layer 26. In this case, the third portion of the gate electrode 16 is located on the depletion layer in the semiconductor layer 10b. This increases the intrinsic gate-drain capacitance sandwiching the depletion layer. On the other hand, in Example 1, the first portion 14a of the drain electrode 14 is not located on the depletion layer in the semiconductor layer 10b. Therefore, the first portion 14a has almost no effect on the intrinsic gate-drain capacitance sandwiching the depletion layer. The first portion 14a of the drain electrode 14 contributes only to the gate-drain parasitic capacitance sandwiching the insulating layers 26, 28, 30, and 32. Thus, Example 1 can suppress an increase in gate-drain capacitance and degradation of high-frequency characteristics compared to Comparative Example 1. Note that, as shown in FIG. 2, in Example 1 as well, a portion of the gate electrode 16 close to the drain electrode 14 is provided on the insulating layer 26. This is to reduce the margin for misalignment between the opening 26c and the gate electrode 16 and to reduce the gate resistance. For this reason, the portion of the gate electrode 16 close to the source electrode 12 is also provided on the insulating layer 26. The gate electrode 16 does not have to extend over the insulating layer 26.

[0041] 7, the length L1 of the first portion 14a can be set to be 0.1 to 0.6 times the distance (i.e., Ldg) between the region where the gate electrode 16 contacts the semiconductor layer 10b and the region where the drain electrode 14 contacts the semiconductor layer 10b. By setting L1 / Ldg to be 0.1 or more, current transients can be suppressed, and by setting L1 / Ldg to be 0.6 or less, gate-drain parasitic capacitance can be suppressed.

[0042] If the thickness T26 of the insulating layer 26 is large, the electric field of the first portion 14a passes through the insulating layer 26 and is less likely to affect the channel. From this perspective, the thickness T26 can be set to ½ or less, ½.5 or less, or ⅓ or less of the length L1 of the first portion 14a. This can further suppress transient current phenomena. If the thickness T26 is too thin, there is a possibility that part of the first portion 14a will come into contact with the semiconductor layer 10b. From this perspective, the thickness T26 can be set to ⅕ or more of the length L1.

[0043] 11 is a cross-sectional view of a semiconductor device according to Modification 1 of Example 1. As shown in FIG. 11, in a semiconductor device 102 according to Modification 1 of Example 1, both ends of the source electrode 12 in the X direction are disposed on the insulating layer 26. This ensures a margin for misalignment between the opening 26a and the source electrode 12. The other configurations are the same as those of Example 1, and therefore a description thereof will be omitted.

[0044] As the distance between the source electrode 12 and the gate electrode 16 decreases, the gate-source parasitic capacitance across the insulating layers 26, 28, and 30 increases. Therefore, the first length L1 of the first portion 14a is made longer than the second length L2 of the second portion 12a of the source electrode 12 that is located near the gate electrode 16 and on the insulating layer 26. This makes it possible to suppress current transients and also suppress the gate-source parasitic capacitance.

[0045] From the viewpoint of suppressing gate-source parasitic capacitance, the first length L1 can be set to 1.5 times or more, or even twice or more, the second length L2.

[0046] Second Embodiment FIG. 12 is a cross-sectional view of a semiconductor device according to a second embodiment. As shown in FIG. 12 , in a semiconductor device 104 according to the second embodiment, an insulating layer 29 is provided between insulating layers 28 and 30. The insulating layer 29 is an inorganic insulating layer such as a silicon nitride layer. Around the source electrode 12 in a plan view, the insulating layer 29 is provided between the source electrode 12 and the metal layer 22. Around the drain electrode 14 in a plan view, the insulating layer 29 is provided between the drain electrode 14 and the metal layer 24. In the central portions of the source electrode 12 and the drain electrode 14 in a plan view, the insulating layer 29 has openings 29 a and 29 b, respectively. The source electrode 12 and the metal layer 22 are in contact with each other in the opening 29 a, and the drain electrode 14 and the metal layer 24 are in contact with each other in the opening 29 b. The other configurations are the same as those of the first embodiment, and therefore will not be described again.

[0047] FIG. 13 is a cross-sectional view of a semiconductor device according to a first embodiment. In FIG. 13 , openings 34 and 36 are provided in insulating layers 30 and 32 on metal layers 22 and 24. Openings 34 and 36 represent openings provided in the source pad and drain pad, respectively. The source pad and drain pad are provided on the inactive region 13 in a different location from the source electrode 12 and drain electrode 14 in the active region 11, but are schematically illustrated on the metal layers 22 and 24 in FIG. 13 . As indicated by arrows 50, moisture and the like penetrate through the interfaces between the insulating layer 30 and the metal layers 22 and 24 at openings 34 and 36. If moisture and the like reaches the source electrode 12 and drain electrode 14, the source electrode 12 and drain electrode 14 may corrode, potentially causing a short circuit between the source electrode 12 and drain electrode 14 and the gate electrode 16.

[0048] FIG. 14 is a cross-sectional view of a semiconductor device according to a second embodiment. In FIG. 14, the tip of arrow 50 splits into two arrows 50a and 50b at the insulating layer 29. In this way, the intrusion paths of moisture and the like can be dispersed compared to FIG. 13. The intrusion paths of moisture and the like from openings 34 and 36 to source electrode 12 and drain electrode 14 are longer than arrow 50 in FIG. 13, as indicated by arrows 50 and 50a. This makes it possible to suppress moisture and the like from invading source electrode 12 and drain electrode 14.

[0049] As described above, according to the second embodiment, the insulating layer 29 (second insulating layer) is provided on the insulating layer 26 and the drain electrode 14. The insulating layer 29 is provided between at least the portion 14b of the first portion 14a that is close to the gate electrode 16 and the metal layer 24. This makes it possible to prevent moisture and the like from penetrating into the drain electrode 14.

[0050] From the viewpoint of preventing the intrusion of moisture and the like, the length L3 of the portion 14b in the X direction can be set to be at least half the length L1, or can be set to be at least 1. The thickness of the insulating layer 29 is, for example, at least the thickness T26 of the insulating layer 26, and is, for example, 200 nm.

[0051] [First Modification of Second Embodiment] FIG. 15 is a cross-sectional view of a semiconductor device according to the first modification of the second embodiment. As shown in FIG. 15 , in a semiconductor device 106 according to the first modification of the second embodiment, the second portion 12a of the source electrode 12 rides on the insulating layer 26. The second portion 12a is provided on the insulating layer 29 between at least a portion 12b of the second portion 12a close to the gate electrode 16 and the metal layer 24. This can prevent moisture and the like from entering the source electrode 12. From the viewpoint of preventing moisture and the like from entering, the length L4 of the portion 12b in the X direction can be set to be at least half the length L2, or can be set to be at least equal to the length L2. The other configurations are the same as those of the second embodiment, and therefore a description thereof will be omitted.

[0052] In the first and second embodiments and their modifications, examples in which the field plate 18 is provided have been described, but the field plate 18 does not necessarily have to be provided.

[0053] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the scope of the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

[0054] 10, 10a Substrate 10b Semiconductor layer 10c Travel layer 10d Barrier layer 10e Cap layer 11 Active region 12 Source electrode 12a Second portion 12b, 14b Portion 13 Inactive region 14 Drain electrode 14a First portion 15 Channel 16 Gate electrode 18 Field plate 22, 24 Metal layer 26, 28, 29, 30, 32 Insulating layer 26a, 26b, 26c, 29a, 29b, 34, 36 Opening 50, 50a, 50b Arrows 100, 102, 104, 106 Semiconductor device

Claims

1. A semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; a source electrode and a drain electrode provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source electrode and the drain electrode, wherein of a first portion of the drain electrode close to the gate electrode and a second portion of the source electrode close to the gate electrode, only the first portion of the drain electrode close to the gate electrode is provided on the first insulating layer.

2. A semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; a source electrode and a drain electrode provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source electrode and the drain electrode, wherein the length of a first portion of the drain electrode that is close to the gate electrode and provided on the first insulating layer is 0.1 to 0.6 times the distance between a region where the gate electrode contacts the nitride semiconductor layer and a region where the drain electrode contacts the nitride semiconductor layer.

3. The semiconductor device according to claim 2, wherein a second portion of said source electrode close to said gate electrode is provided on said first insulating layer.

4. A semiconductor device comprising: a first insulating layer provided on a nitride semiconductor layer; a source electrode and a drain electrode provided on the nitride semiconductor layer and in ohmic contact with the nitride semiconductor layer; and a gate electrode provided on the nitride semiconductor layer between the source electrode and the drain electrode, wherein a first length of a first portion of the drain electrode that is close to the gate electrode and provided on the first insulating layer is greater than a second length of a second portion of the source electrode that is close to the gate electrode and provided on the first insulating layer.

5. The semiconductor device according to claim 4, wherein said first length is at least 1.5 times said second length.

6. A semiconductor device according to any one of claims 1 to 5, comprising: a second insulating layer provided on the first insulating layer and the drain electrode; and a metal layer on and in contact with the drain electrode, the second insulating layer being provided between at least a portion of the first portion close to the gate electrode and the metal layer.

7. A semiconductor device according to any one of claims 1 to 5, wherein the thickness of the first insulating layer is equal to or less than half the length of the first portion provided on the first insulating layer.

8. A semiconductor device according to any one of claims 1, 2 and 5, wherein the length of the first portion provided on the first insulating layer is 0.1 to 0.6 times the length of the contact area of the drain electrode with the nitride semiconductor layer.

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