Semiconductor device

Abstract

Provided is a semiconductor device in which a first cathode region and a second cathode region are repeatedly provided in a first direction, one or more first cathode regions are provided in a second direction intersecting the first direction, and a length Lx between both ends in the second direction of the one or more first cathode regions, and a width Dyn in the first direction of one first cathode region satisfy the following formula.　0.001 < Dyn / Lx ≤ 0.1

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, a structure in which N-type and P-type regions are mixed as the cathode region of a diode has been known (see, for example, Patent Documents 1 and 2). Problem to be solved

[0003] In a semiconductor device, it is preferable to arrange N-type and P-type cathode regions so as to have predetermined characteristics. General disclosure

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device including a semiconductor substrate having an upper surface and a lower surface, and a diode section having a longitudinal axis in a first direction provided in the semiconductor substrate. In the above semiconductor device, the diode section may include a drift region of a first conductivity type provided in the semiconductor substrate. In any of the above semiconductor devices, the diode section may include a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the diode section may include a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the first cathode region and the second cathode region may be repeatedly provided in the first direction. In any of the above semiconductor devices, one or more first cathode regions may be provided in the lower surface of the semiconductor substrate in a second direction perpendicular to the first direction. In any of the above semiconductor devices, a length Lx between both ends of the one or more first cathode regions in the second direction and a width Dyn of one of the first cathode regions in the first direction may satisfy the following formula: 0.001<Dyn / Lx≦0.1

[0005] In any of the above semiconductor devices, on the lower surface, a total area Sn of the first cathode regions and a total area Sp of the second cathode regions may satisfy the following formula: 0.1≦Sn / (Sn+Sp)<1.

[0006] In any of the above semiconductor devices, the total area Sn and the total area Sp may satisfy the following formula: 0.4≦Sn / (Sn+Sp)<0.8.

[0007] In any of the above semiconductor devices, the total area Sn and the total area Sp may satisfy the following formula: 0.5≦Sn / (Sn+Sp)<0.75.

[0008] In any of the above semiconductor devices, a width Dyp of one of the second cathode regions in the first direction and a width Dyn of one of the first cathode regions in the first direction may satisfy the following formula: 0.1≦Dyn / (Dyn+Dyp)<1.

[0009] In any of the above semiconductor devices, the width Dyp and the width Dyn may satisfy the following formula: 0.4≦Dyn / (Dyn+Dyp)<0.8

[0010] In any of the above semiconductor devices, the width Dyp and the width Dyn may satisfy the following formula: 0.5≦Dyn / (Dyn+Dyp)<0.75.

[0011] In any of the above semiconductor devices, a width Dyn of one of the first cathode regions in the first direction may be larger than a width Dyp of one of the second cathode regions in the first direction.

[0012] A second aspect of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section having a longitudinal axis in a first direction provided in the semiconductor substrate. In the semiconductor device, the diode section may include a drift region of a first conductivity type provided in the semiconductor substrate. In any of the semiconductor devices described above, the diode section may include a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. In any of the semiconductor devices described above, the diode section may include a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate. In any of the semiconductor devices described above, the first cathode region and the second cathode region may be repeatedly provided in the first direction. In any of the semiconductor devices described above, one or more first cathode regions may be provided in the lower surface of the semiconductor substrate in a second direction perpendicular to the first direction. In any of the above semiconductor devices, a length Lx between both ends of the one or more first cathode regions in the second direction and a width Dyn of one of the first cathode regions in the first direction may satisfy the following formula: 0.001<Dyn / Lx≦0.4 In any of the above semiconductor devices, on the lower surface, a total area Sn of the first cathode regions and a total area Sp of the second cathode regions may satisfy the following formula: 0.5≦Sn / (Sn+Sp)<0.75

[0013] In any of the semiconductor devices described above, the first cathode regions may be discretely arranged in both the first direction and the second direction. In any of the semiconductor devices described above, the spacing between the first cathode regions at the center of the diode section in the second direction may be smaller than the spacing between the first cathode regions at end sections of the diode section in the second direction.

[0014] In any of the above semiconductor devices, the width Dxn in the second direction of one of the first cathode regions at the center of the diode section in the second direction may be smaller than the width Dxn in the second direction of one of the first cathode regions at an end of the diode section in the second direction.

[0015] In any of the semiconductor devices described above, one of the first cathode regions arranged at an end of the diode section in the second direction may have a width in the second direction greater than a width in the first direction.

[0016] In any of the above semiconductor devices, the width of one of the second cathode regions in the first direction may be greater than the width of the first cathode region in the depth direction of the semiconductor substrate.

[0017] In any of the above semiconductor devices, the width of one of the second cathode regions in the first direction may be greater than the width of the second cathode region in the depth direction of the semiconductor substrate.

[0018] In any of the semiconductor devices described above, an upper surface of the first cathode region in the depth direction may have a flat portion that is a uniform distance from the lower surface of the semiconductor substrate, and a distance between the flat portions of two first cathode regions adjacent to each other in the first direction may be greater than 1.6 times the distance between the flat portion and the lower surface.

[0019] In any of the above semiconductor devices, on the underside of the semiconductor substrate, the first cathode region may include a straight first end edge and a straight second end edge that is inclined relative to the first end edge, and the first end edge and the second end edge may be connected by a curve.

[0020] In any of the above semiconductor devices, a width Dyp of one of the second cathode regions in the first direction may be smaller than a radius of curvature of the curve.

[0021] In any of the semiconductor devices described above, the semiconductor substrate may be provided with transistor portions arranged alternately with the diode portions in the second direction, and the transistor portions may have a plurality of gate trench portions on the top surface of the semiconductor substrate, the longitudinal direction of which extends in the first direction.

[0022] Any of the above semiconductor devices may further include a third cathode region of the second conductivity type provided in contact with an upper surface of the first cathode region.

[0023] In any of the above semiconductor devices, the third cathode region may be connected to the second cathode region.

[0024] In any of the above semiconductor devices, the first cathode region may be sandwiched between two of the second cathode regions in a direction parallel to the bottom surface of the semiconductor substrate, and the third cathode region may be connected to the two second cathode regions that sandwich the first cathode region.

[0025] In any of the above semiconductor devices, the position of the upper surface of the second cathode region and the position of the upper surface of the third cathode region may be different in the depth direction of the semiconductor substrate.

[0026] In any of the semiconductor devices described above, the diode section may include a plurality of the first cathode regions, and a thickness of any of the first cathode regions in the depth direction may be different from a thickness of any other of the first cathode regions in the depth direction.

[0027] Any of the above semiconductor devices may include a third cathode region of the second conductivity type provided in contact with an upper surface of each of the first cathode regions.

[0028] Any of the above semiconductor devices may include a third cathode region of the second conductivity type provided in contact with an upper surface of at least one of the first cathode regions. In any of the above semiconductor devices, the third cathode region may not be provided on an upper surface of at least one of the first cathode regions. In any of the above semiconductor devices, the position of the upper surface of the first cathode region not provided with the third cathode region may be deeper than the position of the upper surface of the third cathode region.

[0029] In any of the semiconductor devices described above, the position of an upper surface of each of the second cathode regions may be deeper than the position of an upper surface of the first cathode region. In any of the semiconductor devices described above, the position of an upper surface of any of the second cathode regions may be deeper than the position of an upper surface of any other of the second cathode regions.

[0030] In any of the above semiconductor devices, the width in the first direction of the second cathode region whose upper surface is located at the deepest position among the plurality of second cathode regions may be larger than the width in the first direction of any of the other second cathode regions.

[0031] Any of the above semiconductor devices may include a lifetime adjusting region provided on the lower surface side of the semiconductor substrate, the lifetime adjusting region exhibiting a minimum value of the carrier lifetime. In any of the above semiconductor devices, the third cathode region may be disposed between the lifetime adjusting region and the lower surface.

[0032] A third aspect of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section having a longitudinal axis in a first direction provided in the semiconductor substrate. In the semiconductor device, the diode section may include a drift region of a first conductivity type provided in the semiconductor substrate. In any of the semiconductor devices described above, the diode section may include a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. In any of the semiconductor devices described above, the diode section may include a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate. In any of the semiconductor devices described above, the diode section may include a third cathode region of a second conductivity type provided in contact with an upper surface of the first cathode region. In any of the semiconductor devices described above, the position of the upper surface of the second cathode region and the position of the upper surface of the third cathode region may be different in the depth direction of the semiconductor substrate.

[0033] In any of the above semiconductor devices, the position of the upper surface of the second cathode region may be deeper than the position of the upper surface of the third cathode region.

[0034] In any of the above semiconductor devices, the position of the upper surface of the second cathode region may be shallower than the position of the upper surface of the third cathode region.

[0035] In any of the above semiconductor devices, the position of the upper surface of some of the third cathode regions may be shallower than the position of the upper surface of the second cathode region, and the position of the upper surface of other parts of the third cathode regions may be deeper than the position of the upper surface of the second cathode region.

[0036] In any of the semiconductor devices described above, the diode section may include a plurality of the first cathode regions and a plurality of the third cathode regions, and a thickness of any of the third cathode regions in the depth direction may be different from a thickness of any other of the third cathode regions in the depth direction.

[0037] In any of the above semiconductor devices, the first cathode region may have a first concentration peak of dopant in the depth direction. In any of the above semiconductor devices, the second cathode region may have a second concentration peak of dopant in the depth direction. In any of the above semiconductor devices, the second concentration peak may be located deeper than the first concentration peak.

[0038] In any of the above semiconductor devices, the first cathode region may have a first concentration peak of dopant in the depth direction. In any of the above semiconductor devices, the second cathode region may have a second concentration peak of dopant in the depth direction. In any of the above semiconductor devices, the first concentration peak may include a first skirt portion whose concentration monotonically decreases toward the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the second concentration peak may include a second skirt portion whose concentration monotonically decreases toward the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the second skirt portion may be provided deeper than the first skirt portion.

[0039] A fourth aspect of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section extending in a first direction. The diode section of the semiconductor device may include a drift region of a first conductivity type provided in the semiconductor substrate. The diode section of any of the semiconductor devices may include a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. The diode section of any of the semiconductor devices may include a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate. The diode section of any of the semiconductor devices may include a third cathode region of a second conductivity type that contacts the first cathode region in a depth direction from the lower surface to the upper surface of the semiconductor substrate and that contacts the second cathode region in a direction parallel to the lower surface. In any of the semiconductor devices, the first cathode region and the second cathode region may be repeatedly provided in the first direction.

[0040] In any of the above semiconductor devices, the maximum depth from the lower surface of the third cathode region in contact with the first cathode region may be the same as or substantially the same as the maximum depth from the lower surface of the second cathode region.

[0041] In any of the above semiconductor devices, the chemical concentration distribution of the acceptor in the second cathode region may be smooth without any discontinuities.

[0042] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0043] 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an enlarged view of region D in FIG. 1. It is a diagram showing an example of a cross section taken along line e-e in FIG. 2. It is a diagram showing an example of an arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. It is a diagram showing the relationship between the ratio of the length Lx and the width Dyn and the reverse recovery loss Err. It is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err when the width Dyn and the width Dyp are changed. It is a diagram showing another example of an arrangement of the first cathode region 81 and the second cathode region 82. It is a diagram showing another example of an arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. It is a diagram showing another example of an arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. It is a diagram showing another example of an arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. 17 is a diagram showing the time waveform of the anode current during reverse recovery. It is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err when the width Dyn and the width Dyp are changed. It is a diagram showing the relationship between the forward voltage of the diode section 80 and the anode-cathode current when the width Dyp is changed. It is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the forward surge current tolerance (IFSM tolerance) when the width Dyp is changed. It is a diagram showing an example of the A-A cross section shown in FIG. 4. It is a diagram showing an example of the shape of the first cathode region 81 in a top view. It is a diagram showing another example of the Y-Z cross section. It is a diagram showing an example of the chemical concentration distribution of phosphorus and boron in the first cathode region 81, the second cathode region 82, and the third cathode region 84. It is a diagram showing an example of the doping concentration distribution along the line B-B in FIG. 17. It is a diagram showing an example of the doping concentration distribution along the line CC in FIG. It is a diagram showing another example of the Y-Z cross section. It is a diagram showing another example of the Y-Z cross section. Fig. 1 is a diagram showing another example of a YZ cross section. Fig. 2 is a diagram showing another example of a YZ cross section. Fig. 3 is a diagram showing another example of a YZ cross section. Fig. 4 is a diagram showing an example of a G-G cross section in Fig. 1. Fig. 5 is a diagram showing another example of a G-G cross section. Fig. 6 is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err.

[0044] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0045] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0046] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0047] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0048] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0049] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0050] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0051] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0052] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, in which a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as a donor that supplies electrons. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded. Alternatively, an interstitial Si—H in a silicon semiconductor, in which an interstitial silicon (Si-i) is bonded to hydrogen, or a CiOi-H in which an interstitial carbon (Ci) is bonded to interstitial oxygen (Oi) and hydrogen, also functions as a donor that supplies electrons. In this specification, a VOH defect, CiOi-H, or interstitial Si—H may be referred to as a hydrogen donor.

[0053] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants contained substantially uniformly in the ingot that is the base of the semiconductor substrate when the ingot is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors include, but are not limited to, phosphorus, antimony, arsenic, selenium, or sulfur. In this example, the bulk donors are phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), and the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 １７ ~7 x 10 １７ / cm ３ The oxygen concentration in the substrate manufactured by the FZ method is 1×10 １５ ~5 x 10 １６ / cm ３ The higher the oxygen concentration, the more likely it is that hydrogen donors are generated. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or may be a value between 90% and 100% of the chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 １０ / cm ３ That's it, 5 x 10 １２ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 １１ / cm ３ The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 １２ / cm ３ The concentrations in the present invention may be values ​​at room temperature, for example, values ​​at 300 K (Kelvin) (approximately 26.9° C.).

[0054] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0055] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0056] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0057] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0058] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of these chemical concentrations. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. The semiconductor substrate may be silicon, silicon carbide, gallium nitride, diamond, or gallium oxide.

[0059] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0060] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0061] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0062] The active section 160 is provided with a diode section 80 including a diode element such as a free wheel diode (FWD). The active section 160 may further be provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT). The transistor section 70 and the diode section 80 are connected in anti-parallel to each other. That is, the emitter of the transistor section 70 and the anode of the diode section 80 are electrically connected, and the collector of the transistor section 70 and the cathode of the diode section 80 are electrically connected.

[0063] In FIG. 1 , the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1 ). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0064] The diode section 80 has an N+ type first cathode region and a P type second cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, a repeating structure including the first cathode region and the second cathode region is periodically arranged in a predetermined direction on the lower surface of the semiconductor substrate 10. The region in which the first cathode region or the second cathode region is arranged is referred to as the diode section 80. A P type collector region may be provided on the lower surface of the semiconductor substrate 10 in a region other than the diode section 80.

[0065] The transistor section 70 has a P-type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0066] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0067] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0068] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0069] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0070] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0071] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0072] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y axis direction. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0073] The semiconductor device 100 may include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which simulates the operation of a transistor section provided in the active section 160.

[0074] In the present example, the semiconductor device 100 includes an edge termination structure 150 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 150 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 150 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 150 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0075] 2 is an enlarged view of region D in FIG. 1 . Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0076] An interlayer insulating film is provided between the emitter electrode 52 and the active side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0077] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0078] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0079] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0080] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0081] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0082] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0083] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0084] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a linear section 29 and a tip section 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without tip sections 31 and dummy trench sections 30 with tip sections 31.

[0085] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0086] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0087] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e located at one end of each mesa portion in the extension direction, a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 may be provided in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0088] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0089] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0090] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction of the trench portion (Y-axis direction). For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0091] The mesa portion 61 of the diode section 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0092] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact region 15 does not have to be provided in the diode portion 80. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0093] In the diode section 80, a cathode region 83 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. The cathode region 83 is a region in which N+ type first cathode regions and P type second cathode regions are periodically arranged. In FIG. 2, the first cathode region and the second cathode region are omitted. In the region of the lower surface of the semiconductor substrate 10 where the cathode region 83 is not provided, a P type collector region 22 may be provided. The cathode region 83 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. The cathode region 83 and the collector region 22 may be in contact with the lower surface 23 of the semiconductor substrate 10. In FIG. 2, a boundary 90 between the cathode region 83 and the collector region 22 is indicated by a dotted line.

[0094] The boundary 90 may coincide with the boundary between the transistor portion 70 and the diode portion 80 in a top view seen from the upper surface 21. The position of the boundary 90 may be the boundary between the transistor portion 70 and the diode portion 80, determined based on the structure of the upper surface 21 side of the semiconductor substrate 10. Of the portion of the diode portion 80 that contacts the lower surface of the semiconductor substrate 10, the N-type region may be the first cathode region, and the P-type region may be the second cathode region. The boundary 90 in the X-axis direction may be located in a trench portion between the mesa portion 60 of the transistor portion 70 that is closest to the diode portion 80 and the mesa portion 61 of the diode portion 80 that is closest to the transistor portion 70. The boundary 90 in the X-axis direction may be the center of the trench portion in the X-axis direction. The trench portion that serves as the boundary 90 may be the trench portion that is closest to the diode portion 80 among the trench portions that contact the emitter region 12. The trench portion may be the gate trench portion 40 or the dummy trench portion 30.

[0095] In a top view seen from the upper surface 21, the boundary 90 in the Y-axis direction may be located more inward (in this example, on the +Y-axis direction side) than the end in the Y-axis direction of the contact hole 54 provided in the diode section 80, and may be located so as to overlap with the base region 14 exposed at the upper surface 21. In a top view seen from the upper surface 21, the distance from the end in the Y-axis direction of the contact hole 54 provided in the diode section 80 to the boundary 90 in the Y-axis direction may be equal to or greater than a length equivalent to half the thickness of the semiconductor substrate 10, may be equal to or greater than a length equivalent to 75% of the thickness of the semiconductor substrate 10, or may be equal to or greater than a length equivalent to the thickness of the semiconductor substrate 10.

[0096] The first cathode region included in the cathode region 83 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the N+ type first cathode region and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the first cathode region in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the first cathode region in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0097] 3 is a diagram showing an example of the ee cross section in FIG. 2. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 83. The cathode region 83 has an N+ type first cathode region 81 and a P type second cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0098] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact holes 54 described with reference to FIG. 2 .

[0099] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0100] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0101] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0102] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0103] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0104] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0105] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80 in contact with the upper surface 21 of the semiconductor substrate 10. The base region 14 of the diode portion 80 functions as the anode region of the diode portion 80. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61.

[0106] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0107] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower end of the base region 14 from reaching the collector region 22 and the cathode region 83.

[0108] In the transistor section 70, a P-type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0109] In the diode section 80, an N-type first cathode region 81 and a P-type second cathode region 82 are provided below the buffer region 20. In the example of FIG. 3 , the first cathode region 81 is in contact with the collector region 22, but the second cathode region 82 may also be in contact with the collector region 22.

[0110] The donor concentration of the first cathode region 81 is higher than the donor concentration of the drift region 18. The donor of the first cathode region 81 is, for example, arsenic, hydrogen, or phosphorus. The acceptor of the second cathode region 82 is, for example, boron, indium, or aluminum. The acceptor concentration of the second cathode region 82 may be higher than the acceptor concentration of the base region 14. The acceptor concentration of the second cathode region 82 may be the same as or different from that of the acceptor region of the collector region 22. Note that the elements that serve as the donor and acceptor in each region are not limited to the above-mentioned examples.

[0111] When the second cathode region 82 and the collector region 22 have the same acceptor concentration and are in contact with each other, the trench portion between the mesa portion 60 in which the emitter region 12 is disposed and the mesa portion 61 in which the emitter region 12 is not disposed may be the boundary position between the second cathode region 82 and the collector region 22. More specifically, the center position of the trench portion in the X-axis direction may be the boundary position between the second cathode region 82 and the collector region 22.

[0112] The collector region 22 and the cathode region 83 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0113] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0114] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary 90 in the X-axis direction between the diode section 80 and the transistor section 70 is located at the boundary between the cathode region 83 and the collector region 22.

[0115] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0116] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0117] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0118] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0119] By including the second cathode region 82 in the diode section 80, holes in the drift region 18 and the like can be extracted via the second cathode region 82. This suppresses the accumulation of holes in the diode section 80 in the on-state, reducing loss during reverse recovery. Furthermore, by providing the second cathode region 82, the forward voltage of the diode section 80 in the on-state changes. By adjusting the arrangement of the first cathode region 81 and the second cathode region 82, characteristics such as reverse recovery loss and forward voltage can be adjusted.

[0120] 4 is a diagram showing an example of the arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. FIG. 4 shows an example of the arrangement of the first cathode region 81 and the second cathode region 82 in one diode section 80. The arrangement of the first cathode region 81 and the second cathode region 82 in all diode sections 80 may be any of the arrangements described in this specification. FIG. 4 also shows the collector region 22 around the diode section 80.

[0121] In this example, the first cathode region 81 and the second cathode region 82 are repeatedly provided in the first direction. One or more first cathode regions 81 are provided in the second direction intersecting the first direction. In the example of FIG. 4, only one first cathode region 81 is provided in the second direction. In other words, the first cathode regions 81 are not provided discretely in the second direction. The first direction and the second direction may be orthogonal. In the example of FIG. 4, the first direction is the Y-axis direction, and the second direction is the X-axis direction.

[0122] A structure of first cathode regions 81 and second cathode regions 82 repeated in a predetermined direction is referred to as a repeating structure 85. In the example of Fig. 4, the repeating structure 85 includes only one set of first cathode regions 81 and second cathode regions 82 arranged alternately in the first direction. In the diode section 80, at least two repeating structures 85 are provided side by side in the first direction.

[0123] The length between both ends in the X-axis direction of one or more first cathode regions 81 provided in one diode section 80 is defined as Lx. When only one first cathode region 81 is provided in the X-axis direction, the length Lx is the length in the X-axis direction of that one first cathode region 81. When multiple first cathode regions 81 are provided in the X-axis direction, the length Lx is the length of a region including, among the multiple first cathode regions 81, a first cathode region 81 arranged at one end in the X-axis direction to a first cathode region 81 arranged at the other end.

[0124] Let Ly be the length between both ends in the Y-axis direction of one or more first cathode regions 81 provided in one diode section 80. When multiple first cathode regions 81 are provided in the Y-axis direction as shown in Fig. 4, the length Ly is the length of a region including, among the multiple first cathode regions 81, a first cathode region 81 arranged at one end in the Y-axis direction to a first cathode region 81 arranged at the other end.

[0125] The diode section 80 in this example has a longitudinal direction in the first direction (the Y-axis direction in this example). When the length Ly is greater than the length Lx, the diode section 80 may be considered to have a longitudinal direction in the first direction. The transistor section 70 or the trench section provided in the diode section 80 may also have a longitudinal direction in the first direction. The gate trench section 40 of the transistor section 70 may also have a longitudinal direction in the first direction. The direction parallel to the longest straight line among the end sides of the trench section in a top view may be considered to be the longitudinal direction of the trench section.

[0126] The width of one first cathode region 81 in the X-axis direction is defined as Dxn. As shown in FIG. 4 , when a first cathode region 81 is surrounded by a second cathode region 82 in top view, the first cathode region 81 surrounded by the second cathode region 82 is defined as one first cathode region 81. The width Dxn may be the maximum width of the first cathode region 81 in the X-axis direction. The width of one first cathode region 81 in the Y-axis direction is defined as Dyn. The width Dyn may be the maximum width of the first cathode region 81 in the Y-axis direction.

[0127] The width of one second cathode region 82 in the Y-axis direction is defined as Dyp. When the second cathode region 82 surrounds a plurality of first cathode regions 81 in top view as shown in Figure 4, the width of the portion of the second cathode region 82 that is sandwiched between two first cathode regions 81 in the Y-axis direction is defined as width Dyp. The minimum width in the Y-axis direction of the second cathode region 82 that is sandwiched between two first cathode regions 81 may be used as width Dyp.

[0128] In this specification, the lengths (Px and Py in this example) of the repeating structure 85 in the directions in which the first cathode regions 81 and the second cathode regions 82 are repeatedly arranged (the X-axis direction and the Y-axis direction in FIG. 4 ) may be referred to as the repeat pitch of the first cathode regions 81 and the second cathode regions 82 in each direction. In this example, the length Px of the repeating structure 85 in the X-axis direction is the same as the width Dxn of the first cathode region 81. In this example, the length Py of the repeating structure 85 in the Y-axis direction is the sum of the width Dyn of the first cathode region 81 and the width Dyp of the second cathode region 82. Furthermore, the area of ​​the first cathode region 81 included in one repeating structure 85 is defined as S1, and the area of ​​the second cathode region 82 included in one repeating structure 85 is defined as S2. The sum of the areas S1 of the first cathode regions 81 in one diode section 80 is defined as a total area Sn, and the sum of the areas S2 of the second cathode regions 82 is defined as a total area Sp.

[0129] Fig. 5 is a diagram showing the relationship between the ratio of length Lx to width Dyn and reverse recovery loss Err. In this example, Dxn = Lx, as shown in Fig. 4. In Fig. 5, the solid line indicates the case where width Dyn is equal to width Dyp. The dashed lines indicate the cases where width Dyn is larger than width Dyp and the cases where width Dyn is smaller than width Dyp.

[0130] In either case, the closer the ratio Dyn / Lx is to 1, the greater the reverse recovery loss Err. On the other hand, when the ratio Dyn / Lx is 0.1 or less, the reverse recovery loss Err is significantly reduced. When the width Dyn of the first cathode region 81 is reduced, holes present above the first cathode region 81 during reverse recovery are more likely to be extracted by the adjacent second cathode region 82. This makes it possible to reduce the reverse recovery loss Err. In the diode section 80, the ratio Dyn / Lx may be 0.1 or less.

[0131] If the width Dyn of the first cathode region 81 becomes too small, the diode section 80 will have difficulty operating as a diode. In the example of Figure 5, when the ratio Dyn / Lx becomes smaller than 0.001, the reverse recovery loss Err increases rapidly, becoming an abnormal value. In the diode section 80, the ratio Dyn / Lx may be 0.001 or greater.

[0132] At least one diode section 80 may satisfy formula (1). 0.001<Dyn / Lx≦0.1 (1) All diode sections 80 may satisfy formula (1). The upper limit of the ratio Dyn / Lx shown on the right side of formula (1) may be 0.05, 0.03, or 0.01. The lower limit of the ratio Dyn / Lx shown on the left side of formula (1) may be 0.003, 0.005, or 0.01.

[0133] The width Dyn may be the same as the width Dyp. The width Dyn may be smaller than the width Dyp. The width Dyn may be 90% or less of the width Dyp, 75% or less, or 50% or less. The width Dyn may be 10% or more of the width Dyp, 20% or more, or 30% or more.

[0134] The width Dyn may be larger than the width Dyp. In this case, it is easier to ensure a region that operates as a diode. The width Dyn may be 110% or more of the width Dyp, 125% or more, or 150% or more. The width Dyn may be 300% or less of the width Dyp, 200% or less, or 175% or less.

[0135] FIG. 6 shows the relationship between the forward voltage Vf and the reverse recovery loss Err of the diode section 80 when the width Dyn and the width Dyp are changed. In this example, the width Dyn and the width Dyp are the same. N50 / P50, N25 / P25, N15 / P15, N10 / P10, and N5 / P5 in FIG. 6 show examples where the width Dyn and the width Dyp are 50 μm, 25 μm, 15 μm, 10 μm, and 5 μm, respectively. The "N only" plot in FIG. 6 shows an example without the second cathode region 82. While the diode section 80 in FIG. 6 has the configuration shown in FIG. 4, diode sections 80 having other configurations described herein also exhibit similar characteristics.

[0136] 6, there is a trade-off between the forward voltage Vf and the reverse recovery loss Err in the diode section 80. That is, the lower the reverse recovery loss, the higher the forward voltage. As the forward voltage increases, the loss when the diode section 80 is on increases.

[0137] In order to adjust the forward voltage Vf and the reverse recovery loss Err, a carrier lifetime killer may be formed in the diode section 80. For example, by forming charged particles such as helium below the anode region of the diode section 80, a carrier recombination center is formed at that location, thereby reducing the carrier lifetime.

[0138] The semiconductor device 100 of this example does not require the formation of a carrier lifetime killer in the diode section 80. As shown in Fig. 6, the forward voltage Vf and the reverse recovery loss Err can be adjusted by adjusting the width Dyn and the width Dyp. As shown in Fig. 6, the smaller the width Dyn and the width Dyp, the smaller the reverse recovery loss Err and the larger the forward voltage Vf.

[0139] 6 shows the characteristics when the widths Dyn and Dyp are the same. On the other hand, when the width Dyn is larger than the width Dyp and when the width Dyn is smaller than the width Dyp, the reverse recovery loss Err decreases and the forward voltage Vf increases as the widths Dyn and Dyp decrease, as in the case of FIG.

[0140] The carrier lifetime in the drift region 18 of the diode section 80 may be 1 μs or more throughout the entire drift region 18. The carrier lifetime may be 2 μs or more, or 3 μs or more. The carrier lifetime may be 10 μs or more, 20 μs or more, or 30 μs or more. The carrier lifetime may be 10 ms or less, 1 ms or less, 500 μs or less, 200 μs or less, or 100 μs or less. Furthermore, helium may not be present in the drift region 18 of the diode section 80. The carrier lifetime in the drift region 18 of the diode section 80 may be the maximum value within the semiconductor substrate 10. This allows the step of forming a carrier lifetime killer to be omitted, simplifying the manufacturing process. Furthermore, leakage current due to carrier recombination centers or generation centers can be prevented.

[0141] 7 is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82. In this example, the first cathode region 81 shown in FIG. 4 is replaced with the second cathode region 82, and the second cathode region 82 is replaced with the first cathode region 81. The other structures are similar to those of the example in FIG. 4. Furthermore, in the structures shown in the respective figures of this specification, the first cathode region 81 may be replaced with the second cathode region 82, and the second cathode region 82 may be replaced with the first cathode region 81.

[0142] In this example, the width in the Y-axis direction of the first cathode region 81 sandwiched between two second cathode regions 82 in the Y-axis direction is defined as Dyn. The maximum width in the X-axis direction of the first cathode region 81 is defined as Lx, and the maximum width in the Y-axis direction is defined as Ly. In this example, the diode section 80 also exhibits characteristics similar to those shown in FIGS. 5 and 6. In this example, the widths Dyn, Dyp, and length Lx may have the same relationship as in the example described in FIG. 5.

[0143] 8 is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. In this example, the first cathode region 81 and the second cathode region 82 are repeatedly arranged in both the first direction and the second direction. In this example, the first direction and the second direction are perpendicular to each other. In the example of FIG. 8, the first direction is the Y-axis direction, and the second direction is the X-axis direction. In this example, multiple repeating structures 85 are arranged side by side in both the first direction and the second direction.

[0144] In this example, a plurality of first cathode regions 81 are also discretely arranged in the X-axis direction. The width of the portion of the second cathode region 82 sandwiched between two first cathode regions 81 in the X-axis direction is defined as width Dxp. The width Dxp may be the minimum width in the X-axis direction of the second cathode region 82 sandwiched between the two first cathode regions 81.

[0145] When multiple first cathode regions 81 are provided in the X-axis direction, the length Lx is the length between both ends of the multiple first cathode regions 81 in the X-axis direction. Of the multiple first cathode regions 81, the one arranged at the end on the negative side in the X-axis direction is referred to as the first cathode region 81-1, and the one arranged at the end on the positive side in the X-axis direction is referred to as the first cathode region 81-2. The length Lx is the length from the end on the negative side in the X-axis direction of the first cathode region 81-1 to the end on the positive side in the X-axis direction of the first cathode region 81-2. The definitions of length, width, and area other than the width Dxp and length Lx are the same as those in the example of FIG. 4.

[0146] In this example, the width Dxp and the length Lx may have the same relationship as in the example described in FIG. 5 . This allows the reverse recovery loss Err to be reduced. Furthermore, at least one diode section 80 may satisfy formula (2): 0.001<Dxn / Ly≦0.1 (2) All diode sections 80 may satisfy formula (2). The upper limit of the ratio Dxn / Ly shown on the right side of formula (2) may be 0.05, 0.03, or 0.01. The lower limit of the ratio Dxn / Ly shown on the left side of formula (2) may be 0.003, 0.005, or 0.01.

[0147] By repeatedly arranging the first cathode region 81 and the second cathode region 82 in both the first direction and the second direction, holes above the first cathode region 81 can be more easily extracted from the second cathode region 82. This makes it possible to further reduce the reverse recovery loss Err.

[0148] 9 is a diagram showing another example of the arrangement of the first cathode region 81 and the second cathode region 82 on the lower surface 23 of the semiconductor substrate 10. The diode section 80 of this example differs from the example of FIG. 8 in the arrangement of the first cathode region 81 and the second cathode region 82 in the X-axis direction. The other structures are similar to the example of FIG. 8. In this example, the widths Dyn, Dyp and length Lx may have the same relationship as in the example described in FIG. 5. This allows the reverse recovery loss Err to be reduced.

[0149] Of the multiple first cathode regions 81 arranged side by side in the X-axis direction, the width in the X-axis direction of one first cathode region 81 closest to the center of the diode section 80 in the X-axis direction is defined as Dxn2. Of the multiple first cathode regions 81 arranged side by side in the X-axis direction, the width in the X-axis direction of one first cathode region 81 closest to the end of the diode section 80 in the X-axis direction is defined as Dxn1. In this example, the width Dxn2 is smaller than the width Dxn1.

[0150] Of the second cathode regions 82 sandwiched between two first cathode regions 81 in the X-axis direction, the width in the X-axis direction of the second cathode region 82 closest to the center of the diode section 80 in the X-axis direction is defined as Dxp2. The width Dxp2 corresponds to the distance between the first cathode regions 81 at the center of the diode section 80 in the X-axis direction.

[0151] Of the second cathode regions 82 sandwiched between two first cathode regions 81 in the X-axis direction, the width in the X-axis direction of the region closest to the end of the diode section 80 in the X-axis direction is defined as Dxp1. The width Dxp1 corresponds to the distance between the first cathode regions 81 at the end of the diode section 80 in the X-axis direction. In this example, the width Dxp2 is smaller than the width Dxp1.

[0152] When a semiconductor device 100 such as an RC-IGBT is operated, the temperature near the center of the diode section 80 may become higher than in other regions. In response to this, by reducing the width of at least one of the first cathode region 81 and the second cathode region 82 at the center of the diode section 80 as in this example, the temperature rise at the center of the diode section 80 can be suppressed. The width Dxp2 may be 3 / 4 times or less than half the width Dxp1. The width Dxn2 may be 3 / 4 times or less than half the width Dxn1. The density of the second cathode region 82 at the center of the diode section 80 may be higher than the density of the second cathode region 82 at the center of the diode section 80. The density of the second cathode region 82 is the ratio of the area of ​​the second cathode region 82 to a unit area.

[0153] 9 , the width Dyn of the first cathode region 81 in the Y-axis direction is constant, and the width Dyp of the second cathode region 82 is also constant. In another example, the width Dyn at the center of the diode section 80 in the Y-axis direction may be smaller than the width Dyn at the ends of the diode section 80 in the Y-axis direction. Similarly, the width Dyp at the center of the diode section 80 in the Y-axis direction may be smaller than the width Dyp at the ends of the diode section 80 in the Y-axis direction. This makes it possible to suppress a temperature rise at the center of the diode section 80 in the Y-axis direction as well.

[0154] In one first cathode region 81 arranged at the end of the diode section 80 in the X-axis direction, the width Dxn1 in the X-axis direction may be greater than the width Dyn in the Y-axis direction. The width Dxn1 and the width Dyn may satisfy the following formula (3): 0.001<Dyn / Dxn1<1 (3) The upper limit value of the ratio Dyn / Dxn1 shown on the right side of formula (3) may be 0.9 or 0.8. The lower limit value of the ratio Dyn / Dxn1 shown on the left side of formula (3) may be 0.01 or 0.1.

[0155] 10 is a diagram showing another example of the arrangement of the first cathode regions 81 and the second cathode regions 82 on the lower surface 23 of the semiconductor substrate 10. The first cathode regions 81 in this example are discretely arranged in both the X-axis direction and the Y-axis direction, similar to the example in FIG. 8 . However, in this example, two first cathode regions 81 adjacent to each other in the Y-axis direction are located at different positions on the X-axis. The first cathode regions 81 in this example are arranged at equal intervals along the X-axis direction, and are also arranged at equal intervals in a direction forming an angle of less than 90 degrees with respect to the X-axis direction.

[0156] 8 to 10, the shape of the first cathode region 81 in top view may be substantially rectangular as shown in Fig. 8, circular as shown in Fig. 10, or another shape. In this example, the width Dxp and the length Lx may have the same relationship as in the example described in Fig. 5. This allows the reverse recovery loss Err to be reduced.

[0157] In each example described in this specification, the total area Sn of the first cathode region 81 and the total area Sp of the second cathode region 82 may satisfy the following formula (4): 0.1≦Sn / (Sn+Sp)<1 (4) As described above, by providing the second cathode region 82 in the diode section 80, the reverse recovery loss Err can be reduced.

[0158] The total area Sn of the first cathode regions 81 and the total area Sp of the second cathode regions 82 may satisfy the following formula (5): 0.4≦Sn / (Sn+Sp)<0.8 (5) Setting the total area Sp of the second cathode regions 82 to 20% or more of the total area facilitates reducing the reverse recovery loss Err. Furthermore, setting the total area Sn of the first cathode regions 81 to 40% or more of the total area facilitates maintaining the function of the diode section 80.

[0159] The total area Sn of the first cathode regions 81 and the total area Sp of the second cathode regions 82 may satisfy the following formula (6): 0.5≦Sn / (Sn+Sp)<0.75 (6) By setting the total area Sp of the second cathode regions 82 to 25% or more of the total area, it becomes easier to further reduce the reverse recovery loss Err. Furthermore, by setting the total area Sn of the first cathode regions 81 to 50% or more of the total area, it becomes easier to maintain the function of the diode section 80. The area ratio Sn / (Sn+Sp) may be 0.7 or less, or may be 0.65 or less.

[0160] In the formulas (4) to (6), the total area Sn may be replaced with the area S1, and the total area Sp may be replaced with the area S2. Even in this case, the same effects as those of the formulas (4) to (6) can be achieved.

[0161] In each example described in this specification, the width Dyp of one second cathode region 82 and the width Dyn of one first cathode region 81 may satisfy the following formula (7-1): 0.1≦Dyn / (Dyn+Dyp)<1 (7-1) As described above, by providing the second cathode region 82 in the diode section 80, the reverse recovery loss Err can be reduced.

[0162] The width Dyp of one second cathode region 82 and the width Dyn of one first cathode region 81 may satisfy the following formula (8-1): 0.4≦Dyn / (Dyn+Dyp)<0.8 (8-1) By making the width of the second cathode region 82 20% or more of the overall width, it becomes easier to reduce the reverse recovery loss Err. Furthermore, by making the width of the first cathode region 81 40% or more of the overall width, it becomes easier to maintain the function of the diode section 80.

[0163] The width Dyp of one second cathode region 82 and the width Dyn of one first cathode region 81 may satisfy the following formula (9-1): 0.5≦Dyn / (Dyn+Dyp)<0.75 (9-1) By making the width of the second cathode region 82 25% or more of the overall width, it becomes easier to further reduce the reverse recovery loss Err. Furthermore, by making the width of the first cathode region 81 50% or more of the overall width, it becomes easier to maintain the function of the diode section 80. The width ratio Dyn / (Dyn+Dyp) may be 0.7 or less, or may be 0.65 or less.

[0164] The length Lx and width Dyn shown in FIG. 4 and other figures may satisfy the following formula (10): 0.001<Dyn / Lx≦0.4 (10) As shown in FIG. 5, by setting Dyn / Lx to 0.4 or less, the reverse recovery loss Err can be reduced. In this case, the total area Sn of the first cathode regions 81 and the total area Sp of the second cathode regions 82 may satisfy the above-mentioned formula (6). Furthermore, the width Dyp of one second cathode region 82 and the width Dyn of one first cathode region 81 may satisfy the above-mentioned formula (9-1).

[0165] When the first cathode regions 81 and the second cathode regions 82 are repeatedly provided in the X-axis direction as well, the width Dxp of one second cathode region 82 and the width Dxn of one first cathode region 81 may satisfy any one of the following formulas (7-2), (8-2), and (9-2): 0.1≦Dxn / (Dxn+Dxp)<1 (7-2) 0.4≦Dxn / (Dxn+Dxp)<0.8 (8-2) 0.5≦Dxn / (Dxn+Dxp)<0.75 (9-2)

[0166] Fig. 11 is a diagram showing the time waveform of the anode current during reverse recovery. The dashed waveform in Fig. 11 shows a comparative example having the first cathode region 81 but not the second cathode region 82. The solid waveform in Fig. 11 shows an example having both the first cathode region 81 and the second cathode region 82. Each waveform in the example is an example in which the area ratio of the first cathode region 81 to the second cathode region 82 is changed. In all of the examples, the reverse recovery current is smaller than in the comparative example, and the reverse recovery loss Err can be reduced.

[0167] Fig. 12 is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err when the width Dyn and the width Dyp are changed. The plots of N25 / P25, N15 / P15, N10 / P10, and N5 / P5 in Fig. 12 are the same as those in Fig. 6. In Fig. 12, the plot of N15 / P1 shows an example where Dyn = 15 μm and Dyp = 1 μm, the plot of N15 / P2 shows an example where Dyn = 15 μm and Dyp = 2 μm, the plot of N15 / P5 shows an example where Dyn = 15 μm and Dyp = 5 μm, the plot of N15 / P10 shows an example where Dyn = 15 μm and Dyp = 10 μm, and the plot of N10 / P15 shows an example where Dyn = 10 μm and Dyp = 15 μm. The diode section 80 in FIG. 12 has the configuration shown in FIG. 4, but diode sections 80 having other configurations described in this specification also exhibit similar characteristics.

[0168] As shown in the examples of N15 / P1, N15 / P2, N15 / P5, and N15 / P10, when the width Dyn is made larger than the width Dyp, the trade-off characteristics between the forward voltage Vf and the reverse recovery loss Err shift downward. On the other hand, as shown in the example of N10 / P15, when the width Dyp is made larger than the width Dyn, the trade-off characteristics hardly shift at all.

[0169] The width Dyn of one first cathode region 81 may be larger than the width Dyp of one second cathode region 82. This improves the trade-off characteristics between the forward voltage Vf and the reverse recovery loss Err. The width Dyn may be 1.5 times or more, 3 times or more, 5 times or more, or 10 times or more of the width Dyp. The width Dyn may be 50 times or less, or 20 times or less of the width Dyp.

[0170] The width Dyn may be 5 μm or more, 10 μm or more, 15 μm or more, or 25 μm or more. The width Dyn may be 100 μm or less, or 50 μm or less. The width Dyp may be 15 μm or less, 10 μm or less, 5 μm or less, or 2 μm or less. The width Dyp may be 0.1 μm or more, or 1 μm or more.

[0171] 13 is a diagram showing the relationship between the forward voltage of the diode section 80 and the anode-cathode current when the width Dyp is changed. As shown in FIG. 13, the forward voltage Vf of the diode section 80 decreases as the width Dyp decreases. Note that when the width Dyp is reduced, the reverse recovery current shown in FIG. 11 tends to increase. As shown in FIG. 12, by reducing the width Dyp, the trade-off characteristics between the forward voltage Vf and the reverse recovery loss Err are improved.

[0172] 14 is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the forward surge current resistance (IFSM resistance) when the width Dyp is changed. As shown in FIG. 14, when the width Dyp is reduced, the forward voltage Vf decreases and the IFSM resistance improves.

[0173] Fig. 15 is a diagram showing an example of the A-A cross section shown in Fig. 4. The A-A cross section is a YZ plane passing through the first cathode region 81 and the second cathode region 82. Fig. 15 shows the vicinity of the lower surface 23 of the semiconductor substrate 10, and omits the structure on the upper surface 21 side. Furthermore, although the semiconductor substrate 10 in Fig. 15 is provided with a buffer region 20, a drift region 18 may be provided instead of the buffer region 20.

[0174] On the lower surface 23 of the semiconductor substrate 10, the first cathode regions 81 and the second cathode regions 82 are alternately provided along the Y-axis direction. The width of the first cathode region 81 in the depth direction (Z-axis direction) is designated Z1, and the width of the second cathode region 82 in the depth direction is designated Z2. The width Z1 may be the maximum width of the first cathode region 81 in the depth direction. The width Z2 may be the maximum width of the second cathode region 82 in the depth direction.

[0175] The second cathode region 82 is formed by implanting P-type dopant ions into the lower surface 23 of the semiconductor substrate 10 and performing a heat treatment. The second cathode region 82 and the collector region 22 of the transistor section 70 may be formed simultaneously by implanting P-type dopant ions into the entire lower surface 23. The second cathode region 82 may have the same doping concentration as the collector region 22.

[0176] After forming a P-type region over the entire lower surface 23, N-type dopant ions are locally implanted and heat-treated to form the first cathode region 81. The width Z1 of the first cathode region 81 in the depth direction may be smaller than the width Z2 of the second cathode region 82 in the depth direction.

[0177] By locally implanting N-type dopant ions and then performing a heat treatment, the P-type dopant also diffuses in the Y-axis direction. Therefore, if the width Dyp of the second cathode region 82 is designed to be too large, the first cathode region 81 will disappear due to the diffusion of the P-type dopant. It is preferable that the first cathode region 81 be large enough to remain even if the diffusion of the P-type dopant in the Y-axis direction becomes large due to manufacturing variations, etc.

[0178] The width Dyp of one second cathode region 82 in the Y-axis direction may be larger than the width Z2 of the second cathode region 82 in the Z-axis direction. Increasing the width Dyp makes it easier for the first cathode region 81 to remain. The width Dyp may be 1.5 times or more, 2 times or more, 3 times or more, or 5 times or more the width Z2.

[0179] The width Dyp of one second cathode region 82 in the Y-axis direction may be larger than the width Z1 of the first cathode region 81 in the Z-axis direction. The larger the width Z1, the more likely the first cathode region 81 will expand in the Y-axis direction. Therefore, by setting the width Dyp according to the width Z1, the first cathode region 81 will be more likely to remain. The width Dyp may be 1.5 times or more, 2 times or more, 3 times or more, or 5 times or more of the width Z1.

[0180] The first cathode region 81 has an upper surface 86 in the depth direction. The upper surface 86 may be a region of the surface of the first cathode region 81 whose normal intersects with the upper surface 21 of the semiconductor substrate 10. In this example, the upper surface 86 has a flat portion 87 whose distance from the lower surface 23 of the semiconductor substrate 10 is uniform. The flat portion 87 includes a portion whose distance from the lower surface 23 is the maximum width Z1 of the first cathode region 81. The flat portion 87 may refer to a continuous region whose distance from the lower surface 23 is 90% or more of the maximum width Z1 of the first cathode region 81.

[0181] The distance Dyf in the Y-axis direction between the flat portions 87 of two first cathode regions 81 adjacent in the Y-axis direction may be greater than 1.6 times the distance Z1 between the flat portions 87 and the lower surface 23. The portion of the first cathode region 81 outside the flat portions 87 corresponds to the region into which the N-type dopant is diffused by heat treatment. The N-type dopant, such as phosphorus, diffuses in the Y-axis direction by approximately 0.8 times the width Z1 of the first cathode region 81. Therefore, by making the distance Dyf greater than 1.6 times the width Z1, it becomes easier to leave the second cathode region 82. The distance Dyf may be greater than 1.6 times the width Z1 by 1 μm or more, 2 μm or more, 5 μm or more, 10 μm or more, or 15 μm or more. The distance Dyf may be equal to or less than 1.6 times the width Z1 plus 50 μm, or may be equal to or less than 30 μm, or may be equal to or less than 15 μm.

[0182] The semiconductor device 100 may have a third cathode region 84. The third cathode region 84 is a P-type region that contacts the first cathode region 81 in the depth direction (Z-axis direction) from the lower surface 23 toward the upper surface 21 of the semiconductor substrate 10, and contacts the second cathode region 82 in a direction parallel to the lower surface 23 (X-axis direction or Y-axis direction). The third cathode region 84 in this example is a P-type region between the first cathode region 81 and the buffer region 20 in the Z-axis direction.

[0183] The doping concentration of the third cathode region 84 may be lower than the doping concentration of the second cathode region 82. The doping concentration of the third cathode region 84 may be lower than the doping concentration of the first cathode region 81. The second cathode region 82 and the third cathode region 84 may be formed simultaneously by the same ion implantation and annealing process. The PN junction surface between the second cathode region 82 and the buffer region 20 and the PN junction surface between the third cathode region 84 and the buffer region 20 may be located at the same depth from the lower surface 23. That is, the maximum depth from the lower surface 23 of the third cathode region 84 in contact with the first cathode region 81 may be the same as the maximum depth from the lower surface 23 of the second cathode region. Here, the phrase "the same maximum depth" may include a case where the maximum depths from the lower surface 23 differ by within a range of ±10%.

[0184] 16 is a diagram showing an example of the shape of the first cathode region 81 in a top view. Fig. 16 shows the shape of the first cathode region 81 on the lower surface 23 of the semiconductor substrate 10. The shapes of the first cathode region 81 and the second cathode region 82 in a top view shown in each drawing in this specification are the shapes on the lower surface 23 of the semiconductor substrate 10.

[0185] In this example, the first cathode region 81 has a straight first end side 88 and a straight second end side 89. The second end side 89 is inclined relative to the first end side 88. In this example, the first end side 88 is parallel to the Y-axis, and the second end side 89 is parallel to the X-axis. In this example, the first end side 88 and the second end side 89 are connected by a curved line 79. The straight end sides of the first cathode region 81 may be connected to each other by a curved line 79. In the example of FIG. 16 , the first cathode region 81 has a rectangular shape with four rounded corners. By including the curved lines 79 in the shape of the first cathode region 81, electric field concentration at the corner portions of the first cathode region 81 can be alleviated.

[0186] The radius of curvature of the curve 79 is defined as R. When the first cathode region 81 has multiple curves 79, the average radius of curvature of the multiple curves 79 may be defined as R. The width Dyp of the second cathode region 82 in the Y-axis direction may be smaller than the radius of curvature R of the curve 79. Reducing the width Dyp of the second cathode region 82 can adjust the reverse recovery loss Err and the forward voltage Vf. The radius of curvature R may be 5 μm or less, 4 μm or less, or 3 μm or less. The radius of curvature R may be 1 μm or more, or 2 μm or more.

[0187] 17 is a diagram showing another example of the YZ cross section. The YZ cross section in this example has a larger range in the Y-axis direction than the A-A cross section. The YZ cross section in this example includes more first cathode regions 81 and second cathode regions 82 than the A-A cross section shown in FIG.

[0188] 15 , a third cathode region 84 is provided between each first cathode region 81 and the buffer region 20. The third cathode region 84 may be provided in contact with an upper surface 86 of the first cathode region 81. The third cathode region 84 may cover the entire upper surface 86 of the first cathode region 81.

[0189] The upper surface 92 of the second cathode region 82 may be provided in contact with the buffer region 20. The PN junction surface between the second cathode region 82 and the buffer region 20 may be referred to as the upper surface 92. The upper surface 94 of the third cathode region 84 may be provided in contact with the buffer region 20. The PN junction surface between the third cathode region 84 and the buffer region 20 may be referred to as the upper surface 94. The upper surfaces 92 and 94 may be provided at the same depth from the lower surface 23. In this example, all of the upper surfaces 92 and all of the upper surfaces 94 are provided at the same depth from the lower surface 23. The depth position of the portion of the upper surface 92 that is farthest from the lower surface 23 may be referred to as the depth position of the upper surface 92. Similarly, the depth position of the portion of the upper surface 94 that is farthest from the lower surface 23 may be referred to as the depth position of the upper surface 94.

[0190] The third cathode region 84 may be connected to the second cathode region 82. The first cathode region 81 may be sandwiched between two second cathode regions 82 in a direction parallel to the lower surface 23 of the semiconductor substrate 10. The third cathode region 84 may be connected to the two second cathode regions 82 that sandwich the first cathode region 81.

[0191] In this example, the second cathode regions 82 and the third cathode regions 84 are alternately arranged in the Y-axis direction. In this case, the third cathode regions 84 are connected to one or more second cathode regions 82 adjacent to each other in the Y-axis direction. At the same depth position, the second cathode regions 82 and the third cathode regions 84 may have the same acceptor concentration or different acceptor concentrations. The second cathode regions 82 and the third cathode regions 84 may be formed simultaneously by the same ion implantation process and the same annealing process.

[0192] According to this example, the second cathode region 82 is provided deeper than the first cathode region 81. Furthermore, the third cathode region 84 is provided above the first cathode region 81. Therefore, when the diode section 80 is turned off, holes are more easily extracted via the second cathode region 82 and the third cathode region 84, shortening the reverse recovery time. This reduces the reverse recovery loss Err. Furthermore, during switching operations of the semiconductor device 100, a depletion layer may extend from the top surface 21, causing carrier depletion and resulting in oscillation of the voltage or current waveform. By providing the third cathode region 84 above the first cathode region 81, carrier depletion can be suppressed, thereby suppressing waveform oscillation.

[0193] 18 is a diagram showing an example of the chemical concentration distribution of phosphorus and boron in the first cathode region 81, the second cathode region 82, and the third cathode region 84. In this example, the second cathode region 82 and the third cathode region 84 are formed in the same process by implanting boron into the entire region where the cathode region 83 is to be formed. Furthermore, the first cathode region 81 is formed by selectively implanting phosphorus. Note that the dashed dotted line in FIG. 18 represents the doping concentration distribution in the B-B cross section of FIG. 17.

[0194] Because the activation rates of phosphorus and boron are very high, the phosphorus chemical concentration distribution almost coincides with the donor concentration distribution, and the boron chemical concentration distribution almost coincides with the acceptor concentration distribution. The buffer region 20 in this example is formed by implanting hydrogen ions. Therefore, the phosphorus chemical concentration in the buffer region 20 exhibits a flat distribution. The phosphorus chemical concentration in the buffer region 20 in this example corresponds to the bulk donor concentration.

[0195] In this example, phosphorus and boron are implanted near the lower surface 23 of the semiconductor substrate 10, and then the semiconductor substrate 10 is heat-treated to diffuse the phosphorus and boron in the depth direction. In this example, the phosphorus and boron are implanted at the same depth. Boron diffuses more easily inside the semiconductor substrate 10 than phosphorus. Therefore, boron diffuses to a deeper position than phosphorus.

[0196] The doping concentration in the second cathode region 82 is approximately equal to the chemical concentration of boron. The doping concentrations in the first cathode region 81 and the third cathode region 84 correspond to the difference between the chemical concentrations of phosphorus and boron. The region where the chemical concentration of phosphorus is higher than the chemical concentration of boron becomes the first cathode region 81, and the region where the chemical concentration of boron is higher than the chemical concentration of phosphorus becomes the third cathode region 84.

[0197] The first cathode region 81 may have a first concentration peak 221 of the dopant (phosphorus in this example) in the depth direction. The concentration peak is a portion where the concentration distribution exhibits a mountain-like shape. The concentration peak may have an apex and a base. The apex is a portion where the concentration exhibits a maximum value. The base is a portion where the concentration monotonically decreases with increasing distance from the apex. If the dopant concentration in the first cathode region 81 is at its maximum value at the lower surface 23 of the semiconductor substrate 10, the lower surface 23 may be considered to be the position of the apex of the first concentration peak 221. The first concentration peak 221 has a first base 231 where the dopant concentration monotonically decreases from the lower surface 23 to the upper surface 21.

[0198] The second cathode region 82 may have a second concentration peak 222 of the dopant (boron in this example) in the depth direction. If the dopant concentration in the second cathode region 82 is maximum at the lower surface 23 of the semiconductor substrate 10, the lower surface 23 may be the apex of the second concentration peak 222. The second concentration peak 222 has a second skirt 232 in which the dopant concentration monotonically decreases from the lower surface 23 to the upper surface 21. The boron chemical concentration of the second cathode region 82 may continuously decrease in the depth direction (Z-axis direction) of the second cathode region 82 from the lower surface 23 to at least the buffer region 20. "Continuously decreasing" may mean a monotonically decreasing decrease, or a smooth decrease without discontinuous portions (discontinuous points). This allows the boron chemical concentration distributions in both the second cathode region 82 and the third cathode region 84 to be formed smoothly. Note that the values ​​of adjacent measurement points in SR measurement, SIMS measurement, etc. may be discontinuous. In other words, when a measurement device or the like measures discretely arranged measurement points, the measured values ​​may be discrete (discontinuous).

[0199] As described above, the second skirt 232 is formed deeper than the first skirt 231. The region of the second skirt 232 where the concentration is higher than the concentration of the first skirt 231 becomes the third cathode region 84. According to this example, the second cathode region 82 and the third cathode region 84 can be formed in the same process, thereby simplifying the manufacturing process of the semiconductor device 100. This makes it possible to suppress variations in the performance of the semiconductor device 100 and reduce manufacturing costs.

[0200] Fig. 19 is a diagram showing an example of the doping concentration distribution along line BB in Fig. 17. Line BB is a straight line parallel to the Z axis that passes through the first cathode region 81 and the third cathode region 84. Unlike the example in Fig. 18, the semiconductor device 100 of this example has donors such as phosphorus and acceptors such as boron implanted at different depths.

[0201] The first cathode region 81 of this example has a first concentration peak 201 of the doping concentration in the depth direction. As described above, a first concentration peak of a dopant such as phosphorus is provided at the same depth position Zn as the first concentration peak 201.

[0202] In this example, the third cathode region 84 has a third concentration peak 204 of doping concentration in the depth direction. As described above, a third concentration peak of a dopant, such as boron, is provided at the same depth position Zp as the third concentration peak 204. The depth position Zp is provided at a position deeper than the depth position Zn. In this specification, the terms "deep" and "shallow" refer to positions based on the closer surface, either the top surface 21 or the bottom surface 23, of the semiconductor substrate 10. For example, the depth position Zp located on the bottom surface 23 side of the semiconductor substrate 10 is located at a greater distance from the bottom surface 23 than the depth position Zn, and is therefore provided deeper than the depth position Zn.

[0203] The chemical concentration distribution of boron forming the third cathode region 84 is indicated by a dashed-dotted line. The boron chemical concentration distribution of the third cathode region 84 may vary continuously from the lower surface 23 to at least the buffer region 20. "Varying continuously" may mean that the concentration varies smoothly without any discontinuous portions (discontinuous points). Note that, for multiple adjacent measurement points in SR measurement, SIMS measurement, etc., the values ​​at the measurement points may be discontinuous.

[0204] The buffer region 20 may have one or more concentration peaks 203 of doping concentration in the depth direction. The concentration peaks 203 may be concentration peaks of hydrogen donors.

[0205] Fig. 20 is a diagram showing an example of the doping concentration distribution along line CC in Fig. 17. Line CC is a straight line parallel to the Z axis that passes through the second cathode region 82. In this example, the second cathode region 82 has a second concentration peak 202 of the doping concentration in the depth direction.

[0206] The depth position of the second concentration peak 202 may be the same as the depth position Zp of the third concentration peak 204. In this case, the depth position Zp of the second concentration peak 202 is deeper than the depth position Zn of the first concentration peak 201. Furthermore, the second cathode region 82 and the third cathode region 84 can be manufactured using the same process. The doping concentration distribution of the second cathode region 82 may vary continuously from the lower surface 23 to at least the buffer region 20. "Continuously varying" may mean a smooth change without discontinuous portions (discontinuous points). For example, the dotted line in FIG. 20 indicates a case where discontinuous points are present. In other words, a discontinuous concentration distribution refers to a distribution in which the concentration suddenly increases or decreases at a certain depth position, resulting in an extremely large absolute value of the differential value of the concentration distribution. Note that, for multiple adjacent measurement points in SR measurement, SIMS measurement, etc., the values ​​at the measurement points may be discontinuous.

[0207] In another example, the depth position of the second concentration peak 202 may be different from the depth position Zp of the third concentration peak 204. In this case, the second cathode region 82 and the third cathode region 84 are formed in different processes. The second cathode region 82 and the third cathode region 84 may each be formed by selectively implanting a dopant such as boron in the XY plane. In this case, the position and thickness of the third cathode region 84 in the depth direction can be set independently of the position and thickness of the second cathode region 82.

[0208] 21 is a diagram showing another example of the YZ cross section. In this example, the position of the upper surface 92 of the second cathode region 82 and the position of the upper surface 94 of the third cathode region 84 are different in the depth direction of the semiconductor substrate 10. The other structure is similar to any of the examples described in this specification. As described above, in this example, the second cathode region 82 and the third cathode region 84 may be formed by implanting dopants at different depth positions in different processes.

[0209] 21 , the position of the upper surface 92 of the second cathode region 82 is deeper than the position of the upper surface 94 of the third cathode region 84. This allows the thickness of the third cathode region 84 in the depth direction to be reduced. Reducing the thickness of the third cathode region 84 can promote carrier injection from the first cathode region 81 and suppress waveform oscillation during switching operation. In particular, this can promote carrier injection when the diode section 80 is turned on, and reduce the peak voltage in the transient waveform of the forward voltage.

[0210] The thickness of the third cathode region 84 may be less than 1 time, 0.5 times or less, or 0.25 times or less the thickness of the first cathode region 81. In other examples described in this specification, the relationship between the thickness of the third cathode region 84 and the thickness of the first cathode region 81 may be the same as in this example. The thickness of each region may be the thickness at the center of each region in the Y-axis direction.

[0211] The distance in the depth direction between the upper surface 92 and the upper surface 94 may be 0.1 times or more, 0.2 times or more, or 0.5 times or more the thickness of the third cathode region 84. The distance may be 2 times or less the thickness of the third cathode region 84, or 1 time or less.

[0212] 22 is a diagram showing another example of a YZ cross section. In this example, the position of the upper surface 92 of the second cathode region 82 is shallower than the position of the upper surface 94 of the third cathode region 84. The other structure is similar to the example of FIG. 21. By making the third cathode region 84 deeper, holes above the first cathode region 81 are more easily extracted. Furthermore, when the diode section 80 is in the on state, holes above the upper surface 94 move along the upper surface 94, reach the second cathode region 82, and are more likely to be extracted to the collector electrode 24.

[0213] The thickness of the third cathode region 84 may be 0.25 times or more, 0.5 times or more, or 1 time or more that of the first cathode region 81. The thickness of the third cathode region 84 may be 2 times or less, or 1.5 times or less that of the first cathode region 81.

[0214] The distance in the depth direction between the upper surface 92 and the upper surface 94 may be 0.1 times or more, 0.2 times or more, or 0.5 times or more the thickness of the third cathode region 84. The distance may be 2 times or less the thickness of the third cathode region 84, or 1 time or less.

[0215] 23 is a diagram showing another example of the YZ cross section. In this example, the position of the upper surface 94 of some of the third cathode regions 84-1 is deeper than the position of the upper surface 94 of some of the other third cathode regions 84-2. The other structure is similar to any of the examples described in this specification.

[0216] In this example, the position of the upper surface 94 of the third cathode region 84-2 is shallower than the position 92 of the upper surface of the second cathode region 82. Furthermore, the position of the upper surface 94 of the third cathode region 84-1 is deeper than the position of the upper surface 92 of the second cathode region 82. The third cathode regions 84-1 and the third cathode regions 84-2 may be arranged alternately in the Y-axis direction. The second cathode region 82 is arranged between the third cathode region 84-1 and the third cathode region 84-2.

[0217] With this configuration, it is possible to obtain the effects of the example in Figure 21 and the effects of the example in Figure 22. In the Y-axis direction, the width of the third cathode region 84-1 may be smaller than, larger than, or the same as the width of the third cathode region 84-2. The structure of the third cathode region 84-1, such as its thickness, may be the same as that of the example in Figure 22. The structure of the third cathode region 84-2, such as its thickness, may be the same as that of the example in Figure 21.

[0218] The thickness of the third cathode region 84-1 in the depth direction may be different from the thickness of the other third cathode region 84-2 in the depth direction. In the example of FIG. 23 , the thickness of the third cathode region 84-1 is greater than the thickness of the third cathode region 84-2. In another example, the thickness of the third cathode region 84-1 may be the same as the thickness of the third cathode region 84-2. In this case, the thickness of the first cathode region 81 below the third cathode region 84-1 may be greater than the thickness of the first cathode region 81 below the third cathode region 84-2. This allows the position of the upper surface 94 of the third cathode region 84-1 to be deeper than the position of the upper surface 94 of the third cathode region 84-2.

[0219] 24 is a diagram showing another example of the YZ cross section. In this example, the thickness in the depth direction of the first cathode region 81-1 is different from the thickness in the depth direction of the other first cathode region 81-2. The other structure is similar to any of the examples described in this specification.

[0220] In this example, the thickness of the first cathode region 81-1 is smaller than the thickness of the first cathode region 81-2. The first cathode region 81-1 and the first cathode region 81-2 may be arranged alternately in the Y-axis direction. The upper surface 94 of the third cathode region 84 above the first cathode region 81-1 may be provided at the same depth as the upper surface 94 of the third cathode region 84 above the first cathode region 81-2. In this case, the third cathode region 84 above the first cathode region 81-1 is thicker than the third cathode region 84 above the first cathode region 81-2. Even with this configuration, the same effect as the example of FIG. 23 can be obtained.

[0221] FIG. 25 is a diagram showing another example of the YZ cross section. In this example, a third cathode region 84 is provided in contact with an upper surface 86 of at least one first cathode region 81-1. Furthermore, the third cathode region 84 is not provided on an upper surface 86 of at least one first cathode region 81-2. The position of the upper surface 86 of the first cathode region 81-2 is deeper than the position of the upper surface 94 of the third cathode region 84. The other structures are similar to any of the examples described in this specification. Even with this configuration, it is possible to obtain the same effects as the example of FIG. 23.

[0222] An upper surface 86 of the first cathode region 81-2 may be disposed deeper than an upper surface 92 of the second cathode region 82. In this example, the upper surface 86 of the first cathode region 81-2 contacts the buffer region 20 or the drift region 18.

[0223] 26 is a diagram showing another example of the YZ cross section. In this example, the position of the upper surface 92 of each second cathode region 82 is deeper than the position of the upper surface 86 of the first cathode region 81. Furthermore, the position of the upper surface 92 of any one of the second cathode regions 82-1 is deeper than the position of the upper surface 92 of any other one of the second cathode regions 82-2. In this example, the third cathode region 84 is not provided. According to this example, the ease of hole extraction can be adjusted by the position in the Y-axis direction.

[0224] Of the multiple second cathode regions 82, the width in the Y-axis direction of the second cathode region 82-1 whose top surface 92 is located at the deepest position may be larger than the width in the Y-axis direction of any of the other second cathode regions 82-2. This can further promote extraction of holes.

[0225] 27 is a diagram showing an example of the G-G cross section in FIG. 1. The G-G cross section is a YZ cross section passing through the diode section 80 and the peripheral gate wiring 130. The peripheral gate wiring 130 in this example has semiconductor wiring 132 and metal wiring 133. The semiconductor wiring 132 is made of a semiconductor such as polysilicon doped with impurities. The metal wiring 133 is made of a metal such as aluminum.

[0226] The metal wiring 133 is arranged outside the emitter electrode 52. The semiconductor wiring 132 is arranged below the metal wiring 133 so as to overlap partially or entirely with the metal wiring 133. In this example, the semiconductor wiring 132 also extends below the emitter electrode 52. An interlayer insulating film 38 is provided between the semiconductor wiring 132 and the metal wiring 133 and emitter electrode 52. The interlayer insulating film 38 is also provided between the semiconductor wiring 132 and the metal wiring 133 and the semiconductor substrate 10. The semiconductor wiring 132 and the metal wiring 133 are electrically connected by contact holes provided in the interlayer insulating film 38.

[0227] A well region 11 is provided in the semiconductor substrate 10 below the peripheral gate wiring 130. The well region 11 is in contact with the upper surface 21 of the semiconductor substrate 10 and is formed deeper than the base region 14. The well region 11 may have a higher doping concentration than the base region 14. The well region 11 may be provided so as to overlap the entire semiconductor wiring 132.

[0228] The cathode region 83 may be provided from the diode portion 80 to below the well region 11. The cathode region 83 may extend beyond the well region 11. At least one first cathode region 81 may be provided beyond the well region 11. At least one second cathode region 82 may be provided beyond the well region 11. At least one third cathode region 84 may be provided beyond the well region 11. The cathode region 83 is similar to any of the examples described herein. The cathode region 83 in FIG. 27 has a first cathode region 81, a second cathode region 82, and a third cathode region 84. According to this example, holes injected from the well region 11 can be efficiently extracted.

[0229] 28 is a diagram showing another example of the G-G cross section. The semiconductor device 100 of this example differs from the other examples in this specification in that it is provided on the lower surface 23 side of the semiconductor substrate 10 and includes a lifetime adjusting region 210 in which the carrier lifetime exhibits a minimum value. The other structures are similar to any of the examples described in this specification.

[0230] The lifetime adjusting region 210 can be formed by injecting charged particles such as helium into the semiconductor substrate 10. By injecting charged particles into the semiconductor substrate 10, carrier recombination centers 211 are formed at the locations, thereby reducing the carrier lifetime.

[0231] The lifetime adjusting region 210 is provided in at least a part of the diode section 80. The lifetime adjusting region 210 may be provided in the entire diode section 80 in a top view. The lifetime adjusting region 210 may extend to below the well region 11, or may extend to the outside of the well region 11.

[0232] The third cathode region 84 is disposed between the lifetime adjusting region 210 and the lower surface 23. The lifetime adjusting region 210 in this example is provided in the buffer region 20. The second cathode region 82 may also be disposed between the lifetime adjusting region 210 and the lower surface 23. According to this example, the lifetime of holes can be shortened when the diode section 80 is turned off, and therefore the reverse recovery loss Err can be further reduced.

[0233] FIG. 29 is a diagram showing the relationship between the forward voltage Vf of the diode section 80 and the reverse recovery loss Err. FIG. 29 shows the relationship between the forward voltage Vf and the reverse recovery loss Err of the semiconductor devices according to Examples 1, 2, 3, and 4. Examples 1 to 3 are examples in which the lifetime adjusting region 210 is not provided, and Example 4 is an example in which the lifetime adjusting region 210 is provided. Example 1 is an example in which the first cathode region 81 is provided, but the second cathode region 82 and the third cathode region 84 are not provided. Example 2 is an example in which the first cathode region 81 and the second cathode region 82 are provided, but the third cathode region 84 is not provided. Examples 3 and 4 are examples in which the first cathode region 81, the second cathode region 82, and the third cathode region 84 are provided.

[0234] 29, the reverse recovery loss Err can be reduced by providing the second cathode region 82. Moreover, the reverse recovery loss Err can be further reduced by providing the third cathode region 84. Moreover, the reverse recovery loss Err can be further reduced by providing the lifetime adjusting region 210.

[0235] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0236] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0237] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 41...Tip portion, 42...Gate insulating film, 44...Gate conductive portion, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa portion, 70...Transistor portion, 79...Curve, 80...Diode portion, 81...First cathode region, 82...Second 2 cathode region, 83... cathode region, 84... third cathode region, 85... repeating structure, 86... upper surface, 87... flat portion, 88... first edge, 89... second edge, 90... boundary, 92... upper surface, 94... upper surface, 100... semiconductor device, 130... peripheral gate wiring, 131... active side gate wiring, 132... semiconductor wiring, 133... metal wiring, 150... edge termination structure portion, 160... active portion, 162... edge, 164... gate pad, 201... first concentration peak, 202... second concentration peak, 203... concentration peak, 204... third concentration peak, 210... lifetime adjusting region, 211... recombination center, 221... first concentration peak, 222... second concentration peak, 231... first skirt portion, 232... second skirt portion

Claims

1. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section having a length in a first direction provided in the semiconductor substrate, wherein the diode section has: a drift region of a first conductivity type provided in the semiconductor substrate; a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate, wherein the first cathode regions and the second cathode regions are repeatedly provided in the first direction, and one or more first cathode regions are provided on the lower surface of the semiconductor substrate in a second direction intersecting the first direction, and a length Lx between both ends of the one or more first cathode regions in the second direction and a width Dyn of one of the first cathode regions in the first direction satisfy the following formula: 0.001<Dyn / Lx≦0.

1.

2. The semiconductor device according to claim 1, wherein on the lower surface, the total area Sn of the first cathode regions and the total area Sp of the second cathode regions satisfy the following formula: 0.1≦Sn / (Sn+Sp)<1.

3. The semiconductor device according to claim 2, wherein the total area Sn and the total area Sp satisfy the following formula: 0.4≦Sn / (Sn+Sp)<0.

8.

4. The semiconductor device according to claim 2, wherein the total area Sn and the total area Sp satisfy the following formula: 0.5≦Sn / (Sn+Sp)<0.

75.

5. The semiconductor device according to claim 1, wherein the width Dyp of one of the second cathode regions in the first direction and the width Dyn of one of the first cathode regions in the first direction satisfy the following formula: 0.1≦Dyn / (Dyn+Dyp)<1.

6. The semiconductor device according to claim 5, wherein the width Dyp and the width Dyn satisfy the following formula: 0.4≦Dyn / (Dyn+Dyp)<0.

8.

7. The semiconductor device according to claim 5, wherein the width Dyp and the width Dyn satisfy the following formula: 0.5≦Dyn / (Dyn+Dyp)<0.

75.

8. The semiconductor device according to claim 1, wherein the width Dyn of one of the first cathode regions in the first direction is larger than the width Dyp of one of the second cathode regions in the first direction.

9. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section having a length in a first direction provided in the semiconductor substrate, wherein the diode section has: a drift region of a first conductivity type provided in the semiconductor substrate; a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate, wherein the first cathode regions and the second cathode regions are repeatedly provided in the first direction, and one or more first cathode regions are provided on the lower surface of the semiconductor substrate in a second direction intersecting with the first direction, and a length Lx between both ends of one or more first cathode regions in the second direction and a width Dyn of one first cathode region in the first direction satisfy the following formula: 0.001<Dyn / Lx≦0.4 A semiconductor device, wherein on the lower surface, a total area Sn of the first cathode regions and a total area Sp of the second cathode regions satisfy the following formula: 0.5≦Sn / (Sn+Sp)<0.

75.

10. A semiconductor device according to any one of claims 1 to 9, wherein the first cathode regions are arranged discretely in both the first direction and the second direction, and the spacing between the first cathode regions at the center of the diode section in the second direction is smaller than the spacing between the first cathode regions at the ends of the diode section in the second direction.

11. The semiconductor device according to claim 10, wherein the width Dxn in the second direction of one of the first cathode regions at the center in the second direction of the diode section is smaller than the width Dxn in the second direction of one of the first cathode regions at an end in the second direction of the diode section.

12. The semiconductor device according to claim 11, wherein the width in the second direction of one of the first cathode regions arranged at the end of the diode section in the second direction is greater than the width in the first direction.

13. The semiconductor device according to any one of claims 1 to 9, wherein the width of one of the second cathode regions in the first direction is greater than the width of the first cathode region in the depth direction of the semiconductor substrate.

14. The semiconductor device according to any one of claims 1 to 9, wherein the width of one of the second cathode regions in the first direction is greater than the width of the second cathode region in the depth direction of the semiconductor substrate.

15. A semiconductor device described in any one of claims 1 to 9, wherein the upper surface of the first cathode region in the depth direction has a flat portion that is at a uniform distance from the lower surface of the semiconductor substrate, and the distance between the flat portions of two first cathode regions adjacent to each other in the first direction is greater than 1.6 times the distance between the flat portion and the lower surface.

16. A semiconductor device according to any one of claims 1 to 9, wherein on the lower surface of the semiconductor substrate, the first cathode region includes a first straight edge and a second straight edge that is inclined relative to the first edge, and the first edge and the second edge are connected by a curve.

17. The semiconductor device according to claim 16, wherein the width Dyp of one of the second cathode regions in the first direction is smaller than the radius of curvature of the curve.

18. A semiconductor device according to any one of claims 1 to 9, wherein the semiconductor substrate is provided with transistor sections arranged alternately with the diode sections in the second direction, and the transistor sections have a plurality of gate trench sections on the top surface of the semiconductor substrate, the longitudinal direction of which extends in the first direction.

19. The semiconductor device according to any one of claims 1 to 9, further comprising a third cathode region of the second conductivity type provided in contact with an upper surface of the first cathode region.

20. The semiconductor device according to claim 19, wherein the third cathode region is connected to the second cathode region.

21. The semiconductor device according to claim 20, wherein the first cathode region is sandwiched between two of the second cathode regions in a direction parallel to the lower surface of the semiconductor substrate, and the third cathode region is connected to the two second cathode regions that sandwich the first cathode region.

22. The semiconductor device according to claim 19, wherein the position of the upper surface of the second cathode region and the position of the upper surface of the third cathode region are different in the depth direction of the semiconductor substrate.

23. A semiconductor device according to any one of claims 1 to 9, wherein the diode section has a plurality of the first cathode regions, and the thickness in the depth direction of any one of the first cathode regions is different from the thickness in the depth direction of any other one of the first cathode regions.

24. The semiconductor device according to claim 23, further comprising a third cathode region of the second conductivity type provided in contact with the upper surface of each of the first cathode regions.

25. The semiconductor device described in claim 23, further comprising a third cathode region of the second conductivity type provided in contact with an upper surface of at least one of the first cathode regions, wherein the third cathode region is not provided on the upper surface of at least one of the first cathode regions, and the position of the upper surface of the first cathode region not provided with the third cathode region is deeper than the position of the upper surface of the third cathode region.

26. A semiconductor device according to any one of claims 1 to 9, wherein the position of the upper surface of each of the second cathode regions is deeper than the position of the upper surface of the first cathode region, and the position of the upper surface of any of the second cathode regions is deeper than the position of the upper surface of any other of the second cathode regions.

27. The semiconductor device described in claim 26, wherein the width in the first direction of the second cathode region whose top surface is located at the deepest position among the plurality of second cathode regions is greater than the width in the first direction of any of the other second cathode regions.

28. The semiconductor device according to claim 19, further comprising a lifetime adjusting region provided on the lower surface side of the semiconductor substrate, in which the carrier lifetime exhibits a minimum value, and the third cathode region is disposed between the lifetime adjusting region and the lower surface.

29. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section having a length in a first direction provided in the semiconductor substrate, wherein the diode section comprises: a drift region of a first conductivity type provided in the semiconductor substrate; a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate; and a third cathode region of the second conductivity type provided in contact with the upper surface of the first cathode region, wherein the position of the upper surface of the second cathode region differs from the position of the upper surface of the third cathode region in the depth direction of the semiconductor substrate.

30. The semiconductor device according to claim 29, wherein the upper surface of the second cathode region is located deeper than the upper surface of the third cathode region.

31. The semiconductor device according to claim 29, wherein the position of the upper surface of the second cathode region is shallower than the position of the upper surface of the third cathode region.

32. The semiconductor device according to claim 29, wherein the position of the upper surface of some of the third cathode regions is shallower than the position of the upper surface of the second cathode regions, and the position of the upper surface of other parts of the third cathode regions is deeper than the position of the upper surface of the second cathode regions.

33. The semiconductor device according to claim 32, wherein the diode section has a plurality of the first cathode regions and a plurality of the third cathode regions, and the thickness of any one of the third cathode regions in the depth direction is different from the thickness of any other one of the third cathode regions in the depth direction.

34. A semiconductor device according to any one of claims 29 to 33, wherein the first cathode region has a first concentration peak of dopant in the depth direction, the second cathode region has a second concentration peak of dopant in the depth direction, and the second concentration peak is located at a deeper position than the first concentration peak.

35. A semiconductor device as described in any one of claims 29 to 33, wherein the first cathode region has a first concentration peak of dopant in the depth direction, the second cathode region has a second concentration peak of dopant in the depth direction, the first concentration peak includes a first skirt portion whose concentration monotonically decreases toward the upper surface of the semiconductor substrate, and the second concentration peak includes a second skirt portion whose concentration monotonically decreases toward the upper surface of the semiconductor substrate, and the second skirt portion is provided deeper than the first skirt portion.

36. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, and a diode section having a length in a first direction provided in the semiconductor substrate, wherein the diode section comprises: a drift region of a first conductivity type provided in the semiconductor substrate; a first cathode region of the first conductivity type provided in contact with the lower surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second cathode region of a second conductivity type provided in contact with the lower surface of the semiconductor substrate; and a third cathode region of a second conductivity type that contacts the first cathode region in a depth direction from the lower surface toward the upper surface of the semiconductor substrate and contacts the second cathode region in a direction parallel to the lower surface, wherein the first cathode region and the second cathode region are repeatedly provided in the first direction.

37. The semiconductor device according to claim 36, wherein the maximum depth from the lower surface of the third cathode region in contact with the first cathode region is the same as the maximum depth from the lower surface of the second cathode region.

38. The semiconductor device according to claim 36, wherein the acceptor chemical concentration profile in the second cathode region is smooth without any discontinuities.

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