Display device

Abstract

The present invention provides a display device comprising: a pixel unit including sub-pixel circuits arranged in a row direction and a column direction, and data lines corresponding to the sub-pixel circuits; a data driving circuit for outputting a data signal through output lines; a data distribution unit for selectively connecting the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal; and a control circuit for alternately outputting the first control signal and the second control signal. The data lines include: a first data line and a second data line which are adjacent to each other and receive corresponding data signals by different control signals among the first control signal and the second control signal; and a third data line and a fourth data line which are adjacent to each other and receive corresponding data signals by the same control signal among the first control signal and the second control signal. The first data line and the second data line are spaced apart from each other while having at least one sub-pixel circuit column therebetween, and two adjacent data lines among the first data line, the second data line, the third data line, and the fourth data line are arranged to face each other.

Description

display device

[0001] Embodiments of the present invention relate to a display device.

[0002] A display device may include a plurality of pixels. Each pixel may include a light-emitting diode and a pixel circuit for controlling the brightness of the light-emitting diode, etc. The pixel circuit may include transistors and capacitors connected to wires such as data lines, gate lines, and voltage lines.

[0003] In order to apply a data signal to each of the multiple data lines, the data driver must be equipped with a number of output lines corresponding to the number of data lines, and there is a problem that manufacturing costs increase as multiple integrated circuits are required.

[0004] Embodiments of the present invention provide a display device capable of reducing the number of output lines of a data driver. Furthermore, embodiments of the present invention provide a display device capable of reducing image quality degradation due to interference between adjacent data lines. The purpose of this disclosure is to provide such a display device. However, these tasks are exemplary and are not intended to limit the scope of the present invention.

[0005] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0006] According to one aspect of the present invention, a pixel unit including subpixel circuits arranged in a row direction and a column direction and data lines connected to the corresponding subpixel circuits, a data driving circuit outputting a data signal through output lines, a data distribution unit selectively connecting the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal, and a control circuit alternately outputting the first control signal and the second control signal, wherein the data lines include a first data line and a second data line that are adjacent to each other and receive corresponding data signals by different control signals among the first control signal and the second control signal, and a third data line and a fourth data line that are adjacent to each other and receive corresponding data signals by the same control signal among the first control signal and the second control signal, wherein the first data line and the second data line are arranged to be spaced apart from each other with at least one subpixel circuit column therebetween, and the first data line, the second data line, the third data line, and A display device is provided in which two adjacent data lines among the above-mentioned fourth data lines are arranged facing each other.

[0007] In one embodiment, each of the data lines may be arranged on a first side or a second side of a corresponding subpixel circuit row, the third data line may be arranged on the second side of the corresponding subpixel circuit row, and the fourth data line may be arranged on the first side of the corresponding subpixel circuit row.

[0008] In one embodiment, the data lines further include a fifth data line and a sixth data line, the fifth data line and the sixth data line are adjacent to each other and receive corresponding data signals according to the same control signal among the first control signal and the second control signal, the fifth data line is connected to a first output line among the output lines by the first control signal, the sixth data line is connected to a second output line among the output lines by the first control signal, the first data line is connected to a third output line among the output lines by the first control signal, the second data line is connected to the first output line by the second control signal, the third data line is connected to the second output line by the second control signal, and the fourth data line is connected to the third output line by the second control signal.

[0009] In one embodiment, each of the first data line and the second data line may be arranged on the first side of the corresponding subpixel circuit row.

[0010] In one embodiment, a subpixel circuit row corresponding to the first data line may be arranged between the first data line and the second data line.

[0011] In one embodiment, the fifth data line may be arranged on the first side of the corresponding subpixel circuit row, and the sixth data line may be arranged on the second side of the corresponding subpixel circuit row.

[0012] In one embodiment, the subpixel circuit column corresponding to the fifth data line and the subpixel circuit column corresponding to the sixth data line can overlap on one driving voltage line.

[0013] In one embodiment, the first data line may be arranged on the first side of the corresponding subpixel circuit row, and the second data line may be arranged on the second side of the corresponding subpixel circuit row.

[0014] In one embodiment, the subpixel circuit column corresponding to the first data line and the subpixel circuit column corresponding to the second data line can overlap on one driving voltage line.

[0015] In one embodiment, the fifth data line and the sixth data line may be arranged facing each other.

[0016] According to another aspect of the present invention, a pixel unit including subpixel circuits repeatedly arranged in a row direction and a column direction, data lines connected to the corresponding subpixel circuits, and first voltage transmission lines extending in the column direction, a data driving circuit outputting a data signal through output lines, a data distribution unit selectively connecting the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal, and a control circuit alternately outputting the first control signal and the second control signal, wherein the data lines include first groups and second groups, each of the first groups including a first data line, a second data line, and a third data line supplied with a data signal by the first control signal and sequentially arranged in the row direction, each of the second groups including a fourth data line, a fifth data line, and a sixth data line supplied with a data signal by the second control signal and sequentially arranged in the row direction, and wherein the first group and the second group They are arranged alternately in the above row direction, and one of the first voltage transmission lines can be arranged between the third data line and the fourth data line.

[0017] In one embodiment, each of the data lines may be arranged on a first side or a second side of a corresponding subpixel circuit row, each of the odd-numbered data lines among the data lines may be arranged on the second side of the corresponding subpixel circuit row, and each of the even-numbered data lines among the data lines may be arranged on the first side of the corresponding subpixel circuit row.

[0018] In one embodiment, the first data line may be connected to a first output line among the output lines by the first control signal, the second data line may be connected to a second output line among the output lines by the first control signal, the third data line may be connected to a third output line among the output lines by the first control signal, the fourth data line may be connected to the first output line by the second control signal, the fifth data line may be connected to the second output line by the second control signal, and the sixth data line may be connected to the third output line by the second control signal.

[0019] In one embodiment, the pixel portion further includes second voltage transmission lines extending in the row direction, and the first voltage transmission lines can be connected to the second voltage transmission lines.

[0020] In one embodiment, six data lines may be arranged between two adjacent first voltage transmission lines among the first voltage transmission lines.

[0021] According to another aspect of the present invention, a pixel unit including subpixel circuits repeatedly arranged in a row direction and a column direction, data lines connected to corresponding subpixel circuits, and first voltage transmission lines extending in the column direction, a data driving circuit outputting a data signal through output lines, a data distribution unit selectively connecting the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal, and a control circuit alternately outputting the first control signal and the second control signal, wherein the data lines include first groups and second groups, each of the first groups including a first data line, a second data line, and a third data line connected to corresponding output lines by the first control signal and sequentially arranged in the row direction, each of the second groups including a fourth data line, a fifth data line, and a sixth data line connected to corresponding output lines by the second control signal and sequentially arranged in the row direction, and wherein the first group and the A display device is provided in which the second group is arranged alternately in the row direction, and one of the first voltage transmission lines is arranged between the sixth data line and the first data line.

[0022] In one embodiment, each of the data lines may be arranged on a first side or a second side of a corresponding subpixel circuit row, and each of the odd-numbered data lines among the data lines may be arranged on the first side of the corresponding subpixel circuit row, and each of the even-numbered data lines among the data lines may be arranged on the second side of the corresponding subpixel circuit row.

[0023] In one embodiment, the first data line may be connected to a first output line among the output lines by the first control signal, the second data line may be connected to a second output line among the output lines by the first control signal, the third data line may be connected to a third output line among the output lines by the first control signal, the fourth data line may be connected to the first output line by the second control signal, the fifth data line may be connected to the second output line by the second control signal, and the sixth data line may be connected to the third output line by the second control signal.

[0024] In one embodiment, the pixel portion further includes second voltage transmission lines extending in the row direction, and the first voltage transmission lines can be connected to the second voltage transmission lines.

[0025] In one embodiment, six data lines may be arranged between two adjacent first voltage transmission lines among the first voltage transmission lines.

[0026] Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims and detailed description of the invention.

[0027] According to one embodiment of the present invention, as described above, a display device capable of displaying high-quality images can be implemented while reducing the number of output lines of the data driver. Of course, the scope of the present invention is not limited by these effects.

[0028] The above-described aspects, features and effects of specific embodiments can be more clearly understood by referring to the present specification and drawings.

[0029] FIG. 1 is a plan view schematically illustrating a display device according to one embodiment of the present invention.

[0030] FIGS. 2A to 2C are each an equivalent circuit diagram schematically showing one subpixel included in a display device in one embodiment of the present invention.

[0031] FIG. 3 is a drawing schematically showing a display device according to one embodiment of the present invention.

[0032] FIG. 4 is a drawing schematically illustrating a demultiplexer according to one embodiment of the present invention.

[0033] Figure 5 is a timing diagram explaining the operation of the demultiplexer illustrated in Figure 4.

[0034] Fig. 6 is a drawing schematically explaining the pixel portion and data distribution portion of the display device illustrated in Fig. 3.

[0035] FIG. 7 is a plan view schematically illustrating subpixel circuits and data lines according to one embodiment of the present invention.

[0036] FIG. 8 is a plan view schematically illustrating driving voltage lines and data lines according to one embodiment of the present invention.

[0037] FIG. 9 is a drawing schematically illustrating a pixel portion and a data distribution portion of a display device according to one embodiment of the present invention.

[0038] FIG. 10 is a drawing schematically illustrating first voltage transmission lines and second voltage transmission lines according to one embodiment of the present invention.

[0039] FIG. 11A is a schematic diagram illustrating a display device according to one embodiment of the present invention.

[0040] Fig. 11b is a drawing schematically explaining the pixel portion and data distribution portion of the display device illustrated in Fig. 11a.

[0041] FIG. 12a is a drawing schematically showing a display device according to one embodiment of the present invention.

[0042] Figure 12b is a drawing schematically illustrating the pixel portion and data distribution portion of the display device illustrated in Figure 12a.

[0043] This specification provides specific details to aid in understanding various embodiments. It should be noted that these embodiments are not limited to the devices or methods described herein, and may include equivalents. Various embodiments may be implemented without these specific details, or through one or more equivalent arrangements. Furthermore, the various embodiments are not mutually exclusive and are not limited to the embodiments disclosed herein. For example, specific features, configurations, or characteristics of one embodiment may be applied to other embodiments.

[0044] Unless otherwise specified, the embodiments depicted in the drawings are to be understood as representing features of one embodiment of the present invention. Accordingly, unless otherwise specified, features, components, modules, layers, membranes, panels, regions, and / or aspects (hereinafter referred to as "components") of the various embodiments may be combined, separated, exchanged, or rearranged within the technical spirit of the present invention.

[0045] Hatching in the drawings may be indicated to distinguish adjacent components. Accordingly, hatching in the drawings does not indicate or require specific materials, material properties, dimensions, proportions, commonalities between components, or other characteristics. Furthermore, the sizes (or relative sizes) of components may be exaggerated for illustrative purposes. If one embodiment can be implemented differently, a specific process sequence may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order described. Identical or corresponding components may be assigned the same drawing reference numerals.

[0046] When a component is said to be 'disposed', 'connected', or 'coupled' to another component or layer, it can include not only cases where it is directly disposed, connected, or coupled to the other component or layer, but also cases where there are intermediate elements or layers therebetween. On the other hand, 'directly disposed', 'directly connected', or 'directly coupled' indicates cases where there are no intermediate elements or layers between the component and the other component or layer. Here, the term 'connected' can indicate a physical, electrical, and / or fluid connection, and can be used regardless of the presence or absence of intermediate elements. In addition, the X-axis, Y-axis, and Z-axis in the present specification are not limited to the three axes (x, y, z-axes) of a rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can be in a direction other than perpendicular.

[0047] In this specification, 'at least one of A and B' can be interpreted as A, B, or A and B. In addition, 'at least one of X, Y, Z' and 'at least one selected from the group consisting of X, Y, Z' can be interpreted as X, Y, Z, XY, YZ, XZ, and XYZ. The term 'and / or' in this specification can include any combination of one or more of the listed items.

[0048] Terms such as "first" and "second" may be used to describe different components, and are not intended to limit the components. Terms such as "first" and "second" are used to distinguish one component from another, and the first component may also be referred to as the second component.

[0049] Spatially relative terms such as "below," "under," "below," "above," and "above" may be used to describe the relationship of one component to another as depicted in the drawings. Spatially relative terms may be understood to include orientations in which the device is used or operated other than those depicted in the drawings. For example, when the device depicted in the drawings is turned over, components described as "below" or "beneath" may be viewed as components positioned "above." Thus, the terms "below" and "beneath" may refer to any orientation that varies depending on the orientation of the device. The device may be positioned in various orientations (e.g., rotated 90 degrees), and the spatially relative terms used herein may be interpreted to take this into account.

[0050] In this specification, elements indicated in the singular are to be understood to include the plural, unless the context clearly indicates otherwise. In this specification, terms such as "comprises," "has," and the like indicate the presence of features, elements, steps, operations, configurations, and / or groups described herein, but do not exclude the presence or addition of one or more features, elements, steps, operations, configurations, and / or groups. In addition, terms such as "substantially," "about," and the like indicate values ​​that take into account deviations that can be readily accommodated by those skilled in the art from the measured, calculated, or provided values.

[0051] Embodiments may be described with reference to schematic drawings, such as cross-sectional views and / or plan views. The embodiments may differ from the shapes depicted in the drawings due to limitations in manufacturing techniques and other factors. Therefore, the embodiments are not limited to the shapes depicted in the drawings and may include shapes altered due to manufacturing processes and other factors. The areas depicted in the drawings are schematically illustrated, and the shapes of these areas do not limit the shapes of the actual areas of the device.

[0052] Some embodiments are described and illustrated in the drawings in the form of functional blocks, components, and / or modules. Those skilled in the art will appreciate that such blocks, components, and / or modules are physically implemented by electronic circuits (or optical circuits) such as logic circuits, microprocessors, hard-wired circuits, memory elements, wiring, etc. When such blocks, components, and / or modules are implemented by microprocessors or similar hardware, they may be programmed and controlled to perform various functions using software (e.g., microcode), and may be driven by firmware and / or software. Each block, component, and / or module may be implemented as dedicated hardware, or a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuitry) to perform some functions. Furthermore, in some embodiments, each block, component, and / or module may be composed of two or more blocks, components, and / or modules that are physically separate from each other and interact with each other, or may be composed of a more complex combination of blocks, components, and / or modules.

[0053] Unless otherwise specified, terms used herein are to be interpreted with the same meanings commonly understood in the relevant technical fields. Furthermore, terms defined in commonly used dictionaries are to be interpreted in a way consistent with the relevant technical fields and the technical concepts of the present invention, and are not to be interpreted in an overly idealistic or formal sense.

[0054] FIG. 1 is a plan view schematically illustrating a display device (10) according to one embodiment of the present invention.

[0055] Referring to FIG. 1, a display device (10) may include a display area (DA) for displaying an image and a peripheral area (PA) outside the display area (DA). The display device (10) may provide a predetermined image using light emitted from a plurality of pixels arranged in the display area (DA). Each pixel may include one or more subpixels. In one embodiment, one pixel may include a first subpixel that emits red light, a second subpixel that emits green light, and a third subpixel that emits blue light.

[0056] On a plane, the display area (DA) may have a rectangular shape. In other embodiments, the display area (DA) may have another polygonal shape, a circular shape, an oval shape, an irregular shape, etc. The display area (DA) may have a shape with rounded corners at the edges.

[0057] In one embodiment, the display device (10) may have a display area (DA) whose length in the first direction (x direction) is longer than its length in the second direction (y direction). In another embodiment, the display device (10) may have a display area (DA) whose length in the first direction (x direction) is shorter than its length in the second direction (y direction).

[0058] The peripheral area (PA) is an area arranged around the display area (DA), and the peripheral area (PA) may surround at least a portion of the display area (DA). In one embodiment, the peripheral area (PA) may be a type of non-display area where no pixels are arranged. Various wires, circuits, and pads to which printed circuit boards or driver IC chips are attached that transmit electrical signals to be applied to the display area (DA) may be located in the peripheral area (PA).

[0059] The display device (10) according to embodiments of the present invention is a device that displays a moving image or a still image, and can be used as a display screen of various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT) device, etc. In addition, the display device (10) according to one embodiment can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the display device (10) according to one embodiment can be used as a dashboard of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, a display placed on the back of a front seat for rear seat entertainment of a vehicle, etc.

[0060] Hereinafter, a display device (10) according to one embodiment of the present invention will be described using an organic light emitting display device as an example, but the display device of the present invention is not limited thereto. As another embodiment, the display device (10) of the present invention may be a display device such as an inorganic light emitting display device (Inorganic Light Emitting Display or Inorganic EL Display) or a quantum dot light emitting display device.

[0061] Each of FIGS. 2A to 2C is an equivalent circuit diagram schematically showing one subpixel (Ps) included in a display device (10) in one embodiment of the present invention.

[0062] Referring to FIG. 2a, a subpixel circuit (PCs) can be connected to a light-emitting element to realize light emission of the subpixel (Ps). The light-emitting element may be an organic light-emitting diode (OLED). The subpixel circuit (PCs) can include a first transistor (T1) which is a driving transistor, a second transistor (T2) which is a switching transistor, and a capacitor (Cst). The second transistor (T2) is connected to a gate line (GL) and a data line (DL), and can transmit a data signal (DATA) input through the data line (DL) to the first transistor (T1) according to a gate signal input through the gate line (GL).

[0063] The capacitor (Cst) is connected to the second transistor (T2) and the driving voltage line (PL), and can store a voltage corresponding to the difference between the voltage received from the switching transistor (T2) and the first power voltage (ELVDD) supplied to the driving voltage line (PL).

[0064] The first transistor (T1) is connected to a driving voltage line (PL) and a capacitor (Cst), and can control a driving current flowing from the driving voltage line (PL) to the organic light-emitting diode (OLED) in response to a voltage value stored in the capacitor (Cst). The organic light-emitting diode (OLED) can emit light at a predetermined brightness depending on the driving current.

[0065] Referring to FIG. 2B, the subpixel circuit (PCs) may include first to seventh transistors (T1 to T7) and a storage capacitor (Cst). Depending on the type of transistor (p-type or n-type) and / or operating conditions, the first terminal of each of the first to seventh transistors (T1 to T7) may be a source or a drain, and the second terminal may be a terminal different from the first terminal. For example, when the first terminal is a source, the second terminal may be a drain. The first transistor (T1) may be a driving transistor in which the size of the source-drain current is determined according to a gate-source voltage (Vgs), and the second to seventh transistors (T2 to T7) may be switching transistors that are turned on or off according to the gate-source voltage or the gate voltage.

[0066] The subpixel circuits (PCs) can be connected to a first gate line (GWL) that transmits a first gate signal (GW), a second gate line (GIL) that transmits a second gate signal (GI), a third gate line (GBL) that transmits a third gate signal (GB), an emission control line (EL) that transmits an emission control signal (EM), a data line (DL) that transmits a data signal (DATA), a driving voltage line (PL) that transmits a driving voltage (ELVDD), and an initialization voltage line (VL) that transmits an initialization voltage (VINT).

[0067] The first transistor (T1) may include a gate connected to a second node (N2), a first terminal connected to the first node (N1), and a second terminal connected to a third node (N3). The first transistor (T1) receives a data signal (Dm) according to a switching operation of the second transistor (T2) and supplies a driving current (Id) to a light-emitting element. The light-emitting element may be an organic light-emitting diode (OLED).

[0068] The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on in response to a first gate signal (GW) received through the first gate line (GWL) and may perform a switching operation to transmit a data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0069] The third transistor (T3) may include a gate connected to the first gate line (GWL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The third transistor (T3) may be turned on according to the first gate signal (GW) received through the first gate line (GWL) to diode-connect the first transistor (T1).

[0070] The fourth transistor (T4) may include a gate connected to a second gate line (GIL), a first terminal connected to an initialization voltage line (VL), and a second terminal connected to a second node (N2). The fourth transistor (T4) may be turned on according to a second gate signal (GI) received through the second gate line (GIL) to transmit an initialization voltage (VINT) to the gate of the first transistor (T1) to initialize the gate voltage of the first transistor (T1).

[0071] The fifth transistor (T5) may include a gate connected to an emission control line (EL), a first terminal connected to a driving voltage line (PL), and a second terminal connected to a first node (N1). The sixth transistor (T6) may include a gate connected to the emission control line (EL), a first terminal connected to a third node (N3), and a second terminal connected to a pixel electrode of an organic light-emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) may be turned on simultaneously according to an emission control signal (EM) received through the emission control line (EL), so that a driving current (Id) may flow to the organic light-emitting diode (OLED).

[0072] The seventh transistor (T7) may include a gate connected to the third gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and the pixel electrode of the organic light-emitting diode (OLED), and a second terminal connected to the initialization voltage line (VL). The seventh transistor (T7) may be turned on according to the third gate signal (GB) received through the third gate line (GBL) to transmit the initialization voltage (VINT) to the pixel electrode of the organic light-emitting diode (OLED) to initialize the pixel electrode of the organic light-emitting diode (OLED). The seventh transistor (T7) may be omitted.

[0073] The storage capacitor (Cst) may include a first capacitor electrode connected to a second node (N2) and a second capacitor electrode connected to a driving voltage line (PL).

[0074] An organic light-emitting diode (OLED) includes a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode) facing the pixel electrode, and the common electrode can receive a common voltage (ELVSS). The organic light-emitting diode (OLED) can display an image by receiving a driving current (Id) from a first transistor (T1) and emitting light with a predetermined color.

[0075] Referring to FIG. 2c, the subpixel circuits (PCs) may include first to eighth transistors (T1 to T8) and a storage capacitor (Cst). The first transistor (T1) may be a driving transistor whose source-drain current size is determined according to a gate-source voltage (Vgs), and each of the second to eighth transistors (T2 to T8) may be a switching transistor that transmits a signal.

[0076] The subpixel circuits (PCs) can be connected to a first gate line (GWL) for transmitting a first gate signal (GW), a second gate line (GCL) for transmitting a second gate signal (GC), a third gate line (GIL) for transmitting a third gate signal (GI), a fourth gate line (GBL) for transmitting a fourth gate signal (GB), an emission control line (EML) for transmitting an emission control signal (EM), a data line (DL) for transmitting a data signal (Dm), a driving voltage line (PL) for transmitting a driving voltage (ELVDD), a first initialization voltage line (VL1) for transmitting a first initialization voltage (VINT), a second initialization voltage line (VL2) for transmitting a second initialization voltage (VAINT), and a bias voltage line (VL3) for transmitting a bias voltage (VOBS).

[0077] The first transistor (T1) may include a gate connected to a second node (N2), a first terminal connected to the first node (N1), and a second terminal connected to a third node (N3). The first transistor (T1) receives a data signal (Dm) according to the switching operation of the second transistor (T2) and supplies a driving current (Id) to the light-emitting element.

[0078] The second transistor (T2) may include a gate connected to the first gate line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on in response to a first gate signal (GW) received through the first gate line (GWL) and may perform a switching operation to transmit a data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0079] The third transistor (T3) may include a gate connected to the second gate line (GCL), a first terminal connected to the second node (N2), and a second terminal connected to the third node (N3). The third transistor (T3) may be turned on according to a second gate signal (GC) received through the second gate line (GCL), thereby diode-connecting the first transistor (T1).

[0080] The fourth transistor (T4) may include a gate connected to a third gate line (GIL), a first terminal connected to a first initialization voltage line (VL1), and a second terminal connected to a second node (N2). The fourth transistor (T4) may be turned on according to a third gate signal (GI) received through the third gate line (GIL), and may transmit an initialization voltage (VINT) to the gate of the first transistor (T1) to initialize the gate voltage of the first transistor (T1).

[0081] The fifth transistor (T5) may include a gate connected to an emission control line (EML), a first terminal connected to a driving voltage line (PL), and a second terminal connected to a first node (N1). The sixth transistor (T6) may include a gate connected to the emission control line (EML), a first terminal connected to a third node (N3), and a second terminal connected to a pixel electrode of an organic light-emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) may be simultaneously turned on by an emission control signal (EM) received through the emission control line (EML), so that a driving current (Id) may flow to the organic light-emitting diode (OLED).

[0082] The seventh transistor (T7) may include a gate connected to the fourth gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and the pixel electrode of the organic light-emitting diode (OLED), and a second terminal connected to the second initialization voltage line (VL2). The seventh transistor (T7) may be turned on by the fourth gate signal (GB) received through the fourth gate line (GBL) and may transmit the second initialization voltage (VAINT) from the second initialization voltage line (VL2) to the pixel electrode of the organic light-emitting diode (OLED), thereby initializing the pixel electrode of the organic light-emitting diode (OLED).

[0083] The eighth transistor (T8) may include a gate connected to a fourth gate line (GBL), a first terminal connected to a first node (N1), and a second terminal connected to a bias voltage line (VL3). The eighth transistor (T8) may be turned on by a fourth gate signal (GB) transmitted through the fourth gate line (GBL), and may transmit a bias voltage (VOBS) from the bias voltage line (VL3) to the first node (N1).

[0084] The storage capacitor (Cst) may include a first capacitor electrode connected to a second node (N2) and a second capacitor electrode connected to a driving voltage line (PL).

[0085] An organic light-emitting diode (OLED) includes a pixel electrode (e.g., an anode) and a common electrode (e.g., a cathode) facing the pixel electrode, and the common electrode can receive a common voltage (ELVSS). The organic light-emitting diode (OLED) can display an image by receiving a driving current (Id) from a first transistor (T1) and emitting light with a predetermined color.

[0086] Although the transistors of the subpixel circuits (PCs) in FIGS. 2A and 2B are illustrated as P-type transistors, the embodiments of the present invention are not limited thereto. For example, the transistors of the subpixel circuits (PCs) may be N-type transistors, or as illustrated in FIG. 2C, some may be P-type transistors and others may be N-type transistors. For example, the third transistor (T3) and the fourth transistor (T4) may be N-type transistors and the rest may be P-type transistors. The subpixel circuits (PCs) of FIGS. 2A to 2C are exemplary, and the subpixel circuits (PCs) of the present invention may be designed in various ways.

[0087] FIG. 3 is a drawing schematically showing a display device (10) according to one embodiment of the present invention.

[0088] Referring to FIG. 3, the display device (10) may include a pixel unit (110), a gate driver (130), a data driver (150), a data distribution unit (170), control circuits (180), and a control unit (190).

[0089] A display area (DA, see Fig. 1) may be provided with a pixel unit (110) in which a plurality of pixel circuits (PCij) are arranged. A peripheral area (PA, see Fig. 1) may be provided with a gate driver (130), a data driver (150), a data distribution unit (170), control circuits (180), and a control unit (190).

[0090] In one embodiment, the gate driver (130) and the data distribution unit (170) may be formed directly on the substrate. The data driver (150), the control circuit (180), and the control unit (190) may be arranged on a flexible printed circuit board (FPCB) electrically connected to pads arranged on one side of the substrate. In another embodiment, the data driver (150) and the control circuit (180) may be arranged directly on the substrate in a COG (Chip On Glass) or COP (Chip On Plastic) manner.

[0091] Each pixel circuit (PCij) may include multiple subpixel circuits (PCs). For example, one pixel circuit (PCij) may include a first subpixel circuit (PCs1), a second subpixel circuit (PCs2), and a third subpixel circuit (PCs3).

[0092] Each of the plurality of subpixel circuits (PCs) may be connected to a corresponding gate line among the plurality of gate lines (GL1 to GLn) and a corresponding data line among the plurality of data lines (DL1 to DLm) (DL1, DL2, DL3, DL4, DL5, DL6, ..., DL3i-2, DL3i-1, DL3i, ..., DLm-2, DLm-1, DLm). The gate lines (GL1 to GLn) may each extend in a first direction (e.g., x direction, row direction) and be connected to subpixel circuits positioned in the same row. The gate lines (GL1 to GLn) may each transmit a gate signal to the subpixel circuits (PCs) in the same row. The data lines (DL1 to DLm) may each extend in a second direction (e.g., y direction, column direction) and be connected to subpixel circuits positioned in the same column. Hereinafter, when a single wire is connected to a single subpixel circuit row or subpixel circuit column, it means that the wire is connected to the subpixel circuits located in the corresponding row or column.

[0093] The gate driver (130) is connected to a plurality of gate lines (GL1 to GLn), and generates a gate signal in response to a gate driving control signal (GCS) from the control unit (190), and can sequentially supply the gate signal to the gate lines (GL1 to GLn). When the gate signal is sequentially supplied to the gate lines (GL1 to GLn), subpixel circuits (PCs) can be selected in units of rows. The data lines (DL1 to DLm) can transmit a data signal to each selected subpixel circuit row. The gate line can be connected to the gate of a transistor included in the subpixel circuit (PCs). The gate signal can be a gate control signal that controls turning on and off of the transistor connected to the gate line. The gate signal can be a square wave signal in which an on voltage that can turn on the transistor and an off voltage that can turn off the transistor are repeated.

[0094] The data driving unit (150) is connected to a plurality of data output lines (OL1 to OLm / i), and the plurality of data output lines (OL1 to OLm / i) can be connected to a plurality of data lines (DL1 to DLm) through a data distribution unit (170). The data driving unit (150) can convert an image signal into a data signal in the form of voltage or current according to a data driving control signal (DCS) input from the control unit (190). The data driving unit (150) can supply the data signal to the data distribution unit (170) through the data output lines (OL1 to OLm / i).

[0095] Control circuits (180) are connected to a plurality of power output lines (POLs), and the plurality of power output lines (POLs) can be connected to a data distribution unit (170). The control circuits (180) can supply control signals of a sub-demultiplexer (DMX) to the data distribution unit (170) through the power output lines (POLs) according to a distribution control signal (CCS) input from the control unit (190).

[0096] A data distribution unit (170) may be connected between a plurality of data output lines (OL1 to OLm / i) and a plurality of data lines (DL1 to DLm). The data distribution unit (170) may include m / i (i is a natural number greater than or equal to 2) sub-demultiplexers (DMXs) including a plurality of switches. That is, the data distribution unit (170) may have the same number of sub-demultiplexers (DMXs) as the number of data output lines. One end of the sub-demultiplexer (DMX) may be connected to a corresponding data output line among the plurality of data output lines (OL1 to OLm / i). And the other end of the sub-demultiplexer (DMX) may be connected to i data lines. The sub-demultiplexer (DMX) may supply a data signal supplied from a corresponding data output line to the i data lines. By using a sub-demultiplexer (DMX), the number of data output lines (OL1 to OLm / i) is less than the number of data lines (DL1 to DLm), so that the number of data output lines connected to the data driver (150) is reduced, thereby reducing manufacturing costs. The sub-demultiplexer (DMX) may include a plurality of switches connected to each of the corresponding data output lines and the i data lines. In one embodiment, i may be 2.

[0097] The control unit (190) can generate a data drive control signal (DCS), a gate drive control signal (GCS), and a distribution control signal (CCS) in response to externally supplied synchronization signals. The control unit (190) can output the data drive control signal (DCS) to the data drive unit (150) and output the gate drive control signal (GCS) to the gate drive unit (130). The control unit (190) can output the distribution control signal (CCS) to the control circuits (180), and the control circuits (180) can output control signals of the sub-demultiplexers (DMX) in response to the distribution control signal (CCS). The data distribution unit (170) can selectively connect the data output lines (OL1 to OLm / i) and the data lines (DL1 to DLm) in response to the control signals of the sub-demultiplexers (DMX).

[0098] When the display device (10) is an organic light emitting display device, a driving voltage (ELVDD) and a common voltage (ELVSS) can be supplied to subpixel circuits (PCs) and organic light emitting diodes (OLEDs, see FIGS. 2A to 2C) of the display device (10). The driving voltage (ELVDD) can be a high-level voltage provided to a first electrode (pixel electrode or anode electrode) of each organic light emitting diode (OLED). The common voltage (ELVSS) can be a low-level voltage provided to a second electrode (counter electrode or cathode electrode) of each organic light emitting diode (OLED).

[0099] FIG. 4 is a drawing schematically illustrating a demultiplexer according to one embodiment of the present invention.

[0100] Referring to FIG. 4, the sub-demultiplexer (DMX) can selectively connect the p-th data output line (OLp) to a pair of the k-th data line (DLk) and the k+3-th data line (DLk+3). The sub-demultiplexer (DMX) can include a first switch (SW1) and a second switch (SW2).

[0101] The k-th data line (DLk) and the k+3-th data line (DLk+3) may be data lines spaced three columns apart. For example, the k+1-th data line and the k+2-th data line may be spaced between the k-th data line (DLk) and the k+3-th data line (DLk+3). The k-th data line (DLk) may be connected to the k-th subpixel circuit column, and the k+3-th data line (DLk+3) may be connected to the k+3-th subpixel circuit column.

[0102] The control signals (CCS) of the sub-demultiplexer (DMX) output by the control circuit (180, see FIG. 3) may include a first control signal (CLA) and a second control signal (CLB). The first control signal (CLA) and the second control signal (CLB) may be applied alternately without overlapping at different timings.

[0103] A first switch (SW1) may be provided between the pth data output line (OLp) and the kth data line (DLk). The first switch (SW1) may connect the pth data output line (OLp) and the kth data line (DLk) by a first control signal (CLA), and may apply a data signal (DATA) applied to the pth data output line (OLp) to the kth data line (DLk).

[0104] A second switch (SW2) may be provided between the pth data output line (OLp) and the k+3rd data line (DLk+3). The second switch (SW2) may connect the pth data output line (OLp) and the k+3rd data line (DLk+3) by a second control signal (CLB), and may apply a data signal (DATA) applied to the pth data output line (OLp) to the k+3rd data line (DLk+3).

[0105] In one embodiment, the subpixels connected to the k-th data line (DLk) and the k+3-th data line (DLk+3) may be subpixels that emit light of the same color. In another embodiment, the subpixels connected to the k-th data line (DLk) and the k+3-th data line (DLk+3) may include subpixels that emit light of a first color and subpixels that emit light of a second color different from the first color, and the subpixels connected to the k+1-th data line and the k+4-th data line may be subpixels that emit light of a third color.

[0106] The gate lines (GLn-2, ​​GLn-1, GLn) illustrated in FIG. 4 may correspond to the gate lines (GL) illustrated in FIG. 2a, or the first gate lines (GWL) illustrated in FIGS. 2b and 2c.

[0107] Figure 5 is a timing diagram explaining the operation of the demultiplexer illustrated in Figure 4.

[0108] Referring to FIGS. 4 and 5, the first control signal (CLA) and the second control signal (CLB) can be supplied from the control circuit (180, see FIG. 3) to the sub-demultiplexer (DMX) through the power output lines (POL, see FIG. 3).

[0109] The first control signal (CLA) and the second control signal (CLB) may be square wave signals that repeat an on voltage that can turn on the first switch (SW1) and the second switch (SW2) and an off voltage that can turn off the first switch (SW1) and the second switch (SW2). In one embodiment, the on voltage of the first control signal (CLA) and the second control signal (CLB) may be a high-level voltage (first-level voltage), and the off voltage may be a low-level voltage (second-level voltage).

[0110] The first control signal (CLA) and the second control signal (CLB) may be signals having the same waveform but shifted in phase. For example, the timing at which the voltage levels of the first control signal (CLA) and the second control signal (CLB) are inverted may be the same. The period during which the on voltage of the first control signal (CLA) is maintained (hereinafter referred to as the 'on voltage period') may overlap the period during which the off voltage of the second control signal (CLB) is maintained (hereinafter referred to as the 'off voltage period'), and the off voltage period of the first control signal (CLA) may overlap the on voltage period of the second control signal (CLB).

[0111] During one frame (e.g., during a single frame), the gate signals (Gn-2, Gn-1, Gn) can be sequentially supplied as on voltages through the gate lines (GLn-2, ​​GLn-1, GLn) from the gate driver (130, see FIG. 3). The gate signals (Gn-2, Gn-1, Gn) can be gate signals that control turning on and turning off a data write transistor (e.g., a second transistor, T2). The gate signals (Gn-2, Gn-1, Gn) can be supplied as an on voltage that can turn on the data write transistor and an off voltage that can turn off the data write transistor. In one embodiment, the on voltage of the gate signals (Gn-2, Gn-1, Gn) can be a high level voltage (a first level voltage), and the off voltage can be a low level voltage (a second level voltage).

[0112] The on voltage period of the gate signals (Gn-2, Gn-1, Gn) may be referred to as a line time (LT). The line time (LT) may be a time required to write a data signal (DATA) to one sub-pixel circuit row in a display device (10, see FIG. 1). In one embodiment, the line time (LT) may be approximately 2H. The line time (LT) may include a first sub-line time (LT1) and a second sub-line time (LT2) following the first sub-line time (LT1). Each of the first sub-line time (LT1) and the second sub-line time (LT2) may be approximately 1H. The first sub-line time (LT1) of the current gate signal may overlap the second sub-line time (LT2) of the previous gate signal.

[0113] The on voltage of the first control signal (CLA) and the on voltage of the second control signal (CLB) may be alternately supplied to the sub demultiplexer (DMX) for each of the first subline time (LT1) and the second subline time (LT2). For example, the first control signal (CLA) may be supplied as an on voltage for each of the first subline time (LT1) and the second subline time (LT2) of the line time of the row to which the gate signal is supplied (hereinafter referred to as the “current line time”), and thereafter, the first control signal (CLA) may transition to an off voltage and the second control signal (CLB) may be supplied as an on voltage.

[0114] The data signal supplied during the first subline time (LT1) may be a data signal of a previous line time corresponding to a row (previous line) to which a previous gate signal is supplied, and the data signal supplied during the second subline time (LT2) may be a data signal of a current line time corresponding to a row (current line) to which a current gate signal is supplied. In other words, during the second subline time (LT2), a data signal (DATA) corresponding to the current line time may be written to the subpixel circuits (PCs) of the current line.

[0115] The data drive unit (150, see Fig. 2) can supply a data signal (DATA) to the data output line (OLp) in synchronization with control signals (CLA, CLB).

[0116] The first subline time (LT1) of the (n-1)th gate signal (Gn-1) can overlap with the second subline time (LT2) of the (n-2)th gate signal (Gn-2). Therefore, during the first subline time (LT1) of the (n-1)th gate signal (Gn-1), the data write transistors of the subpixel circuits (PCs1a, PCs1b) connected to the (n-2)th gate line (GLn-2) and the subpixel circuits (PCs2a, PCs2b) connected to the (n-1)th gate line (GLn-1) can be turned on.

[0117] During the first subline time (LT1) of the (n-1)th gate signal (Gn-1), the first control signal (CLA) can first be supplied with an on voltage to the first switch (SW1) of the sub-demultiplexer (DMX). Accordingly, the data signal (D1a) can be supplied to the sub-pixel circuits (PCs1a, PCs1b) connected to the (n-2)th gate line (GLn-2) and the sub-pixel circuits (PCs2a, PCs2b) connected to the (n-1)th gate line (GLn-1), among which the first switch (SW1) is connected to the data line (DLk).

[0118] Thereafter, the second control signal (CLB) can be supplied to the second switch (SW2) of the sub-demultiplexer (DMX). Accordingly, the data signal (D1b) can be supplied to the sub-pixel circuits (PCs1a, PCs1b) connected to the n-2th gate line (GLn-2) and the sub-pixel circuits (PCs2a, PCs2b) connected to the n-1th gate line (GLn-1), among which the second switch (SW2) is connected to the data line (DLk+3).

[0119] The second subline time (LT2) of the (n-1)th gate signal (Gn-1) may overlap with the first subline time (LT1) of the n-th gate signal (Gn). Therefore, during the second subline time (LT2) of the (n-1)th gate signal (Gn-1), the data write transistors of the subpixel circuits (PCs2a, PCs2b) connected to the (n-1)th gate line (GLn-1) and the subpixel circuits (PCs3a, PCs3b) connected to the n-th gate line (GLn) may be turned on.

[0120] During the second subline time (LT2) of the (n-1)th gate signal (Gn-1), the first control signal (CLA) can first be supplied to the first switch (SW1) of the sub-demultiplexer (DMX). Accordingly, the data signal (D2a) can be supplied to the sub-pixel circuits (PCs2a, PCs2b) connected to the (n-1)th gate line (GLn-1) and the sub-pixel circuits (PCs3a, PCs3b) connected to the nth gate line (GLn) among the sub-pixel circuits connected to the data line (DLk) to which the first switch (SW1) is connected.

[0121] Thereafter, the second control signal (CLB) can be supplied to the second switch (SW2) of the sub-demultiplexer (DMX). Accordingly, the data signal (D2b) can be supplied to the sub-pixel circuits (PCs2a, PCs2b) connected to the n-1th gate line (GLn-1) and the sub-pixel circuits (PCs3a, PCs3b) connected to the nth gate line (GLn) among the sub-pixel circuits (PCs2b, PCs3b) connected to the data line (DLk+3) to which the second switch (SW2) is connected.

[0122] The data signal of the previous line time written to the subpixel circuits (PCs) during the first subline time (LT1) can be overwritten by the data signal of the current line time written to the subpixel circuits (PCs) during the second subline time (LT2). By the method described above, the data drive (150) can write data to all the subpixel circuits of one row during one line time (LT).

[0123] FIG. 6 is a drawing schematically explaining the pixel unit (110) and data distribution unit (170) of the display device (10) illustrated in FIG. 3.

[0124] The data distribution unit (170) includes first switches (SW1) and second switches (SW2), and the pixel unit (110) may include a plurality of pixel circuits (PC). One pixel circuit (PC) may include a red subpixel circuit (PCr), a green subpixel circuit (PCg), ​​and a blue subpixel circuit (PCb). The subpixel circuits (PCr, PCg, PCb) may be arranged repeatedly in a first direction (x-axis direction, row direction) and a second direction (y-axis direction, column direction).

[0125] In the pixel unit (110), a column in which red subpixel circuits (PCr) are arranged in the second direction (y-axis direction), a column in which green subpixel circuits (PCg) are arranged in the second direction (y-axis direction), and a column in which blue subpixel circuits (PCb) are arranged in the second direction (y-axis direction) may be alternately repeated in the first direction (e.g., x-axis direction).

[0126] A plurality of data lines (DL1, DL2, ..., DL6) and a plurality of gate lines (GL1, GL2, GL3) may be arranged in the pixel portion (110). The gate lines (GL1, GL2, GL3) may correspond to the gate line (GL) illustrated in FIG. 2a, or the first gate line (GWL) illustrated in FIGS. 2b and 2c.

[0127] One gate line can be connected to subpixel circuits arranged in the same row. One data line can be connected to subpixel circuits arranged in the same column. Subpixels connected to the ith data line (DLi) and subpixels connected to the i+3th data line (DLi+3) may be subpixels that emit light of the same color. For example, subpixel circuit columns connected to the first data line (DL1) and the fourth data line (DL4) may include red subpixel circuits (PCr), subpixel circuit columns connected to the second data line (DL2) and the fifth data line (DL5) may include green subpixel circuits (PCg), ​​and subpixel circuit columns connected to the third data line (DL3) and the sixth data line (DL6) may include blue subpixel circuits (PCb).

[0128] For convenience of explanation, FIG. 6 illustrates only six data lines (DL1, DL2, ..., DL6), three gate lines (GL1, GL2, GL3) and three data output lines (OL1, OL2, OL3), but the number of data lines, gate lines and data output lines may be greater.

[0129] The data distribution unit (170) can selectively connect the data output lines (OL1, OL2, OL3) to one of a pair of data lines corresponding to each other. For example, the data distribution unit (170) can selectively connect the first data output line (OL1) to one of the first data line (DL1) and the fourth data line (DL4), selectively connect the second data output line (OL2) to one of the second data line (DL2) and the fifth data line (DL5), and selectively connect the third data output line (OL3) to one of the third data line (DL3) and the sixth data line (DL6).

[0130] Each of the first switches (SW1) may be provided between the first data output line (OL1) and the first data line (DL1), between the second data output line (OL2) and the second data line (DL2), and between the third data output line (OL3) and the third data line (DL3). The first switches (SW1) may be turned on by the first control signal (CLA) to connect the first data output line (OL1) and the first data line (DL1), connect the second data output line (OL2) and the second data line (DL2), and connect the third data output line (OL3) and the third data line (DL3).

[0131] Each of the second switches (SW2) may be provided between the first data output line (OL1) and the fourth data line (DL4), between the second data output line (OL2) and the fifth data line (DL5), and between the third data output line (OL3) and the sixth data line (DL6). The second switches (SW2) may be turned on by the second control signal (CLB) to connect the first data output line (OL1) and the fourth data line (DL4), connect the second data output line (OL2) and the fifth data line (DL5), and connect the third data output line (OL3) and the sixth data line (DL6).

[0132] The control circuit (180, see FIG. 3) can supply a first control signal (CLA) to the first switches (SW1) through a first control signal line (CL1) and supply a second control signal (CLB) to the second switches (SW2) through a second control signal line (CL2). The first control signal line (CL1) and the second control signal line (CL2) may be part of power output lines (POL). In one embodiment, the first switches (SW1) and the second switches (SW2) may be switching transistors that are turned on or off according to a gate voltage. The first control signal line (CL1) may be connected to a gate electrode of each of the first switches (SW1), and the second control signal line (CL2) may be connected to a gate electrode of each of the second switches (SW2).

[0133] The first data line (DL1) and the second data line (DL2), which are adjacent to each other, can receive data signals by the same control signal. That is, the first data line (DL1) is connected to the first data output line (OL1) by the first control signal (CLA) and receives the first data signal (DATA[1]), and the second data line (DL2) is connected to the second data output line (OL2) by the first control signal (CLA) and receives the second data signal (DATA[2]).

[0134] Here, the fact that two data lines are adjacent to each other indicates that no other data lines are placed between the two data lines.

[0135] The third data line (DL3) and the fourth data line (DL4), which are adjacent to each other, can receive data signals by different control signals. That is, the third data line (DL3) can be connected to the third data output line (OL3) by the first control signal (CLA) and receive the third data signal (DATA[3]), and the fourth data line (DL4) can be connected to the first data output line (OL1) by the second control signal (CLB) and receive the first data signal (DATA[1]).

[0136] The fifth data line (DL5) and the sixth data line (DL6), which are adjacent to each other, can receive data signals by the same control signal. That is, the fifth data line (DL5) can be connected to the second data output line (OL2) by the second control signal (CLB) and receive the second data signal (DATA[2]), and the sixth data line (DL6) can be connected to the third data output line (OL3) by the second control signal (CLB) and receive the third data signal (DATA[3]).

[0137] At this time, the third data line (DL3) and the fourth data line (DL4), which are supplied with data signals by different control signals, may be arranged to be spaced apart from each other with the third sub-pixel circuit column (PCb11, PCb21, PCb31) connected to the third data line (DL3) interposed therebetween. Here, the fact that the two data lines are arranged to be spaced apart from each other with the sub-pixel circuit column interposed therebetween means that the driving transistors (first transistor, T1, see FIGS. 2a to 2c) included in the sub-pixel circuit column are arranged between the two data lines.

[0138] The fifth data line (DL5) and the sixth data line (DL6), which receive data signals by the same control signals, may be arranged facing each other. Here, the two data lines being arranged facing each other means that the two data lines are arranged adjacent to each other by being arranged between the subpixel circuit rows connected to each of the two data lines.

[0139] Each of the data lines (DL1, DL2, ..., DL6) can be arranged on the first side or the second side of the subpixel circuit row to which it is connected. In this specification, the first side of the subpixel circuit row means the -x direction (left) with respect to the center of the subpixel circuit row, and the second side means the +x direction (right).

[0140] The first data line (DL1) is connected to the first subpixel circuit column (PCr11, PCr21, PCr31) and may be arranged on the first side of the first subpixel circuit column (PCr11, PCr21, PCr31), and the second data line (DL2) is connected to the second subpixel circuit column (PCg11, PCg21, PCg31) and may be arranged on the second side of the second subpixel circuit column (PCg11, PCg21, PCg31).

[0141] The third data line (DL3) is connected to the third sub-pixel circuit column (PCb11, PCb21, PCb31) and may be arranged on the first side of the third sub-pixel circuit column (PCb11, PCb21, PCb31), and the fourth data line (DL4) is connected to the fourth sub-pixel circuit column (PCr12, PCr22, PCr32) and may be arranged on the first side of the fourth sub-pixel circuit column (PCr12, PCr22, PCr32).

[0142] The fifth data line (DL5) is connected to the fifth sub-pixel circuit column (PCg12, PCg22, PCg32) and may be arranged on the second side of the fifth sub-pixel circuit column (PCg12, PCg22, PCg32), and the sixth data line (DL6) is connected to the sixth sub-pixel circuit column (PCb12, PCb22, PCb32) and may be arranged on the first side of the sixth sub-pixel circuit column (PCb12, PCb22, PCb32).

[0143] In one embodiment, the subpixel circuits belonging to the first subpixel circuit row (PCr11, PCr21, PCr31) may have a symmetrical shape with respect to the subpixel circuits belonging to the second subpixel circuit row (PCg11, PCg21, PCg31). The first subpixel circuit row (PCr11, PCr21, PCr31) and the second subpixel circuit row (PCg11, PCg21, PCg31) may overlap with one driving voltage line. The subpixel circuits belonging to the fourth subpixel circuit row (PCr12, PCr22, PCr32) may have a symmetrical shape with respect to the subpixel circuits belonging to the fifth subpixel circuit row (PCg12, PCg22, PCg32). The fourth subpixel circuit column (PCr12, PCr22, PCr32) and the fifth subpixel circuit column (PCg12, PCg22, PCg32) can overlap with one driving voltage line. According to embodiments of the present invention, by flipping the subpixel circuits arranged in the second subpixel circuit column (PCg11, PCg21, PCg31) and the fifth subpixel circuit column (PCg12, PCg22, PCg32), the first subpixel circuit column (PCr11, PCr21, PCr31) and the second subpixel circuit column (PCg11, PCg21, PCg31) can share one driving voltage line, and the fourth subpixel circuit column (PCr12, PCr22, PCr32) and the fifth subpixel circuit column (PCg12, PCg22, PCg32) can share one driving voltage line. Therefore, the area required by the pixel circuit (PCij) can be reduced.

[0144] As a comparative example, when two data lines that are adjacent to each other and receive data signals by different control signals are arranged facing each other, coupling may occur between the two data lines. Accordingly, the potential of the data line that receives the data signal by the first control signal among the two data lines may change depending on the potential of the data line that receives the data signal by the second control signal. Accordingly, embodiments of the present invention can reduce or prevent coupling between data lines by having two data lines (DL3, DL4) that are adjacent to each other and receive data signals by different control signals be arranged spaced apart from each other with at least one subpixel circuit row therebetween.

[0145] At this time, data lines (DL5, DL6) that are adjacent to each other and are supplied with data signals by the same control signal can be immediately restored to the corresponding data potential because they are each supplied with data signals even when they are arranged facing each other and coupled to each other.

[0146] FIG. 7 is a plan view schematically illustrating subpixel circuits and data lines according to one embodiment of the present invention.

[0147] Referring to FIG. 7, the display device (10, see FIG. 1) may include a [1, 1]th red subpixel circuit (PCr11) and a [1, 1]th green subpixel circuit (PCg11) that are arranged adjacent to each other in a first direction (x-axis direction). The [1, 1]th red subpixel circuit (PCr11) and the [1, 1]th green subpixel circuit (PCg11) may include first to eighth transistors (T1 to T8) and a storage capacitor (Cst), respectively.

[0148] The first data line (DL1) may be connected to the second transistor (T2) of the [1,1]th red subpixel circuit (PCr11), and the second data line (DL2) may be connected to the second transistor (T2) of the [1,1]th green subpixel circuit (PCg11). The first data line (DL1) may be arranged on the first side (left) of the [1,1]th red subpixel circuit (PCr11), and the second data line (DL2) may be arranged on the second side (right) of the [1,1]th green subpixel circuit (PCg11).

[0149] In other words, the [1,1]th red subpixel circuit (PCr11) and the [1,1]th green subpixel circuit (PCg11) may be arranged between the first data line (DL1) and the second data line (DL2). As described above, the arrangement of the [1,1]th red subpixel circuit (PCr11) and the [1,1]th green subpixel circuit (PCg11) between the first data line (DL1) and the second data line (DL2) means that the first transistor (T1) of the [1,1]th red subpixel circuit (PCr11) and the first transistor (T1) of the [1,1]th green subpixel circuit (PCg11) are arranged between the first data line (DL1) and the second data line (DL2). The [1,1]th red subpixel circuit (PCr11) and the [1,1]th green subpixel circuit (PCg11) may have a line-symmetric shape with an imaginary straight line (VL) extending in the second direction (y-axis direction) along the boundary between the two subpixel circuits as an axis of symmetry.

[0150] The driving voltage line (PL) can be connected to one capacitor electrode of the storage capacitor (Cst) of each subpixel circuit to transmit a driving voltage (ELVDD, see FIGS. 2a to 2c). By flipping the [1,1]th green subpixel circuit (PCg11), two subpixel circuits (PCr11, PCg11) arranged between the first data line (DL1) and the second data line (DL2) can share one driving voltage line (PL). Therefore, compared to the case where a driving voltage line is arranged for each subpixel circuit, the area required for each subpixel circuit can be reduced.

[0151] FIG. 8 is a plan view schematically illustrating driving voltage lines and data lines according to one embodiment of the present invention.

[0152] Referring to FIG. 8, the pixel unit (110) may include subpixel circuits (PCr11, PCg11, PCb11), driving voltage lines (PL1, PL2), and data lines (DL1, DL2, DL3, DL4). The driving voltage lines (PL1, PL2) may extend in the second direction (y-axis direction) and may be arranged to overlap the subpixel circuits (PCr11, PCg11, PCb11). The data lines (DL1, DL2, DL3, DL4) may extend in the second direction (y-axis direction) and may be arranged on one side of the subpixel circuits (PCr11, PCg11, PCb11).

[0153] The first data line (DL1) is connected to the [1,1]th red subpixel circuit (PCr11) and may be arranged on a first side of the [1,1]th red subpixel circuit (PCr11). The second data line (DL2) is connected to the [1,1]th green subpixel circuit (PCg11) and may be arranged on a second side of the [1,1]th green subpixel circuit (PCg11). The [1,1]th red subpixel circuit (PCr11) and the [1,1]th green subpixel circuit (PCg11) arranged between the first data line (DL1) and the second data line (DL2) may overlap the first driving voltage line (PL1). The first driving voltage line (PL1) can transmit a driving voltage (ELVDD, see FIGS. 2a to 2c) to the [1,1]th red subpixel circuit (PCr11) and the [1,1]th green subpixel circuit (PCg11).

[0154] The third data line (DL3) is connected to the [1,1]th blue subpixel circuit (PCb11) and may be arranged on the first side of the [1,1]th blue subpixel circuit (PCb11). The fourth data line (DL4) is connected to the [1,2]th red subpixel circuit (PCr12) and may be arranged on the first side of the [1,2]th red subpixel circuit (PCr12).

[0155] As described with reference to FIG. 6, the first data line (DL1), the second data line (DL2), and the third data line (DL3) may receive data signals by the first control signal (CLA), and the fourth data line (DL4) may receive data signals by the second control signal (CLB). Therefore, the third data line (DL3) and the fourth data line (DL4) may be spaced apart from each other with the [1,1]th blue subpixel circuit (PCb11) therebetween to prevent or reduce coupling. The second driving voltage line (PL2) disposed between the third data line (DL3) and the fourth data line (DL4) may overlap the [1,1]th blue subpixel circuit (PCb11).

[0156] In one embodiment, the driving voltage lines (PL1, PL2) and the data lines (DL1, DL2, DL3) may be arranged on the same layer. In this specification, components arranged on the same layer mean that they are formed by the same process and have the same material, layer structure, and characteristics.

[0157] FIG. 9 is a drawing schematically illustrating a pixel unit (110) and a data distribution unit (170) of a display device according to one embodiment of the present invention.

[0158] Figure 9 is similar to Figure 6, but differs in the arrangement of sub-pixel circuits and data lines. Below, descriptions of identical or similar components will be omitted, and the differences will be explained.

[0159] The data distribution unit (170) may include first switches (SW1) and second switches (SW2), and the pixel unit (110) may include a plurality of pixel circuits (PCij). One pixel circuit (PC) may include a red subpixel circuit (PCr), a green subpixel circuit (PCg), ​​and a blue subpixel circuit (PCb). The subpixel circuits (PCr, PCg, PCb) may be arranged repeatedly in a first direction (x-axis direction, row direction) and a second direction (y-axis direction, column direction).

[0160] In the pixel unit (110), a column in which red subpixel circuits (PCr) are arranged in the second direction (y-axis direction), a column in which green subpixel circuits (PCg) are arranged in the second direction (y-axis direction), and a column in which blue subpixel circuits (PCb) are arranged in the second direction (y-axis direction) may be alternately repeated in the first direction (e.g., x-axis direction).

[0161] The data distribution unit (170) can selectively connect the data output lines (OL1, OL2, OL3) to one of a pair of data lines corresponding to each other. Each of the first switches (SW1) can be provided between the first data output line (OL1) and the first data line (DL1), between the second data output line (OL2) and the second data line (DL2), and between the third data output line (OL3) and the third data line (DL3). Each of the second switches (SW2) can be provided between the first data output line (OL1) and the fourth data line (DL4), between the second data output line (OL2) and the fifth data line (DL5), and between the third data output line (OL3) and the sixth data line (DL6).

[0162] The control circuit (180, see FIG. 3) can supply a first control signal (CLA) to the first switches (SW1) through the first control signal line (CL1) and supply a second control signal (CLB) to the second switches (SW2) through the second control signal line (CL2).

[0163] The first data line (DL1) is connected to the first data output line (OL1) by the first control signal (CLA) and receives the first data signal (DATA[1]), the second data line (DL2) is connected to the second data output line (OL2) by the first control signal (CLA) and receives the second data signal (DATA[2]), and the third data line (DL3) is connected to the third data output line (OL3) by the first control signal (CLA) and receives the third data signal (DATA[3]). The fourth data line (DL4) is connected to the first data output line (OL1) by the second control signal (CLB) and receives the first data signal (DATA[1]), the fifth data line (DL5) is connected to the second data output line (OL2) by the second control signal (CLB) and receives the second data signal (DATA[2]), and the sixth data line (DL6) is connected to the third data output line (OL3) by the second control signal (CLB) and receives the third data signal (DATA[3]).

[0164] The first data line (DL1) and the second data line (DL2), which are adjacent to each other and receive data signals by the same control signals, can be arranged facing each other. The third data line (DL3) and the fourth data line (DL4), which are adjacent to each other and receive data signals by different control signals, can be arranged spaced apart from each other with the third sub-pixel circuit column (PCb11, PCb21, PCb31) connected to the third data line (DL3) and the fourth sub-pixel circuit column (PCr12, PCr22, PCr32) connected to the fourth data line (DL4) interposed therebetween.

[0165] Each of the data lines (DL1, DL2, ..., DL6) can be placed on the first or second side of the subpixel circuit row to which it is connected.

[0166] The first data line (DL1) is connected to the first subpixel circuit column (PCr11, PCr21, PCr31) and may be arranged on the second side of the first subpixel circuit column (PCr11, PCr21, PCr31), and the second data line (DL2) is connected to the second subpixel circuit column (PCg11, PCg21, PCg31) and may be arranged on the first side of the second subpixel circuit column (PCg11, PCg21, PCg31).

[0167] The third data line (DL3) is connected to the third sub-pixel circuit column (PCb11, PCb21, PCb31) and may be arranged on the first side of the third sub-pixel circuit column (PCb11, PCb21, PCb31), and the fourth data line (DL4) is connected to the fourth sub-pixel circuit column (PCr12, PCr22, PCr32) and may be arranged on the second side of the fourth sub-pixel circuit column (PCr12, PCr22, PCr32).

[0168] The fifth data line (DL5) is connected to the fifth sub-pixel circuit column (PCg12, PCg22, PCg32) and may be arranged on the first side of the fifth sub-pixel circuit column (PCg12, PCg22, PCg32), and the sixth data line (DL6) is connected to the sixth sub-pixel circuit column (PCb12, PCb22, PCb32) and may be arranged on the first side of the sixth sub-pixel circuit column (PCb12, PCb22, PCb32).

[0169] The subpixel circuits belonging to the first subpixel circuit row (PCr11, PCr21, PCr31) can have a symmetrical shape with the subpixel circuits belonging to the second subpixel circuit row (PCg11, PCg21, PCg31). The subpixel circuits belonging to the fourth subpixel circuit row (PCr12, PCr22, PCr32) can have a symmetrical shape with the subpixel circuits belonging to the fifth subpixel circuit row (PCg12, PCg22, PCg32).

[0170] The third subpixel circuit column (PCb11, PCb21, PCb31) and the fourth subpixel circuit column (PCr12, PCr22, PCr32) can overlap with one driving voltage line. The sixth subpixel circuit column (PCb12, PCb22, PCb32) and the seventh subpixel circuit column can overlap with one driving voltage line. According to embodiments of the present invention, since the subpixel circuits arranged in the third subpixel circuit column (PCb11, PCb21, PCb31) and the fourth subpixel circuit column (PCr12, PCr22, PCr32) have a flipped structure, the third subpixel circuit column (PCb11, PCb21, PCb31) and the fourth subpixel circuit column (PCr12, PCr22, PCr32) can share one driving voltage line. Therefore, the area required by the pixel circuit (PCij) can be reduced.

[0171] FIG. 10 is a drawing schematically illustrating first voltage transmission lines (VLv) and second voltage transmission lines (VLh) according to one embodiment of the present invention.

[0172] Referring to FIG. 10, the display device (10) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). In the display area (DA), first voltage transmission lines (VLv) extending in a second direction (y-axis direction) and second voltage transmission lines (VLh) extending in a first direction (x-axis direction) may be arranged.

[0173] The first voltage transmission lines (VLv) and the second voltage transmission lines (VLh) may intersect each other and have a mesh structure on a plane. The first voltage transmission lines (VLv) and the second voltage transmission lines (VLh) may be arranged in different layers, and at least one insulating layer may be arranged between the first voltage transmission lines (VLv) and the second voltage transmission lines (VLh). The first voltage transmission lines (VLv) and the second voltage transmission lines (VLh) may be electrically connected through contact holes (CNT) penetrating the at least one insulating layer. The contact holes (CNT) are arranged in a display area (DA), and the first voltage transmission lines (VLv) and the second voltage transmission lines (VLh) may be electrically connected in the display area (DA).

[0174] The first voltage transmission lines (VLv) and the second voltage transmission lines (VLh) may be lines that transmit a constant voltage. The constant voltage may be a driving voltage (ELVDD, see FIGS. 2a to 2c), a common voltage (ELVSS, see FIGS. 2a to 2c), a first initialization voltage (VINT, see FIGS. 2a to 2c), a second initialization voltage (VAINT, see FIGS. 2a to 2c), a bias voltage (VOBS, see FIGS. 2a to 2c), etc. In one embodiment, the second voltage transmission lines (VLh) may be a first initialization voltage line (VL1, see FIGS. 2a to 2c), a second initialization voltage line (VL2, see FIGS. 2a to 2c), or a bias voltage line (VL3, see FIGS. 2a to 2c).

[0175] By means of the first voltage transmission lines (VLv) and the second voltage transmission lines (VLh), a constant voltage of a certain magnitude can be transmitted to the subpixel circuits regardless of their positions. Therefore, the display device (10) according to one embodiment of the present invention can prevent or reduce luminance deviation between pixels due to voltage drop, thereby displaying high-quality images.

[0176] FIG. 11a is a drawing schematically showing a display device (10) according to one embodiment of the present invention, and FIG. 11b is a drawing schematically explaining a pixel unit (110) and a data distribution unit (170) of the display device (10) shown in FIG. 11a.

[0177] Referring to FIG. 11a, the display device (10) may include a pixel unit (110), a gate driver (130), a data driver (150), a data distribution unit (170), control circuits (180), and a control unit (190).

[0178] The pixel unit (110) may include a plurality of pixel circuits (PCij), a plurality of gate lines (GL1 to GLn), a plurality of data lines (DL1 to DLm), and a plurality of first voltage transmission lines (VLv). Each pixel circuit (PCij) may include a plurality of sub-pixel circuits (PCs). For example, one pixel circuit (PCij) may include a first sub-pixel circuit (PCs1), a second sub-pixel circuit (PCs2), and a third sub-pixel circuit (PCs3).

[0179] Each of the plurality of subpixel circuits (PCs) can be connected to a corresponding gate line among the plurality of gate lines (GL1 to GLn) and a corresponding data line among the plurality of data lines (DL1 to DLm).

[0180] The gate driver (130) is connected to a plurality of gate lines (GL1 to GLn), generates a gate signal in response to a gate drive control signal (GCS) from the control unit (190), and can sequentially supply the gate signal to the gate lines (GL1 to GLn).

[0181] The data driving unit (150) is connected to a plurality of data output lines (OL1 to OLm / i), and the plurality of data output lines (OL1 to OLm / i) can be connected to a plurality of data lines (DL1 to DLm) through the data distribution unit (170).

[0182] The first voltage transmission line (VLv) can transmit a constant voltage. Here, the constant voltage can be a driving voltage (ELVDD), a common voltage (ELVSS), a first initialization voltage (VINT, see FIGS. 2a to 2c), a second initialization voltage (VAINT, see FIGS. 2a to 2c), a bias voltage (VOBS, see FIGS. 2a to 2c), etc.

[0183] The first voltage transmission lines (VLv) are not arranged for each pixel circuit (PCij), but may be arranged according to a predetermined rule. For example, six data lines may be arranged between two adjacent first voltage transmission lines (VLv). Here, the fact that two first voltage transmission lines are adjacent to each other means that no other first voltage transmission lines are arranged between the two first voltage transmission lines.

[0184] Control circuits (180) are connected to a plurality of power output lines (POLs), and the plurality of power output lines (POLs) can be connected to a data distribution unit (170). The control circuits (180) can supply control signals of a sub-demultiplexer (DMX) to the data distribution unit (170) through the power output lines (POLs) according to a distribution control signal (CCS) input from the control unit (190).

[0185] One end of the sub-demultiplexer (DMX) can be connected to a corresponding data output line among a plurality of data output lines (OL1 to OLm / i). The other end of the sub-demultiplexer (DMX) can be connected to i data lines. The sub-demultiplexer (DMX) can supply data signals supplied from the corresponding data output lines to the i data lines.

[0186] The control unit (190) can generate a data drive control signal (DCS), a gate drive control signal (GCS), and a distribution control signal (CCS) in response to externally supplied synchronization signals. The control circuits (180) can output control signals of sub-demultiplexers (DMXs) in response to the distribution control signal (CCS). The data distribution unit (170) can selectively connect data output lines (OL1 to OLm / i) and data lines (DL1 to DLm) in response to the control signals of the sub-demultiplexers (DMXs).

[0187] A driving voltage (ELVDD) and a common voltage (ELVSS) can be supplied to the subpixel circuits (PCs) and organic light-emitting diodes (OLEDs, see FIGS. 2a to 2c) of the display device (10).

[0188] Referring to FIG. 11b, the data distribution unit (170) may include first switches (SW1) and second switches (SW2), and the pixel unit (110) may include a plurality of pixel circuits (PCij). One pixel circuit (PC) may include a red subpixel circuit (PCr), a green subpixel circuit (PCg), ​​and a blue subpixel circuit (PCb). The subpixel circuits (PCr, PCg, PCb) may be repeatedly arranged in a first direction (x-axis direction, row direction) and a second direction (y-axis direction, column direction).

[0189] A plurality of data lines (DL1, DL2, ..., DL6), a plurality of gate lines (GL1, GL2, GL3) and a plurality of first voltage transmission lines (VLv) may be arranged in the pixel portion (110). Although not shown in FIG. 11b, the pixel portion (110) may further include a plurality of second voltage transmission lines (VLh, see FIG. 10) that are electrically connected to the first voltage transmission lines (VLv) and extend in the first direction (x-axis direction).

[0190] A single gate line can be connected to subpixel circuits arranged in the same row. A single data line can be connected to subpixel circuits arranged in the same column.

[0191] The data distribution unit (170) can selectively connect the data output lines (OL1, OL2, OL3) to one of a pair of data lines corresponding to each other. For example, the data distribution unit (170) can selectively connect the first data output line (OL1) to one of the first data line (DL1) and the fourth data line (DL4), selectively connect the second data output line (OL2) to one of the second data line (DL2) and the fifth data line (DL5), and selectively connect the third data output line (OL3) to one of the third data line (DL3) and the sixth data line (DL6).

[0192] Each of the first switches (SW1) may be provided between the first data output line (OL1) and the first data line (DL1), between the second data output line (OL2) and the second data line (DL2), and between the third data output line (OL3) and the third data line (DL3). The first switches (SW1) may be turned on by the first control signal (CLA) to connect the first data output line (OL1) and the first data line (DL1), connect the second data output line (OL2) and the second data line (DL2), and connect the third data output line (OL3) and the third data line (DL3).

[0193] Each of the second switches (SW2) may be provided between the first data output line (OL1) and the fourth data line (DL4), between the second data output line (OL2) and the fifth data line (DL5), and between the third data output line (OL3) and the sixth data line (DL6). The second switches (SW2) may be turned on by the second control signal (CLB) to connect the first data output line (OL1) and the fourth data line (DL4), connect the second data output line (OL2) and the fifth data line (DL5), and connect the third data output line (OL3) and the sixth data line (DL6).

[0194] The control circuit (180, see FIG. 3) can supply a first control signal (CLA) to the first switches (SW1) through the first control signal line (CL1) and supply a second control signal (CLB) to the second switches (SW2) through the second control signal line (CL2).

[0195] The data lines (DL1, DL2, ..., DL6) can be divided into a first group including a first data line (DL1), a second data line (DL2), and a third data line (DL3) that receive data signals by a first control signal (CLA) and are sequentially arranged in a first direction (x-axis direction), and a second group including a fourth data line (DL4), a fifth data line (DL5), and a sixth data line (DL6) that receive data signals by a second control signal (CLB) and are sequentially arranged in the first direction (x-axis direction). The first group and the second group can be alternately arranged in the first direction (x-axis direction).

[0196] The odd-numbered sub-pixel circuit rows may have a flipped shape. Accordingly, the odd-numbered data lines (DL1, DL3, DL5) and the even-numbered data lines (DL2, DL4, DL6) that are adjacent to each other may be arranged to face each other in pairs. For example, the first data line (DL1) and the second data line (DL2) may be arranged to face each other, the third data line (DL3) and the fourth data line (DL4) may be arranged to face each other, and the fifth data line (DL5) and the sixth data line (DL6) may be arranged to face each other.

[0197] At this time, a first voltage transmission line (VLv) may be arranged between the third data line (DL3) and the fourth data line (DL4). The third data line (DL3) and the fourth data line (DL4), which receive data signals by different control signals, are arranged to be spaced apart from each other with the first voltage transmission line (VLv) therebetween, thereby reducing or preventing coupling of the two data lines.

[0198] Each of the data lines (DL1, DL2, ..., DL6) can be arranged on the first side (left) or the second side (right) of the subpixel circuit row to which it is connected. Each of the odd-numbered data lines (DL1, DL3, DL5) can be arranged on the second side of the subpixel circuit row to which it is connected, and each of the even-numbered data lines (DL2, DL4, DL6) can be arranged on the first side of the subpixel circuit row to which it is connected.

[0199] That is, the first data line (DL1) is connected to the first subpixel circuit column (PCr11, PCr21, PCr31) and may be arranged on the second side of the first subpixel circuit column (PCr11, PCr21, PCr31), and the second data line (DL2) is connected to the second subpixel circuit column (PCg11, PCg21, PCg31) and may be arranged on the first side of the second subpixel circuit column (PCg11, PCg21, PCg31).

[0200] The third data line (DL3) is connected to the third sub-pixel circuit column (PCb11, PCb21, PCb31) and may be arranged on the second side of the third sub-pixel circuit column (PCb11, PCb21, PCb31), and the fourth data line (DL4) is connected to the fourth sub-pixel circuit column (PCr12, PCr22, PCr32) and may be arranged on the first side of the fourth sub-pixel circuit column (PCr12, PCr22, PCr32).

[0201] The fifth data line (DL5) is connected to the fifth sub-pixel circuit column (PCg12, PCg22, PCg32) and may be arranged on the second side of the fifth sub-pixel circuit column (PCg12, PCg22, PCg32), and the sixth data line (DL6) is connected to the sixth sub-pixel circuit column (PCb12, PCb22, PCb32) and may be arranged on the first side of the sixth sub-pixel circuit column (PCb12, PCb22, PCb32).

[0202] In one embodiment, the subpixel circuits belonging to the second subpixel circuit row (PCg11, PCg21, PCg31) may have a symmetrical shape with the subpixel circuits belonging to the third subpixel circuit row (PCb11, PCb21, PCb31).

[0203] The second subpixel circuit rows (PCg11, PCg21, PCg31) and the third subpixel circuit rows (PCb11, PCb21, PCb31) can be overlapped on one driving voltage line.

[0204] The subpixel circuits belonging to the fourth subpixel circuit row (PCr12, PCr22, PCr32) can have a symmetrical shape with the subpixel circuits belonging to the fifth subpixel circuit row (PCg12, PCg22, PCg32). The fourth subpixel circuit row (PCr12, PCr22, PCr32) and the fifth subpixel circuit row (PCg12, PCg22, PCg32) can overlap on a single driving voltage line.

[0205] FIG. 12a is a drawing schematically showing a display device (10) according to one embodiment of the present invention, and FIG. 12b is a drawing schematically explaining a pixel unit (110) and a data distribution unit (170) of the display device (10) shown in FIG. 12a.

[0206] Figures 12a and 12b are similar to Figures 11a and 11b, respectively, but differ in the arrangement of subpixel circuits, data lines, and first voltage transmission lines. Below, descriptions of identical or similar components will be omitted, and the differences will be explained.

[0207] Referring to FIGS. 12a and 12b, the first to sixth data lines (DL1, DL2, ..., DL6) can be divided into a first group including a first data line (DL1), a second data line (DL2), and a third data line (DL3) that receive data signals by a first control signal (CLA) and are sequentially arranged in a first direction (x-axis direction), and a second group including a fourth data line (DL4), a fifth data line (DL5), and a sixth data line (DL6) that receive data signals by a second control signal (CLB) and are sequentially arranged in the first direction (x-axis direction).

[0208] The seventh to twelfth data lines (DL7, DL8, ..., DL12) can be divided into a first group including the seventh data line (DL7), the eighth data line (DL8), and the ninth data line (DL9) which receive data signals by the first control signal (CLA) and are sequentially arranged in the first direction (x-axis direction), and a second group including the tenth data line (DL10), the eleventh data line (DL11), and the twelfth data line (DL12) which receive data signals by the second control signal (CLB) and are sequentially arranged in the first direction (x-axis direction). In other words, the first group and the second group can be alternately arranged in the first direction (x-axis direction).

[0209] Even-numbered subpixel circuit rows may have a flipped shape. Accordingly, adjacent even-numbered data lines (DL2, DL4, DL6, DL8, DL10) and odd-numbered data lines (DL3, DL5, DL7, DL9, DL11) may be arranged to face each other in pairs. For example, the second data line (DL2) and the third data line (DL3) may be arranged to face each other, the fourth data line (DL4) and the fifth data line (DL5) may be arranged to face each other, the sixth data line (DL6) and the seventh data line (DL7) may be arranged to face each other, the eighth data line (DL8) and the ninth data line (DL9) may be arranged to face each other, and the tenth data line (DL10) and the eleventh data line (DL11) may be arranged to face each other.

[0210] At this time, two subpixel circuit columns may be arranged between the third data line (DL3) and the fourth data line (DL4), a first voltage transmission line (VLv) may be arranged between the sixth data line (DL6) and the seventh data line (DL7), and two subpixel circuit columns may be arranged between the ninth data line (DL9) and the tenth data line (DL10). Two data lines that receive data signals by different control signals and are adjacent to each other may be arranged to be spaced apart from each other by being placed between the two subpixel circuit columns or the first voltage transmission line (VLv), thereby reducing or preventing coupling.

[0211] Each of the data lines (DL1, DL2, ..., DL6) can be arranged on the first side (left) or the second side (right) of the subpixel circuit row to which it is connected. Each of the odd-numbered data lines (DL1, DL3, DL5) can be arranged on the first side of the subpixel circuit row to which it is connected, and each of the even-numbered data lines (DL2, DL4, DL6) can be arranged on the second side of the subpixel circuit row to which it is connected.

[0212] In one embodiment, a pair of subpixel circuit columns arranged between two data lines may overlap a single driving voltage line. For example, a first subpixel circuit column (PCr11, PCr21, PCr31) and a second subpixel circuit column (PCg11, PCg21, PCg31) may overlap a single driving voltage line.

[0213] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will appreciate that various modifications and equivalent alternative embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A pixel unit including subpixel circuits arranged in the row and column directions and data lines connected to the corresponding subpixel circuits; A data drive circuit that outputs data signals through output lines; A data distribution unit that selectively connects the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal; and A control circuit that alternately outputs the first control signal and the second control signal; The above data lines include a first data line and a second data line that are adjacent to each other and receive corresponding data signals by different control signals among the first control signal and the second control signal, and a third data line and a fourth data line that are adjacent to each other and receive corresponding data signals by the same control signal among the first control signal and the second control signal. A display device, wherein the first data line and the second data line are arranged spaced apart from each other with at least one sub-pixel circuit row therebetween, and two adjacent data lines among the first data line, the second data line, the third data line, and the fourth data line are arranged facing each other.

2. In paragraph 1, Each of the above data lines is arranged on the first or second side of the corresponding subpixel circuit row, A display device, wherein the third data line is arranged on the second side of the corresponding subpixel circuit row, and the fourth data line is arranged on the first side of the corresponding subpixel circuit row.

3. In paragraph 2, The above data lines further include a fifth data line and a sixth data line, The fifth data line and the sixth data line are adjacent to each other and receive corresponding data signals according to the same control signal among the first control signal and the second control signal. The fifth data line is connected to the first output line among the output lines by the first control signal, the sixth data line is connected to the second output line among the output lines by the first control signal, and the first data line is connected to the third output line among the output lines by the first control signal. A display device, wherein the second data line is connected to the first output line by the second control signal, the third data line is connected to the second output line by the second control signal, and the fourth data line is connected to the third output line by the second control signal.

4. In paragraph 3, A display device, wherein each of the first data line and the second data line is arranged on the first side of the corresponding subpixel circuit row.

5. In paragraph 4, A display device, wherein a sub-pixel circuit row connected to the first data line is arranged between the first data line and the second data line.

6. In paragraph 4, A display device, wherein the fifth data line is arranged on the first side of the corresponding subpixel circuit row, and the sixth data line is arranged on the second side of the corresponding subpixel circuit row.

7. In paragraph 4, A display device in which a subpixel circuit column connected to the fifth data line and a subpixel circuit column connected to the sixth data line overlap on a single driving voltage line.

8. In paragraph 3, A display device, wherein the first data line is arranged on the first side of the corresponding subpixel circuit row, and the second data line is arranged on the second side of the corresponding subpixel circuit row.

9. In paragraph 8, A display device in which a subpixel circuit column connected to the first data line and a subpixel circuit column connected to the second data line overlap on one driving voltage line.

10. In paragraph 8, A display device in which the fifth data line and the sixth data line are arranged facing each other 11. A pixel unit including subpixel circuits repeatedly arranged in the row and column directions, data lines connected to the corresponding subpixel circuits, and first voltage transmission lines extending in the column direction; A data drive circuit that outputs data signals through output lines; A data distribution unit that selectively connects the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal; and A control circuit that alternately outputs the first control signal and the second control signal; The above data lines include first groups and second groups, Each of the above first groups includes a first data line, a second data line, and a third data line that are supplied with a data signal by the first control signal and are sequentially arranged in the row direction, Each of the second groups includes a fourth data line, a fifth data line, and a sixth data line that are supplied with a data signal by the second control signal and are sequentially arranged in the row direction, A display device in which the first group and the second group are arranged alternately in the row direction, and one of the first voltage transmission lines is arranged between the third data line and the fourth data line.

12. In paragraph 11, Each of the above data lines is arranged on the first or second side of the corresponding subpixel circuit row, Each of the odd-numbered data lines among the above data lines is arranged on the second side of the corresponding subpixel circuit row, A display device, wherein each of the even-numbered data lines among the above data lines is arranged on the first side of the corresponding subpixel circuit row.

13. In paragraph 11, The first data line is connected to the first output line among the output lines by the first control signal, The second data line is connected to the second output line among the output lines by the first control signal, The third data line is connected to the third output line among the output lines by the first control signal, The fourth data line is connected to the first output line by the second control signal, The fifth data line is connected to the second output line by the second control signal, A display device, wherein the sixth data line is connected to the third output line by the second control signal.

14. In paragraph 11, The pixel portion further includes second voltage transmission lines extending in the row direction, A display device in which the first voltage transmission lines are connected to the second voltage transmission lines.

15. In paragraph 11, A display device in which six data lines are arranged between two adjacent first voltage transmission lines among the above first voltage transmission lines.

16. A pixel unit including subpixel circuits repeatedly arranged in the row and column directions, data lines connected to the corresponding subpixel circuits, and first voltage transmission lines extending in the column direction; A data drive circuit that outputs data signals through output lines; A data distribution unit that selectively connects the output lines to one of a pair of data lines corresponding to each of the output lines among the data lines according to a first control signal and a second control signal; and A control circuit that alternately outputs the first control signal and the second control signal; The above data lines include first groups and second groups, Each of the first groups includes a first data line, a second data line, and a third data line that are connected to corresponding output lines by the first control signal and are sequentially arranged in the row direction, Each of the second groups includes a fourth data line, a fifth data line, and a sixth data line sequentially arranged in the row direction and connected to corresponding output lines by the second control signal, A display device in which the first group and the second group are arranged alternately in the row direction, and one of the first voltage transmission lines is arranged between the sixth data line and the first data line.

17. In paragraph 16, Each of the above data lines is arranged on the first or second side of the corresponding subpixel circuit row, Each of the odd-numbered data lines among the above data lines is arranged on the first side of the corresponding subpixel circuit row, A display device, wherein each of the even-numbered data lines among the above data lines is arranged on the second side of the corresponding subpixel circuit row.

18. In paragraph 16, The first data line is connected to the first output line among the output lines by the first control signal, The second data line is connected to the second output line among the output lines by the first control signal, The third data line is connected to the third output line among the output lines by the first control signal, The fourth data line is connected to the first output line by the second control signal, The fifth data line is connected to the second output line by the second control signal, A display device, wherein the sixth data line is connected to the third output line by the second control signal.

19. In paragraph 16, The pixel portion further includes second voltage transmission lines extending in the row direction, A display device in which the first voltage transmission lines are connected to the second voltage transmission lines.

20. In paragraph 16, A display device in which six data lines are arranged between two adjacent first voltage transmission lines among the above first voltage transmission lines.

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