Time offset calibration apparatus and method, chip, and electronic device

Abstract

The present disclosure relates to a time offset calibration apparatus and method, a chip, and an electronic device. The time offset calibration apparatus is used for calibrating a multi-channel analog-to-digital converter, and comprises an input buffer and a time offset extraction module. The input buffer inputs, into the analog-to-digital converter, a summed signal of a reference clock signal modulated by means of a random jitter signal and a signal to be processed, so that a plurality of channels of the analog-to-digital converter are used for sampling and quantifying the summed signal in turn according to a preset sequence, to output a raw output signal of each channel. On the basis of the raw output signal of each channel of the analog-to-digital converter and the random jitter signal, the time offset extraction module determines a time offset used for calibrating a sampling clock of the analog-to-digital converter and a calibration result of the raw output signal. The time offset calibration apparatus of the present disclosure can work under any input signal, can perform background calibration, has high calibration precision, and expands application scenarios.

Description

Time deviation calibration device, method, chip and electronic equipment Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a time deviation calibration device, method, chip, and electronic device. Background Art

[0002] Calibration circuits in analog mixed-signal integrated circuits can be used to correct for non-idealities in analog circuits. These circuits can consist of both analog and digital circuits, combining them to achieve accuracy requirements that cannot be achieved by analog circuits alone. An analog-to-digital converter (ADC) is an electronic system that converts analog signals into digital signals and can be implemented within an integrated circuit. High-speed, high-performance ADCs (e.g., those with sampling rates greater than 100MS / s) are used in wireless communications, LiDAR, wired transmission, and other fields.

[0003] In order to achieve a high sampling rate, the analog-to-digital converter can adopt a time-interleaved structure, that is, the analog-to-digital converter can include N (N≥2) identical sub-channels, and the input signal is sampled and quantized in turn through the N sub-channels, thereby increasing the sampling rate by N times as a whole. Figure 1 shows a sampling timing diagram of a two-channel time-interleaved analog-to-digital converter in the related art. As shown in Figure 1, under ideal conditions, the sampling time intervals of each sub-channel are uniform, and are all sampling periods T S However, in actual chips, there will inevitably be mismatches between sub-channels due to wiring and components, so the sampling time intervals between different channels will be different from the ideal sampling period T S The offset occurs, resulting in a time deviation Δt, which seriously affects the performance of the time-interleaved ADC. Therefore, the time-interleaved ADC needs to calibrate the time deviation between channels to meet the high performance requirements of the ADC.

[0004] Summary of the Invention

[0005] In view of this, the present disclosure proposes a time offset calibration solution.

[0006] According to one aspect of the present disclosure, a time deviation calibration device is provided, which is used to calibrate a multi-channel analog-to-digital converter. The time deviation calibration device includes an input buffer and a time deviation extraction module, the input buffer is connected to the input end of the analog-to-digital converter, and the time deviation extraction module is connected to the output end of the analog-to-digital converter; the input buffer is used to inject a reference clock signal modulated by a random jitter signal and a sum signal of the signal to be processed into the analog-to-digital converter, so that multiple channels of the analog-to-digital converter sample and quantize the sum signal in turn according to a preset sequence, and output the original output signal of each channel; the time deviation extraction module is used to determine the time deviation used to calibrate the sampling clock of the analog-to-digital converter, and the calibration result of the original output signal, based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal.

[0007] In one possible implementation, the input buffer includes a first push-pull circuit and a second push-pull circuit having the same circuit structure, the first push-pull circuit is used to follow the signal to be processed, and the second push-pull circuit is used to follow the reference clock signal modulated by a random jitter signal, and the output end of the first push-pull circuit and the output end of the second push-pull circuit are connected to the input end of the analog-to-digital converter.

[0008] In a possible implementation, the input buffer further includes a first bootstrap circuit and a second bootstrap circuit having the same circuit structure, the first bootstrap circuit is connected to the first push-pull circuit, and the second bootstrap circuit is connected to the second push-pull circuit.

[0009] In one possible implementation, the time deviation extraction module includes a reference clock signal prediction circuit, a time deviation extraction circuit, and an output calibration circuit. The output end of the reference clock signal prediction circuit is respectively connected to the input end of the time deviation extraction circuit and the input end of the output calibration circuit. The reference clock signal prediction circuit is used to extract the reference clock prediction signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal; the time deviation extraction circuit is used to determine the time deviation based on the reference clock prediction signal, and the time deviation includes a positive deviation or a negative deviation; the output calibration circuit is used to determine the calibration result of the original output signal based on the reference clock prediction signal, the random jitter signal, and the original output signal.

[0010] In one possible implementation, the reference clock signal prediction circuit includes a first multiplier and a low-pass filter, wherein the first multiplier is connected to the low-pass filter; the first multiplier is used to multiply the original output signal of each channel of the analog-to-digital converter with the random jitter signal to obtain a first product result; the low-pass filter is used to perform low-pass filtering on the first product result to obtain a reference clock prediction signal.

[0011] In one possible implementation, the time deviation extraction circuit includes a first subtractor and a comparator, wherein the first subtractor is connected to the comparator; the first subtractor is used to subtract the reference clock prediction signal from a preset reference value to obtain a difference; the comparator is used to compare the difference with a preset threshold value and use the comparison result as the time deviation. The preset reference value may include the reference clock prediction signal extracted by the time deviation extraction module corresponding to any channel (e.g., a fixed channel). For example, in a 4-channel time-interleaved analog-to-digital converter, if the reference clock prediction signal extracted by the time deviation extraction module corresponding to channel 3 is taken as the reference value, then for channels 1, 2, and 4, the reference value is the reference clock prediction signal extraction value of channel 3.

[0012] In one possible implementation, the output calibration circuit includes a second multiplier and a second subtractor, and the second multiplier is connected to the second subtractor; the second multiplier is used to multiply the reference clock prediction signal with the random jitter signal to obtain a second product result; the second subtractor is used to perform a difference between the original output signal and the second product result to obtain a calibration result of the original output signal.

[0013] In one possible implementation, the time deviation calibration device also includes an adjustable delay line, which receives the time deviation extracted by the time deviation extraction module and performs background calibration of the time deviation of the multi-channel analog-to-digital converter; wherein, when the time deviation extracted by the time deviation extraction module of the current channel is a positive deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be ahead of a preset number of steps; or, when the time deviation extracted by the time deviation extraction module of the current channel is a negative deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be behind a preset number of steps.

[0014] According to another aspect of the present disclosure, a time deviation calibration method is provided. The time deviation calibration method is applied to a time deviation calibration device, which is used to calibrate a multi-channel analog-to-digital converter. The time deviation calibration device includes an input buffer and a time deviation extraction module, the input buffer is connected to the input end of the analog-to-digital converter, and the time deviation extraction module is connected to the output end of the analog-to-digital converter. The time deviation calibration method includes: the input buffer injects a reference clock signal modulated by a random jitter signal and a sum signal of the signal to be processed into the analog-to-digital converter, so that multiple channels of the analog-to-digital converter sample and quantize the sum signal in turn according to a preset sequence, and output an original output signal of each channel; the time deviation extraction module outputs a time deviation for calibrating the sampling clock of the analog-to-digital converter and a calibration result of the original output signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal.

[0015] In one possible implementation, the input buffer includes a first push-pull circuit and a second push-pull circuit having the same circuit structure, the first push-pull circuit is used to follow the signal to be processed, and the second push-pull circuit is used to follow the reference clock signal modulated by a random jitter signal, and the output end of the first push-pull circuit and the output end of the second push-pull circuit are connected to the input end of the analog-to-digital converter.

[0016] In a possible implementation, the input buffer further includes a first bootstrap circuit and a second bootstrap circuit having the same circuit structure, the first bootstrap circuit is connected to the first push-pull circuit, and the second bootstrap circuit is connected to the second push-pull circuit.

[0017] In one possible implementation, the time deviation extraction module includes a reference clock signal prediction circuit, a time deviation extraction circuit, and an output calibration circuit. The output end of the reference clock signal prediction circuit is connected to the input end of the time deviation extraction circuit and the input end of the output calibration circuit, respectively. The time deviation extraction module outputs a time deviation for calibrating the sampling clock of the analog-to-digital converter based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal, as well as a calibration result of the original output signal, including:

[0018] The reference clock signal prediction circuit extracts a reference clock prediction signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal; the time deviation extraction circuit determines the time deviation based on the reference clock prediction signal, and the time deviation includes a positive deviation or a negative deviation; the output calibration circuit determines the calibration result of the original output signal based on the reference clock prediction signal, the random jitter signal, and the original output signal.

[0019] In one possible implementation, the reference clock signal prediction circuit includes a first multiplier and a low-pass filter, the first multiplier is connected to the low-pass filter, and the reference clock signal prediction circuit extracts the reference clock prediction signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal, including: the first multiplier multiplies the original output signal of each channel of the analog-to-digital converter with the random jitter signal to obtain a first product result; the low-pass filter performs low-pass filtering on the first product result to obtain the reference clock prediction signal.

[0020] In one possible implementation, the time deviation extraction circuit includes a first subtractor and a comparator, the first subtractor is connected to the comparator, and the time deviation extraction circuit determines the time deviation based on the reference clock prediction signal, including: the first subtractor subtracts the reference clock prediction signal from a preset reference value to obtain a difference; the comparator compares the difference with a preset threshold and uses the comparison result as the time deviation.

[0021] In one possible implementation, the output calibration circuit includes a second multiplier and a second subtractor, the second multiplier is connected to the second subtractor, and the output calibration circuit determines the calibration result of the original output signal based on the reference clock prediction signal, the random jitter signal, and the original output signal, including: the second multiplier multiplies the reference clock prediction signal by the random jitter signal to obtain a second product result; the second subtractor performs a difference between the original output signal and the second product result to obtain the calibration result of the original output signal.

[0022] In one possible implementation, the time deviation calibration device also includes an adjustable delay line, and the method also includes: the adjustable delay line receives the time deviation extracted by the time deviation extraction module, and performs background calibration of the time deviation on the multi-channel analog-to-digital converter; wherein, when the time deviation extracted by the time deviation extraction module of the current channel is a positive deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be ahead of a preset number of steps; or, when the time deviation extracted by the time deviation extraction module of the current channel is a negative deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be behind a preset number of steps.

[0023] According to another aspect of the present disclosure, a chip is provided, comprising the time deviation calibration device as described above.

[0024] According to another aspect of the present disclosure, an electronic device is provided, comprising the time deviation calibration device as described above.

[0025] The time deviation calibration device of the disclosed embodiment, through the coordinated operation of an input buffer and a time deviation extraction module, can extract time deviation independently of the properties of the input signal to be processed (e.g., without requiring the derivative, autocorrelation function, or time-domain zero crossing of the signal to be processed). The signal to be processed can be any signal, and the device can operate with any input signal to be processed. The device can perform background calibration without interrupting the normal operation of the analog-to-digital converter. Furthermore, the device has high calibration accuracy, is unaffected by inter-channel routing and component mismatch, and leaves no residual time deviation after calibration.

[0026] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0028] FIG1 shows a sampling timing diagram of a two-channel time-interleaved analog-to-digital converter in the related art.

[0029] FIG2 is a schematic diagram showing two implementation schemes for time deviation calibration using a reference clock signal in related art.

[0030] FIG3 is a schematic diagram showing the reasons why calibration accuracy is limited in the related art.

[0031] FIG4 shows a schematic diagram of a time deviation calibration device according to an embodiment of the present disclosure.

[0032] FIG5 shows a schematic diagram of a time deviation calibration device according to an embodiment of the present disclosure.

[0033] FIG6 shows a schematic diagram of an input buffer circuit according to an embodiment of the present disclosure.

[0034] FIG. 7 is a schematic diagram showing the advantages of the input buffer according to an embodiment of the present disclosure.

[0035] FIG8 shows a schematic diagram of another input buffer according to an embodiment of the present disclosure.

[0036] FIG9 shows a schematic diagram of another time deviation calibration device according to an embodiment of the present disclosure.

[0037] FIG10 shows a flowchart of a time offset calibration method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0039] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0040] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0041] In the related art, the calibration method for time deviation in a time-interleaved multi-channel analog-to-digital converter can use the statistical characteristics of the input signal of the multi-channel analog-to-digital converter to extract the time deviation; or, a reference channel can be set for the multi-channel analog-to-digital converter, and the derivative characteristics of the reference channel and the input signal of the multi-channel analog-to-digital converter can be used to extract the time deviation.

[0042] However, the aforementioned calibration methods all rely on the properties of the input signal (e.g., its derivative, autocorrelation function, time-domain zero-crossing characteristics, etc.), and impose corresponding requirements on the input signal (e.g., requiring the input signal to be AC, wide-stationary, or time-domain zero-crossing). Therefore, the aforementioned calibration methods cannot work with any input signal and cannot meet system requirements in many application scenarios, such as when the system needs to support DC or non-stationary signal inputs.

[0043] In this case, a reference clock signal can be set for the multi-channel analog-to-digital converter, and the reference clock signal can be used to calibrate the time deviation. The calibration principle does not depend on the properties of the input signal and can be well adapted to any input signal.

[0044] FIG2 is a schematic diagram showing two implementation schemes for time deviation calibration using a reference clock signal in related art.

[0045] As shown in Figure 2, in solution 1, channel 1 and channel 2 are two channels of the time-interleaved analog-to-digital converter, V in Represents the input signal of the time-interleaved analog-to-digital converter, CLK ref=Represents the reference clock signal, CLK1 represents the sampling clock signal of channel 1, CLK2 represents the sampling clock signal of channel 2, △t represents the time deviation between channel 1 and channel 2. △V represents the difference between the reference clock signal CLK1 and channel 2 due to the time deviation △t between channel 1 and channel 2. ref Sampling error. Solution 1: The reference clock signal CLK ref It is injected from the input of the time-interleaved analog-to-digital converter, and each channel (such as channel 1 and channel 2) samples and quantizes it. The time deviation information is extracted and calibrated by comparing the sizes of the quantization results.

[0046] As shown in Figure 2, in Scheme 2, Channel 1 and Channel 2 are two channels of the time-interleaved analog-to-digital converter, V in Represents the input signal of the time-interleaved analog-to-digital converter, PN represents the random jitter signal, CLK ref Represents the reference clock signal, C D1 and C D2 Indicates the reference clock signal CLK ref The sampling capacitor C S1 and C S2 Indicates the input signal V in Sampling capacitor. Solution 2 will reference clock signal CLK ref After being modulated by a random jitter signal PN, the local input of each channel (such as channel 1 and channel 2) is injected into the time-interleaved analog-to-digital converter. After sampling and quantization, the output signal of each channel is correlated with the PN signal to extract the reference clock signal CLK of each channel. ref The sampling and quantization results are compared to realize the extraction and calibration of time deviation information.

[0047] It can be seen that when performing time deviation calibration in Scheme 1, the switch at the input end of the analog-to-digital converter should be changed from the input signal V in Switch to the reference clock signal CLK ref , which requires interrupting the normal operation of the ADC. Therefore, Solution 1 is a foreground calibration method that is difficult to apply in many scenarios. Foreground calibration requires inputting a known signal into the ADC and extracting calibration information based on the characteristics of the known signal. This calibration method interrupts the normal operation of the ADC.

[0048] Solution 2 uses random jitter signal PN to realize the reference clock signal CLK ref With the input signal V inThe time-interleaved ADC is injected simultaneously and the two can be separated at the output, thus achieving background calibration without interrupting the normal operation of the ADC. Background calibration extracts calibration information while the ADC is operating, without interrupting the ADC's normal operation. However, scheme 2 suffers from low calibration accuracy, resulting in a large residual error in time offset after calibration, primarily due to mismatches in routing and components between channels.

[0049] FIG3 is a schematic diagram showing the reasons for the limited calibration accuracy in the related art. As shown in FIG3, since the scheme 2 converts the reference clock signal CLK ref From the local injection of each channel, when there is a mismatch between the routing, switches, capacitors and other components of the reference clock signal between channels, different channels will see different reference clock signals CLK even if there is no time deviation between channels. ref , thus affecting the calibration of time deviation; when the input signal V in When there is mismatch in the wiring, switches, capacitors and other components, the time deviation generated by this part cannot be referenced by the clock signal CLK ref This can be perceived, thus affecting the calibration of the time offset. Therefore, Scheme 2 suffers from a large residual error after time offset calibration and low accuracy, making it difficult to achieve widespread application. This calibration scheme cannot simultaneously address both background operation capabilities (e.g., the ability to extract calibration information while the ADC is operating normally, without interrupting the ADC's normal operation) and calibration accuracy requirements, significantly limiting its application scenarios.

[0050] Considering that the time deviation calibration method in the related art cannot work under any input signal, and the method of using the reference clock signal for time deviation calibration cannot meet the requirements of background work and calibration accuracy at the same time, the existing method cannot be applied to industrial products.

[0051] In view of this, an embodiment of the present disclosure proposes a time deviation calibration device, which can operate under any input signal, can perform background calibration, and has high calibration accuracy (for example, there is no residual time deviation after calibration). Figure 4 shows a schematic diagram of the time deviation calibration device of an embodiment of the present disclosure. As shown in Figure 4, the time deviation calibration device 1 is used to calibrate a multi-channel analog-to-digital converter 2, wherein the analog-to-digital converter 2 may include N (N≥2) channels, that is, the analog-to-digital converter 2 can be composed of N identical analog-to-digital converters connected in parallel, each analog-to-digital converter can serve as a channel, and the N channels of the analog-to-digital converter 2 can take turns sampling and quantizing the input signal in a preset order (for example, including the order from channel 1 to channel N).

[0052] As shown in FIG4 , the time deviation calibration device 1 includes an input buffer 11 and a time deviation extraction module 12 , wherein the input buffer 11 is connected to the input end of the analog-to-digital converter 2 , and the time deviation extraction module 12 is connected to the output end of the analog-to-digital converter 2 ;

[0053] The input buffer 11 is used to convert the reference clock signal V modulated by the random jitter signal PN into d and the signal to be processed V in The sum signal V in,ADC , is injected into the analog-to-digital converter 2 so that the multiple channels of the analog-to-digital converter 2 take turns to process the sum signal V in a preset order. in,ADC Sampling and quantization are performed to output the original output signal D of each channel raw ;

[0054] Among them, the initial reference clock signal CLK ref By introducing random jitter signal PN for modulation, the modulated reference clock signal V can be generated. d The random jitter signal PN may be a signal with a positive voltage or a signal with a negative voltage. The embodiment of the present disclosure does not limit the magnitude of the random jitter signal PN.

[0055] The time deviation extraction module 12 is used to extract the original output signal D of each channel of the analog-to-digital converter 2 raw and the random jitter signal PN, determine the time deviation Δt used to calibrate the sampling clock of the analog-to-digital converter 2, and the original output signal D raw The calibration result D out .

[0056] Compared with the solution 1 in FIG2 , the time deviation calibration device 1 of the embodiment of the present disclosure introduces a random jitter signal PN to change the initial reference clock signal CLK ref After random jitter signal PN modulation, the modulated reference clock signal V is obtained. d , and use the input buffer 11 to modulate the reference clock signal V d and the signal to be processed V in The sum signal V in,ADC Injected into the input of the time-interleaved multi-channel analog-to-digital converter 2. And at the output of the analog-to-digital converter 2, the predicted reference clock signal is extracted from the input original output signal D using the time deviation extraction module 12. raw The calibration can be performed in the presence of a continuous input signal without interrupting the normal operation of the analog-to-digital converter 2, thus realizing background calibration.

[0057] Compared with the solution 2 in FIG2 , the time deviation calibration device 1 of the embodiment of the present disclosure converts the modulated reference clock signal V d The injection position is moved from the local analog-to-digital converter of each sub-channel (see solution 2 in Figure 2) to the input end of the analog-to-digital converter 2 containing multiple channels, so that the calibration accuracy is not affected by the mismatch between the wiring and components between channels. Specifically, in the time deviation calibration device 1 of the embodiment of the present disclosure, since the modulated reference clock signal V d and the input signal to be processed V in It is injected from the input end of the analog-to-digital converter 2 through the input buffer 11. For the analog-to-digital converter of each sub-channel contained in the analog-to-digital converter 2, the wiring, switches, capacitors and other components passed by the two are consistent. When the wiring, switches, capacitors and other components of the input signal between channels are mismatched and a time deviation occurs, the modulated reference clock signal V d Can sense the input signal to be processed V in The mismatch of the same traces, switches, capacitors and other components can be extracted to extract the time deviation caused by this mismatch and calibrate it. Therefore, after calibration, the time deviation calibration device 1 of the embodiment of the present disclosure has no residual time deviation, which greatly improves the calibration accuracy.

[0058] It can be seen that the time deviation calibration device 1 of the embodiment of the present disclosure can extract the time deviation Δt independently of the input signal to be processed V by cooperating with the input buffer 11 and the time deviation extraction module 12. in properties (e.g., including the absence of a signal to be processed V in derivative, autocorrelation function, time domain zero crossing), the signal to be processed V in It can be any signal, and can be any input signal to be processed V in The time deviation calibration device 1 can realize background calibration without interrupting the normal operation of the analog-to-digital converter 2. In addition, the time deviation calibration device 1 has high calibration accuracy and is not affected by the mismatch between the wiring and components between channels. After the calibration is completed, there is no residual time deviation.

[0059] In one possible implementation, each channel of the analog-to-digital converter 2 may correspond to a time deviation extraction module 12. For example, if the analog-to-digital converter 2 has N channels, the time deviation calibration device 1 may include N time deviation extraction modules 12. The output end of the first channel of the analog-to-digital converter 2 may be connected to the first time deviation extraction module 12, the output end of the second channel of the analog-to-digital converter 2 may be connected to the second time deviation extraction module 12, and so on. The output end of the Nth channel of the analog-to-digital converter 2 may be connected to the Nth time deviation extraction module 12.

[0060] In this way, the N time deviation extraction modules 12 can take turns according to the original output signal D of each channel of the analog-to-digital converter 2 in a preset order. raw and the random jitter signal PN, determine the time deviation Δt used to calibrate the sampling clock of the analog-to-digital converter 2, and the original output signal D raw The calibration result D out .

[0061] For example, the N channels of the analog-to-digital converter 2 may take turns to process the input sum signal V in the order of 1 to N in each cycle. in,ADC Sampling and quantization are performed, that is, for any P-th cycle, the first channel can be P The summation signal V in,ADC For sampling and quantization, the second channel can be P +(2-1)×T S The summation signal V in,ADC Sampling and quantization are performed, and so on, the Nth channel can be sampled and quantized at T P +(N-1)×T S The summation signal V in,ADC Sampling and quantization are performed, where T P Indicates the sampling time of the first channel at the beginning of the P cycle, T S Indicates the phase difference between the sampling start times of any two adjacent channels in the same cycle.

[0062] The time deviation extraction module 12 corresponding to each channel can extract M (for example, M is 10 7 ) cycles as a group, and the sampling clock of the channel is calibrated once every M cycles. It should be understood that the embodiment of the present disclosure does not limit the specific value of M, and it can be set according to the actual application scenario. In this way, it is the turn of the Kth channel of the analog-to-digital converter 2 (K is any value from 1 to N) to calibrate the input sum signal V in,ADC When sampling and quantization are performed, the Kth channel outputs the original output signal D after sampling and quantization. raw To the corresponding K-th time deviation extraction module 12, if the current group has not reached M cycles, the time deviation extraction module 12 of the K-th channel can accumulate the original output signal D of the K-th channel in the current cycle raw and random jitter signal PN, which is used to determine the reference clock prediction signal D of the current group when M cycles are accumulated. d , and according to the original output signal D of the current cycle raw and random jitter signal PN, combined with the original output signal D over a set of M cycles raw and the reference clock prediction signal D determined by the random jitter signal PN d, determine the original output signal D after sampling and quantization of the Kth channel in the current cycle raw The calibration result D out If the current group reaches M cycles, the time deviation extraction module 12 can be based on the original output signal D of the Kth channel of the current cycle raw and random jitter signal PN, and the original output signal D of the Kth channel accumulated in the previous M-1 cycles raw and random jitter signal PN to determine the reference clock prediction signal D of the current group d , and then predict the signal D based on the reference clock of the current group d And the original output signal D of the Kth channel in the current cycle raw and random jitter signal PN, determine the time deviation △t used to calibrate the sampling clock of the K-th channel of the analog-to-digital converter 2, and the original output signal D after the K-th channel sampling and quantization raw The calibration result D out .

[0063] It should be understood that, under the condition that each channel of the analog-to-digital converter 2 corresponds to a time deviation extraction module 12, the embodiments of the present disclosure do not impose specific restrictions on the number of channels of the analog-to-digital converter 2 and the number of time deviation extraction modules 12, and can be set according to the actual application scenario.

[0064] FIG5 is a schematic diagram of a time deviation calibration device according to an embodiment of the present disclosure. The following uses FIG5 as an example to describe the time deviation calibration device 1 according to an embodiment of the present disclosure. As shown in FIG5 , the analog-to-digital converter 2 has two channels (e.g., channel 1 and channel 2). Channel 1 and channel 2 can take turns sampling and quantizing the signal input to the analog-to-digital converter 2. S1 represents the sampling capacitor of channel 1, C S2 represents the sampling capacitor of channel 2. To match the dual-channel analog-to-digital converter 2 and perform time offset calibration on the dual-channel analog-to-digital converter 2, the time offset calibration device 1 of the present embodiment may include an input buffer 11 and two time offset extraction modules 12. The input buffer 11 is connected to the input of the analog-to-digital converter 2, one time offset extraction module 12 is connected to the output of channel 1 of the analog-to-digital converter 2 (not shown in FIG. 5 ), and the other time offset extraction module 12 is connected to the output of channel 2 of the analog-to-digital converter 2.

[0065] As shown in FIG5 , the initial reference clock signal CLK ref After being modulated by the random jitter signal PN (e.g. +1 or -1), the modulated reference clock signal V can be obtained. d The modulated reference clock signal V d The input buffer 11 and the input signal to be processed Vin Sum and get the sum signal V in,ADC and the sum signal V in,ADC Injected into the input of the time-interleaved analog-to-digital converter 2.

[0066] The input buffer 11 can be a differential mode buffer having a positive (p) terminal and a negative (n) terminal. A selector can be provided, whose output terminals are connected to the positive (p) terminal and the negative (n) terminal of the input buffer 11, respectively. If the random jitter signal PN is +1, the modulated reference clock signal V d =V d,p , is injected into the positive (p) terminal of the input buffer 11 through the selector; if the random jitter signal PN is -1, the modulated reference clock signal V d =V d,n , is injected into the negative (n) terminal of the input buffer 11 through the selector. Then, the input buffer 11 can d (For example, including V d,p or V from the negative terminal d,n ) and the signal to be processed V in The sum signal V in,ADC , injected into the input terminal of analog-to-digital converter 2. Analog-to-digital converter 2 receives the sum signal V in,ADC , channel 1 and channel 2 of analog-to-digital converter 2 can take turns to add the signal V in,ADC Sampling and quantization are performed to output the original output signal D of each channel raw To the corresponding time deviation extraction module 12, the time deviation extraction module 12 can be based on the original output signal D of each channel of the analog-to-digital converter 2 raw and random jitter signal PN, determine the time deviation △t used to calibrate the sampling clock of analog-to-digital converter 2, and the original output signal D raw The calibration result D out .

[0067] In a possible implementation, the time deviation extraction module 12 includes a reference clock signal prediction circuit 121, a time deviation extraction circuit 122, and an output calibration circuit 123. The output end of the reference clock signal prediction circuit 121 is connected to the input end of the time deviation extraction circuit 122 and the input end of the output calibration circuit 123 respectively; the reference clock signal prediction circuit 121 is used to calculate the time deviation according to the original output signal D of each channel of the analog-to-digital converter 2. raw The random jitter signal PN is used to extract the reference clock prediction signal. For example, as shown in FIG5 , the reference clock prediction signal D is extracted by the reference clock signal prediction circuit 121 corresponding to channel 2. d,2 , the reference clock prediction signal D extracted by the reference clock signal prediction circuit 121 corresponding to channel 1d,1 , the last digit of the subscript represents the number of channels; the time deviation extraction circuit 122 is used to determine the time deviation Δt according to the reference clock prediction signal, and the time deviation Δt includes a positive deviation or a negative deviation; the output calibration circuit 123 is used to calibrate the original output signal D according to the reference clock prediction signal, the random jitter signal PN, and the original output signal D raw , determine the original output signal D raw The calibration result D out For example, as shown in FIG5 , the output calibration circuit 123 corresponding to channel 2 can determine the original output signal D of channel 2. raw,2 The calibration result D out,2 , where the last digit of the subscript represents the number of channels.

[0068] The following describes the reference clock signal prediction circuit 121, the time deviation extraction circuit 122, and the output calibration circuit 123 in the time deviation extraction module 12. It should be understood that since the working principle of the time deviation extraction module 12 corresponding to each channel is the same, the following description will take the time deviation extraction module 12 corresponding to channel 2 as an example. For ease of description, the last digit of each signal subscript can be added with a number indicating the corresponding channel number. For example, the original output signal D output by channel 1 can be raw Denoted as D raw,1 , the original output signal D of channel 2 raw Denoted as D raw,2 .

[0069] In a possible implementation, the reference clock signal prediction circuit 121 includes a first multiplier and a low-pass filter LPF, wherein the first multiplier is connected to the low-pass filter LPF; the first multiplier is used to convert the original output signal D of the channel 2 of the analog-to-digital converter 2 into raw,2 Multiplying the random jitter signal PN to obtain a first product result D raw,2 ×PN; the low-pass filter LPF is used to raw,2 ×PN is low-pass filtered to obtain the reference clock prediction signal D d,2 Similarly, the reference clock signal prediction circuit 121 connected to channel 1 of the analog-to-digital converter 2 can obtain the reference clock prediction signal D d,1 .

[0070] Among them, the low-pass filter LPF is the first product result D raw,2 ×PN performs an averaging operation to extract the positive and negative time deviations, which requires a lot of sampling samples. For example, you can choose 10 7 The reference clock signal V after the analog-to-digital converter 2 is modulated by the input buffer 11 for a period ofd Inject the original output signal D output by the analog-to-digital converter 2 raw,2 Multiply the random jitter signal PN, and then 7 The reference clock prediction signal D is obtained by averaging the samples. d,2 . Among them, 10 of a single channel 7 The sampling of the cycle is equivalent to 10 for the analog-to-digital converter 2 as a whole. 7 It should be understood that the embodiment of the present disclosure is only based on 10 7 As an example, it is related to the injected signal to be processed V in Amplitude, modulated reference clock signal V d The embodiment of the present disclosure does not limit this.

[0071] The reference clock signal prediction circuit 121 can be used to predict the original output signal D of the analog-to-digital converter 2 channel 2. raw,2 Accurately separate the reference clock prediction signal D d,2 It should be understood that each channel of the analog-to-digital converter 2 is a signal to be processed V in and the modulated reference clock signal V d The sum signal V in,ADC Sampling and quantization are performed, and the reference clock predicts the signal D d,2 It is equivalent to separately modulating the reference clock signal V d The quantized signal obtained by inputting channel 2 of the analog-to-digital converter 2 is actually the reference clock signal V after the modulation is not input separately to the analog-to-digital converter 2. d The step of obtaining the quantized signal actually performs the processing of the signal V in and the modulated reference clock signal V d The sum signal V in,ADC The original output signal D is then output by channel 2 of the analog-to-digital converter 2. raw,2 Multiply it with the random jitter signal PN, and then use the low-pass filter LPF to take the average, and the signal to be processed V in The quantized signal and the modulated reference clock signal V d The quantized signal of the two is separated to obtain the reference clock prediction signal D d,2 , the reference clock prediction signal D d,2 Can represent the modulated reference clock signal V d quantized signal.

[0072] In a possible implementation, the time deviation extraction circuit 122 includes a first subtractor and a comparator, wherein the first subtractor is connected to the comparator; taking the time deviation extraction circuit 122 corresponding to channel 2 as an example, the first subtractor is used to extract the reference clock prediction signal D d,2 Compared with the preset reference value D d,ref (For example, the reference clock prediction signal D of channel 1 d,1 ) to obtain a difference; the comparator is used to compare the difference with a preset threshold (for example, 0), and use the comparison result as the time deviation △t2 of channel 2, wherein the comparator compares the difference with 0 to determine whether the difference is greater than 0. The comparator can also be replaced by a module with a function of taking the sign of the difference (for example, the sgn function).

[0073] The time deviation extraction circuit 122 essentially extracts the reference clock prediction signal D from channel 2. d,2 , and the preset reference value D d,ref Compare the predicted signal D with the reference clock d,2 With reference value D d,ref The predicted reference clock signal V d,2 and the reference value V before quantization d,ref (D d,ref is the quantized V d,ref ), thereby obtaining whether the time deviation △t2 is a positive deviation or a negative deviation, that is, whether the current channel of the analog-to-digital converter 2 lags behind or leads the ideal sampling time.

[0074] Among them, the reference value D d,ref It can be a preset value, or it can be taken as a reference clock prediction signal extracted from a fixed channel, such as the reference clock prediction signal D of channel 1. d,1 , the embodiments of the present disclosure are not limited to this. It should be understood that if the reference value D d,ref is the reference clock prediction signal extracted from a fixed channel, then the reference value D d,ref It can change dynamically. For example, when the environment changes (voltage, temperature, etc.), the reference clock prediction signal D extracted by the channel d will change, then other channels will also use this changed reference value D d,ref Perform calibration.

[0075] In one possible implementation, the time deviation calibration device 1 also includes an adjustable delay line, which receives the time deviation extracted by the time deviation extraction module and performs background calibration of the time deviation of the multi-channel analog-to-digital converter 2; wherein, when the time deviation Δt extracted by the time deviation extraction module 12 of the current channel is a positive deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter 2 to be ahead of a preset number of steps; or, when the time deviation Δt extracted by the time deviation extraction module 12 of the current channel is a negative deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter 2 to be behind a preset number of steps.

[0076] In the example, the time deviation extraction circuit 122 in the time deviation extraction module 12 obtains the positive or negative value of the time deviation Δt, and can adjust the sampling clock of the current channel through the adjustable delay line to lag 1 step or advance 1 step. Similarly, the time deviation extraction circuit 122 can continuously extract the time deviation Δt, and continue to adjust the sampling clock of each channel according to the positive or negative value of each time deviation Δt. Because the time deviation calibration device 1 of the embodiment of the present disclosure is a background calibration, as the analog-to-digital converter 2 works, the calibration is carried out at all times, the extraction of the time deviation Δt is carried out continuously, and the updating of the sampling clock of each channel is also carried out continuously. Among them, the time deviation calibration device 1 completes the calibration of the analog-to-digital converter 2, that is, each channel of the analog-to-digital converter 2 will continuously lag 1 step, then advance 1 step, and then lag 1 step, always relative to a moment +1 -1 +1 -1 step.

[0077] In a possible implementation, the output calibration circuit 123 includes a second multiplier and a second subtractor, wherein the second multiplier is connected to the second subtractor; taking the output calibration circuit 123 corresponding to channel 2 as an example, the second multiplier is used to convert the reference clock prediction signal D d,2 Multiplying the random jitter signal PN to obtain a second product result D d ,2×PN; The second subtractor is used to subtract the original output signal D of channel 2 raw,2 and the second product result D d,2 ×PN is used to make the difference and get the original output signal D of channel 2 raw,2 The calibration result D out,2 =D raw,2 -D d,2 ×PN, the calibration result D out,2 The original output signal D from channel 2 raw,2 The restored actual input signal to be processed V in quantified results.

[0078] The lower part of FIG5 shows the reference clock prediction signal D extracted by the reference clock signal prediction module 12 of channel 1. d,1 As a reference value D d,ref The waveform of D d,2 CLK represents the reference clock prediction signal extracted by the reference clock signal prediction module 12 of channel 2; ref Represents the initial reference clock signal, PN represents the random jitter signal, V d,p / n 5 represents the modulated reference clock signal, wherein the subscript p / n is used to indicate that after being modulated by the random jitter signal PN, it is injected into the positive (p) terminal or the negative (n) terminal of the input buffer 11 according to the polarity of the random jitter signal PN. Part 52 in FIG5 represents the waveform of the modulated reference clock signal injected into the positive terminal, and part 51 in FIG5 represents the waveform of the modulated reference clock signal injected into the negative terminal; V d,2 Represents the modulated reference clock signal V injected into channel 2 of the analog-to-digital converter 2 d,p / n In fact, the embodiment of the present disclosure does not perform the modulation of the reference clock signal V d,p / n The reference clock prediction signal D extracted by the reference clock signal prediction module 12 is separately injected into the analog-to-digital converter 2 for sampling and quantization. d,2 Can be seen as V d,2 quantized signal. CLK1 represents the sampling clock of channel 1 of analog-to-digital converter 2, CLK2 represents the sampling clock of channel 2 of analog-to-digital converter 2, Δt2 represents the time deviation extracted by the time deviation extraction module 12 corresponding to channel 2, and the time deviation Δt2 is a positive deviation.

[0079] From the waveform, we can see that the time deviation of channel 2 relative to channel 1 is △t2, which causes channel 2 to be less sensitive to the initial reference clock signal CLK ref The sampling signal (V d,2 ) relative to channel 1 (V d,1 ) has an error, so channel 2 has an error in the reference clock signal CLK ref The quantization result (reference clock prediction signal D d,2 ) relative to channel 1 (reference clock prediction signal D d,1 ) has an error. The quantization result of channel 1 (reference clock prediction signal D d,1 ) as a reference value D d,ref , perform time deviation calibration on other channels, that is, take D d,ref =D d,1 .

[0080] In one possible implementation, in order to save hardware resources and reduce hardware complexity and power consumption, when there is an input buffer structure at the input end of the multi-channel analog-to-digital converter 2, the time deviation calibration device 1 can reuse the input buffer structure of the analog-to-digital converter 2 and directly use it as the input buffer 11; optionally, if the analog-to-digital converter 2 does not have a buffer, or the performance of the existing buffer in the analog-to-digital converter 2 (such as bandwidth, noise performance, etc.) cannot meet the requirements of the time deviation calibration device 1, a new input buffer 11 can also be designed according to the specific application scenario, and the embodiments of the present disclosure are not limited to this.

[0081] FIG6 shows a schematic diagram of an input buffer circuit according to an embodiment of the present disclosure. As shown in FIG6 , the input buffer 11 includes a first push-pull circuit 111 and a second push-pull circuit 112 having the same circuit structure, and a first bootstrap circuit 113 and a second bootstrap circuit 114 having the same circuit structure. The first push-pull circuit 111 is used to follow the signal to be processed V in The second push-pull circuit 112 is used to follow the reference clock signal V modulated by the random jitter signal PN. d The output end of the first push-pull circuit 111 and the output end of the second push-pull circuit 112 are connected to the input end of the analog-to-digital converter 2, the first bootstrap circuit 113 is connected to the first push-pull circuit 111, and the second bootstrap circuit 114 is connected to the second push-pull circuit 112.

[0082] As shown in FIG6 , the first push-pull circuit 111 may include a first transistor M 1n , the second transistor M 1p , a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. Among them, the first transistor M 1n It can be an NMOS transistor, the second transistor M 1p The second push-pull circuit 112 may include a third transistor M 1n,d , the fourth transistor M 1p,d , a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4. Among them, the third transistor M 1n,d It can be an NMOS transistor, the fourth transistor M 1p,d It may be a PMOS transistor.

[0083] The first bootstrap circuit 113 may include a fifth transistor M 2n , the sixth transistor M 2p , a fifth resistor R5, a sixth resistor R6, a fifth capacitor C5, and a sixth capacitor C6. Among them, the fifth transistor M 2n With the first transistor M 1nThe same, is an NMOS transistor, the sixth transistor M 2p With the second transistor M 1p The second bootstrap circuit 114 may include a seventh transistor M 2n,d , the eighth transistor M 2p,d , a seventh resistor R7, an eighth resistor R8, a seventh capacitor C7, and an eighth capacitor C8. Among them, the seventh transistor M 2n,d With the third transistor M 1n,d The eighth transistor M is the same as that of the NMOS transistor. 2p,d With the fourth transistor M 1p,d The same as that of the MOSFET, which is a PMOS transistor.

[0084] In the first push-pull circuit 111 and the first bootstrap circuit 113, the fifth transistor M 2n The drain of the fifth transistor M is connected to the power supply. 2n The source of the first transistor M is connected 1n The drain of the first transistor M 1n The source of the second transistor M is connected 1p The source of the first push-pull circuit 111 is used as the output terminal of the second transistor M 1p The drain of the sixth transistor M is connected to 2p Source, sixth transistor M 2p The drain of the fifth transistor M is connected to the ground; 2n The gate of the fifth transistor M is connected to the first end of the fifth resistor R5 and the first end of the fifth capacitor C5; the second end of the fifth capacitor C5 is connected to the first transistor M 1n The gate of the second transistor M is connected to the first end of the first resistor R1 and the first end of the first capacitor C1; 1p The gate of the sixth transistor M is connected to the first end of the second resistor R2, the first end of the second capacitor C2, and the first end of the sixth capacitor C6; 2p The gate of the first push-pull circuit 111 is connected to the second end of the sixth capacitor C6 and the first end of the sixth resistor R6; the second end of the first capacitor C1 is connected to the second end of the second capacitor C2, serving as the input end of the first push-pull circuit 111 for receiving the input signal to be processed V in .

[0085] In the second push-pull circuit 112 and the second bootstrap circuit 114, the seventh transistor M 2n,d The drain of the seventh transistor M is connected to the power supply. 2n,d The source of the third transistor M is connected 1n,d The drain of the third transistor M 1n,d The source of the fourth transistor M is connected 1p,d The source of the fourth transistor M is used as the output terminal of the second push-pull circuit 112. 1p,dThe drain of the eighth transistor M is connected to 2p,d Source, eighth transistor M 2p,d The drain of the seventh transistor M is connected to the ground; 2n,d The gate of the seventh transistor is connected to the first end of the seventh resistor R7 and the first end of the seventh capacitor C7; the second end of the seventh capacitor C7 is connected to the third transistor M 1n,d The gate of the fourth transistor M is connected to the first end of the third resistor R3 and the first end of the third capacitor C3; 1p,d The gate of the eighth transistor M is connected to the first end of the fourth resistor R4, the first end of the fourth capacitor C4, and the first end of the eighth capacitor C8; 2p,d The gate of the third capacitor C3 is connected to the second end of the eighth capacitor C8 and the first end of the eighth resistor R8; the second end of the third capacitor C3 is connected to the second end of the fourth capacitor C4, serving as the input end of the second push-pull circuit 112, for receiving the input reference clock signal V modulated by the random jitter signal PN. d .

[0086] The second end of the first resistor R1 in the first push-pull circuit 111 and the second end of the third resistor R3 in the second push-pull circuit 112 are connected to a first point for receiving a bias voltage V BN1 The second end of the second resistor R2 in the first push-pull circuit 111 and the second end of the fourth resistor R4 in the second push-pull circuit 112 are connected to a second point for receiving the bias voltage V BP1 The second end of the fifth resistor R5 in the first bootstrap circuit 113 and the second end of the seventh resistor R7 in the second bootstrap circuit 114 are connected to a third point for receiving a bias voltage V of an external bias circuit. BN2 The second end of the sixth resistor R6 in the first bootstrap circuit 113 and the second end of the eighth resistor R8 in the second bootstrap circuit 114 are connected to a fourth point for receiving the bias voltage V BP2 The output terminal of the first push-pull circuit 111 is connected to the output terminal of the second push-pull circuit 112, for the first push-pull circuit 111 to follow the signal to be processed V in , and the modulated reference clock signal V followed by the second push-pull circuit 112 d Combine and get the sum signal V in,ADC =V in +V d and the sum signal V in,ADC The first bootstrap circuit 113 is used to improve the first push-pull circuit 111 to follow the signal to be processed V in The second bootstrap circuit 114 is used to improve the accuracy of the second push-pull circuit 112 following the modulated reference clock signal V d accuracy.

[0087] FIG7 is a schematic diagram showing the advantages of the input buffer of the embodiment of the present disclosure. As shown in FIG7 , the input buffer 11 is used to follow the input signal to be processed V in The input buffer 11 is used to follow the modulated reference clock signal V d The output terminals of the two parts are connected as the output terminals of the input buffer 11, and the sum signal V is injected into the analog-to-digital converter 2. in,ADC , the sum signal V in,ADC The modulated reference clock signal V d and the signal to be processed V in Converged.

[0088] Since the reference clock signal V d The physical size of the transistor in the circuit is larger than that used to follow the signal to be processed V in The physical size of the transistor in the circuit is much smaller, that is, the third transistor M 1n,d , the fourth transistor M 1p,d , the seventh transistor M 2n,d , the eighth transistor M 2p,d The size of the first transistor M 1n , the second transistor M 1p , the fifth transistor M 2n , the sixth transistor M 2p The size is much smaller. For example, as shown in Figure 7, it is used to follow the modulated reference clock signal V d The physical size of the transistor in the circuit can be used to follow the signal to be processed V in 1 / 24 of the physical size of the transistor in the circuit, correspondingly, used to follow the modulated reference clock signal V d Current I in the circuit d , is used to follow the signal to be processed V in 1 / 24 of the current in the circuit, therefore, is used to follow the modulated reference clock signal V d The additional noise and power consumption added by the circuit is used to follow the signal to be processed V in The circuit is 1 / 24, and its impact on noise and linearity is negligible. The 24 in Figure 7 is only an example and is used to follow the modulated reference clock signal V d The physical size of the transistor in the circuit is related to the size of the transistor used to follow the signal to be processed V inThe physical size ratio of the transistors in the circuit is sufficient to follow the modulated reference clock signal V d When the additional noise and power consumption added by the circuit and the deterioration of linearity are negligible and the convergence speed of the time deviation calibration meets the actual application requirements, it can be set according to the implemented application scenario, and the present disclosure does not impose any restrictions on this.

[0089] It should be understood that the reference clock signal V d The physical size of the transistor in the circuit is related to the size of the transistor used to follow the signal to be processed V in The physical size ratio of the transistors in the circuit determines the injected reference clock signal V d With the signal to be processed V in Since the ratio affects the convergence speed of the time offset calibration, the number of cycles M for calibrating the sampling clock of a certain channel every M cycles can be determined based on the ratio.

[0090] In addition, considering the input network (such as package bonding wire inductance, etc.) shown in FIG7 , since the signal is difficult to pass through the first transistor M 1n and the second transistor M 1p The output source is passed to the input gate, and the modulated reference clock signal V d The kickback interference (Kickback) of the injection to the input network can be 1n and the second transistor M 1p Isolation helps improve the accuracy of the analog-to-digital converter.

[0091] In one possible implementation, in certain applications with lower precision, in order to reduce hardware overhead or avoid using a high power supply voltage, the bootstrap function portion (e.g., the first bootstrap circuit 113 and the second bootstrap circuit 114 in FIG. 6 ) may be omitted from the input buffer 11, as a variant of the input buffer 11. FIG. 8 shows a schematic diagram of another input buffer according to an embodiment of the present disclosure. As shown in FIG. 8 , the first push-pull circuit 111 may include a first transistor M 1n , the second transistor M 1p , a first resistor R1, a second resistor R2, a first capacitor C1, and a second capacitor C2. Among them, the first transistor M 1n It can be an NMOS transistor, the second transistor M 1p It may be a PMOS transistor.

[0092] The second push-pull circuit 112 may include a third transistor M 1n,d , the fourth transistor M 1p,d , a third resistor R3, a fourth resistor R4, a third capacitor C3, and a fourth capacitor C4. Among them, the third transistor M 1n,dIt can be an NMOS transistor, the fourth transistor M 1p,d It may be a PMOS transistor.

[0093] In the first push-pull circuit 111, the first transistor M 1n The source of the second transistor M is connected 1p The source of the first push-pull circuit 111 is used as the output terminal of the first transistor M 1n The drain of the first transistor M is connected to the power supply. 1n The gate of the second transistor M is connected to the first end of the first resistor R1 and the first end of the first capacitor C1. 1p The drain of the second transistor M is connected to the ground. 1p The gate of the first push-pull circuit 111 is connected to the first end of the second resistor R2 and the first end of the second capacitor C2, and the second end of the first capacitor C1 is connected to the second end of the second capacitor C2, serving as the input end of the first push-pull circuit 111 for receiving the input signal to be processed V in .

[0094] In the second push-pull circuit 112, the third transistor M 1n,d The source of the fourth transistor M is connected 1p,d The source of the third transistor M is used as the output terminal of the second push-pull circuit 112. 1n,d The drain of the third transistor M is connected to the power supply. 1n,d The gate of the fourth transistor M is connected to the first end of the third resistor R3 and the first end of the third capacitor C3. 1p,d The drain of the fourth transistor M is connected to the ground. 1p,d The gate of the first terminal of the fourth resistor R4 and the first terminal of the fourth capacitor C4 are connected, and the second terminal of the third capacitor C3 is connected to the second terminal of the fourth capacitor C4, serving as the input terminal of the second push-pull circuit 112, for receiving the input reference clock signal V modulated by the random jitter signal PN. d .

[0095] The second end of the first resistor R1 in the first push-pull circuit 111 and the second end of the third resistor R3 in the second push-pull circuit 112 are connected to a first point for receiving a bias voltage V BN1 The second end of the second resistor R2 in the first push-pull circuit 111 and the second end of the fourth resistor R4 in the second push-pull circuit 112 are connected to a second point for receiving the bias voltage V BP1 The output terminal of the first push-pull circuit 111 is connected to the output terminal of the second push-pull circuit 112, for the first push-pull circuit 111 to follow the signal to be processed V in , and the modulated reference clock signal V followed by the second push-pull circuit 112 d Combine and get the sum signal Vin,ADC =V in +V d and the sum signal V in,ADC Injected into the input of the time-interleaved analog-to-digital converter 2.

[0096] FIG9 is a schematic diagram of another time deviation calibration device according to an embodiment of the present disclosure. As shown in FIG9 , the analog-to-digital converter 2 has four channels (e.g., channels 1 to 4). Channels 1 to 4 can sample and quantize the signal input to the analog-to-digital converter 2 in turn according to a preset sequence (e.g., the sequence of 1234, or the sequence of 1324). To match the analog-to-digital converter 2 having four channels, the time deviation calibration device 1 may include an input buffer 11 and four time deviation extraction modules 12. The input buffer 11 is connected to the input end of the analog-to-digital converter 2, and each channel of the analog-to-digital converter 2 can be connected to a corresponding time deviation extraction module 12.

[0097] In Figure 9, V inp With V inn Is the signal to be processed V in The input buffer 11 is injected through the differential structure end. In Figures 4 to 8, the input buffer 11 is a single-ended structure, which means that the signal to be processed V in The initial reference clock signal CLK ref After being modulated by the random jitter signal PN generated by the random jitter signal generator, the modulated reference clock signal V can be obtained. d If the random jitter signal PN is +1, the modulated reference clock signal V d =V d,p , can be injected into the positive (p) terminal of the input buffer 11; if the random jitter signal PN is -1, the modulated reference clock signal V d =V d,n , can be injected into the negative (n) terminal of the input buffer 11. Then, the input buffer 11 can modulate the reference clock signal V d (For example, including V d,p or V from the negative terminal d,n ) and the signal to be processed V in The sum signal V in,ADC , injected into the input of analog-to-digital converter 2.

[0098] The analog-to-digital converter 2 receives the sum signal V in,ADC , channels 1 to 4 of the analog-to-digital converter 2 can take turns to add the signal V in,ADC Sampling and quantization are performed to output the original output signal D of each channel raw,1～4 To the corresponding time deviation extraction module 12, each time deviation extraction module 12 can be based on the original output signal D of the corresponding channelraw,1～4 and random jitter signal PN, determine the sampling clock CLK for calibrating each channel of analog-to-digital converter 2 1～4 Time deviation △t 1～4 , and the original output signal D raw,1～4 The calibration result D out .

[0099] For example, channel 1 can convert the original output signal D raw,1 The time deviation extraction module 12 is connected to the time deviation extraction module 12, which can extract the original output signal D of channel 1 according to the original output signal D of channel 1. raw,1 and random jitter signal PN, determine the time deviation △t1 used to calibrate the sampling clock CLK1 of channel 1, and the original output signal D raw,1 The calibration result D out,1 ;

[0100] Channel 2 can convert the original output signal D raw,2 The time deviation extraction module 12 is connected to the time deviation extraction module 12, which can extract the original output signal D of channel 2 according to the original output signal D of channel 2. raw,2 and random jitter signal PN, determine the time deviation △t2 used to calibrate the sampling clock CLK2 of channel 2, and the original output signal D raw,2 The calibration result D out,2 ;

[0101] Channel 3 can convert the original output signal D raw,3 The time deviation extraction module 12 is connected to the time deviation extraction module 12, which can extract the original output signal D of channel 3 according to the original output signal D of channel 3. raw,3 and random jitter signal PN, determine the time deviation △t3 used to calibrate the sampling clock CLK3 of channel 3, and the original output signal D raw,3 The calibration result D out,3 ;

[0102] Channel 4 can convert the original output signal D raw,4 The time deviation extraction module 12 is connected to the time deviation extraction module 12, which can extract the original output signal D of channel 4 according to the original output signal D of channel 4. raw,4 and random jitter signal PN, determine the time deviation △t4 used to calibrate the sampling clock CLK4 of channel 4, and the original output signal D raw,4 The calibration result D out,4 .

[0103] Optionally, the time deviation calibration device 1 may further include a multiplexer for calibrating the calibration results D of each time deviation extraction module 12. out,1～4 Perform 4 selection 1, select the output result of the current working time deviation extraction module 12 as the calibration result D outIn this way, the multiplexer can select the output of the time deviation extraction module 12 corresponding to the four channels in turn to form the calibration result D of the output signal of the analog-to-digital converter 2. out .

[0104] Among them, CLK in It is the master clock of the time-interleaved analog-to-digital converter 2. After the clock divider and the adjustable delay line, the sampling clock CLK of each channel is obtained. k , k represents the number of channels. For example, a 4GS / s sampling rate, 4-channel time-interleaved analog-to-digital converter 2, the clock divider will generate 4-phase 1GHz sampling clocks CLK1 to CLK4, and the adjustable delay line can be adjusted according to the time deviation △t of each channel. 1～4 Adjust the sampling clocks CLK1 to CLK4 of each channel.

[0105] It can be seen that the time deviation calibration device 1 of the embodiment of the present disclosure does not depend on the properties of the input signal for extracting time deviation information, and can work under any input signal. Moreover, the time deviation calibration device 1 realizes background calibration and does not need to interrupt the normal working state of the analog-to-digital converter 2 during operation; furthermore, the time deviation calibration device 1 has high precision, is not restricted by the routing and component mismatch between channels, has no residual time deviation after calibration, and is also compatible with the input buffer structure of the analog-to-digital converter 2. There is no need to add additional analog circuit modules, only digital circuit modules that perform related operations need to be added. The hardware complexity and power consumption cost are small, and the advantages are obvious under advanced technology.

[0106] At the application level, the time deviation calibration device 1 of the disclosed embodiment can be applied to various time-interleaved analog-to-digital converter products for time deviation calibration, including high-speed, medium-high precision (e.g., sampling rate <5GS / s, quantization accuracy of 10-14 bits), ultra-high-speed, low-precision (e.g., sampling rate >5GS / s, quantization accuracy of 6-10 bits), and other analog-to-digital converter products. Since time deviation calibration is a component module of time-interleaved analog-to-digital converter products, compared to related technologies where these products have limited input signals and low time deviation calibration accuracy, the time deviation calibration device 1 of the disclosed embodiment can simultaneously operate under any input signal, perform background calibration, and have high calibration accuracy (no residual time deviation after calibration), thus expanding the application scenarios.

[0107] It can be understood that the above-mentioned embodiments mentioned in the present disclosure can be combined with each other to form combined embodiments without violating the principle logic. Due to space limitations, the present disclosure will not elaborate on them.

[0108] FIG10 is a flowchart of a time deviation calibration method according to an embodiment of the present disclosure. As shown in FIG10 , the time deviation calibration device is used to calibrate a multi-channel analog-to-digital converter. The time deviation calibration device includes an input buffer and a time deviation extraction module. The input buffer is connected to the input end of the analog-to-digital converter, and the time deviation extraction module is connected to the output end of the analog-to-digital converter. The time deviation calibration method includes:

[0109] In step S11, the input buffer injects the sum of the reference clock signal modulated by the random jitter signal and the signal to be processed into the analog-to-digital converter, so that multiple channels of the analog-to-digital converter sample and quantize the sum in turn according to a preset order, and output the original output signal of each channel;

[0110] In step S12, the time deviation extraction module outputs a time deviation for calibrating the analog-to-digital converter clock signal and a calibration result of the original output signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal.

[0111] In one possible implementation, the input buffer includes a first push-pull circuit and a second push-pull circuit having the same circuit structure, the first push-pull circuit is used to follow the signal to be processed, and the second push-pull circuit is used to follow the reference clock signal modulated by a random jitter signal, and the output end of the first push-pull circuit and the output end of the second push-pull circuit are connected to the input end of the analog-to-digital converter.

[0112] In a possible implementation, the input buffer further includes a first bootstrap circuit and a second bootstrap circuit having the same circuit structure, the first bootstrap circuit is connected to the first push-pull circuit, and the second bootstrap circuit is connected to the second push-pull circuit.

[0113] In one possible implementation, the time deviation extraction module includes a reference clock signal prediction circuit, a time deviation extraction circuit, and an output calibration circuit, and the output end of the reference clock signal prediction circuit is respectively connected to the input end of the time deviation extraction circuit and the input end of the output calibration circuit. Step S12 may include: the reference clock signal prediction circuit extracts a reference clock prediction signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal; the time deviation extraction circuit determines the time deviation based on the reference clock prediction signal, and the time deviation includes a positive deviation or a negative deviation; the output calibration circuit determines the calibration result of the original output signal based on the reference clock prediction signal, the random jitter signal, and the original output signal.

[0114] In one possible implementation, the reference clock signal prediction circuit includes a first multiplier and a low-pass filter, the first multiplier is connected to the low-pass filter, and the reference clock signal prediction circuit extracts the reference clock prediction signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal, including: the first multiplier multiplies the original output signal of each channel of the analog-to-digital converter with the random jitter signal to obtain a first product result; the low-pass filter performs low-pass filtering on the first product result to obtain the reference clock prediction signal.

[0115] In one possible implementation, the time deviation extraction circuit includes a first subtractor and a comparator, the first subtractor is connected to the comparator, and the time deviation extraction circuit determines the time deviation based on the reference clock prediction signal, including: the first subtractor subtracts the reference clock prediction signal from a preset reference value to obtain a difference; the comparator compares the difference with a preset threshold and uses the comparison result as the time deviation.

[0116] In one possible implementation, the output calibration circuit includes a second multiplier and a second subtractor, the second multiplier is connected to the second subtractor, and the output calibration circuit determines the calibration result of the original output signal based on the reference clock prediction signal, the random jitter signal, and the original output signal, including: the second multiplier multiplies the reference clock prediction signal by the random jitter signal to obtain a second product result; the second subtractor performs a difference between the original output signal and the second product result to obtain the calibration result of the original output signal.

[0117] In one possible implementation, the time deviation calibration device also includes an adjustable delay line, and the method also includes: the adjustable delay line receives the time deviation extracted by the time deviation extraction module, and performs background calibration of the time deviation on the multi-channel analog-to-digital converter; wherein, when the time deviation extracted by the time deviation extraction module of the current channel is a positive deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be ahead of a preset number of steps; or, when the time deviation extracted by the time deviation extraction module of the current channel is a negative deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be behind a preset number of steps.

[0118] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0119] The embodiment of the present disclosure further provides a chip, which includes the time deviation calibration device as described above.

[0120] The present disclosure also provides an electronic device including the aforementioned time offset calibration apparatus. The electronic device may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, or the like, without limitation in the present disclosure.

[0121] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A time deviation calibration device, characterized in that: The time deviation calibration device is used to calibrate a multi-channel analog-to-digital converter, and the time deviation calibration device includes an input buffer and a time deviation extraction module, the input buffer is connected to the input end of the analog-to-digital converter, and the time deviation extraction module is connected to the output end of the analog-to-digital converter; The input buffer is used to inject a sum signal of the reference clock signal modulated by the random jitter signal and the signal to be processed into the analog-to-digital converter, so that multiple channels of the analog-to-digital converter sample and quantize the sum signal in turn according to a preset order and output an original output signal of each channel; The time deviation extraction module is used to determine the time deviation for calibrating the sampling clock of the analog-to-digital converter and the calibration result of the original output signal according to the original output signal of each channel of the analog-to-digital converter and the random jitter signal.

2. The time deviation calibration device according to claim 1, characterized in that: The input buffer includes a first push-pull circuit and a second push-pull circuit with the same circuit structure. The first push-pull circuit is used to follow the signal to be processed, and the second push-pull circuit is used to follow the reference clock signal modulated by a random jitter signal. The output end of the first push-pull circuit and the output end of the second push-pull circuit are connected to the input end of the analog-to-digital converter.

3. The time deviation calibration device according to claim 2, characterized in that: The input buffer further includes a first bootstrap circuit and a second bootstrap circuit having the same circuit structure, the first bootstrap circuit is connected to the first push-pull circuit, and the second bootstrap circuit is connected to the second push-pull circuit.

4. The time deviation calibration device according to claim 1, characterized in that: The time deviation extraction module includes a reference clock signal prediction circuit, a time deviation extraction circuit, and an output calibration circuit. The output end of the reference clock signal prediction circuit is connected to the input end of the time deviation extraction circuit and the input end of the output calibration circuit respectively. The reference clock signal prediction circuit is used to extract a reference clock prediction signal based on the original output signal of each channel of the analog-to-digital converter and the random jitter signal; The time deviation extraction circuit is used to determine the time deviation according to the reference clock prediction signal, and the time deviation includes a positive deviation or a negative deviation; The output calibration circuit is used to determine a calibration result of the original output signal according to the reference clock prediction signal, the random jitter signal, and the original output signal.

5. The time deviation calibration device according to claim 4, characterized in that: The reference clock signal prediction circuit includes a first multiplier and a low-pass filter, wherein the first multiplier is connected to the low-pass filter; The first multiplier is used to multiply the original output signal of each channel of the analog-to-digital converter by the random jitter signal to obtain a first product result; The low-pass filter is used to perform low-pass filtering on the first product result to obtain a reference clock prediction signal.

6. The time deviation calibration device according to claim 4, characterized in that: The time deviation extraction circuit includes a first subtractor and a comparator, wherein the first subtractor is connected to the comparator; the first subtractor is used to perform a subtraction between the reference clock prediction signal and a preset reference value to obtain a difference; the comparator is used to compare the difference with a preset threshold value and use the comparison result as the time deviation; The output calibration circuit includes a second multiplier and a second subtractor, the second multiplier is connected to the second subtractor; the second multiplier is used to multiply the reference clock prediction signal by the random jitter signal to obtain a second product result; the second subtractor is used to perform a difference between the original output signal and the second product result to obtain a calibration result of the original output signal.

7. The time deviation calibration device according to claim 1, characterized in that: The time deviation calibration device further includes an adjustable delay line, which receives the time deviation extracted by the time deviation extraction module and performs background calibration of the time deviation on the multi-channel analog-to-digital converter; Wherein, when the time deviation extracted by the time deviation extraction module of the current channel is a positive deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to be ahead by a preset number of steps; Alternatively, when the time deviation extracted by the time deviation extraction module of the current channel is a negative deviation, the adjustable delay line adjusts the sampling clock of the current channel of the multi-channel analog-to-digital converter to lag behind by a preset number of steps.

8. A time deviation calibration method, characterized in that: The time deviation calibration method is applied to a time deviation calibration device, which is used to calibrate a multi-channel analog-to-digital converter. The time deviation calibration device includes an input buffer and a time deviation extraction module, wherein the input buffer is connected to the input end of the analog-to-digital converter, and the time deviation extraction module is connected to the output end of the analog-to-digital converter. The time deviation calibration method includes: The input buffer injects a sum signal of the reference clock signal modulated by the random jitter signal and the signal to be processed into the analog-to-digital converter, so that multiple channels of the analog-to-digital converter sample and quantize the sum signal in turn according to a preset sequence, and output an original output signal of each channel; The time deviation extraction module outputs a time deviation for calibrating the sampling clock of the analog-to-digital converter and a calibration result of the original output signal according to the original output signal of each channel of the analog-to-digital converter and the random jitter signal.

9. A chip, characterized in that: The chip includes the time deviation calibration device according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The electronic device comprises the time deviation calibration device according to any one of claims 1 to 7.

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