Semiconductor device, power amplifier, electronic device, and preparation method for semiconductor device

Abstract

The present application relates to a semiconductor device, a power amplifier, an electronic device, and a preparation method for a semiconductor device. The semiconductor device comprises a base, an epitaxial layer, source electrodes, gate electrodes and drain electrodes, wherein the base and the epitaxial layer are arranged in a stacked manner in a third direction; the source electrodes, the gate electrodes and the drain electrodes are arranged on the side of the epitaxial layer facing away from the base; and the source electrodes, the gate electrodes and the drain electrodes are alternately distributed in a first direction. The semiconductor device further comprises source bumps for being welded to a substrate; the semiconductor device comprises an active region; at least part of the projection of each source bump in the third direction is located within the range of the active region; and the distance between each source bump and a heat source of the active region is relatively short, and when heat is dissipated from the active region of the semiconductor device by means of the source bumps, the thermal resistance of the active region is relatively low, and the heat dissipation efficiency is relatively high, so that the temperature of the semiconductor device during a working process is reduced, and the performance of the semiconductor device is ensured. In addition, when heat is dissipated by means of the source bumps, it is unnecessary to additionally provide a heat dissipation structure for the semiconductor device, so that the structure of the semiconductor device is simplified.

Description

Semiconductor device, power amplifier, electronic device and method for manufacturing semiconductor device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 8, 2024, with application number 202410177007.4 and invention name “Semiconductor device, power amplifier, electronic device and method for preparing semiconductor device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a power amplifier, an electronic device, and a method for manufacturing a semiconductor device. Background Art

[0003] Gallium nitride semiconductor materials have excellent application prospects in high-temperature, high-frequency, and high-power scenarios due to their advantages such as wide bandgap, high breakdown field strength, high thermal conductivity, and high electron saturation velocity. Gallium nitride high electron mobility transistors (GaN HEMTs) feature high breakdown field strength, high saturation drift rate, low leakage current, and high surface density, making them widely used as transistors in integrated circuits of electronic devices. These transistors generate heat during operation, and excessively high temperatures can reduce the transistor's output current and power, degrading semiconductor device performance and potentially leading to transistor failure.

[0004] Application Contents

[0005] The present application provides a semiconductor device, a power amplifier, an electronic device, and a method for manufacturing a semiconductor device, which are used to improve the heat dissipation performance of the semiconductor device.

[0006] A first aspect of an embodiment of the present application provides a semiconductor device, comprising a substrate, an epitaxial layer, a source electrode, a gate electrode, and a drain electrode, wherein the substrate and the epitaxial layer are stacked along a third direction, the source electrode, the gate electrode, and the drain electrode are arranged on a side of the epitaxial layer away from the substrate, and the source electrode, the gate electrode, and the drain electrode are alternately distributed along a first direction; the semiconductor device also comprises a source bump for welding to a substrate, the semiconductor device comprises an active area, and at least a portion of a projection of the source bump along the third direction is located within the range of the active area.

[0007] In this embodiment, the projection of the source bump is located within the projection of the active area. The distance between the source bump and the heat source in the active area is relatively short. When the active area of ​​the semiconductor device dissipates heat through the source bump, its thermal resistance is low and the heat dissipation efficiency is high. This reduces the operating temperature of the semiconductor device and ensures its performance. Furthermore, when heat is dissipated through the source bump, there is no need to provide a separate heat dissipation structure for the semiconductor device, simplifying the structure of the semiconductor device.

[0008] In a specific embodiment, the source bump is electrically connected to the source electrode of the active region. During semiconductor device packaging, the source bump is used to solder to a substrate electrode of a substrate, electrically connecting the substrate electrode and the source electrode of the semiconductor device via the source bump, enabling signal transmission between the two. In summary, the source bump serves as both an electrical signal transmission path and a heat dissipation path for the semiconductor device.

[0009] In a specific embodiment, the semiconductor device further includes a connecting bridge and a raising layer, the source electrode of the active area is electrically connected through the connecting bridge, the raising layer is located on the side of the connecting bridge away from the substrate, and the height of the raising layer along the third direction is greater than the height of the connecting bridge along the third direction, the raising layer is provided with a first through hole, and the source bump is electrically connected to the source electrode through the first through hole.

[0010] Since the source bump is above the connecting bridge, the source bump with a rectangular structure or a runway-shaped structure is heavy. In order to prevent the source bump from collapsing the connecting bridge below it, a raising layer is set at the position where the connecting bridge is located. The raising layer is located on the side of the gate fork and the drain fork facing the source bump, and the dimension of the raising layer along the third direction Z is larger than the dimension of the connecting bridge along the third direction, that is, the position where the connecting bridge is located is raised.

[0011] In one specific embodiment, the source bump includes a first portion and a second portion. The first portion is used for soldering to the substrate and is located on the side of the raised layer facing away from the substrate. The second portion fills the first through-hole, and the first portion is electrically connected to the source electrode via the second portion. In this embodiment, the source electrode and the source bump transmit electrical signals through the second portion, and heat from the source electrode can be transferred to the first portion via the second portion. Because the second portion is connected to the source electrode in the active area and the first portion, the distance between the first portion and the source electrode in the active area is reduced, thereby reducing the heat dissipation path and improving heat dissipation efficiency.

[0012] In a specific embodiment, the melting point of the material of the second part is higher than the melting point of the material of the first part. The higher melting point of the second part enables the thickness of the second part to be higher when it is filled in the first through hole, so that the thickness of the second part is greater than or equal to the thickness of the padding layer. When the semiconductor device is flipped on the substrate and the source bump is welded to the substrate electrode, the melting point of the first part is lower, which facilitates welding, and the second part is not easy to melt, so that the source bump and the source electrode remain electrically connected through the second part, thereby improving the reliability of the semiconductor device. After the source bump is welded to the substrate electrode, the second part that is not easy to melt can also create a certain gap between the semiconductor device and the substrate (that is, the semiconductor device is supported by the unmelted second part), which facilitates the injection of packaging filler into the gap for packaging.

[0013] In a specific embodiment, the ratio of the melting point of the material of the second portion to the melting point of the material of the first portion is 1.5-2.5.

[0014] In a specific embodiment, the semiconductor device further comprises a source bridge pier, which is disposed on a side of the source electrode facing the elevated layer and is electrically connected to or integrally formed with the connecting bridge. The connecting bridge is electrically connected to the source interdigital fingers via the source bridge pier. The source bridge pier is located between the elevated layer and the source interdigital fingers, and the second portion of the source bump is electrically connected to the source bridge pier, thereby electrically connecting the first portion of the source bump to the source interdigital fingers via the second portion and the source bridge pier. The material of the source interdigital fingers and the source bridge pier can be the same, so that the interface resistance between the two is low.

[0015] In a specific embodiment, the projection of the first through hole in the plane where the first direction and the second direction are located is a polygon, and its internal angle is greater than or equal to 90°, thereby reducing stress concentration on the inner wall of the first through hole and preventing the formation of an overly small first through hole, which results in an overly small contact area between the source bump and the source electrode.

[0016] In a specific embodiment, the size of the first through hole along the first direction is c, and the size of the first through hole along the second direction is d, c<d, so that the second part filled in the first through hole will not occupy too much space of the source fingers, gate fingers and drain fingers, thereby ensuring the performance of the semiconductor device.

[0017] In a specific embodiment, the dimension w of the connecting bridge along the first direction satisfies: c+6≤w, thereby facilitating the formation of the connecting bridge.

[0018] In a specific embodiment, the minimum distance between the side wall of the first through hole along the first direction and the edge of the source electrode along the first direction is e, e≥0.5um, so that the first through hole will not be too close to the edge, thereby improving the reliability of the first through hole, and the first through hole will not be too close to the connecting bridge, thereby preventing the projection of the first through hole along the third direction from falling on the connecting bridge, causing the second part of the source bump to fall on the connecting bridge, thereby preventing the source bump from damaging the connecting bridge.

[0019] In a specific embodiment, a projection of the second portion along the third direction is located in the active area, or a projection of the second portion along the third direction is located outside the active area.

[0020] In a specific embodiment, the source bump includes a plurality of second parts, each of which is located between adjacent connecting bridges, thereby increasing the connection area between the first part of the source bump and the source electrode, and improving heat dissipation efficiency and signal conduction efficiency.

[0021] In a specific embodiment, the semiconductor device further includes a connection layer and an insulating layer. The insulating layer is disposed on a side of the spacer layer facing the source bump, and the connection layer is located between the spacer layer and the insulating layer. The insulating layer is provided with a second through-hole extending along a third direction. The source bump includes a first portion and a second portion. The second portion is located within the second through-hole. The first through-hole has a connecting portion therein. The first portion is electrically connected to the source electrode via the second portion, the connection layer, and the connecting portion. The second portion of the source bump is indirectly electrically connected to the source bridge pier of the source electrode, i.e., the second portion is electrically connected to the source bridge pier via the connection layer and the connecting portion.

[0022] In a specific embodiment, the overlap rate between the projection of the first through hole along the third direction and the projection of the second through hole along the third direction is 0-10%, thereby reducing the risk of stress failure caused by excessive overlap between the projections of the first through hole and the second through hole. For example, during a temperature shock reliability test, due to rapid switching between high and low temperatures, stratification occurs at the interface between the first through hole material and the second through hole material.

[0023] In a specific embodiment, along the first direction, the connecting bridge spans the gate electrode and the drain electrode between the adjacent source electrodes, and there is an isolation space between the connecting bridge and the gate electrode and the drain electrode, or an isolation medium is filled between the connecting bridge and the gate electrode and the drain electrode, and the dielectric constant of the isolation medium is less than 3.9. When the dielectric constant of the medium between the source fingers and the gate fingers is small, the parasitic capacitance between the source fingers and the gate fingers can be effectively reduced; when the dielectric constant of the medium between the gate fingers and the drain fingers is small, the parasitic capacitance between the gate fingers and the drain fingers can be effectively reduced, thereby reducing the impact on the output impedance of the semiconductor device and reducing the risk of degradation of the RF characteristics of the semiconductor device. Among them, the medium between the source fingers and the gate fingers, and between the gate fingers and the drain fingers can be air or the above-mentioned isolation medium.

[0024] In a specific embodiment, the projection of the source bump along the third direction is rectangular or racetrack-shaped. The source bump has a larger cross-sectional area and a larger heat dissipation area, thereby further improving the heat dissipation efficiency of the semiconductor device, reducing the temperature of the semiconductor device during operation, and ensuring that its performance is not degraded due to excessive temperature.

[0025] In a specific embodiment, the semiconductor device further includes a gate bump and a drain bump, the gate bump is electrically connected to the gate electrode, and the drain bump is electrically connected to the drain electrode; the projected area of ​​the gate bump along the third direction is smaller than the projected area of ​​the source bump along the third direction, and the projected area of ​​the drain bump along the third direction is smaller than the projected area of ​​the source bump along the third direction.

[0026] In a specific embodiment, the length of the projection of the source bump along the third direction is a, the width of the projection of the source bump along the third direction is b, and 1≤a / b≤6. When 1≤a / b≤6, the coplanarity of the source bumps is not excessively large, thereby reducing soldering defects and consistency issues caused by excessive coplanarity of the source bumps when the semiconductor device is flip-chip mounted on a substrate, and reducing the risk of poor probe contact during online screening testing of the semiconductor device.

[0027] In a specific embodiment, the projection of the source bump along the third direction at least covers the active area along the first direction, so that the distance between each position of the active area and the source bump is small, so that the heat at each position of the active area can be quickly dissipated, thereby improving the heat dissipation efficiency.

[0028] In a specific embodiment, the source electrode includes source fingers, the gate electrode includes gate fingers, and the drain electrode includes drain fingers, the gate fingers and the drain fingers both extend toward the source electrode, and the source fingers, the gate fingers, and the drain fingers are spaced apart along a first direction; wherein, along the first direction, the spacing between adjacent gate fingers and drain fingers is less than or equal to 3um, and the spacing between adjacent gate fingers and source fingers is less than or equal to 2um.

[0029] A second aspect of an embodiment of the present application provides a power amplifier, which includes a substrate and a semiconductor device soldered to the substrate, wherein the semiconductor device is the semiconductor device described above.

[0030] A third aspect of an embodiment of the present application provides an electronic device, which includes the semiconductor device and / or power amplifier described above.

[0031] A fourth aspect of the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0032] preparing a substrate and an epitaxial layer, and preparing a source electrode, a gate electrode, and a drain electrode on the epitaxial layer;

[0033] preparing a connecting bridge in the active area so that adjacent source electrodes are electrically connected via the connecting bridge;

[0034] preparing a padding layer on a side of the connecting bridge facing away from the epitaxial layer, and opening a first through hole in the padding layer;

[0035] A source bump is prepared on the padding layer, and the source bump is electrically connected to the source electrode through the first through hole.

[0036] In this embodiment, the projection of the source bump of the semiconductor device prepared through the above steps is located within the projection range of the active area. The distance between the source bump and the heat source of the active area is small. When the active area of ​​the semiconductor device dissipates heat through the source bump, its thermal resistance is small and the heat dissipation efficiency is high, thereby reducing the temperature of the semiconductor device during operation and ensuring its performance. In addition, when heat is dissipated through the source bump, there is no need to provide a separate heat dissipation structure for the semiconductor device, simplifying the structure of the semiconductor device. When the semiconductor device is packaged, the source bump is also used to weld to the substrate electrode of the substrate, so that the substrate electrode and the source electrode of the semiconductor device are electrically connected through the source bump, so that the two can transmit signals. Therefore, the source bump serves as an electrical signal transmission path for the semiconductor device and also as a heat dissipation path for the semiconductor device.

[0037] In a specific embodiment, when preparing the connecting bridge, the preparation method specifically includes:

[0038] preparing a support portion between adjacent source electrodes in the active region, wherein the support portion is made of an insulating material;

[0039] preparing a conductive seed layer on the support portion, and making the seed layer at least cover the support portion;

[0040] forming a connection bridge covering the seed layer and a source bridge pier covering the source electrode by electroplating;

[0041] The support portion is removed.

[0042] In the above steps, the support portion facilitates forming the bridge surface structure of the connecting bridge, thereby forming an isolation space between the connecting bridge and the gate electrode and the drain electrode, and the seed layer facilitates electroplating operations to form the connecting bridge and the source bridge pier.

[0043] In a specific embodiment, when electroplating forms a connecting bridge covering the seed layer and a source bridge pier covering the source electrode, the electroplating material is the same as the material of the source electrode, so that the materials of the connecting bridge, the source bridge pier and the source fork fingers are the same, reducing the interface resistance.

[0044] In a specific embodiment, before forming the support portion, an isolation dielectric is deposited between adjacent source electrodes and gate electrodes, and between adjacent gate electrodes and drain electrodes. The isolation dielectric electrically insulates the connecting bridge from the gate and drain fingers, and when the dielectric constant of the dielectric between the source and gate fingers is low, the parasitic capacitance between the source and gate fingers can be effectively reduced. When the dielectric constant of the dielectric between the gate and drain fingers is low, the parasitic capacitance between the gate and drain fingers can be effectively reduced, thereby reducing the impact on the output impedance of the semiconductor device and reducing the risk of degradation of the semiconductor device's radio frequency characteristics.

[0045] In a specific embodiment, the isolation medium is an organic substance with a dielectric constant less than 3.9.

[0046] In a specific embodiment, the isolation medium is benzocyclobutene or epoxy resin.

[0047] In a specific embodiment, when a first through hole is provided on the raising layer, the projection of the first through hole in the plane where the first direction and the second direction are located is a polygon, and its internal angle is greater than or equal to 90°, thereby reducing stress concentration on the inner wall of the first through hole and preventing the formation of an excessively small first through hole, which results in an excessively small contact area between the source bump and the source electrode.

[0048] In a specific embodiment, when a first through hole is provided on the pad layer, a dimension c of the first through hole along the first direction is smaller than a dimension d of the first through hole along the second direction, so that the first material filled in the first through hole does not occupy too much space of the source fingers, gate fingers and drain fingers, thereby ensuring the performance of the semiconductor device.

[0049] In a specific embodiment, when the first through hole is set on the raising layer, the minimum distance e between the side wall of the first through hole along the first direction and the edge of the source electrode along the first direction is ≥ 0.5um, so that the first through hole is not too close to the edge, thereby improving the reliability of the first through hole, and the first through hole is not too close to the connecting bridge, thereby preventing the projection of the first through hole along the third direction from falling on the connecting bridge, causing the second part of the source bump to fall on the connecting bridge, thereby preventing the source bump from damaging the connecting bridge.

[0050] In a specific embodiment, when preparing the connecting bridge, the dimension w of the connecting bridge along the first direction satisfies: c+6≤w.

[0051] In a specific embodiment, when preparing the raising layer, the height of the raising layer is made higher than the height of the connecting bridge, so that the source bump is raised by the raising layer, reducing the risk of the source bump collapsing the connecting bridge.

[0052] In a specific embodiment, when preparing a source bump on the padding layer, the method for preparing the semiconductor device includes:

[0053] Filling the first through hole with a metal of a first material to form a second portion;

[0054] Disposing a metal of a second material on a side of the elevated layer away from the connecting bridge to form a first portion;

[0055] The melting point of the first material is higher than the melting point of the second material.

[0056] The higher melting point of the first material enables it to have a higher thickness when filled in the first through-hole, so that the thickness of the second portion formed by the first material is greater than or equal to the thickness of the spacer layer. When the semiconductor device is flip-chip mounted on the substrate and the source bump is welded to the substrate electrode, the lower melting point of the second material forming the first portion facilitates welding, and the second portion is less likely to melt, allowing the source bump and the source electrode to maintain electrical connection through the second portion, thereby improving the reliability of the semiconductor device. Moreover, after the source bump is welded to the substrate electrode, the less likely to melt second portion can also create a certain gap between the semiconductor device and the substrate (i.e., the semiconductor device is supported by the unmelted second portion), facilitating the injection of encapsulation filler into the gap for encapsulation.

[0057] In a specific embodiment, the ratio of the melting point of the first material to the melting point of the second material satisfies 1.5-2.5.

[0058] In a specific embodiment, when a second metal material is disposed on a side of the elevated layer facing away from the connecting bridge to form the first portion, the length a of the projection of the first portion along the third direction and the width b of the projection along the third direction satisfy the following relationship: 1≤a / b≤6. When 1≤a / b≤6, excessive coplanarity of the source bumps is minimized, thereby reducing soldering defects and consistency issues caused by excessive coplanarity of the source bumps when the semiconductor device is flip-chip mounted on a substrate. Furthermore, the risk of poor probe contact during online screening testing of the semiconductor device is reduced.

[0059] It should be understood that the foregoing general description and the following detailed description are merely illustrative and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] FIG1 shows a schematic diagram of an electronic device in a specific embodiment;

[0061] FIG2 is a schematic diagram showing the working principle of the power amplifier of the electronic device in FIG1 ;

[0062] FIG3 is a schematic diagram of a stacked structure of a semiconductor device provided in an embodiment of the present application;

[0063] FIG4 is a top view of a semiconductor device provided in the present application in a specific embodiment;

[0064] FIG5 is a cross-sectional view taken along the line AA of FIG4 ;

[0065] FIG6 is a partial schematic diagram of the active unit in FIG4 ;

[0066] FIG7 is a schematic diagram of a semiconductor device and a substrate being soldered via bumps;

[0067] FIG8 is a schematic diagram of a semiconductor device after packaging;

[0068] FIG9 is a schematic diagram of the semiconductor device in FIG7 from another perspective;

[0069] FIG10 is a top view of a semiconductor device provided in the present application in a specific embodiment;

[0070] FIG11 is a cross-sectional view taken along line BB of FIG10 in a part of a specific embodiment;

[0071] FIG12 is a cross-sectional view taken along line BB of FIG10 in another embodiment;

[0072] FIG13 is a partial top view of a semiconductor device in another specific embodiment;

[0073] FIG14 is a cross-sectional view taken along line CC of FIG13 ;

[0074] FIG15 is a cross-sectional view taken along line BB of FIG10 in a portion of another embodiment;

[0075] FIG16 is a top view of a semiconductor device provided in another specific embodiment of the present application;

[0076] FIG17 is a partial view of a top view of a semiconductor device in another specific embodiment provided by the present application;

[0077] FIG18 is a schematic diagram of the structure of FIG17 without the source bump;

[0078] FIG19 is a schematic structural diagram of FIG18 with the raised layer removed;

[0079] FIG20 is a flow chart of a method for manufacturing a semiconductor device in a specific embodiment;

[0080] FIG21 a is a schematic diagram of the source electrode, gate electrode and drain electrode obtained in step S1;

[0081] Figure 21b is a cross-sectional view of Figure 21a;

[0082] FIG22 a is a schematic structural diagram of FIG21 a after a support portion is provided in the active area;

[0083] FIG22b is a cross-sectional view taken along line DD of FIG22a;

[0084] FIG23 is a schematic diagram of preparing a seed layer at a first preset position;

[0085] FIG24 a is a schematic diagram of forming a connecting bridge by electroplating in FIG23 ;

[0086] FIG24b is a cross-sectional view taken along the EE line of FIG24a.

[0087] FIG25 a is a schematic diagram of preparing a source bump on FIG24 a;

[0088] FIG25 b is a cross-sectional view taken along line FF of FIG25 a ;

[0089] FIG26a is a schematic diagram of preparing a source bump in FIG25a;

[0090] FIG26 b is a cross-sectional view taken along line GG of FIG26 a ;

[0091] FIG27 is a schematic diagram of application fields of the semiconductor device in this application.

[0092] Reference numerals:

[0093] 100-Semiconductor devices;

[0094] 10-substrate;

[0095] 20-epitaxial layer;

[0096] 201-nuclear layer;

[0097] 202- buffer layer;

[0098] 203-channel layer;

[0099] 204-barrier layer;

[0100] 205-capping layer;

[0101] 30-source electrode;

[0102] 301-Source finger;

[0103] 302-Connecting Bridge;

[0104] 303-source bump;

[0105] 303a-Part I;

[0106] 303b-Part II;

[0107] 304-source bridge pier;

[0108] 305-connecting part;

[0109] 306-insulating medium;

[0110] 40-gate electrode;

[0111] 40a-grid finger strip;

[0112] 40b-gate bump;

[0113] 50-drain electrode;

[0114] 50a_Leaking finger strip;

[0115] 50b-drain bump;

[0116] 60-active area;

[0117] 60a-active unit;

[0118] 70-isolation layer;

[0119] 80-Raised floor;

[0120] 801-first through hole;

[0121] 802-insulation layer;

[0122] 90-connection layer;

[0123] 200-substrate;

[0124] 200a-substrate electrode;

[0125] 300-encapsulation filler;

[0126] 400-support part;

[0127] 500-seed layer.

[0128] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application. DETAILED DESCRIPTION

[0129] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0130] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0131] It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present application are described based on the angles shown in the accompanying drawings and should not be understood as limiting the embodiments of the present application. In addition, in the context, it should be understood that when it is mentioned that an element is connected to another element "on" or "under", it can not only be directly connected to the other element "on" or "under", but also be indirectly connected to the other element "on" or "under" through an intermediate element.

[0132] The embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, tablet, mobile phone, satellite phone, watch, glasses, headphones, router, lidar driver, detector, radar, or other terminal products. The electronic device may also be a device such as a power amplifier for the above-mentioned electronic devices. The embodiments of the present application do not impose any particular restrictions on the specific form of the above-mentioned electronic devices.

[0133] For example, Figure 1 shows a schematic diagram of an electronic device in a specific embodiment. The electronic device may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a camera 193, a display 194, and a subscriber identification module (SIM) card interface 195.

[0134] It is understood that the structures illustrated in the embodiments of the present invention do not constitute specific limitations on the electronic device. In other embodiments of the present application, the electronic device may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0135] The processor 110 may include one or more processing units. For example, the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0136] The controller can generate operation control signals according to the instruction operation code and timing signal to complete the control of instruction fetching and execution.

[0137] Processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in processor 110 is a cache memory. This memory can store instructions or data that have just been used or are being recycled by processor 110. If processor 110 needs to use the same instruction or data again, it can directly access the memory. This avoids duplicate accesses, reduces processor 110 latency, and thus improves system efficiency.

[0138] In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface.

[0139] The I2C interface is a bidirectional synchronous serial bus that includes a serial data line (SDA) and a serial clock line (SCL). In some embodiments, the processor 110 may include multiple I2C busses. The processor 110 may be coupled to the touch sensor 180K, the charger, the flash, the camera 193, and the like via different I2C bus interfaces. For example, the processor 110 may be coupled to the touch sensor 180K via the I2C interface, enabling communication between the processor 110 and the touch sensor 180K via the I2C bus interface, thereby implementing the touch function of the electronic device.

[0140] The I2S interface can be used for audio communication. In some embodiments, the processor 110 can include multiple I2S buses. The processor 110 can be coupled to the audio module 170 via the I2S bus to enable communication between the processor 110 and the audio module 170. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the I2S interface, enabling the function of answering calls through a Bluetooth headset.

[0141] The PCM interface can also be used for audio communication, sampling, quantizing, and encoding analog signals. In some embodiments, the audio module 170 and the wireless communication module 160 can be coupled via a PCM bus interface. In some embodiments, the audio module 170 can also transmit audio signals to the wireless communication module 160 via the PCM interface, enabling the function of answering calls via a Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.

[0142] The UART interface is a universal serial data bus used for asynchronous communication. This bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication. In some embodiments, the UART interface is typically used to connect the processor 110 and the wireless communication module 160. For example, the processor 110 communicates with the Bluetooth module in the wireless communication module 160 via the UART interface to implement Bluetooth functionality. In some embodiments, the audio module 170 can transmit audio signals to the wireless communication module 160 via the UART interface, enabling the function of playing music through Bluetooth headphones.

[0143] The MIPI interface can be used to connect the processor 110 to peripheral devices such as the display 194 and the camera 193. MIPI interfaces include the camera serial interface (CSI) and the display serial interface (DSI). In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the electronic device's camera function. The processor 110 and the display 194 communicate via the DSI interface to implement the electronic device's display function.

[0144] The GPIO interface can be configured via software. The GPIO interface can be configured as either a control signal or a data signal. In some embodiments, the GPIO interface can be used to connect the processor 110 to the camera 193, display 194, wireless communication module 160, audio module 170, sensor module 180, etc. The GPIO interface can also be configured as an I2C interface, an I2S interface, a UART interface, a MIPI interface, etc.

[0145] USB port 130 is an interface that complies with USB standards and may be a Mini USB port, a Micro USB port, a USB Type-C port, or the like. USB port 130 can be used to connect a charger to charge an electronic device, transfer data between the electronic device and peripherals, connect headphones to play audio, and connect other electronic devices, such as augmented reality devices.

[0146] It is understood that the interface connection relationship between the modules illustrated in the embodiments of the present invention is only a schematic illustration and does not constitute a structural limitation of the electronic device. In other embodiments of the present application, the electronic device may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0147] The charging management module 140 is configured to receive charging input from a charger. The charger can be either a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 can receive charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 can receive wireless charging input via the electronic device's wireless charging coil. While charging the battery 142, the charging management module 140 can also power the electronic device through the power management module 141.

[0148] The power management module 141 is used to connect the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140, and provides power to the processor 110, the internal memory 121, the display 194, the camera 193, and the wireless communication module 160. The power management module 141 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage, impedance). In some other embodiments, the power management module 141 can also be set in the processor 110. In other embodiments, the power management module 141 and the charging management module 140 can also be set in the same device.

[0149] The wireless communication function of the electronic device can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor.

[0150] Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in an electronic device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In other embodiments, the antennas can be used in conjunction with a tuning switch.

[0151] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G applied in electronic devices. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0152] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.) or displays an image or video through the display screen 194. In some embodiments, the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be set in the same device as the mobile communication module 150 or other functional modules.

[0153] The wireless communication module 160 can provide wireless communication solutions for electronic devices, including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. The wireless communication module 160 can be one or more devices that integrate at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0154] In some embodiments, the antenna 1 of the electronic device is coupled to the mobile communication module 150, and the antenna 2 is coupled to the wireless communication module 160, so that the electronic device can communicate with the network and other devices through wireless communication technology. The wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS) and / or satellite based augmentation system (SBAS).

[0155] The electronic device implements display functionality through a GPU, display screen 194, and an application processor. A GPU is a microprocessor for image processing that connects display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. Processor 110 may include one or more GPUs that execute program instructions to generate or modify display information.

[0156] Display screen 194 is used to display images, videos, and the like. Display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, the electronic device can include one or N display screens 194, where N is a positive integer greater than one.

[0157] The electronic device can realize the shooting function through the ISP, camera 193, video codec, GPU, display 194 and application processor.

[0158] The ISP processes data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and converted into a visible image. The ISP can also perform algorithmic optimization on image noise, brightness, and skin tone. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 193.

[0159] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, and then passes the electrical signal to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0160] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when an electronic device selects a frequency, the DSP performs a Fourier transform on the frequency energy.

[0161] Video codecs are used to compress or decompress digital video. Electronic devices may support one or more video codecs. This allows them to play or record videos in a variety of encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, and MPEG4.

[0162] The NPU is a neural network (NN) computing processor. Drawing on the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it rapidly processes input information and can continuously self-learn. The NPU enables intelligent cognitive applications in electronic devices, such as image recognition, face recognition, speech recognition, and text comprehension.

[0163] The external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device. The external memory card communicates with the processor 110 via the external memory interface 120 to implement data storage functions. For example, files such as music and videos can be stored on the external memory card.

[0164] The internal memory 121 can be used to store computer executable program codes, which include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory 121 and / or instructions stored in a memory provided in the processor.

[0165] The electronic device can implement audio functions such as music playback and recording through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor.

[0166] The audio module 170 is used to convert digital audio information into analog audio signal output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be provided in the processor 110, or some functional modules of the audio module 170 can be provided in the processor 110.

[0167] The SIM card interface 195 is used to connect a SIM card. The SIM card can be connected to and separated from the electronic device by inserting it into or removing it from the SIM card interface 195. The electronic device can support 1 or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, and the like. Multiple cards can be inserted into the same SIM card interface 195 at the same time. The types of the multiple cards can be the same or different. The SIM card interface 195 can also be compatible with different types of SIM cards. The SIM card interface 195 can also be compatible with external memory cards. Electronic devices interact with the network through SIM cards to implement functions such as calls and data communications. In some embodiments, the electronic device uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device and cannot be separated from the electronic device.

[0168] The present invention also provides a power amplifier circuit that can be used in a power amplifier of the mobile communication module 150 or the wireless communication module 160 in the electronic device shown in Figure 1. It is understood that any of the above electronic devices that require a power amplifier circuit in a power amplifier to amplify a signal fall within the application scenarios of the present invention.

[0169] For example, FIG2 shows a schematic diagram of the working principle of the power amplifier of the electronic device in FIG1. ​​The RF signal generated by the RF chip is input into the power amplifier. The power amplifier includes a shell and a high-power semiconductor device located in the shell. The RF signal is amplified by the power amplifier and sent to the antenna end to complete the RF signal transmission of the transmission path. According to the supported frequency band of the power amplifier, a switch can be added to the transmission path to support the amplification requirements of RF signals in different frequency bands. The RF signal received by the antenna end is input into the RF chip through modules such as filters and low-noise amplifiers to complete the RF signal transmission of the receiving path.

[0170] Among them, the high-power semiconductor device in the power amplifier can be a gallium nitride high electron mobility transistor (GaN HEMT) device. Due to the advantages of gallium nitride semiconductor materials such as a wide bandgap, high breakdown field strength, high thermal conductivity, and electron saturation velocity, it has very good application prospects in high temperature, high frequency, and high power scenarios. GaN-based high electron mobility transistor (HEMT) devices have the characteristics of high breakdown field strength, high saturation drift rate, low leakage current, and high surface density, and are widely used as transistors in integrated circuits of electronic devices. The following description takes the semiconductor device provided in the embodiment of the present application as a HEMT device as an example.

[0171] FIG3 is a schematic diagram of a stacked structure of a semiconductor device provided in an embodiment of the present application. Referring to FIG3 , the semiconductor device includes a substrate 10, an epitaxial layer 20, a source electrode 30, a gate electrode 40, and a drain electrode 50. The material of the substrate 10 can be Si, SiC, Al2O3, or GaN. The epitaxial layer 20 is disposed on the substrate 10. The source electrode 30, the drain electrode 40, and the gate electrode 50 are disposed on a side of the epitaxial layer 20 facing away from the substrate 10. The materials of the source electrode 30, the drain electrode 50, and the gate electrode 40 can include Ti, Al, Ni, TiN, TaN, or Au.

[0172] The epitaxial layer 20 may include a core layer 201, a buffer layer 202, a channel layer 203, and a barrier layer 204 stacked in sequence on the substrate 10, and the source electrode 30, the drain electrode 50, and the gate electrode 40 are disposed on the barrier layer 204. In another specific embodiment, the epitaxial layer 20 may include a core layer 201, a buffer layer 202, a channel layer 203, a barrier layer 204, and a cap layer 205 (the layers are not shown in the figure) stacked in sequence on the substrate 10, and the source electrode 30, the drain electrode 50, and the gate electrode 40 are disposed on the cap layer 205, which protects the barrier layer 204.

[0173] A two-dimensional electron gas (2DEG) is formed between the barrier layer 204 and the channel layer 203 under the action of polarization. The source electrode 30 and the drain electrode 50 can cause the two-dimensional electron gas to flow in the channel layer 203 between the source electrode 30 and the drain electrode 50 under the electric field effect, and the source electrode 30 and the drain electrode 50 are connected at the two-dimensional electron gas in the channel layer 203. The gate electrode 40 can extend between the source electrode 30 and the drain electrode 50 to apply an electrical signal to control the concentration of the two-dimensional electron gas between the source electrode 30 and the drain electrode 50. The 2EDG has a very high electron saturation velocity (2.7×107cm / s) and mobility (approximately 2000cm2 / Vs), making the semiconductor device have very high power and radio frequency application prospects.

[0174] Please refer to Figure 4, which is a top view of the semiconductor device provided in this application in a specific embodiment. The semiconductor device 100 can be a finger-type structure, that is, the source electrode 30 includes a source finger 301, the gate electrode 40 includes a gate finger 40a, and the drain electrode 50 includes a drain finger 50a. The gate finger 40a and the drain finger 50a both extend in the direction of the source electrode 30, and the source finger 301 and the drain finger 50a are cross-distributed, and the gate finger 40a is located between the two. The semiconductor device 100 includes an active area and a passive area, and the area outside the active area is the passive area. Two-dimensional electron gas exists only in the active area, and there is no two-dimensional electron gas in the passive area or the two-dimensional electron gas is destroyed. Specifically, the barrier layer in the passive area can be removed by etching or the like, or the barrier layer in the passive area can be invalidated by injecting impurities into the barrier layer in the passive area, so that the two-dimensional electron gas cannot be formed between the barrier layer and the channel layer in the passive area.

[0175] In the embodiment shown in FIG4 , the semiconductor device 100 may include a plurality of source electrodes 30 , a plurality of drain electrodes 50 , and a plurality of gate electrodes 40 . The combination of at least one source electrode 30 , at least one gate electrode 40 , and at least one drain electrode 50 forms an active unit 60 a . The active region of the semiconductor device 100 may include a plurality of active units 60 a , and the inactive region is located between two adjacent active units 60 a to isolate the two-dimensional electron gas between the two adjacent active units 60 a .

[0176] When the semiconductor device is working, heat is generated, and the heat is mainly concentrated in the above-mentioned active unit. Please refer to Figures 5 and 6, Figure 5 is a cross-sectional view taken along the AA direction of Figure 4, and Figure 6 is a partial schematic diagram of the active unit in Figure 4. The heat generated when the semiconductor device is working is mainly concentrated between the source finger 301 and the drain finger 50a (the position within the dotted line frame in Figure 6), causing the temperature of the semiconductor device 100 to be too high. When the temperature of the semiconductor device is too high, it will cause the carrier energy to increase, making it easier for the carriers to cross the barrier layer and cause the gate electrode leakage current to increase, causing the semiconductor device to fail. It will also cause the two-dimensional electron gas mobility to decrease, reducing the output current and output power of the semiconductor device, and reducing the performance of the semiconductor device. The insulating medium between adjacent source fingers 301 and gate fingers 40a, and between adjacent gate fingers 40a and drain fingers 50a is not shown in Figure 6.

[0177] In order to reduce the temperature of semiconductor devices, a heat dissipation component is usually provided in the semiconductor device, and the heat generated during the operation of the semiconductor is dissipated to the environment through the heat dissipation component.

[0178] The aforementioned semiconductor devices can be combined with auxiliary components such as resistors, capacitors, and inductors to form a power amplifier, which can then be assembled and packaged on a substrate. Flip-chip technology involves placing a chip with its functional area facing downward, facing away from the substrate, and interconnecting it with solder bumps. Because the chip's placement is opposite to the functional area of ​​a traditional packaged chip, it is called a flip-chip. In one specific embodiment, the semiconductor device can be packaged using flip-chip technology.

[0179] Please refer to Figures 7 and 8. Figure 7 is a schematic diagram of a semiconductor device and a substrate being soldered together via bumps, and Figure 8 is a schematic diagram of the semiconductor device after packaging. The substrate 200 includes a substrate electrode 200a. The source electrode of the semiconductor device 100 is soldered to the substrate electrode 200a via source bumps 303, the gate electrode is soldered to the substrate electrode 200a via gate bumps 40b, and the drain electrode is soldered to the substrate electrode 200a via drain bumps 50b. After soldering, the semiconductor device 100 is encapsulated using a packaging filler 300. Alternatively, the semiconductor device 100 can be packaged together with other components such as filters, low-noise amplifiers, and switching devices.

[0180] Please refer to Figure 9, which is a schematic diagram of the semiconductor device in Figure 7 from another perspective. The source electrode 30 is provided with a source bump 303 for welding to the substrate electrode, the gate electrode 40 is provided with a gate bump 40b for welding to the substrate electrode, and the drain electrode 50 is provided with a drain bump 50b for welding to the substrate electrode. The source bump 303, gate bump 40b, and drain bump 50b can serve as a signal transmission path for the semiconductor device 100. At the same time, due to the high thermal conductivity of each bump, the source bump 303 can also serve as a heat dissipation channel for the semiconductor device 100, dissipating heat generated during the operation of the semiconductor device 100, reducing the heat of the semiconductor device 100 and ensuring the performance of the semiconductor device 100. This eliminates the need for a separate heat dissipation structure for the semiconductor device, simplifying the structure of the semiconductor device.

[0181] In the embodiment shown in FIG9 , source bump 303 is located between two adjacent active cells 60a. Heat generated during operation of semiconductor device 100 is primarily concentrated between source fingers 301 and drain fingers 50a of active cell 60a (the heat is concentrated within the dotted box in FIG6 ). The distance between source bump 303 and the heat source is relatively large, resulting in poor heat dissipation from source bump 303. FIG9 does not show the insulating dielectrics between adjacent source fingers 301 and gate fingers 40a, and between adjacent gate fingers 40a and drain fingers 50a.

[0182] The present application improves the heat dissipation effect of the source bump by reducing the distance between the source bump and the heat source of the active unit. The specific implementation method is described in detail below.

[0183] Please refer to Figures 10 and 11. Figure 10 is a top view of a semiconductor device provided in a specific embodiment of the present application, and Figure 11 is a portion of a cross-sectional view taken along the BB axis of Figure 10 in a specific embodiment. From the perspectives shown in Figures 10 and 11, the first direction X, the second direction Y, and the third direction Z are three mutually perpendicular directions. The distribution direction of the source fingers, gate fingers, and drain fingers described above is the first direction X, the stacking direction of the substrate and epitaxial layer is the third direction Z shown in Figure 11, and the second direction Y is a direction perpendicular to both the first direction X and the third direction Z.

[0184] The gate electrode 40 of the semiconductor device 100 is provided with a gate bump 40a, the drain electrode 50 is provided with a drain bump 50a, and the source electrode 30 is provided with a source bump 303. In this embodiment, the cross-sections of the gate bumps 40a and the drain bumps 50a are circular, while the cross-section of the source bump 301 is rectangular or racetrack-shaped. That is, the dimension of the source bump 303 along the first direction X is greater than its dimension along the second direction Y. The dimension of the source bump 303 along the first direction X is greater than the dimension of the gate bump 40a along the first direction X, and the dimension of the source bump 303 along the first direction X is greater than the dimension of the drain bump 50a along the first direction X. The cross-sectional area of ​​the source bump 301 is greater than the cross-sectional area of ​​the gate bump 40a and the drain bump 50a.

[0185] The size of the source bump 303 along the first direction X is the same as the size of the active area 60 (the area shown in the dotted box in Figures 10 and 11) along the first direction X. The size of the source bump 303 along the second direction Y can be the same as the size of the active area 60 along the second direction Y, or the size of the source bump 303 along the second direction Y can be smaller than the size of the active area 60 along the second direction Y. In the embodiment shown in Figure 11, along the third direction Z, the projection of the source bump 303 is located within the projection range of the active area 60, that is, the source bump 303 is located above the active area 60. Therefore, the projection of the source bump 303 along the third direction Z is located within the projection range of the active area 60.

[0186] Comparing Figures 9 and 10 , it can be seen that the projection of source bump 303 in Figure 9 is located outside the projection range of the active area, while the projection of source bump 303 in Figure 10 is located within the projection range of active area 60. Therefore, the distance between source bump 303 and the heat source of active area 60 in Figure 10 is smaller than the distance between source bump 303 and the heat source of active area 60 in Figure 9 . In Figure 10 , when the active area 60 dissipates heat through source bump 303, its thermal resistance is smaller and the heat dissipation efficiency is higher. Furthermore, the cross-sectional area of ​​source bump 301 in the embodiment shown in Figure 10 is larger than the cross-sectional area of ​​source bump 303 in the embodiment shown in Figure 9 , which increases the heat dissipation area of ​​source bump 303 in the embodiment shown in Figure 10 , thereby further improving the heat dissipation efficiency.

[0187] Meanwhile, referring to FIG11 , source bump 303 is electrically connected to source fingers 301. During semiconductor device packaging, source bump 303 is soldered to the substrate electrode of the substrate, electrically connecting the substrate electrode and the source electrode of the semiconductor device through source bump 303, enabling signal transmission between the two. In summary, source bump 303 serves as both an electrical signal transmission path for the semiconductor device and a heat dissipation path for the semiconductor device.

[0188] In the active region 60 of the semiconductor device, adjacent source fingers 301 can be electrically connected via a connecting bridge 302. Along the third direction Z, the connecting bridge 302 is located between the first portion 303a of the source bump 303 and the source fingers 301. The connecting bridge 302 spans the gate fingers 40a and the drain fingers 50a between the adjacent source fingers 301. Along the third direction Z, the connecting bridge 302 is electrically insulated from the gate fingers 40a and the drain fingers 50a. In a specific embodiment, a gap can be provided between the connecting bridge 302 and the gate fingers 40a and the drain fingers 50a. The gap can contain air, thereby electrically insulating the connecting bridge 302 from the gate fingers 40a and the drain fingers 50a. In another specific embodiment, the gaps between the connecting bridge 302 and the gate fingers 40a and drain fingers 50a can be filled with an isolation dielectric (not shown). The isolation dielectric can be an organic material with a dielectric constant less than 3.9, such as benzocyclobutene or epoxy resin. The isolation dielectric electrically insulates the connecting bridge 302 from the gate fingers 40a and drain fingers 50a. Furthermore, the isolation dielectric can support the connecting bridge 302, reducing the risk of deformation and damage to the connecting bridge 302.

[0189] The capacitance formula C = (εS) / d, where ε, S, and d are the dielectric constant, cross-sectional area, and thickness of the dielectric between the source finger 301 and the gate finger 40b, and between the gate finger 40b and the drain finger 50b, respectively. This formula shows that a low dielectric constant of the dielectric between the source finger 301 and the gate finger 40b effectively reduces the parasitic capacitance between the source finger 301 and the gate finger 40b. Similarly, a low dielectric constant of the dielectric between the gate finger 40b and the drain finger 50b effectively reduces the parasitic capacitance between the gate finger 40b and the drain finger 50b, thereby reducing the impact on the output impedance of the semiconductor device and the risk of degradation of the semiconductor device's radio frequency characteristics. The dielectric between the source finger 301 and the gate finger 40b, and between the gate finger 40b and the drain finger 50b, can be air or the aforementioned isolation medium.

[0190] Since the source bump 303 is located above the connecting bridge 302, the source bump 303, which is a rectangular or runway-shaped structure, is heavy. In order to prevent the source bump 303 from collapsing the connecting bridge 302 below it, a raising layer 80 is provided at the location of the connecting bridge 302. The raising layer 80 is located on the side of the gate fork 40a and the drain fork 50b facing the source bump 303, and the dimension of the raising layer 80 along the third direction Z is greater than the dimension of the connecting bridge 302 along the third direction Z, that is, the location of the connecting bridge 302 is raised.

[0191] The source bump 303 includes a first portion 303a and a second portion 303b. Along the third direction Z, the first portion 303a is located on the side of the raised layer 80 facing away from the gate fingers 40a and drain fingers 50a. The bottom surface of the first portion 303a abuts the top surface of the raised layer 80. During semiconductor device packaging, the first portion 303a is used for soldering to the substrate electrode. The raised layer 80 is provided with a first through-hole extending along the third direction Z. At least part of the material of the second portion 303b is located within the first through-hole. The source bump 303 is electrically connected to the source fingers 301 through the second portion 303b.

[0192] The source bump 303 may be comprised of at least two metal materials, and the melting point of the portion near the first through-hole of the raising layer 80 is higher than the melting point of the portion away from the first through-hole of the raising layer 80. The first portion 303a and the second portion 303b may be made of different metal materials. The higher melting point of the second portion 303b enables the thickness of the second portion 303b to be greater when filling the first through-hole, so that the thickness of the second portion 303b is greater than or equal to the thickness of the raising layer 80. When the semiconductor device is flip-chip mounted on a substrate and the source bump 303 is soldered to the substrate electrode, the lower melting point of the first portion 303a facilitates soldering, while the second portion is less likely to melt, allowing the source bump 303 to maintain electrical connection with the source electrode via the second portion 303b, thereby improving the reliability of the semiconductor device. Furthermore, after the source bump 303 is soldered to the substrate electrode, the less likely to melt second portion 303b can create a certain gap between the semiconductor device and the substrate (i.e., the semiconductor device is supported by the unmelted second portion 303b), facilitating the injection of encapsulation filler into the gap for encapsulation.

[0193] Specifically, the ratio of the melting point of the material of the second portion 303b to the melting point of the material of the first portion 303a is 1.5-2.5. For example, the ratio of the melting point of the material of the second portion 303b to the melting point of the material of the first portion 303a can be 1.5, 1.8, 1.9, 2, 2.2, 2.3, 2.5, etc. For example, the material of the first portion 303a can be tin or a metal alloy containing tin.

[0194] Referring to FIG11 , the source bump 303 includes a plurality of spaced-apart second portions 303 b. The raised layer 80 is provided with a plurality of first through-holes. The first portion 303 a is electrically connected to the source fingers 301 via the plurality of second portions 303 b, thereby providing a more reliable electrical connection between the source bump 303 and the source fingers 301. The second portions 303 b are located between adjacent connecting bridges 302.

[0195] 11 , source fingers 301 are covered by an isolation layer 70, and the source fingers 301, gate fingers 40 a, and drain fingers 50 a are isolated from each other by the isolation layer 70. The isolation layer 70 can be a single layer or multiple layers. For example, a layer of SixN1-x material is first deposited, followed by a layer of an organic material, such as benzocyclobutene.

[0196] As shown in FIG11 , along the first direction X, the spacing between adjacent gate fingers 40 a and drain fingers 50 a may be less than or equal to 3 μm, and the spacing between adjacent gate fingers 40 a and source fingers 301 may be less than or equal to 2 μm. For example, the spacing between adjacent gate fingers 40 a and drain fingers 50 a may be 3 μm, 2.5 μm, 2.2 μm, 2 μm, 1.5 μm, 1 μm, etc. The spacing between adjacent gate fingers 40 a and source fingers 301 may be 2 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm, 1.45 μm, 1.3 μm, 1.2 μm, 1 μm, 0.8 μm, etc.

[0197] The solution in the embodiment of the present application can be used in low-power semiconductor devices (the spacing between adjacent gate fingers 40a and drain fingers 50a can be less than or equal to 3 μm, and the spacing between adjacent gate fingers 40a and source fingers 301 can be less than or equal to 2 μm). It can also be used in high-power semiconductor devices. Therefore, the present application does not limit the spacing between adjacent gate fingers 40a and drain fingers 50a, or the spacing between adjacent gate fingers 40a and source fingers 301.

[0198] Please refer to Figure 12, which is a portion of the BB cross-sectional view of Figure 10 in another specific embodiment. The source electrode may also include a source bridge pier 304. The source bridge pier 304 and the connecting bridge 302 are integrally formed. The source bridge pier 304 contacts the source fingers 301, electrically connecting the connecting bridge 302 to the source fingers 301 through the source bridge pier 304. The source bridge pier 304 is located between the raised layer 80 and the source fingers 301. The second portion 303b of the source bump is electrically connected to the source bridge pier, thereby electrically connecting the first portion 303a of the source bump to the source fingers 301 through the second portion 303b and the source bridge pier 304. The material of the source fingers 301 and the source bridge pier 304 can be the same, so that the interface resistance between the two is low.

[0199] In this embodiment, along the first direction X, the source bump includes two second portions 303b, with the gate fingers 40a and the drain fingers 50a located between the two second portions 303b. No second portion 303b is provided between adjacent connecting bridges 302. The size of the second portion 303b along the first direction X in FIG12 is larger than the size of the second portion 303b along the first direction X in FIG11, thereby enhancing the connection reliability between the first portion 303a and the source electrode.

[0200] The other structures of the embodiment shown in FIG. 12 may be the same as those of the embodiment shown in FIG. 11 , and will not be described in detail here.

[0201] Please refer to Figures 13 and 14. Figure 13 is a partial top view of a semiconductor device in another specific embodiment, and Figure 14 is a cross-sectional view taken along the CC line of Figure 13. The active area 60 of this embodiment is the area enclosed by the dotted line in the figure. As can be seen from the figure, the dimension of the source bump 303 along the first direction X in this embodiment is smaller than the dimension of the active area 60 along the first direction X. That is, a portion of the projection of the source bump 303 along the third direction Z is located within the projection of the active area 60, while another portion is located outside the projection of the active area 60.

[0202] In the embodiment shown in Figure 14, the projection of the second part 303b of the source bump 303 along the third direction Z is located outside the projection range of the active area 60, that is, the raising layer 80 within the range of the active area 60 is not provided with the first through hole, and the first through hole is provided in the raising layer 80 outside the range of the active area 60.

[0203] In other embodiments, the raising layer 80 located within the active area 60 may also be provided with a first through hole, that is, the source bump 303 also has a second part within the active area 60. At this time, the source bump 303 and the source electrode are electrically connected in both the active area 60a and the passive area through the second part 303b of the source bump 303.

[0204] The other structures of the embodiments shown in FIG. 13 and FIG. 14 may be the same as those of the embodiment shown in FIG. 12 , and are not described again here.

[0205] Please refer to Figure 15, which is a portion of the BB cross-sectional view of Figure 10 in yet another specific embodiment. In this embodiment, the second portion 303b of the source bump can also be indirectly electrically connected to the source bridge pier 304 of the source electrode, that is, the second portion 303b is electrically connected to the source bridge pier 304 via a connecting layer 90 and a connecting portion 305. The semiconductor device in this embodiment can also include an insulating layer 802, a stepping layer 80 disposed on the side of the source bridge pier 304 and the connecting bridge 302 facing the source bump, and an insulating layer 802 disposed on the side of the stepping layer 80 facing the source bump. The connecting layer 90 is located between the stepping layer 80 and the insulating layer 802.

[0206] The padding layer 80 has a first through-hole extending along the third direction Z, with the connecting portion 305 located within the first through-hole. The insulating layer 802 has a second through-hole extending along the third direction Z, with the second portion 303b of the source bump located within the second through-hole. The overlap between the projection of the first through-hole along the third direction Z and the projection of the second through-hole along the third direction Z is 0-10%, thereby reducing the risk of stress failure caused by excessive overlap between the projections of the first and second through-holes, including delamination at the interface between the filler material in 303b and the filler material in 305 under the impact of rapid high and low temperature switching during temperature shock reliability testing. For example, the overlap between the projection of the first through-hole along the third direction Z and the projection of the second through-hole along the third direction Z can be 0, 1%, 1.6%, 2%, 4%, 5%, 6%, 8%, 9%, 10%, etc.

[0207] In the embodiment shown in Figure 15, the source bump may include multiple second parts 303b, and there is a connecting portion 305 between each adjacent connecting bridge 302, that is, it includes multiple connecting portions 305. Accordingly, multiple connecting layers 90 can be arranged between the raising layer 80 and the insulating layer 802. The multiple connecting layers 90 are spaced apart along the first direction X, and the adjacent two connecting layers 90 are separated by the insulating layer 802. The raising layer 80 and / or the insulating layer 802 are provided with an installation groove, and the connecting layer 90 is located in the installation groove.

[0208] In other embodiments, a connection layer 90 may be provided between the raising layer 80 and the insulating layer 802 , and the connection layer 90 separates the insulating layer 802 and the raising layer 80 along the third direction Z, that is, the connection layer 90 covers the raising layer 80 and the insulating layer 802 along the first direction X.

[0209] The material of the connection layer 90 includes conductive materials such as Au, Cu, Al, and Ti. The material of the insulating layer 802 may include organic substances with a dielectric constant less than 3.9, such as benzocyclobutene, epoxy resin, and the like.

[0210] The other structures of the embodiment shown in FIG. 15 may be the same as those of the embodiment shown in FIG. 12 , and will not be described in detail here.

[0211] Please refer to Figure 16, which is a top view of another embodiment of the semiconductor device provided by the present application. In this embodiment, the cross-sections of the source bump 303, the gate bump 40a, and the drain bump 50a are all racetrack-shaped or rectangular.

[0212] Please refer to Figure 17, which is a partial view of a top view of another specific embodiment of the semiconductor device provided by the present application. In this embodiment, the dimension of the source bump 303a along the first direction X (the length of the source bump 303a) is a, and the dimension along the second direction Y (the width of the source bump 303a) is b. The ratio of a to b satisfies the following: 1≤a / b≤6. For example, a / b can be 1, 2, 3, 4, 5, 5.5, 6, etc.

[0213] During the source bump processing, if the source bump is too long, the center may bulge upward and the edges may sag downward, resulting in a decrease in the source bump's coplanarity. The longer the source bump, the higher the coplanarity. This can lead to poor soldering or consistency issues when flip-chipping the semiconductor device onto the substrate. Excessive coplanarity can also cause poor probe contact during online screening tests of the semiconductor device. The source bump's coplanarity refers to the height difference between the highest and lowest points of the source bump.

[0214] When 1≤a / b≤6, the coplanarity of the source bump 303 will not be too large. For example, the coplanarity can be ±10%, which reduces the poor welding and consistency problems caused by the excessive coplanarity of the source bump 303 when the semiconductor device is flip-chip mounted on the substrate, and can reduce the risk of poor probe contact during online screening testing of the semiconductor device.

[0215] Please refer to Figure 18, which is a schematic diagram of the structure of Figure 17 without the source bump. The raised layer 80 is provided with a plurality of first through-holes 801. The projection of the first through-holes 801 on the XY plane can be a polygon, with the internal angle of the polygon being no less than 90°. This reduces stress concentration on the inner wall of the first through-holes 801 and prevents the formation of too small a through-hole, which would result in an insufficient contact area between the source bump and the source electrode. In the embodiment shown in Figure 18, the projection of the first through-holes 801 on the XY plane is a rectangle or a racetrack, i.e., the internal angle of the first through-holes 801 is 90°.

[0216] The dimension of the first through-hole 801 along the first direction X is c, and the dimension of the first through-hole 801 along the second direction Y is d. The minimum distance between the sidewall of the first through-hole 801 along the first direction X and the edge of the source finger 301 along the first direction X is e. Where c < d, meaning the dimension of the first through-hole 801 along the first direction X is smaller than the dimension along the second direction Y, this ensures that the second portion filled in the first through-hole 801 does not excessively occupy the space between the source, gate, and drain fingers, thereby ensuring the performance of the semiconductor device. e ≥ 0.5 μm ensures that the first through-hole 801 is not too close to the edge, improving the reliability of the first through-hole 801. It also prevents the first through-hole 801 from being too close to the connection bridge, preventing the projection of the first through-hole 801 along the third direction from falling on the connection bridge, causing the second portion of the source bump to fall on the connection bridge, thereby preventing the source bump from damaging the connection bridge. For example, e can be 0.5 μm, 0.8 μm, 1 μm, etc.

[0217] Please refer to Figures 18 and 19. Figure 19 is a schematic diagram of the structure of Figure 18 without the raised layer. In Figure 19, the dimension of the connecting bridge 302 along the first direction X is w. The difference between w and the minimum dimension x of the first through hole 801 satisfies: x+6≤w. In the embodiment shown in Figure 18, the minimum dimension x of the first through hole 801 is the dimension c of the first through hole 801 along the first direction X. In this case, c+6≤w. When the dimensions of the connecting bridge 302 satisfy the above relationship, it is convenient to form the connecting bridge 302.

[0218] FIG19 does not show the insulating medium between adjacent source fingers 301 and gate fingers 40 a and between adjacent gate fingers 40 a and drain fingers 50 a.

[0219] The embodiments of the present application also provide a method for preparing a semiconductor device, which is used to manufacture the semiconductor devices described in the above embodiments.

[0220] Please refer to FIG20 , which is a flow chart of a method for manufacturing a semiconductor device in a specific embodiment. The method for manufacturing a semiconductor device may include the following steps:

[0221] S1: Prepare a substrate and an epitaxial layer, and prepare a source electrode, a gate electrode, and a drain electrode on the epitaxial layer;

[0222] S2: preparing connecting bridges in the active area;

[0223] S3: preparing a pad layer above the connecting bridge, and opening a first through hole in the pad layer;

[0224] S4: preparing a source bump on the padding layer, so that the source bump is electrically connected to the source electrode through the first through hole.

[0225] The semiconductor device obtained through the above steps may be the semiconductor device described in any of the above embodiments.

[0226] Please refer to Figures 21a and 21b. Figure 21a is a schematic diagram of the source electrode, gate electrode and drain electrode obtained by step S1, and Figure 21b is a cross-sectional view of Figure 21a. When preparing the source electrode, drain electrode and gate electrode in step S1, a substrate 10 is first formed, and then an epitaxial layer 20 is prepared on the substrate 10. In a specific embodiment, a core layer 201, a buffer layer 202, a channel layer 203, a barrier layer 204 and a cap layer 205 can be sequentially deposited on the substrate 10 by metal organic chemical vapor deposition or the like. In some embodiments, the epitaxial layer 20 may not include the buffer layer 202 and the cap layer 205. Among them, the material of the core layer 201 includes but is not limited to AlN and GaN. The material of the buffer layer 202 includes but is not limited to AlGaN and GaN. The material of the channel layer 203 includes but is not limited to GaN. The material of the barrier layer 204 may include at least one of aluminum and indium. For example, the material of the barrier layer 204 may include but is not limited to AlGaN, InAlGaN, InGaN, and AlN.

[0227] When the epitaxial layer 20 includes a capping layer 205, the source electrode 30, drain electrode 50, and gate electrode 40 are formed on the capping layer 205. When the epitaxial layer 20 does not include a capping layer 205, the source electrode 30, drain electrode 50, and gate electrode 40 are formed on the barrier layer 204. The materials of the source electrode 30, drain electrode 50, and gate electrode 40 may include Ti, Al, Ni, TiN, TaN, and Au. After preparation, the source fingers 301, gate fingers 40a, and drain fingers 50a are spaced apart and distributed along the first direction X.

[0228] In addition, the barrier layer is removed by etching or other methods outside the area of ​​the dotted line frame shown in FIG21a, or impurities are injected into the barrier layer outside the dotted line frame area to render the barrier layer in that part inoperative, thereby forming a passive region outside the dotted line area. The region within the dotted line frame is the active region 60 of the semiconductor device. This step can be before or after the step of preparing the source electrode 30, the drain electrode 50, and the gate electrode 40.

[0229] Please refer to Figures 22a and 22b. Figure 22a is a schematic diagram of the structure after the support portion is set in the active area of ​​Figure 21a, and Figure 22b is a DD-direction cross-sectional view of Figure 22a. In the process of preparing the connecting bridge in step S2, first, an isolation dielectric 306 is deposited between the adjacent source fingers 301 and the gate fingers 40a and the adjacent gate fingers 40a and the drain fingers 50a to form a passivation layer to improve the current collapse effect of the semiconductor device (the source-drain current value of the semiconductor device is lower than the ideal current value, resulting in an increase in the resistance of the semiconductor device in the on state). Thereafter, a support portion 400 is set at a first preset position in the active area, and the first preset position at least covers the setting position of the connecting bridge. The support portion 400 is used to provide support for the connecting bridge when forming the connecting bridge in subsequent steps. Among them, the support portion 400 can be a structure with an arc-shaped surface to form an arc-shaped connecting bridge. In the embodiment shown in FIG. 22 a , the support portion 400 can be disposed at any position between adjacent source fingers 301 , that is, the first preset position is the space between adjacent source fingers 301 .

[0230] Specifically, an insulating material such as photoresist can be coated only at the first preset position to form the support portion 400. Alternatively, an insulating material such as photoresist or photosensitive organic matter can be spin-coated on the entire surface of the active area, and then the source fork finger 301 is exposed through photolithography exposure, leaving only the photoresist or photosensitive organic matter at the first preset position, and then the edge of the photoresist or photosensitive organic matter is smoothed by reflow.

[0231] Please refer to Figure 23, which is a schematic diagram of preparing a seed layer at a first preset position. The seed layer can be deposited on the entire surface of the active area, and then a photolithography operation is performed to expose only the seed layer located on the support portion 400 in Figures 22a and 22b. As shown in Figure 23, the seed layer 500 is located at a second preset position for forming a connecting bridge, which is the position for forming a connecting bridge. Since the supporting portion 400 is an insulating material such as photoresist, by covering the supporting portion 400 with a conductive seed layer 500, a connecting bridge can be formed on the seed layer 500 by electroplating. After the seed layer 500 is deposited, the seed layer 500 and the source interdigital fingers 301 are both conductive, and electroplating operations can be performed on the seed layer 500 and the source interdigital fingers 301.

[0232] The seed layer 500 may be a copper or gold seed layer, preferably gold.

[0233] Please refer to Figures 24a and 24b. Figure 24a is a schematic diagram of the connection bridge formed by electroplating in Figure 23, and Figure 24b is a cross-sectional view taken along the EE direction of Figure 24a. The electroplating operation is performed to form a source bridge pier 304 with a preset thickness on the source interdigital finger, and a connection bridge 302 with a preset thickness on the seed layer. The source bridge pier 304 and the connection bridge 302 have the same thickness and material. The seed layer and support portion are then removed, thereby forming a space between the connection bridge 302 and the gate interdigital finger 40a and the drain interdigital finger 50a. The shape of the space is the same as that of the support portion. The seed layer and support portion can be removed by wet etching.

[0234] In some embodiments, after removing the seed layer and the support portion, an isolation dielectric may be filled in the space between the connecting bridge 302 and the gate finger 40a and the drain finger 50a. The isolation dielectric may be an organic substance having a dielectric constant less than 3.9, such as benzocyclobutene, epoxy resin, etc. The connecting bridge 302 is electrically insulated from the gate finger 40a and the drain finger 50a through the isolation dielectric. When the dielectric constant of the medium between the source finger 301 and the gate finger 40b is small, the parasitic capacitance between the source finger 301 and the gate finger 40b can be effectively reduced. When the dielectric constant of the medium between the gate finger 40b and the drain finger 50b is small, the parasitic capacitance between the gate finger 40b and the drain finger 50b can be effectively reduced, thereby reducing the impact on the output impedance of the semiconductor device and reducing the risk of degradation of the RF characteristics of the semiconductor device.

[0235] Please refer to Figures 25a and 25b. Figure 25a is a schematic diagram of forming a source bump on Figure 24a, and Figure 25b is a cross-sectional view taken along the FF axis of Figure 25a. In step S3, a raised layer 80 is deposited on the connecting bridges 302 and source bridge piers 304 in Figures 24a and 24b. The dimension of the raised layer 80 along the third direction Z is greater than the height of the connecting bridges 302 along the third direction Z, that is, the raised layer 80 is higher than the highest point of the bridge surface of the connecting bridge 302. Then, a first through-hole 801 is formed in the raised layer 80. The first through-hole 801 penetrates the raised layer 80 along the third direction Z, exposing the source bridge piers 304 through the first through-hole 801. Multiple first through-holes 801 are provided in the raised layer 80, with at least one first through-hole 801 located in the active area of ​​the semiconductor device. Along the first direction X, the first through-holes 801 are located between adjacent connecting bridges 302.

[0236] The size of the source bump 303 and the size and position of the first through hole 801 satisfy the above relationship, which will not be repeated here. The cross section of the first through hole 801 in the XZ plane can be an inverted trapezoid or other shapes.

[0237] The padding layer 80 is made of insulating material.

[0238] Please refer to Figures 26a and 26b. Figure 26a is a schematic diagram of the preparation of the source bump in Figure 25a, and Figure 26b is a cross-sectional view taken along the GG axis of Figure 26a. In step S4, when preparing the source bump, a metal of a first material is first filled into the first through-hole 801 in Figure 25b to form a second portion 303b as shown in Figure 26b. Then, a metal of a second material is disposed on the side of the raised layer 80 facing away from the connecting bridge 304 to form a first portion 303a as shown in Figure 26b. The source bridge pier 304 exposed through the first through-hole is electrically connected to the first portion 303a of the source bump via the second portion 303b. As shown in Figure 26a, the projection of the source bump 303, including the first portion and the second portion, along the third direction Z can be rectangular or racetrack-shaped.

[0239] The ratio of the melting point of the first material to the melting point of the second material satisfies 1.5-2.5. For example, the ratio of the melting point of the first material to the melting point of the second material can be 1.5, 1.7, 1.9, 2, 2.2, 2.3, 2.4, 2.5, etc.

[0240] In a specific embodiment, the first material filling the first through-hole may be copper, and the second material outside the first through-hole may be an elemental metal or an alloy containing tin.

[0241] In the above steps, when forming the first portion 303b, the length a of the projection of the first portion 303b along the third direction Z and the width b of the projection along the third direction Z satisfy: 1≤a / b≤6. For details, please refer to the description of the embodiment shown in FIG17 and will not be repeated here.

[0242] Please refer to Figure 27, which is a schematic diagram of the application fields of the semiconductor device in this application. The semiconductor devices and power amplifiers described in the above embodiments can be used in terminal products such as tablet computers, mobile phones or satellite phones, watches, glasses, headphones, routers, etc.

Claims

1. A semiconductor device, characterized in that The semiconductor device includes a substrate, an epitaxial layer, a source electrode, a gate electrode, and a drain electrode, wherein the substrate and the epitaxial layer are stacked along a third direction, the source electrode, the gate electrode, and the drain electrode are arranged on a side of the epitaxial layer away from the substrate, and the source electrode, the gate electrode, and the drain electrode are alternately distributed along a first direction; The semiconductor device further includes a source bump for soldering with a substrate. The semiconductor device includes an active region, and at least a portion of a projection of the source bump along a third direction is located within the active region.

2. The semiconductor device according to claim 1, wherein The source bump is electrically connected to the source electrode of the active region.

3. The semiconductor device according to claim 2, wherein: The semiconductor device also includes a connecting bridge and a raising layer, the source electrode of the active area is electrically connected through the connecting bridge, the raising layer is located on the side of the connecting bridge away from the substrate, and the height of the raising layer along the third direction is greater than the height of the connecting bridge along the third direction, the raising layer is provided with a first through hole, and the source bump is electrically connected to the source electrode through the first through hole.

4. The semiconductor device according to claim 3, wherein The source bump includes a first part and a second part, the first part is used for welding with the substrate and is located on the side of the elevated layer away from the substrate, the second part is filled in the first through hole, and the first part is electrically connected to the source electrode through the second part.

5. The semiconductor device according to claim 4, wherein The melting point of the material of the second portion is higher than the melting point of the material of the first portion.

6. The semiconductor device according to claim 3, wherein The projection of the first through hole in the plane where the first direction and the second direction are located is a polygon, and the internal angle of the polygon is greater than or equal to 90°.

7. The semiconductor device according to claim 3, wherein A dimension of the first through hole along the first direction is c, and a dimension of the first through hole along the second direction is d, where c<d.

8. The semiconductor device according to claim 7, wherein: The dimension of the connecting bridge along the first direction is w, c+6≤w.

9. The semiconductor device according to claim 3, wherein A minimum distance between a sidewall of the first through hole along the first direction and an edge of the source electrode along the first direction is e, and e≥0.5 um.

10. The semiconductor device according to any one of claims 3 to 9, wherein: The semiconductor device further comprises a connection layer and an insulating layer, wherein the insulating layer is arranged on a side of the padding layer facing the source bump, and the connection layer is located between the padding layer and the insulating layer; The insulating layer is provided with a second through hole extending along a third direction. The source bump includes a first part and a second part. The second part is located in the second through hole. The first through hole has a connecting part. The first part is electrically connected to the source electrode through the second part, the connecting layer and the connecting part.

11. The semiconductor device according to claim 10, wherein: An overlap rate between a projection of the first through hole along the third direction and a projection of the second through hole along the third direction is 0-10%.

12. The semiconductor device according to any one of claims 3 to 11, characterized in that: The semiconductor device further includes a source bridge pier, which is arranged on a side of the source electrode facing the padding layer and is electrically connected to or integrally formed with the connection bridge; The material of the source electrode is the same as that of the source bridge pier.

13. The semiconductor device according to any one of claims 3 to 12, wherein: Along the first direction, the connecting bridge spans the gate electrode and the drain electrode between adjacent source electrodes, and there is an isolation space between the connecting bridge and the gate electrode and the drain electrode, or an isolation medium is filled between the connecting bridge and the gate electrode and the drain electrode, and the dielectric constant of the isolation medium is less than 3.

9.

14. The semiconductor device according to any one of claims 1 to 13, wherein: The projection of the source bump along the third direction is rectangular or racetrack-shaped.

15. The semiconductor device according to claim 14, wherein: The semiconductor device further comprises a gate bump and a drain bump, wherein the gate bump is electrically connected to the gate electrode, and the drain bump is electrically connected to the drain electrode; The projected area of the gate bump along the third direction is smaller than the projected area of the source bump along the third direction, and the projected area of the drain bump along the third direction is smaller than the projected area of the source bump along the third direction.

16. The semiconductor device according to any one of claims 1 to 15, characterized in that The length of the projection of the source bump along the third direction is a, the width of the projection of the source bump along the third direction is b, and 1≤a / b≤6.

17. The semiconductor device according to any one of claims 1 to 16, wherein: The projection of the source bump along the third direction at least covers the active area along the first direction.

18. The semiconductor device according to any one of claims 1 to 17, wherein: The source electrode includes source fingers, the gate electrode includes gate fingers, and the drain electrode includes drain fingers, the gate fingers and the drain fingers all extend toward the source electrode, and the source fingers, the gate fingers, and the drain fingers are spaced apart and distributed along a first direction; Wherein, along the first direction, the spacing between adjacent gate fingers and drain fingers is less than or equal to 3 um, and the spacing between adjacent gate fingers and source fingers is less than or equal to 2 um.

19. A power amplifier, characterized in that The power amplifier includes a substrate and a semiconductor device soldered to the substrate, and the semiconductor device is the semiconductor device according to any one of claims 1 to 18.

20. An electronic device, characterized in that The electronic device comprises the semiconductor device according to any one of claims 1 to 18 and / or the power amplifier according to claim 19.

21. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: preparing a source electrode, a gate electrode and a drain electrode on the epitaxial layer; preparing a connecting bridge in the active area so that adjacent source electrodes are electrically connected via the connecting bridge; preparing a padding layer on a side of the connecting bridge facing away from the epitaxial layer, and opening a first through hole in the padding layer; A source bump is prepared on the padding layer, and the source bump is electrically connected to the source electrode through the first through hole.

22. The method for preparing a semiconductor device according to claim 21, wherein: When preparing the connecting bridge, the preparation method specifically includes: preparing a support portion between adjacent source electrodes in the active region, wherein the support portion is made of an insulating material; preparing a conductive seed layer on the support portion, and making the seed layer at least cover the support portion; forming a connection bridge covering the seed layer and a source bridge pier covering the source electrode by electroplating; The support portion is removed.

23. The method for preparing a semiconductor device according to claim 22, wherein: Before preparing the supporting portion, an isolation dielectric is deposited between adjacent source electrodes and gate electrodes, and between adjacent gate electrodes and drain electrodes.

24. The method for preparing a semiconductor device according to claim 21, wherein: When the first through hole is provided on the raising layer, the projection of the first through hole in the plane where the first direction and the second direction are located is a polygon, and the internal angle of the polygon is greater than or equal to 90°.

25. The method for preparing a semiconductor device according to claim 24, wherein: When the first through hole is provided on the raising layer, a dimension c of the first through hole along the first direction is smaller than a dimension d of the first through hole along the second direction.

26. The method for manufacturing a semiconductor device according to claim 21, wherein: When the first through hole is provided on the raising layer, a minimum distance e between a sidewall of the first through hole along the first direction and an edge of the source electrode along the first direction is greater than or equal to 0.5 um.

27. The semiconductor device according to claim 25, wherein When preparing the connecting bridge, the dimension w of the connecting bridge along the first direction satisfies: c+6≤w.

28. The method for preparing a semiconductor device according to any one of claims 21 to 27, wherein: When preparing the raising layer, the height of the raising layer is made higher than the height of the connecting bridge.

29. The method for preparing a semiconductor device according to any one of claims 21 to 28, wherein: When preparing the source bump on the padding layer, the method for preparing the semiconductor device includes: Filling the first through hole with a metal of a first material to form a second portion; Disposing a metal of a second material on a side of the elevated layer away from the connecting bridge to form a first portion; The melting point of the first material is higher than the melting point of the second material.

30. The method for manufacturing a semiconductor device according to claim 29, wherein: When a metal of a second material is provided on a side of the raising layer away from the connecting bridge to form a first portion, a length a and a width b of a projection of the first portion along the third direction satisfy: 1≤a / b≤6.

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