Display substrate and display apparatus

Abstract

A display substrate, which has a display area and a binding area, the binding area being located on one side of the display area in a first direction. The display substrate comprises a base, a plurality of signal lines and a light-shielding layer, wherein the plurality of signal lines are located on the base, the signal lines are at least located in the display area, and the plurality of signal lines include a plurality of first-type signal lines and a plurality of first-type fan-out lines, the first-type signal lines receiving constant-voltage electrical signals; the light-shielding layer is located on the side of the plurality of signal lines away from the base, and is located in the display area, and the light-shielding layer comprises a plurality of first openings; the display area comprises a primary display area and a secondary display area located on one side of the primary display area, the light transmittance of the secondary display area being greater than the light transmittance of the primary display area, and the plurality of first openings being located in the secondary display area; the orthographic projections of the plurality of first-type signal lines and the plurality of first-type fan-out lines on the base do not overlap the orthographic projections of the plurality of first openings on the base; and each first-type fan-out line is located between two adjacent first-type signal lines.

Description

Display substrate and display device

[0001] This application claims priority to Chinese patent application No. 202410175990.6, filed on February 7, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display technology uses luminescent materials driven by an electric current to create a display. OLED displays offer advantages such as ultra-lightness, ultra-thinness, high brightness, wide viewing angles, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple manufacturing, minimal use of raw materials, high luminous efficiency, and a wide temperature range. Summary of the Invention

[0004] In one aspect, a display substrate is provided, comprising a display area and a binding area, the binding area being located on one side of the display area along a first direction. The display substrate comprises: a substrate, a plurality of signal lines, and a light shielding layer. The plurality of signal lines are located on the substrate. The signal lines are located at least in the display area. The plurality of signal lines include a plurality of first-type signal lines and a plurality of first-type fan-out lines. The first-type signal lines receive constant-voltage electrical signals. The light shielding layer is located on a side of the plurality of signal lines away from the substrate and is located in the display area. The light shielding layer includes a plurality of first openings. The display area comprises a main display area and a secondary display area located to one side of the main display area. The light transmittance of the secondary display area is greater than that of the main display area. The plurality of first openings are located in the secondary display area. The orthographic projections of the plurality of first-type signal lines and the plurality of first-type fan-out lines on the substrate do not overlap with the orthographic projections of the plurality of first openings on the substrate. The first-type fan-out line is located between two adjacent first-type signal lines.

[0005] In some embodiments, the first-type signal line extends along the first direction. The first-type fan-out line extends along the first direction. A first-type fan-out line located between two adjacent first-type signal lines has a spacing substantially equal to or equal to that between the two adjacent first-type signal lines.

[0006] In some embodiments, two adjacent first-type signal lines located on opposite sides of a same first-type fan-out line are substantially symmetrically arranged or symmetrically arranged with respect to the same first-type fan-out line.

[0007] In some embodiments, the display substrate further comprises: a plurality of pixel circuits. The plurality of pixel circuits are arranged in multiple rows and columns, with the pixel circuits in each row arranged along a second direction and the pixel circuits in each column arranged along a first direction. The second direction intersects the first direction. Two adjacent first-type signal lines located on either side of the first-type fan-out line constitute a first-type signal line group. The two first-type signal lines in the first-type signal line group are connected. One first-type signal line is electrically connected to one column of the pixel circuits.

[0008] In some embodiments, the plurality of signal lines further include: a plurality of first connecting lines, wherein the first connecting lines extend along the second direction, and the first connecting lines connect two first-type signal lines in the first-type signal line group.

[0009] In some embodiments, the first type of signal line includes a first voltage signal line.

[0010] In some embodiments, the plurality of signal lines further include: a plurality of second-category signal lines. The second-category signal lines and the first-category signal lines are configured to receive the same electrical signals. The second-category signal lines extend in the same or substantially the same direction as the first-category signal lines. Compared to the second-category signal lines, the first-category signal lines are closer to a center line extending in the first direction within the display area.

[0011] In some embodiments, the plurality of signal lines further include: a plurality of second-type fan-out lines and a plurality of data signal lines. The data signal lines extend along a first direction, and the second-type fan-out lines extend along a second direction, and the second-type fan-out lines are located in the display area. One second-type fan-out line is connected to one first-type fan-out line. The data signal line is connected to the second-type fan-out line.

[0012] In some embodiments, the display substrate further comprises: a plurality of pixel circuits. The plurality of pixel circuits are arranged in multiple rows and columns, with the pixel circuits in each row arranged along the second direction and the pixel circuits in each column arranged along the first direction, wherein the second direction intersects the first direction. The plurality of signal lines further comprise: a plurality of third-type signal lines. The third-type signal lines are used to receive initial signals. The third-type signal lines extend along the second direction. Two adjacent rows of pixel circuits are connected to the same third-type signal line.

[0013] In some embodiments, the spacing between the two adjacent rows of pixel circuits and the same third-type signal line is equal or approximately equal.

[0014] In some embodiments, the plurality of third-category signal lines include: a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines.

[0015] In some embodiments, the plurality of signal lines further include: a plurality of second connecting lines, wherein the second connecting lines extend along the first direction, and one of the second connecting lines is connected to one of the third type signal lines.

[0016] In some embodiments, the plurality of signal lines further include: a plurality of second connecting lines. The second connecting lines extend along the first direction. The second connecting lines include: at least one break and a plurality of sub-lines. The break is directly opposite the first opening, and the dimension of the break along the first direction is greater than or equal to the dimension of the first opening along the first direction. The plurality of sub-lines are located on opposite sides of each break. One sub-line is connected to one of the third-category signal lines.

[0017] In some embodiments, the plurality of signal lines further include: a plurality of data signal lines. The second connecting line is located between two adjacent data signal lines.

[0018] In some embodiments, the display substrate includes: a first source-drain conductive layer and a second source-drain conductive layer stacked on one side of the substrate. The display substrate also includes: a plurality of second-type fan-out lines and a plurality of data signal lines. The plurality of second-type fan-out lines are located in the first source-drain conductive layer. The plurality of first-type signal lines, the plurality of first-type fan-out lines, and the plurality of data signal lines are located in the second source-drain conductive layer.

[0019] In some embodiments, the display substrate further includes: a first gate conductive layer and a second gate conductive layer stacked between the substrate and the first source-drain conductive layer. The first gate conductive layer is located between the substrate and the second gate conductive layer. The display substrate further includes: a plurality of first connecting lines, a plurality of second connecting lines, and a plurality of third-category signal lines. The plurality of third-category signal lines include: a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines. The plurality of second connecting lines are located in the second source-drain conductive layer. The plurality of first initial signal lines are located in the first source-drain conductive layer. The plurality of second initial signal lines and the plurality of first connecting lines are located in the first gate conductive layer. The plurality of third initial signal lines are located in the second gate conductive layer.

[0020] In some embodiments, the display substrate further comprises: a plurality of light filters; the light shielding layer further comprises a plurality of second openings; the plurality of second openings are located in the main display area; and one light filter is located in one of the second openings.

[0021] In some embodiments, the display substrate further comprises: a plurality of light-emitting devices, wherein the plurality of light-emitting devices are located on a side of the plurality of signal lines away from the substrate; and an encapsulation layer, which is disposed between the light-shielding layer and the plurality of light-emitting devices.

[0022] In another aspect, a display device is provided, comprising: a display substrate as described in any of the above embodiments, and an optical element, wherein the optical element is located on the non-light-emitting side of the display substrate and in the auxiliary display area of ​​the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below should be considered schematic diagrams and are not intended to limit the actual dimensions, etc., of the products involved in the embodiments of the present disclosure.

[0024] FIG1 is a schematic diagram of a display device according to some embodiments of the present disclosure;

[0025] FIG2 is a schematic diagram of another display device according to some embodiments of the present disclosure;

[0026] FIG3 is a structural diagram of another display device according to some embodiments of the present disclosure;

[0027] FIG4 is a structural diagram of a display substrate according to some embodiments of the present disclosure;

[0028] FIG5 is a structural diagram of some film layers in a display substrate according to an implementation of the present disclosure;

[0029] FIG6 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0030] FIG7 is a structural diagram of other film layers in a display substrate according to some embodiments of the present disclosure;

[0031] FIG8 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0032] FIG9 is a structural diagram of a third type of signal line and a second connection line in a display substrate according to some embodiments of the present disclosure;

[0033] FIG10 is an equivalent circuit diagram of a pixel circuit and a light-emitting device according to some embodiments of the present disclosure;

[0034] FIG11 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0035] FIG12 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0036] FIG13 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0037] FIG14 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0038] FIG15 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0039] FIG16 is a structural diagram of some film layers in a display substrate according to some embodiments of the present disclosure;

[0040] FIG. 17 is a structural diagram of some further film layers in a display substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0043] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0044] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0045] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0046] As used herein, "perpendicular" and "equal" include the conditions described and conditions similar to the conditions described, where the range of the similar conditions is within an acceptable deviation range, where the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equalities is less than or equal to 5% of either.

[0047] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0048] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0049] As shown in FIG1 , some embodiments of the present disclosure provide a display device 1000. The display device 1000 can be any display device 1000 that displays either motion (e.g., video) or fixed (e.g., still images) and text or images. More specifically, it is contemplated that the display device 1000 of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry), etc.

[0050] In some examples, as shown in FIG1 , the display device 1000 further includes a display substrate 100 and a frame. The display substrate 100 is embedded in the frame.

[0051] In some embodiments, referring to FIG. 2 , the display device 1000 further includes a driver circuit board 300 . The driver circuit board 300 may include, for example, a timing controller (TCON), a DC / DC power management chip, and an adjustable resistor divider circuit (to generate Vcom), among other driver circuits. The driver circuit board 300 may also include other circuit structures, which are not listed here. The driver circuit board 300 is electrically connected to the display substrate 100 and is configured to transmit control signals to the display substrate 100, thereby driving the display substrate 100 to display images.

[0052] As shown in FIG. 2 , the display substrate 100 includes a display area A and a peripheral area N at least located on one side of the display area A along the second direction X.

[0053] In some embodiments, as shown in FIG2 , a peripheral area N is disposed around the display area A. A gate driver circuit (e.g., a Gate Driver On Array (GOA), control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.), and a bound driver chip (e.g., a Source Driver IC) may be disposed within the peripheral area N. For example, the gate driver circuit may be disposed on opposite sides of the display area A within the peripheral area N. The functions of the peripheral area N include, but are not limited to, these.

[0054] For example, as shown in FIG2 and FIG4 , the peripheral area N includes a binding area B, which is located on one side of the display area A along the second direction X. The binding area B is adjacent to a side edge of the display area A, for example, the lower edge of the display area A. The display substrate 100 is connected to an external driver in the binding area B.

[0055] For example, the binding area B is configured to lead out signal lines (such as the data signal line Data, the first voltage signal line VDD, and the common voltage signal line VSS mentioned below) and bind them to the driver circuit board 300. The binding area B is located on the side of the display substrate 100 for binding the driver circuit board 300. The above-mentioned binding driver chip can be placed in the binding area B.

[0056] Exemplarily, the display substrate 100 includes a plurality of pixels P disposed in a display area A, and each pixel P includes at least three sub-pixels P(x).

[0057] Exemplarily, the plurality of pixels P are arranged in a plurality of rows and columns.

[0058] Exemplarily, as shown in FIG2 , the display area A is an area in the display substrate 100 for displaying images, the sub-pixel P(x) is the smallest light-emitting unit on the display substrate 100 , and the sub-pixel P(x) is used to display images.

[0059] In some examples, the above-mentioned multiple sub-pixels P(x) emit light of the same color. For example, multiple sub-pixels P(x) all emit white light, red light, green light, blue light or other color light. In this case, the color light emitted by the sub-pixel P(x) remains the same color light after passing through the color filter layer, or is converted into other color light for emission. Therefore, when multiple sub-pixels P(x) emit the same color light, the display substrate 100 can achieve multi-color light output.

[0060] In other examples, multiple sub-pixels P(x) emit light of different colors. For example, multiple sub-pixels P(x) include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby realizing multi-color light output of the display substrate 100.

[0061] It should be noted that each pixel P includes at least three sub-pixels P(x), that is, each pixel P may include three, four or more sub-pixels P(x), and the multiple sub-pixels P(x) included in each pixel P may be a row, a column or a group of sub-pixels P(x), and a group of sub-pixels P(x) may be multiple sub-pixels P(x) adjacent to each other, and the adjacent multiple sub-pixels P(x) are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc.

[0062] At the same time, the luminous areas of the multiple sub-pixels P(x) included in each pixel P may be the same or different. The above is only an exemplary description and is not intended to limit the embodiments of the present disclosure. Adaptive design can be performed according to actual needs.

[0063] As shown in FIG. 3 , the display substrate 100 may further include an encapsulation layer 60 disposed on the light-emitting side of the plurality of sub-pixels P(x) and a functional stack 70 disposed on the encapsulation layer 60 .

[0064] For example, the functional stack 70 may include a color filter layer 71, meaning that the display substrate 100 employs a COE (CF On Encapsulation) structure. The functional stack 70 may also include one or more of a touch-sensitive functional layer, an anti-reflective layer, a hardening layer, and an anti-fingerprint layer to enable the display substrate 100 to achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the type and quantity of the functional stacks.

[0065] The display substrate 100 including the COE structure has the advantages of high contrast, low power consumption, and a wide color gamut. It can also reduce the thickness of the display substrate 100, facilitating a lightweight and thin design of the display substrate 100. Furthermore, the display substrate 100 has excellent bendability, enabling the display substrate 100 and the display device 1000 to achieve flexible display.

[0066] In some embodiments, as shown in FIG3 , the display device 1000 may further include an optical element 200 . The optical element 200 is located on the non-light-emitting side of the display substrate 100 . The light-emitting side of the display substrate 100 refers to the side of the display substrate 100 that can display an image. The non-light-emitting side of the display substrate 100 refers to the side opposite to the light-emitting side of the display substrate 100 .

[0067] The display area A is a region of the display substrate 100 used for displaying images.

[0068] The display area A may be in the shape of a rectangle or a rounded rectangle, etc. A rounded rectangle means that all four corners of the rectangle are rounded.

[0069] As shown in Figure 4, the display area A includes a main display area A1 and a secondary display area A2, with the secondary display area A2 located on at least one side of the main display area A1. In this embodiment, the secondary display area A2 is located on one side of the main display area A1, and the secondary display area A2 can be located on one side of the main display area A1. The secondary display area A2 can be surrounded or semi-surrounded by the main display area A1.

[0070] For example, the shape of the auxiliary display area A2 can be circular, elliptical, rectangular, etc.

[0071] For example, the auxiliary display area A2 is located on one side or multiple sides of the main display area A1.

[0072] For example, when the display area A is in the shape of a rectangle, the sub-display area A2 can be located at any position in the middle of the rectangle, or the sub-display area A2 can be located near any corner of the rectangle, or the sub-display area A2 can be located near any side of the rectangle.

[0073] In the following, the auxiliary display area A2 is taken as an example to be close to or facing the center line CL of the display A along the first direction Y.

[0074] For example, in the display substrate 100 , both the portions located in the main display area A1 and the auxiliary display area A2 can be used for image display.

[0075] Exemplarily, the light transmittance of the auxiliary display area A2 is greater than the light transmittance of the main display area A1. For example, the pixel density of the plurality of pixels P(x) located in the main display area A1 of the display substrate 100 is greater than the pixel density of the plurality of pixels P(x) located in the auxiliary display area A2 of the display substrate 100.

[0076] As shown in FIG3 , the optical element 200 is located in the secondary display area A2 of the display substrate 100. Because the light transmittance of the secondary display area A2 is greater than that of the main display area A1, external light is less lost after passing through the secondary display area A2, thereby allowing the optical element 200 to receive sufficient light and avoiding affecting the function of the optical element 200.

[0077] For example, as shown in FIG3 , the optical element 200 may be a camera, a fingerprint recognition sensor, an infrared sensor, and the like.

[0078] When the optical element 200 is working, it is necessary for external light to pass through the auxiliary display area A2 and illuminate the optical element 200 to activate its corresponding function. In the embodiment of the present disclosure, the optical element 200 is taken as a camera as an example.

[0079] For example, when the camera is working, external light can pass through the portion of the display substrate located in the secondary display area A2. In this way, the camera can collect this light to achieve the function of taking pictures or videos. For example, when the camera is working (for example, the user takes a selfie), the secondary display area A2 can present a black screen, and the main display area A1 can present the user's selfie picture, which clearly shows the location of the camera. Alternatively, the secondary display area A2 and the main display area A1 can present the user's selfie picture as a whole, without showing the location of the camera.

[0080] For example, when the camera is not working, the portions of the display substrate located in the auxiliary display area A2 and the main display area A1 can both display images, so that the display substrate and the display device 1000 as a whole can display images.

[0081] In some examples, the color filter layer 71 includes: a light shielding layer 50 .

[0082] Exemplarily, the light-shielding layer 50 may be a black matrix. The material of the black matrix includes an opaque material. The light-shielding layer 50 includes a plurality of first openings 51 and a plurality of second openings 52. The top view of the light-shielding layer 50 may be roughly a mesh structure, with the first openings 51 and the second openings 52 constituting the mesh of the mesh structure. The first openings 51 are located in the secondary display area A2 of the display substrate 100. Since the optical element 200 is located in the secondary display area A2, the plurality of first openings 51 correspond to the optical element 200. External light can pass through the display substrate 100 through the first openings 51 and enter the optical element 200, allowing the optical element 200 to collect external light.

[0083] For example, the plurality of first openings 51 are arranged in an array, and the plurality of second openings 52 are also arranged in an array.

[0084] In some examples, the shape of the first opening 51 may be the same or substantially the same as the shape of the second opening 52 .

[0085] For example, the shape of the first opening 51 is a rectangle, a trapezoid, a circle, a rounded rectangle, an ellipse, etc.

[0086] In other examples, the shape of the first opening 51 may be different from the shape of the second opening 52 .

[0087] The size relationship between the first opening 51 and the second opening 52 can be set according to actual needs, and the implementation of the present disclosure does not impose any limitation on this.

[0088] For example, the area of ​​the first opening 51 is greater than or equal to the area of ​​the second opening 52 .

[0089] For another example, the area of ​​the first opening 51 is smaller than the area of ​​the second opening 52 .

[0090] Exemplarily, the color filter layer 71 further includes: a plurality of filter portions 53. One filter portion 53 is located in one second opening 52. The plurality of second openings 52 are located in the main display area A1 of the display substrate 100. Thus, the filter portion 53 is also located in the main display area A1 of the display substrate 100.

[0091] The filter portion 53 can transmit light within a certain wavelength range, and one filter portion 53 is provided corresponding to one light emitting device 30 .

[0092] The plurality of filter sections 53 may include at least: a plurality of first sub-filter sections, a plurality of second sub-filter sections, and a plurality of third sub-filter sections. The first sub-filter sections can transmit red light, the second sub-filter sections can transmit green light, and the third sub-filter sections can transmit blue light.

[0093] For example, light emitted by the light emitting device 30 passes through the encapsulation layer 60 , enters the corresponding filter portion 53 in the light shielding layer 50 , passes through the filter portion 53 , and is emitted from the display substrate 100 .

[0094] In some embodiments, as shown in FIG. 3 , the display substrate 100 includes a substrate 10 , a plurality of pixel circuits 20 , and a plurality of light emitting devices 30 .

[0095] There are many types of the substrate 10 , which can be selected according to actual needs.

[0096] For example, the substrate 10 may be a rigid substrate 10. The rigid substrate 10 may be a glass substrate or a PMMA (Polymethylmethacrylate) substrate.

[0097] For example, the substrate 10 may be a flexible substrate 10. The flexible substrate 10 may be a PET (Polyethylene terephthalate) substrate 10, a PEN (Polyethylene naphthalate two-formicacid glycolester) substrate 10, or a PI (Polyimide) substrate 10. In this case, the display substrate 100 may realize a flexible display, for example.

[0098] As shown in FIG2 , a plurality of pixel circuits 20 are disposed on one side of a substrate 10 . The plurality of pixel circuits 20 are arranged in multiple rows and columns, with the pixel circuits 20 in each row arranged along a second direction X, and the pixel circuits 20 in each column arranged along a first direction Y. Each row of pixel circuits 20 includes a plurality of pixel circuits 20 spaced apart along the second direction X; each column of pixel circuits 20 includes a plurality of pixel circuits 20 spaced apart along the first direction Y. In other words, the first direction Y is the column direction in which the plurality of pixel circuits 20 are arranged, and the second direction X is the row direction in which the plurality of pixel circuits 20 are arranged. The first direction Y and the second direction X intersect.

[0099] For example, the angle between the first direction Y and the second direction X is 75°, 80°, 90°, 95°, 105°, or 120°.

[0100] 2 , Z represents a third direction, which is perpendicular to the plane of the substrate 10. For example, the third direction Z is perpendicular to both the first direction Y and the second direction X.

[0101] The above-mentioned light-emitting device 30 includes but is not limited to OLED (Organic Light-Emitting Diode), Mini LED (Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode), etc.

[0102] The following description will be made by taking the light emitting device 30 including an OLED as an example.

[0103] The light-emitting device 30 includes a first electrode, a light-emitting functional layer, a second electrode, etc., which are stacked in sequence. The light-emitting functional layer may include a light-emitting layer. Optionally, the light-emitting functional layer may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0104] For example, the first electrode may be one of an anode and a cathode, and the second electrode may be the other of the anode and the cathode, which is not limited in the embodiments of the present disclosure.

[0105] For the convenience of description, the embodiments of the present disclosure are described by taking the first electrode as an anode and the second electrode as a cathode as an example.

[0106] One pixel circuit 20 is connected to one light-emitting device 30, or one pixel circuit 20 is connected to multiple light-emitting devices 30. The pixel circuit 20 and its connected light-emitting devices 30 constitute the aforementioned sub-pixel P(x). The pixel circuit 20 can generate a drive signal (e.g., a drive current). Each light-emitting device 30 can emit light under the drive action of the drive signal generated by the pixel circuit 20 to which it belongs. The light emitted by each light-emitting device 30 is emitted through the filter portion 53 of the color filter layer 71 to form a plurality of different colored light rays. These multiple different colored light rays cooperate with each other, thereby enabling the display substrate 100 and the display device 1000 to achieve a display function.

[0107] In some examples, as shown in FIG2 and FIG3 , the display substrate 100 has a display area A and a binding area B. The binding area B is located on one side of the display area A along the first direction Y. The display substrate 100 further includes a plurality of signal lines 40 .

[0108] The plurality of signal lines 40 are located on the substrate 10 and are located on a side of the pixel circuit 20 away from the substrate 10 and between the plurality of light emitting devices 30 and the pixel circuit 20. The light emitting devices 30 are located on a side of the plurality of signal lines 40 away from the substrate 10.

[0109] As shown in Figures 5 and 6, the plurality of signal lines 40 include a plurality of first-type signal lines 41 and a plurality of first-type fan-out lines 44. The first-type signal lines 41 receive constant-voltage electrical signals. For example, the first-type signal lines 41 and the first-type fan-out lines 44 can be arranged on the same layer.

[0110] 2 , the signal lines 40 are at least located in the display area A. For example, the first type signal lines 41 and the first type fan-out lines 44 extend from the display area A to the binding area B and are connected to the driver circuit board 300 near the binding area B.

[0111] As shown in Figures 3 and 6, the light shielding layer 50 is located on the side of the plurality of signal lines 40 away from the substrate 10. The light shielding layer 50 constitutes a portion of the color filter layer 71. The light shielding layer 50 includes a plurality of first openings 51. The plurality of first openings 51 are arranged at intervals and are located in the secondary display area A2.

[0112] The orthographic projections of the plurality of first-type signal lines 41 and the plurality of first-type fan-out lines 44 on the substrate 10 do not overlap with the orthographic projections of the plurality of first openings 51 on the substrate 10. For example, the orthographic projections of the plurality of first-type signal lines 41 and the plurality of first-type fan-out lines 44 on the substrate 10 do not intersect with the boundary line of the orthographic projections of the first openings 51 on the substrate 10, and the orthographic projections of the plurality of first-type signal lines 41 and the plurality of first-type fan-out lines 44 on the substrate 10 are located outside the boundary line of the orthographic projections of the first openings 51 on the substrate 10.

[0113] For example, external light may enter the interior of the display substrate 100 through the plurality of first openings 51 of the light shielding layer 50 , and then pass through the display substrate 100 to enter the optical element 200 .

[0114] Therefore, in the process of external light entering the optical element 200 through the first opening 51 of the above-mentioned sub-display area A2, the light-shielding layer 50 can avoid blocking the external light, and the external light is not easily or even will not be blocked by the first type signal line 41 and the first type fan-out line 44. The loss of external light is relatively small, which can improve the light transmittance of the sub-display area A2 of the display substrate 100 and the light collection amount of the optical element 200, which is beneficial to optimizing the performance of the optical element 200, such as improving the accuracy of fingerprint recognition by the fingerprint recognition sensor and improving the photo quality of the camera.

[0115] In one implementation, as shown in FIG5 , a first-class fan-out line 44 is located between two adjacent data signal lines Data, and is disposed on the same layer as the two data signal lines Data. A parasitic capacitor is formed between the first-class fan-out line 44 and the two data signal lines Data. When a data signal transmitted by the data signal line Data undergoes a transition, the parasitic capacitor may affect the electrical signal transmitted by the first-class fan-out line 44, causing fluctuations in the electrical signal transmitted by the first-class fan-out line 44, thereby affecting the image display quality of the display substrate and the display device.

[0116] 6 , in some embodiments of the present disclosure, a display substrate 100 is provided with a first-type fan-out line 44 disposed between two adjacent first-type signal lines 41. No other signal lines 40 are disposed between the first-type fan-out line 44 and the two adjacent first-type signal lines 41.

[0117] The first fan-out lines 44 receive electrical signals (eg, data signals) from the driver circuit board or driver chip and transmit them to the pixel circuit 20. The first signal lines 41 receive and transmit constant voltage signals from the driver circuit board or driver chip to the pixel circuit 20.

[0118] The first type of signal line 41 that transmits a constant voltage signal has a certain shielding effect, which can separate the first type of fan-out line 44 from other signal lines 40, so that the distance between the first type of fan-out line 44 and the signal lines 40 other than the first type of signal line 41 (such as the above-mentioned data signal line Data) is larger, so that the first type of signal line 41 is less affected by other signal lines 40, reducing or even avoiding the first type of fan-out line 44 from the influence of the electrical signal that jumps on the adjacent signal line 40 (such as the above-mentioned data signal line Data), improving the stability and accuracy of the electrical signal transmitted by the first type of fan-out signal line 40, improving the driving capability of the pixel circuit 20, and thereby improving the image display quality of the display substrate 100 and the display device 1000.

[0119] The display substrate 100 provided by the embodiment of the present disclosure includes a substrate 10, a plurality of signal lines 40, and a light shielding layer 50. The light transmittance of the auxiliary display area A2 is greater than the light transmittance of the main display area A1. The signal lines 40 are at least located in the display area A. The light shielding layer 50 includes a plurality of first openings 51 located in the auxiliary display area A2. A plurality of first-type signal lines 41 in the plurality of signal lines 40 receive constant-voltage electrical signals. The orthographic projections of the plurality of first-type signal lines 41 and the plurality of first-type fan-out lines 44 on the substrate setting plane are aligned with the plurality of first openings 51. The orthographic projections of the substrate 10 on the plane do not overlap. Therefore, when external light passes through the display substrate 100 through the first opening 51, it is unlikely or even impossible for the light to be blocked by the first-type signal lines 41 and the first-type fan-out lines 44. This results in relatively little external light loss, thereby improving the light transmittance of the secondary display area A2 of the display substrate 100 and the amount of light collected by the optical element 200. This helps optimize the performance of the optical element 200, such as by improving the fingerprint recognition accuracy of the fingerprint sensor and the image quality of the camera. Furthermore, the first-type fan-out line 44 is positioned between two adjacent first-type signal lines 41, minimizing the impact of other signal lines 40 on the first-type signal lines 41. This reduces or even eliminates the impact of transitions on adjacent signal lines 40 (such as the aforementioned data signal lines) on the first-type fan-out lines 44. This improves the stability and accuracy of the electrical signals transmitted by the first-type fan-out signal lines 40, enhances the driving capability of the pixel circuit 20, and thereby enhances the image display quality of the display substrate 100 and the display device 1000.

[0120] 6 , the first-type signal line 41 extends along a first direction Y. The first-type fan-out line 44 extends along the first direction Y.

[0121] 6 , the first type signal line 41 is substantially in the shape of a strip extending along the first direction Y. For another example, as shown in FIG7 , the first type signal line 41 is in the shape of a broken line extending substantially along the first direction Y.

[0122] For example, the first type of fan-out line 44 is substantially in the shape of a long strip, and the long strip extends along the first direction Y.

[0123] For example, the two adjacent first-type signal lines 41 and first-type fan-out lines 44 are parallel or substantially parallel.

[0124] For example, along the second direction X, the spacing between the entire first-type signal line 41 and the entire first-type fan-out line 44 is a uniform value. Specifically, taking the first-type fan-out line 44 including a plurality of interconnected sub-sections, wherein the plurality of sub-sections include a first sub-section and a second sub-section, and the corresponding first-type signal line 41 including a plurality of interconnected sub-sections, wherein the plurality of sub-sections include a third sub-section and a fourth sub-section as an example, along the second direction X, the first sub-section and the third sub-section are directly opposite each other, and the size of the first sub-section along the first direction Y is approximately equal to the size of the third sub-section along the first direction Y. Along the second direction X, the second sub-section and the fourth sub-section are directly opposite each other, and the size of the first sub-section along the first direction Y is approximately equal to the size of the third sub-section along the first direction Y. The spacing between the first sub-section and the third sub-section is equal to or approximately equal to the spacing between the second sub-section and the fourth sub-section.

[0125] For another example, along the second direction X, the spacing between the first-class signal line 41 and the first-class fan-out line 44 is non-uniform. Specifically, taking the first-class fan-out line 44 including a plurality of interconnected sub-sections, wherein the plurality of sub-sections include a first sub-section and a second sub-section, and the corresponding first-class signal line 41 including a plurality of interconnected sub-sections, wherein the plurality of sub-sections include a third sub-section and a fourth sub-section, the first sub-section and the third sub-section correspond to each other. Corresponding here means that along the second direction X, the first sub-section and the third sub-section are directly opposite each other, and the size of the first sub-section along the first direction Y is approximately equal to the size of the third sub-section along the first direction Y. The second sub-section and the fourth sub-section correspond to each other. Corresponding here means that along the second direction X, the second sub-section and the fourth sub-section are directly opposite each other, and the size of the first sub-section along the first direction Y is approximately equal to the size of the third sub-section along the first direction Y. The spacing between the first sub-section and the third sub-section is not equal to the spacing between the second sub-section and the fourth sub-section.

[0126] Exemplarily, as shown in FIG6 and FIG7 , the first-type fan-out line 44 located between two adjacent first-type signal lines 41 is equal to or substantially equal to the spacing between the two adjacent first-type signal lines 41 .

[0127] For example, the spacing between the sub-portions of the first-type fan-out line 44 and the corresponding sub-portions of the first-type signal line 41 on one side thereof, and the spacing between the sub-portions of the first-type fan-out line 44 and the corresponding sub-portions of the first-type signal line 41 on the other side thereof are equal or approximately equal.

[0128] In this way, the shielding effects of the two first-type signal lines 41 on the opposite sides of the first fan-out line can be the same or approximately the same, further reducing the impact of the electrical signal jumps on the first-type fan-out line 44 on the other signal lines 40, effectively improving the stability and accuracy of the electrical signals transmitted by the first-type fan-out signal line 40, improving the driving capability of the pixel circuit 20, and thereby improving the image display quality of the display substrate 100.

[0129] Optionally, two adjacent first-type signal lines 41 located on opposite sides of a same first-type fan-out line 44 are substantially symmetrically arranged or symmetrically arranged with respect to the same first-type fan-out line 44 .

[0130] For example, the first-type fan-out line 44 is a symmetry axis, and the shapes of the two first-type signal lines 41 are symmetrical about the same first-type fan-out line 44 .

[0131] In this way, the shielding protection effects on the relative sides of each sub-section of the first-type fan-out line 44 can be roughly the same, thereby further reducing the impact of electrical signal jumps on other signal lines 40 on the first-type fan-out line 44, and improving the stability and accuracy of the electrical signals transmitted by the first-type fan-out signal line 40.

[0132] In some examples, as shown in FIG. 2 , the display substrate 100 further includes: the plurality of pixel circuits 20 described above.

[0133] The pixel circuit 20 has various structures that can be selected based on actual needs. For example, the pixel circuit 20 may have a "6T1C," "7T1C," "8T1C," or "7T2C" structure. Here, "T" represents a transistor, and the number preceding "T" represents the number of transistors. "C" represents a storage capacitor, and the number preceding "C" represents the number of storage capacitors.

[0134] For example, in the embodiments of the present disclosure, the structure of the pixel circuit 20 is described as an "8T1C" structure. FIG10 shows an equivalent circuit diagram of a sub-pixel.

[0135] In the pixel circuit provided by the embodiment of the present disclosure, the first electrode of each transistor used is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source. In the pixel circuit provided by the embodiment of the present disclosure, nodes such as the first node and the second node do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0136] Exemplarily, as shown in FIG10 , the pixel circuit 20 includes: a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a switching transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a second reset transistor T7 , a third reset transistor T8 and a storage capacitor Cst.

[0137] For example, as shown in FIG10 , the control electrode of the first reset transistor T1 is electrically connected to the first reset signal terminal RN1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal terminal VN1, and the second electrode of the first reset transistor T1 is electrically connected to the first node N1 (i.e., electrically connected to the second electrode of the compensation transistor T2). The first reset transistor T1 is configured to be turned on under the control of the first reset signal provided by the first reset signal terminal RN1, and transmit the first initial signal received from the first initial signal terminal VN1 to the first node N1, thereby resetting the first node N1.

[0138] For example, as shown in FIG10 , the control electrode of the second reset transistor T7 is electrically connected to the second reset signal terminal RN2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal terminal VN2, and the second electrode of the second reset transistor T7 is electrically connected to the second node N2. The second reset transistor T7 is configured to be turned on under the control of the second reset signal provided by the second reset signal terminal RN2, transmit the second initial signal received from the second initial signal terminal VN2 to the second node N2, and reset the second node N2.

[0139] For example, as shown in FIG10 , the control electrode of the switching transistor T4 is electrically connected to the first scan signal terminal SN1, the first electrode of the switching transistor T4 is electrically connected to the data signal terminal DN, and the second electrode of the switching transistor T4 is electrically connected to the third node N3. The switching transistor T4 is configured to be turned on under the control of the first scan signal provided by the first scan signal terminal SN1, and transmit the data signal transmitted by the data signal terminal DN to the third node N3.

[0140] For example, as shown in FIG10 , the control electrode of the driving transistor T3 is electrically connected to the fourth node N4, the first electrode of the driving transistor T3 is electrically connected to the third node N3, and the second electrode of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is configured to be turned on under the control of the voltage of the fourth node N4 and transmit a signal (e.g., a data signal) from the third node N3 to the first node N1.

[0141] For example, as shown in FIG10 , a control electrode of the compensation transistor T2 is electrically connected to the second scan signal terminal SN2, a first electrode of the compensation transistor T2 is electrically connected to the first node N1, and a second electrode of the compensation transistor T2 is electrically connected to the fourth node N4. The compensation transistor T2 is configured to be turned on under the control of the second scan signal provided by the second scan signal terminal SN2, and transmit a signal (e.g., a data signal) from the first node N1 to the fourth node N4.

[0142] For example, as shown in FIG10 , a control electrode of the first emission control transistor T5 is electrically connected to the enable signal terminal EM, a first electrode of the first emission control transistor T5 is electrically connected to the first voltage signal terminal VDD, and a second electrode of the first emission control transistor T5 is electrically connected to the third node N3. The first emission control transistor T5 is configured to be turned on under the control of an enable signal provided by the enable signal terminal EM, and to transmit a voltage signal received from the first voltage signal terminal VDD to the third node N3.

[0143] For example, as shown in FIG10 , a control electrode of the second light-emitting control transistor T6 is electrically connected to the enable signal terminal EM, a first electrode of the second light-emitting control transistor T6 is electrically connected to the first node N1, and a second electrode of the second light-emitting control transistor T6 is electrically connected to the second node N2. The second light-emitting control transistor T6 is configured to be turned on under the control of an enable signal provided by the enable signal terminal EM, and transmit the voltage signal from the first node N1 to the second node N2.

[0144] For example, as shown in FIG10 , a control electrode of the third reset transistor T8 is electrically connected to the second reset signal terminal RN2, a first electrode of the third reset transistor T8 is electrically connected to the third initial signal terminal VN3, and a second electrode of the third reset transistor T8 is electrically connected to the third node N3. The third reset transistor T8 is configured to be turned on under the control of the second reset signal provided by the second reset signal terminal RN2, transmit the third initial signal received from the third initial signal terminal VN3 to the third node N3, and reset the third node N3.

[0145] Exemplarily, as shown in FIG. 10 , a first electrode of the storage capacitor Cst is electrically connected to the fourth node N4 , and a second electrode of the storage capacitor Cst is electrically connected to the first voltage signal terminal VDD.

[0146] One end of the light emitting device 30 is electrically connected to the second node N2, and the other end is electrically connected to the common voltage signal terminal VSS.

[0147] The light emitting device 30 emits light under the action of the electrical signal provided by the second node N2 and the common voltage provided by the common voltage signal terminal VSS.

[0148] The compensation transistor T2 in the pixel circuit 20 may be an LTPO (Low Temperature Polycrystalline Oxide) transistor, and the remaining transistors may be LTPS (Low Temperature Poly-Silicon) transistors.

[0149] For example, since LTPO transistors have low leakage current, configuring the compensation transistor T2 as an oxide transistor can reduce the leakage current of the compensation transistor T2, preventing leakage of the fourth node N4 through the compensation transistor T2 and the first reset transistor T1, thereby ensuring the compensation effect on the drive transistor T3 and the stability of the electrical signal at the fourth node N4, thereby improving the display quality of the display substrate 100. LTPS transistors have higher mobility, and configuring transistors such as the drive transistor T3 as low-temperature polysilicon transistors can accelerate the charging speed of the storage capacitor Cst, thereby further improving the display quality of the display substrate 100.

[0150] In one implementation, as shown in FIG5 , a first-type signal line 41 is connected to two adjacent columns of pixel circuits.

[0151] In some embodiments of the present disclosure, as shown in Figures 6 and 7, two adjacent first-type signal lines 41 located on either side of a first-type fan-out line 44 constitute a first-type signal line group 410. The two first-type signal lines 41 in the first-type signal line group 410 are connected. One first-type signal line 41 is electrically connected to a column of pixel circuits 20.

[0152] Therefore, the position of the corresponding first-type signal line 41 can be set according to the relative position of the pixel circuit 20 in the display area A, so that the relative position of the first-type signal line 41 and the pixel circuit 20 connected thereto can be reasonably adjusted, thereby improving the design flexibility of the first-type signal line 41 and helping to reduce the design difficulty of the display substrate 100.

[0153] 6 , the plurality of signal lines 40 further include a plurality of first connection lines 46 . The first connection lines 46 extend along the second direction X. The first connection lines 46 connect two first-type signal lines 41 in the first-type signal line group 410 .

[0154] For example, the first connecting lines 46 and the corresponding first-type signal lines 41 are located in different film layers.

[0155] The two first-type signal lines 41 in the first-type signal line group 410 extend in a different direction from the first connecting line 46, so that multiple first-type signal lines 41 and multiple first connecting lines 46 intersect with each other to form a mesh structure. Therefore, when the first-type signal line 41 transmits an electrical signal, the difference in the electrical signals transmitted to the various pixel circuits 20 in different rows in the same column is small, thereby reducing the voltage drop of the electrical signal transmitted by the first-type signal line 41, thereby reducing the difference between the light emitted by the sub-pixel and the preset light, and thereby improving the image display quality of the display substrate 100 and the display device 1000.

[0156] In some examples, as shown in FIG6 and FIG7 , the first type of signal line 41 includes a first voltage signal line VDD that transmits a first voltage signal to the pixel circuit 20 connected thereto.

[0157] 5 , the first voltage signal line VDD in the display substrate 100 provides electrical signals to two adjacent columns of pixel circuits. The first voltage signal line VDD is relatively large in the second direction X and is relatively wide.

[0158] In the embodiment of the present disclosure, the first voltage signal line VDD in the above-described implementation is divided into two first voltage signal lines VDD. The two first voltage signal lines VDD respectively provide or transmit the first voltage signal to two adjacent columns of pixel circuits 20. A first-type fan-out line 44 is disposed between the two first voltage signal lines VDD. Thus, the two first voltage signal lines VDD can be used to shield and protect the first-type fan-out line 44. Furthermore, the spacing between the first voltage signal line VDD and the column of pixel circuits 20 to which it is connected can be flexibly adjusted without being affected by the locations of other columns of pixel circuits 20, thereby simplifying the design of the display substrate 100.

[0159] In some examples, as shown in FIG2 , the plurality of signal lines 40 further include a plurality of second-type signal lines 42. The second-type signal lines 42 are used to receive the same electrical signals as the first-type signal lines 41. The second-type signal lines 42 extend in the same or substantially the same direction as the first-type signal lines 41.

[0160] For example, the second type signal lines 42 also include the first voltage signal lines VDD. The second type signal lines 42 are connected to one or two columns of pixel circuits 20 and provide the pixel circuits 20 with first voltage signals.

[0161] Compared with the second-type signal lines 42 , the first-type signal lines 41 are closer to the center line CL extending along the first direction Y in the display area A.

[0162] Thus, the first-class fan-out line 44 located between two adjacent first-class signal lines 41 can be made closer to the center line CL of the display area A, reducing the distance between the first-class fan-out line 44 and the binding area B in the second direction X, which is conducive to ensuring that the first-class fan-out line 44 extends to the binding area B.

[0163] In some examples, as shown in FIG2 and FIG6 , the plurality of signal lines 40 further include: a plurality of second-type fan-out lines 45 and a plurality of data signal lines Data. The data signal lines Data extend along a first direction Y, and the second-type fan-out lines 45 extend along a second direction X. The second-type fan-out lines 45 are located in the display area A. One second-type fan-out line 45 is connected to one first-type fan-out line 44. The data signal line Data is connected to the second-type fan-out line 45.

[0164] For example, the second-type fan-out line 45 and the first-type fan-out line 44 , and the data signal line Data and the second-type fan-out line 45 are connected through vias.

[0165] In the top view shown in Figure 6, along the second direction X, the arrangement order of the multiple signal lines 40 and the first opening 51 is: first-class voltage signal line 41 (or first voltage signal line VDD), first-class fan-out line 44, first-class voltage signal line 41 (or first voltage signal line VDD), data signal line Data, first opening 51, data signal line Data, first-class voltage signal line 41 (or first voltage signal line VDD).

[0166] For example, among the plurality of data signal lines Data, the data signal line Data that is away from the center line CL extending along the first direction Y of the display area A is connected to the second-type fan-out line 45. The data signal line Data is connected to the first-type fan-out line 44 through the second-type fan-out line 45, thereby achieving the extraction of the data signal line Data, facilitating the data signal line Data to receive electrical signals from the binding area B.

[0167] The data signal line Data connected to the second-type fan-out line 45 is a signal line in the display substrate 100 that needs to be sequentially led through the second-type fan-out line 45 and the first-type fan-out line 44 to the bonding area B. This arrangement can be called FIP (Fanout In Pixel). The data signal line Data is spaced relatively far from the center line CL of the display area A along the first direction Y, and is close to the boundary between the display area A and the peripheral area B.

[0168] By adopting the second-class fan-out line 45 and the first-class fan-out line 44 to lead the data signal line Data to the binding area B, the area of ​​the peripheral area N occupied by the data signal line Data and the corresponding second-class fan-out line 45 and the first-class fan-out line 44 can be smaller, so that the area of ​​the peripheral area N of the display substrate 100 can be designed to be smaller, which is conducive to realizing the narrow frame design of the display substrate 100 and the display device 1000.

[0169] At least one of the multiple subsections of the first-class fan-out line 44 is connected to the above-mentioned second-class fan-out line 45. For example, the multiple subsections of the first-class fan-out line 44 can be interconnected and uninterrupted. For another example, as shown in FIG6 , among the multiple subsections 441 of the first-class fan-out line 44, at least one of the multiple adjacent subsections 441 is disconnected from each other. The subsection 441 of the first-class fan-out line 44 connected to the second-class fan-out line 45 is a valid subsection of the first-class fan-out line 44, and the subsection 441 of the first-class fan-out line 44 that is not connected to the second-class fan-out line 45 is a redundant subsection of the first-class fan-out line 44, and the redundant subsection can receive a constant voltage signal, for example, a common voltage signal.

[0170] It is understood that the display substrate 100 is further provided with data signal lines that are not connected to the second-type fan-out lines 45 and the first-type fan-out lines 44. These data signal lines extend along the first direction Y and are spaced relatively close to the binding area B in the second direction X. Alternatively, these data signal lines are directly opposite the binding area B in the first direction Y. Therefore, these data signal lines extend directly to the binding area B without being led out using the first-type fan-out lines 44 and the second-type fan-out lines 45.

[0171] In some examples, as shown in FIG2 , the plurality of signal lines 40 further include a plurality of third-type signal lines 43 . The third-type signal lines 43 receive and transmit initial signals and extend along the second direction X.

[0172] Two adjacent rows of pixel circuits 20 are connected to the same third-type signal line 43. Thus, two adjacent rows of pixel circuits 20 share one third-type signal line 43, which can reduce the number of third-type signal lines 43, reduce the area occupied by the third-type signal lines 43 in the film layer where they are located, reduce the wiring difficulty of the film layer, and reduce the manufacturing cost of the display substrate 100.

[0173] For example, two adjacent rows of pixel circuits 20 are located on opposite sides of the same third-type signal line 43. This can reduce the distance between the third-type signal line 43 and the two rows of pixel circuits 20 to a certain extent, thereby reducing the wiring difficulty of the third-type signal line 43 and facilitating the manufacturing of the display substrate 100.

[0174] In some examples, the spacing between two adjacent rows of pixel circuits 20 and the same third-type signal line 43 is equal or substantially equal.

[0175] The two adjacent rows of pixel circuits 20 may be symmetrically arranged with respect to the third-type signal line 43 .

[0176] As a result, the third-type signal line 43 can be electrically connected to two adjacent rows of pixel circuits 20 via equal or substantially equal paths, resulting in no or minimal difference in the electrical signals transmitted by the third-type signal line 43 to the two rows of pixel circuits 20. This allows the two rows of sub-pixels to emit light with minimal or no difference when the preset brightness is the same, thus improving the image display quality of the display substrate 100 and the display device 1000. Furthermore, the arrangement of the multiple pixel circuits 20 can be more regular, facilitating the rational planning of the relative positions of the first openings 51, thereby increasing the area of ​​the first openings 51, increasing the amount of light collected by the optical element 200, and improving the performance of the optical element 200 and the display device 1000.

[0177] In some examples, as shown in FIG. 2 and FIG. 9 , the plurality of third-type signal lines 43 include: a plurality of first initial signal lines Vinit1 , a plurality of second initial signal lines Vinit2 , and a plurality of third initial signal lines Vinit3 .

[0178] For example, the first initial signal line Vinit1 and the second initial signal line Vinit2 are located on opposite sides of a row of pixel circuits 20 , and the second initial signal line Vinit2 and the third initial signal line Vinit3 are located on the same side of the same row of pixel circuits 20 .

[0179] Taking the example of a plurality of rows of pixel circuits 20 including a first row of pixel circuits 20, a second row of pixel circuits 20, a third row of pixel circuits 20, a fourth row of pixel circuits 20, and a fifth row of pixel circuits 20 arranged sequentially along a first direction Y, a first initial signal line Vinit1 is located between the first row of pixel circuits 20 and the second row of pixel circuits 20, and the first row of pixel circuits 20 and the second row of pixel circuits 20 are symmetrically arranged with respect to the first initial signal line Vinit1. A second initial signal line Vinit2 and a third initial signal line Vinit3 are both located between the second row of pixel circuits 20 and the third row of pixel circuits 20, and the second row of pixel circuits 20 and the third row of pixel circuits 20 are symmetrically arranged with respect to the second initial signal line Vinit2 (or the third initial signal line Vinit3). Another first initial signal line Vinit1 is located between the third row of pixel circuits 20 and the fourth row of pixel circuits 20, and the third row of pixel circuits 20 and the fourth row of pixel circuits 20 are symmetrically arranged with respect to the first initial signal line Vinit1. Another second initial signal line Vinit2 and another third initial signal line Vinit3 are both located between the fourth row pixel circuit 20 and the fifth row pixel circuit 20, and the fourth row pixel circuit 20 and the fifth row pixel circuit 20 are symmetrically arranged about the second initial signal line Vinit2 (or the third initial signal line Vinit3).

[0180] 8 and 9 , the plurality of signal lines 40 further include a plurality of second connection lines 47. The second connection lines 47 extend along the first direction Y.

[0181] For example, as shown in FIG17 , two adjacent columns of pixel circuits 20 located on opposite sides of the second connection line 47 are symmetrically arranged about the second connection line 47. Two adjacent columns of pixel circuits 20 located on opposite sides of the first type of fan-out line 44 are symmetrically arranged about the first type of fan-out line 44. In this way, the arrangement of the plurality of signal lines 40 and the plurality of pixels 20 can be made more regular, the relative positions of the first openings 51 can be reasonably planned, and a larger area can be reserved for the region corresponding to the first openings 51, which is conducive to setting the area of ​​the first openings 51 to a larger area, thereby facilitating improving the light transmittance of the secondary display area A2, improving the aperture ratio of the light shielding layer 50 (the aperture ratio here refers to the ratio of the area of ​​the plurality of first openings 51 to the entire area of ​​the light shielding layer 50), increasing the amount of light collected by the optical element 200, and improving the performance of the optical element 200.

[0182] The second connecting line 47 is connected to at least one third-type signal line 43. The second connecting line 47 can have various structures and can be configured according to actual needs, which is not limited in the embodiments of the present disclosure.

[0183] In some examples, as shown in FIG. 2 , one second connection line 47 is connected to one third-type signal line 43 .

[0184] For example, the second connection lines 47 are continuous and uninterrupted patterns.

[0185] The second connecting line 47 and the third type signal line 43 have different extension directions and are connected, so that the two can form a mesh structure in a local smaller area, so that the voltage drop of the electrical signal transmitted by the third type signal line 43 is small during the transmission to each pixel circuit 20, and the difference between the electrical signals transmitted by the third type signal line 43 to each adjacent two rows of pixel circuits 20 is small or even no difference, thereby ensuring the stability and accuracy of the electrical signals transmitted by the third type signal line 43 to each adjacent two rows of pixel circuits 20, so that the display substrate 100 has a better image display effect.

[0186] In other examples, as shown in FIG. 8 and FIG. 9 , the second connecting line 47 includes at least one break 471 and a plurality of sub-lines 472 .

[0187] For example, the second connecting line 47 includes a break 471 and two sub-lines 472 located on both sides of the break 471 .

[0188] For another example, the second connecting line 47 includes two breaks 471 and three sub-lines 472 , wherein one sub-line 472 is located between the two breaks 471 , and the remaining two sub-lines 472 are located on both sides of the two breaks 471 .

[0189] Illustratively, the break 471 is directly opposite the first opening 51, and the connecting line between the two sub-lines 472 on either side of the break 471 passes through the first opening 51. Furthermore, the dimension of the break 471 along the first direction Y is greater than or equal to the dimension of the first opening 51 along the first direction Y. This ensures that the orthographic projections of the multiple sub-lines 472 of the second connecting line 47 on the plane of the substrate 10 do not overlap with the orthographic projections of the first opening 51 on the plane of the substrate 10. This reduces or even prevents light loss caused by the sub-lines 472 blocking the light as it passes through the display substrate 100 through the first opening 51, thereby increasing the amount of light collected by the optical element 200 and improving its performance.

[0190] Illustratively, the plurality of sub-lines 472 are located on opposite sides of each break 471 . One sub-line 472 is connected to one third-type signal line 43 .

[0191] As shown in Figure 9, it can be understood that multiple sub-lines 472 of the same second connecting line 47 are connected to the same type of third-type signal lines 43 among the multiple third-type signal lines 43. The same type of third-type signal lines 43 herein refers to third-type signal lines 43 that transmit the same electrical signal. For example, the first initial signal line Vinit1 and the second initial signal line Vinit2 are different types of third-type signal lines. The first initial signal line Vinit1 and the third initial signal line Vinit3 are different types of third-type signal lines. The third initial signal line Vinit3 and the second initial signal line Vinit2 are different types of third-type signal lines.

[0192] For example, the plurality of second connection lines 47 include a plurality of first-type connection lines 473 , a plurality of second-type connection lines 474 , and a plurality of third-type connection lines 475 .

[0193] The plurality of sub-lines 472 of the first type of connection line 473 are respectively connected to the plurality of first initial signal lines Vinit1. The plurality of sub-lines 472 of the second type of connection line 474 are respectively connected to the plurality of second initial signal lines Vinit2. The plurality of sub-lines 472 of the third type of connection line 475 are respectively connected to the plurality of third initial signal lines Vinit3.

[0194] Therefore, a second connecting line 47 is respectively connected to multiple third-type signal lines 43, so that a mesh structure can be formed between the multiple second connecting lines 47 and the multiple third-type signal lines 43, so that the voltage drop of the electrical signal transmitted by the third-type signal line 43 is small during the process of being transmitted to each pixel circuit 20, thereby ensuring the stability and accuracy of the electrical signal transmitted by the third-type signal line 43 to each adjacent two rows of pixel circuits 20, so that the display substrate 100 has a better image display effect.

[0195] The broken line BL1 in Figure 9 illustrates the transmission path of the first initial signal transmitted by the first initial signal line Vinit1, the broken line BL2 illustrates the transmission path of the second initial signal transmitted by the second initial signal line Vinit2, and the broken line BL3 illustrates the transmission path of the third initial signal transmitted by the third initial signal line Vinit3.

[0196] In some examples, as shown in FIG. 8 and FIG. 17 , the second connection line 47 is located between two adjacent data signal lines Data.

[0197] In the top view shown in Figure 8, along the second direction X, the arrangement order of the multiple signal lines 40 and the first opening 51 is: first-class voltage signal line 41 (or first voltage signal line VDD), first-class fan-out line 44, first-class voltage signal line 41 (or first voltage signal line VDD), data signal line Data, first opening 51 and second connecting line 47, data signal line Data, first-class voltage signal line 41 (or first voltage signal line VDD).

[0198] For example, the second connection line 47 is provided in the same layer as the two adjacent data signal lines Data.

[0199] Since the second connection line 47 is connected to the third-type signal line 43, the second connection line 47 transmits a constant voltage electrical signal, so that the second connection line 47 can be used to shield the two adjacent data signal lines Data, thereby avoiding mutual interference between the data signals transmitted by the two adjacent data signal lines Data, and improving the stability and accuracy of the data signals transmitted by the two adjacent data signal lines Data, so that the difference between the light emitted by the sub-pixel and the preset light is smaller, thereby improving the image display quality of the display substrate 100 and the display device 1000.

[0200] In some embodiments, as shown in Figures 11 to 17 and Figure 8, the display substrate 100 includes: a shielding layer BSM, a first active layer PL, a third gate conductive layer Gate3, a first gate conductive layer Gate1, a second active layer ZL, a second gate conductive layer Gate2, a first source and drain conductive layer SD1, and a second source and drain conductive layer SD2, which are sequentially arranged on one side of the substrate 10.

[0201] Among them, Figure 11 shows a top-down structure of the shielding layer BSM. Figure 12 shows a top-down structure of the first active layer PL. Figure 13 shows a top-down structure of a stacked arrangement of the first active layer PL and the third gate conductive layer Gate3. Figure 14 shows a top-down structure of the first gate conductive layer Gate1. Figure 15 shows a top-down structure of the second gate conductive layer Gate2. Figure 16 shows a top-down structure of a stacked arrangement of the first gate conductive layer Gate1, the second active layer ZL, and the second gate conductive layer Gate2. Figure 8 shows a top-down structure of a stacked arrangement of the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2. Figure 17 shows a top-down structure of a stacked arrangement of the shielding layer BSM, the first active layer PL, the third gate conductive layer Gate3, the first gate conductive layer Gate1, the second active layer ZL, the second gate conductive layer Gate2, the first source-drain conductive layer SD1, and the second source-drain conductive layer SD2.

[0202] 6 illustrates another top view of the stacked first source / drain conductive layer SD1, the second source / drain conductive layer SD2 and the light shielding layer 50. FIG7 illustrates another top view of the stacked first source / drain conductive layer SD1, the second source / drain conductive layer SD2.

[0203] The shielding layer BSM may be made of a conductive material. The shielding layer BSM may be connected to a signal line that transmits a constant voltage electrical signal (e.g., the first voltage signal line VDD, the common voltage signal line VSS, the first initial signal line Vinit1, the second initial signal line Vinit1, or the third initial signal line Vinit2). This may improve the stability of the electrical signal in a film layer located on a side of the shielding layer BSM away from the substrate 10 (e.g., the film layer where the gate of the driving transistor T4 is located), thereby preventing interference with the signal in the film layer.

[0204] For example, the material of the first active layer PL may include semiconductor materials such as amorphous silicon, single crystal silicon, and polycrystalline silicon.

[0205] Exemplarily, the material of the second active layer ZL may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO for short).

[0206] Exemplarily, the materials of the first gate conductive layer Gate1, the second gate conductive layer Gate2, the third gate conductive layer Gate3, the first source-drain conductive layer SD1, and the second source-drain conductive layer SD2 are all conductive materials. The materials of the first gate conductive layer Gate1, the second gate conductive layer Gate2, and the third gate conductive layer Gate3 can be, for example, the same, and the materials of the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 can be, for example, the same.

[0207] For example, the conductive material may be a metal material, such as Al (aluminum), Ag (silver), Cu (copper), Cr (chromium), etc.

[0208] It should be noted that the orthographic projection of the first active layer PL on the substrate 10 overlaps with the orthographic projection of the third gate conductive layer Gate3 on the substrate 10. After forming the first gate conductive layer Gate1 on the side of the first active layer PL away from the substrate 10, the first active layer PL is doped using the third gate conductive layer Gate3 as a mask. This allows the portion of the first active layer PL covered by the third gate conductive layer Gate3 to constitute the active pattern of some transistors, while the portion of the first active layer PL not covered by the third gate conductive layer Gate3 constitutes a conductor, which can constitute the first or second electrode of some transistors. The portion where the third gate conductive layer Gate3 overlaps with the first active layer PL constitutes the gate pattern of some transistors.

[0209] Furthermore, the orthographic projection of the second active layer ZL on the substrate 10 has the same overlapping pattern as the orthographic projection of the second gate conductive layer Gate2 on the substrate 10 and the orthographic projection of the first gate conductive layer Gate1 on the substrate 10. The portion of the second gate conductive layer Gate2 located within the same overlapping pattern and the portion of the first gate conductive layer Gate1 located within the same overlapping pattern constitute the gate pattern of some transistors, and the portion of the second active layer ZL connected to the same overlapping pattern constitutes the first electrode or the second electrode of some transistors.

[0210] It can be understood that, among the above-mentioned multiple film layers, there may be an insulating layer (not shown in the figure) between any two adjacent film layers, and the figure only illustrates the location of some vias on the insulating layer. Each insulating layer can isolate the conductive film layers located on opposite sides of each other (the conductive film layers here refer to the above-mentioned shielding layer BSM, the first active layer PL, the third gate conductive layer Gate3, the first gate conductive layer Gate1, the second active layer ZL, the second gate conductive layer Gate2, the first source and drain conductive layer SD1, and the second source and drain conductive layer SD2) to avoid short circuits between the conductive film layers located on opposite sides of each insulating layer. The various conductive film layers can be connected by passing through the vias provided on each insulating layer. For example, the material of the above-mentioned insulating layer may include silicon oxide, silicon nitride or silicon oxynitride.

[0211] In one implementation, the aforementioned plurality of signal lines (herein, the plurality of second-type fan-out lines 45, the plurality of first-type signal lines 41, the plurality of first-type fan-out lines 44, the plurality of data signal lines Data, the plurality of second connection lines 47, and the plurality of second-type signal lines 42) are respectively disposed on three different film layers (e.g., the first source-drain conductive layer SD1, the second source-drain conductive layer SD2, and the third source-drain conductive layer) of the display substrate 100. This results in a large number of film layers in the display substrate 100, resulting in a relatively large overall thickness of the display substrate 100, which is not conducive to a lightweight and thin design of the display substrate 100. Furthermore, the cost of the mask used to prepare these three film layers is relatively high, which is not conducive to reducing the manufacturing cost of the display substrate 100.

[0212] In some examples of the present disclosure, as shown in Figures 8 and 17, the plurality of second-type fan-out lines 45 are located in the first source-drain conductive layer SD1, and the plurality of first-type signal lines 41, the plurality of first-type fan-out lines 44, and the plurality of data signal lines Data are located in the second source-drain conductive layer SD2.

[0213] Thus, multiple first-type signal lines 41 , multiple first-type fan-out lines 44 , and multiple data signal lines Data can be located on the same layer, which is beneficial to improving the shielding protection effect of the first-type signal lines 41 on the first-type fan-out lines 44 .

[0214] As shown in FIG8 , the plurality of second connection lines 47 are located in the second source-drain conductive layer SD2. The plurality of first initial signal lines Vinit1 are located in the first source-drain conductive layer SD1. As shown in FIG14 , the plurality of second initial signal lines Vinit2 and the first connection lines 46 are located in the first gate conductive layer Gate1. As shown in FIG15 , the plurality of third initial signal lines Vinit3 are located in the second gate conductive layer Gate2.

[0215] The first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 are located in different film layers, which can reduce the wiring density on each film layer to a certain extent. The first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 are located in different film layers from the second connecting line 47. This ensures that the first initial signal line Vinit1 and the second connecting line 47, the second initial signal line Vinit2 and the second connecting line 47, and the third initial signal line Vinit3 and the second connecting line 47 do not interfere with each other.

[0216] The plurality of data signal lines Data and the plurality of second connection lines 47 are all located in the second source-drain conductive layer SD2 . The second connection line 47 is located between two adjacent data signal lines Data, so that the second connection line 47 can be used to shield and protect the two adjacent data signal lines Data.

[0217] Therefore, the above-mentioned multiple signal lines 40 can be respectively arranged in the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2 of the display substrate 100, thereby reducing the number of film layers in the display substrate 100, reducing the thickness of the display substrate 100, and realizing a lightweight and thin design of the display substrate 100 and the display device 1000. It can also save a mask plate and reduce the preparation cost of the display substrate 100 and the display device 1000.

[0218] In other examples, as shown in FIG6 , the plurality of first connection lines 46 are located in the first source-drain conductive layer SD1 , thereby reducing the wiring density of the first gate conductive layer Gate1 to a certain extent.

[0219] In some examples, the plurality of signal lines 40 further include: a plurality of enable signal lines EML, a plurality of first scan signal lines ScanP, a plurality of second scan signal lines ScanN, a plurality of first reset signal lines ResetP, and a plurality of second reset signal lines ResetN.

[0220] The enable signal line EML, the first scan signal line ScanP, the second scan signal line ScanN, the first reset signal line ResetP, and the second reset signal line ResetN all extend along the second direction X.

[0221] The first scan signal line ScanP, the second scan signal line ScanN, the first reset signal line ResetP, and the second reset signal line ResetN may all be connected to the gate driving circuit to receive electrical signals from the gate driving circuit.

[0222] The enable signal line EML may be connected to an enable driving circuit (EM GOA) located in the peripheral region N of the display substrate 100 , and receive an enable signal from the enable driving circuit.

[0223] For example, as shown in FIG13 , a plurality of enable signal lines EML, a plurality of first scan signal lines ScanP, a plurality of first reset signal lines ResetP, and a plurality of second reset signal lines ResetN are all located in the third gate conductive layer Gate3 .

[0224] As shown in FIG. 16 , a plurality of second scan signal lines ScanN are located in the first gate conductive layer Gate1 and the second gate conductive layer Gate2 .

[0225] For example, the data signal line Data is connected to the data signal line terminal DN in the pixel circuit 20 for transmitting a data signal to the switch transistor T4 in the pixel circuit 20. The first voltage signal line VDD is connected to the first voltage signal terminal VDDN in the pixel circuit 20 for transmitting a first voltage signal to the first light emission control transistor T5 and the storage capacitor Cst in the pixel circuit 20.

[0226] The enable signal line EML is connected to the enable signal terminal EM in the pixel circuit 20 and is used to transmit an enable signal to the first emission control transistor T5 and the second emission control transistor T6 in the pixel circuit 20. The first scan signal line ScanP is connected to the first scan signal terminal SN1 in the pixel circuit 20 and is used to transmit a first scan signal to the switch transistor T4 in the pixel circuit 20. The second scan signal line ScanN is connected to the second scan signal terminal SN2 in the pixel circuit 20 and is used to transmit a second scan signal to the compensation transistor T2 in the pixel circuit 20.

[0227] The first initial signal line Vinit1 is connected to the first initial signal terminal VN1 in the pixel circuit 20 and is used to transmit a first initial signal to the first reset transistor T1 in the pixel circuit 20. The second initial signal line Vinit2 is connected to the second initial signal terminal VN2 in the pixel circuit 20 and is used to transmit a second initial signal to the second reset transistor T7 in the pixel circuit 20. The third initial signal line Vinit3 is connected to the third initial signal terminal VN3 in the pixel circuit 20 and is used to transmit a third initial signal to the third reset transistor T8 in the pixel circuit 20.

[0228] As shown in FIG. 3 , the display substrate 100 further includes an encapsulation layer 60 located on a side of the light emitting device 30 away from the substrate 10 and between the light shielding layer 50 and the plurality of light emitting devices 30 .

[0229] For example, the encapsulation layer 60 can be a thin film encapsulation layer, which can encapsulate the above-mentioned sub-pixels, so that the pixel circuit 20 and the light-emitting device 30 are isolated from external water vapor, etc., thereby improving the luminous performance and luminous life of the light-emitting device 30, and avoiding the oxidation of the pixel circuit 20 and the light-emitting device 30 by water vapor in the event of water vapor intrusion.

[0230] The encapsulation layer 60 has a certain light transmittance, so that the light emitted by the light emitting device 30 can pass through the encapsulation layer 60 and be emitted.

[0231] The encapsulation layer 60 includes an inorganic encapsulation layer and an organic encapsulation layer stacked together. The inorganic encapsulation layer may include a first inorganic encapsulation layer and a second inorganic encapsulation layer. The organic encapsulation layer may be located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0232] For example, the inorganic encapsulation layer can be made of an inorganic material and can be formed using a vapor deposition process. The organic encapsulation layer can be made of an organic material and can be formed using an inkjet printing process. The inorganic encapsulation layer can be made of an OC (Optical Clear) adhesive.

[0233] It can be understood that the organic encapsulation layer is mainly used for planarization and stress relief, and the first inorganic encapsulation layer and the second inorganic encapsulation layer in the inorganic encapsulation layer are mainly used to block water and oxygen, and to wrap the organic encapsulation layer located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0234] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate comprising a display area and a binding area, wherein the binding area is located on one side of the display area along a first direction; the display substrate comprising: substrate; A plurality of signal lines are located on the substrate; the signal lines are at least located in the display area; The plurality of signal lines include a plurality of first-type signal lines and a plurality of first-type fan-out lines; the first-type signal lines receive constant-voltage electrical signals; a light shielding layer, located on a side of the plurality of signal lines away from the substrate and located in the display area; the light shielding layer includes a plurality of first openings; In which, the display area includes a main display area and a secondary display area located on one side of the main display area; the light transmittance of the secondary display area is greater than the light transmittance of the main display area; the multiple first openings are located in the secondary display area; the orthographic projections of the multiple first-type signal lines and the multiple first-type fan-out lines on the substrate have no overlap with the orthographic projections of the multiple first openings on the substrate; the first-type fan-out line is located between two adjacent first-type signal lines.

2. The display substrate according to claim 1, wherein The first type of signal lines extend along the first direction; the first type of fan-out lines extend along the first direction; The first-type fan-out line located between two adjacent first-type signal lines is approximately equal to or the same as the spacing between the two adjacent first-type signal lines.

3. The display substrate according to claim 2, wherein: Two adjacent first-type signal lines located on opposite sides of a same first-type fan-out line are substantially symmetrically arranged or symmetrically arranged with respect to the same first-type fan-out line.

4. The display substrate according to claim 2 or 3, wherein: Also includes: a plurality of pixel circuits; The plurality of pixel circuits are arranged in multiple rows and columns, the pixel circuits in each row are arranged along the second direction, and the pixel circuits in each column are arranged along the first direction; the second direction intersects the first direction; Two adjacent first-type signal lines located on both sides of the first-type fan-out line constitute a first-type signal line group; the two first-type signal lines in the first-type signal line group are connected; and one first-type signal line is electrically connected to a column of the pixel circuits.

5. The display substrate according to claim 4, wherein: The plurality of signal lines further include: a plurality of first connecting lines; the first connecting lines extend along the second direction; and the first connecting lines connect two first-type signal lines in the first-type signal line group. The display substrate according to claim 1 , wherein: The first type of signal lines include first voltage signal lines.

7. The display substrate according to claim 1, wherein: The plurality of signal lines further include: a plurality of second-type signal lines; the second-type signal lines and the first-type signal lines are used to receive the same electrical signals; the extension direction of the second-type signal lines is the same or substantially the same as the extension direction of the first-type signal lines; Compared with the second-type signal lines, the first-type signal lines are closer to a center line extending along the first direction in the display area.

8. The display substrate according to claim 1, wherein: The plurality of signal lines further include: a plurality of second-type fan-out lines and a plurality of data signal lines; the data signal lines extend along the first direction, the second-type fan-out lines extend along the second direction, and the second-type fan-out lines are located in the display area; a second-type fan-out line is connected to a first-type fan-out line; The data signal line is connected to the second-type fan-out line.

9. The display substrate according to claim 1, wherein: Also includes: a plurality of pixel circuits; The plurality of pixel circuits are arranged in a plurality of rows and columns, the pixel circuits in each row are arranged along the second direction, the pixel circuits in each column are arranged along the first direction, and the second direction intersects the first direction; The plurality of signal lines further include: a plurality of third-type signal lines; the third-type signal lines are used to receive initial signals; the third-type signal lines extend along the second direction; The pixel circuits in two adjacent rows are connected to the same third-type signal line.

10. The display substrate according to claim 9, wherein: The distances between the two adjacent rows of pixel circuits and the same third-type signal line are equal or approximately equal.

11. The display substrate according to claim 9, wherein: The plurality of third-category signal lines include: a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines.

12. The display substrate according to claim 9, wherein: The plurality of signal lines further include: a plurality of second connecting lines; the second connecting lines extend along the first direction; and one second connecting line is connected to one of the third type signal lines.

13. The display substrate according to claim 9, wherein: The plurality of signal lines further include: a plurality of second connecting lines; the second connecting lines extend along the first direction; The second connecting line includes: at least one break and a plurality of sub-lines; The break is directly opposite to the first opening, and the size of the break along the first direction is greater than or equal to the size of the first opening along the first direction; the plurality of sub-lines are respectively located on opposite sides of each break; and one sub-line is connected to one of the third-category signal lines.

14. The display substrate according to claim 12, wherein: The plurality of signal lines further include: a plurality of data signal lines; the second connecting line is located between two adjacent data signal lines.

15. The display substrate according to claim 1, wherein The display substrate comprises: a first source-drain conductive layer and a second source-drain conductive layer stacked on one side of the substrate; The display substrate further includes: a plurality of second-type fan-out lines and a plurality of data signal lines; Among them, a plurality of the second-type fan-out lines are located in the first source-drain conductive layer; a plurality of the first-type signal lines, a plurality of the first-type fan-out lines, and a plurality of the data signal lines are located in the second source-drain conductive layer.

16. The display substrate according to claim 15, wherein: The display substrate further comprises: a first gate conductive layer and a second gate conductive layer stacked between the substrate and the first source-drain conductive layer; the first gate conductive layer is located between the substrate and the second gate conductive layer; The display substrate further comprises: a plurality of first connecting lines, a plurality of second connecting lines, and a plurality of third-type signal lines; the plurality of third-type signal lines comprises: a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of third initial signal lines; Wherein, a plurality of the second connecting lines are located in the second source-drain conductive layer; A plurality of the first initial signal lines are located in the first source-drain conductive layer; A plurality of the second initial signal lines and a plurality of the first connection lines are located in the first gate conductive layer; and a plurality of the third initial signal lines are located in the second gate conductive layer.

17. The display substrate according to claim 1, further comprising: A plurality of filter parts; the light shielding layer further comprises a plurality of second openings; the plurality of second openings are located in the main display area; One of the filter parts is located in one of the second openings.

18. The display substrate according to any one of claims 1 to 17, further comprising: a plurality of light-emitting devices, located on a side of the plurality of signal lines away from the substrate; The encapsulation layer is arranged between the light shielding layer and the plurality of light emitting devices.

19. A display device comprising the display substrate according to any one of claims 1 to 18; and an optical element, which is located on the non-light-emitting side of the display substrate and in the auxiliary display area of the display substrate.

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