Process for fabricating a semiconductor device containing purified silicon-28 and device thus obtained

Abstract

Disclosed is a process for fabricating a semiconductor device, the process comprising, starting with an initial SOI structure, SOI being the acronym of silicon-on-insulator, the initial SOI structure comprising a silicon substrate (2), a layer of buried oxide (4), abbreviated BOX, and a first upper layer (6) of silicon on the layer of buried oxide (4), forming by epitaxy a first epitaxial layer (8) of the isotope of silicon Si28 on the first upper layer (6), a homogenizing anneal via which the first epitaxial layer (8) of the isotope of silicon Si28 and the first upper layer (6) of silicon then form a second upper layer with a lower concentration of the isotope Si29 than initially, and thinning the second upper layer.

Description

[0001] METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

[0002] SILICON 28 SO PURIFYING AND DEVICE THUS OBTAINED

[0003] Technical field

[0004] The invention relates to the field of semiconductor devices, and more specifically relates to a method of manufacturing a semiconductor device having an upper layer of silicon in isotope 28 If with very little isotope 29 If, particularly advantageous for producing spin qubits with silicon technology. The invention also relates to a device obtained by said method.

[0005] Technological background

[0006] Standard silicon natively contains the 14- and 15-neutron isotopes, noted respectively 28 If and 29 Yes. Thus, the silicon commonly used in electronics contains nearly 4% of the isotope 29Yes. However, for certain applications, it is desirable to have a silicon layer with a very low concentration of 29 Yes. This is particularly the case for producing devices with spin qubits in silicon technology, where it is desirable to have a silicon layer housing the qubits that is as pure as possible. 28 Yes, in order to avoid rapid decoherence of the qubits.

[0007] If it is known to grow pure layers of silicon of isotope by epitaxy 28 Yes, a problem arises when it is desired to have a pure layer of silicon isotope 28 If on a silicon-on-insulator (SOI) substrate. Such an SOI substrate comprises a silicon substrate, a buried oxide layer (BOX) on the silicon substrate, and a first top layer of silicon on the buried oxide layer.

[0008] The formation of pure isotope silicon layers 28 If is very expensive, because the purified precursor gas contains only the isotope 28 Si is very expensive. It is therefore not economically feasible to manufacture a completely pure SOI substrate from isotope silicon 28 Si. The first top layer of silicon and / or the buried oxide layer therefore generally also contain isotope silicon 29 If.

[0009] A pure layer of isotope silicon 28 If carried out on the first upper layer of silicon it is polluted by isotopes 29 If migrating from the first upper silicon layer and / or the buried oxide layer, since these layers contain them, in particular during the later stages of manufacturing the semiconductor device, such as for example the production of transistors, which generally involve high temperatures likely to cause the isotopes to migrate 29Yes. The performance of the qubits in this layer of silicon is therefore not optimal.

[0010] Presentation of the invention

[0011] The invention therefore aims to propose a method making it possible to obtain at low cost a semiconductor device having an upper layer of silicon with a very low concentration of isotope. 29 If.

[0012] To this end, the invention provides a method for manufacturing a semiconductor device, the method comprising, starting from an initial silicon-on-insulator, SOI, structure comprising a silicon substrate, a buried oxide layer, BOX, and a first upper silicon layer on the buried oxide layer, the first upper silicon layer having a first concentration of the isotope 28 If and a first concentration of the isotope 29 If: a) the formation by epitaxy of a first epitaxial layer of silicon of isotope 28If on the first upper layer (6) of silicon, the first upper layer of silicon having a first thickness and the first epitaxially grown silicon layer of isotope 28 If having a second thickness; b) a first homogenization annealing, the first epitaxial layer of isotope silicon 28 If and the first upper layer of silicon then forming a second upper layer of silicon with a second concentration of the isotope 28 If greater than the first concentration of the isotope 28 Yes, and a second concentration of the isotope 29 If lower than the first concentration of the isotope 29 If; c) a thinning of the second upper layer to a third thickness.

[0013] The process is advantageously supplemented by the following different characteristics taken alone or according to their different possible combinations:

[0014] - the first thickness is less than the third thickness;

[0015] - the first thickness is less than 5 nm, and preferably less than or equal to 3 nm;

[0016] - the second thickness is greater than 50 nm, and preferably greater than 100 nm;

[0017] - the third thickness is between 12 nm and 25 nm.

[0018] Advantageously, the method may comprise, following the thinning of the second upper layer: d) the formation by epitaxy of a second epitaxial layer of isotope silicon 28 If on the second top layer of silicon thinned to the third thickness, the second epitaxial layer of silicon of isotope 28 If having a fourth thickness; e) a second homogenization annealing, the second epitaxial layer of isotope silicon 28If and the second top layer of silicon thinned to the third thickness (T3) then forming a third top layer of silicon with a third concentration of the isotope 28 If greater than the second concentration of the isotope 28 Yes, and a third concentration of the isotope 29 If less than the second concentration of the isotope 29 If.

[0019] In this case, preferably the third thickness is less than or equal to 6 nm. Also preferably, the second thickness and the fourth thickness are greater than 20 nm. Preferably, the second thickness and / or the fourth thickness are less than 60 nm, and more preferably less than 50 nm.

[0020] In all cases, the process can advantageously be supplemented by the following different characteristics taken alone or according to their different possible combinations:

[0021] - the formation by epitaxy of a first epitaxial layer of isotope silicon 28 If and the epitaxial formation of a second epitaxial layer of isotope silicon 28 If they are carried out from a purified precursor gas containing only the isotope 28 If ;

[0022] - the steps of the method are implemented for a first area of ​​a surface of the semiconductor device, and not implemented for a second area of ​​the surface of the semiconductor device, the method subsequently comprising the formation of transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits;

[0023] - the first zone has a thickness at least 2 nm greater than the thickness of the second zone;

[0024] - the method may subsequently comprise the creation of isolation trenches, and the filling of isolation trenches using a purified precursor gas containing only the isotope 28 If ;

[0025] - the method may comprise a subsequent step of localized bombardment of a surface of the structure with argon to standardize the thickness of the third layer of silicon;

[0026] - the method may comprise a prior step of thinning the first upper layer of silicon to the first thickness.

[0027] Another object of the invention relates to a device obtained by the method described above. Said device comprises a silicon substrate, a buried oxide layer, BOX, and an upper layer of silicon on the buried oxide layer. Presentation of the figures

[0028] Other characteristics, aims and advantages of the invention will emerge from the following description, which is purely illustrative and non-limiting, and which must be read in conjunction with the appended drawings in which:

[0029] - figure 1 illustrates an initial silicon-on-insulator structure, according to a possible embodiment of the invention;

[0030] - figure 2 illustrates the structure after thinning of the first upper silicon layer, according to a possible embodiment of the invention;

[0031] - Figure 3 illustrates the structure after epitaxial formation of a first layer of isotope silicon 28 If, according to a possible embodiment of the invention;

[0032] - figure 4 illustrates the structure after the first homogenization annealing, according to a possible embodiment of the invention;

[0033] - figure 5 illustrates the structure after thinning of the second upper layer of silicon, according to a possible embodiment of the invention;

[0034] - Figure 6 illustrates the structure after epitaxial formation of a second layer of isotope silicon 28 If, according to a possible embodiment of the invention;

[0035] - figure 7 illustrates the structure after a second homogenization annealing, according to a possible embodiment of the invention;

[0036] - Figure 8 illustrates the structure after the formation of isolation trenches, according to a possible embodiment of the invention.

[0037] Detailed description

[0038] With reference to Figure 1, the method for manufacturing a semiconductor device is implemented from an initial structure 1 of silicon on insulator, SOI, comprising a silicon substrate 2, a buried oxide layer 4, BOX, and a first upper layer 6 of silicon on the buried oxide layer, the first upper layer 6 of silicon having a first concentration Ci, 28 of the isotope 28 If and a first concentration Ci, 29 of the isotope 29 If. The silicon in the initial structure 1 is standard, that is, it has not been substantially purified of its isotopes 29 If. Typically, the first concentration Ci, 28 of the isotope 28 Si is between 92% and 93%, while the first concentration Ci, 29 of the isotope 29 If is between 4% and 5%. Of the isotope 30Si is also typically present at about 3%, but has no significant consequences, and will not be discussed further, although the process results in an elimination of this isotope 30 If in the same way as the isotope 29 Yes. For non-limiting demonstration purposes, the values ​​of 96% for Ci, 28 and 4% for Ci, 29 are retained. In this text, the concentrations indicated are molar concentrations.

[0039] The initial silicon-on-insulator structure 1 is preferably an FDSOI structure, from the English “fully depleted silicon-on-insulator” where at least the first upper layer 6 is completely depleted. The buried oxide layer 4 is typically made of silicon oxide.

[0040] If the first upper layer 6 of silicon is not thin enough, and for example if it is thicker than a first thickness less than or equal to 5 nm, the method may comprise a prior step of thinning the first upper layer 6 of silicon to a first thickness Ti less than or equal to 5 nm, and preferably less than or equal to 4 nm, and preferably less than or equal to 3 nm. For demonstration purposes for the following examples, 3 nm is chosen as the first thickness Ti. The thinning may for example be carried out by oxidation in a furnace, followed by an etching, for example chemical, in particular using a hydrofluoric acid (HF), known as “HF wet etching”, or by a so-called dry etching, for example using a plasma. Figure 2 shows the structure with the first upper layer 6 of silicon at the first thickness Ti.

[0041] The method comprises epitaxially forming a first epitaxial layer 8 of isotope silicon 28 If on the first upper layer 6 of silicon, the first epitaxial layer 8 of isotope silicon 28 If having a second thickness T2. Preferably, the second thickness T2 is greater than or equal to 15 nm, and more preferably greater than or equal to 20 nm. The epitaxy can be carried out from a purified precursor gas containing only the isotope 28 Yes, that is, at least 99.9% isotope 28 If. For example, from a SiF4 gas, sorting according to mass allows only the 28 SiF4. Chloride compounds then make it possible to obtain the silicon isotope atom 28 If. We then obtain, as illustrated in Figure 3, a first epitaxial layer 8 of silicon of isotope 28If on the first upper layer 6 of silicon, with therefore a thickness above the buried oxide layer 4 corresponding to the sum of the first thickness Ti and the second thickness T2.

[0042] The process then includes a first homogenization thermal annealing, aimed at homogenizing the isotope concentrations 28 If and 29 If between the first epitaxial layer 8 of silicon and the first upper layer 6 of silicon, which then form a second upper layer 10 of silicon, as illustrated in Figure 4. The second upper layer 10 of silicon has a second concentration €2.28 of the isotope 28 If greater than the first concentration Ci, 28 of the isotope 28 If, and a second concentration 62.29 of the isotope 29 If less than the first concentration Ci, 29 of the isotope 29Yes. During the first homogenization thermal annealing, heating structure 1 allows the isotopes 29 If to migrate from the first upper layer 6 of silicon to the first epitaxial layer 8 of silicon. For example, the homogenization thermal annealing can be carried out at a temperature of at least 1000°C for at least 20 minutes, and preferably at least 1050°C for at least 30 minutes. It is however possible to modify the temperature and duration of the thermal annealing as long as the thermal budget allows the isotopes to migrate sufficiently 29 If towards the upper part of the second upper layer 10. It is for example possible to refer to the article by V. Mazzocchi et al. “99.992% 28Si CVD-grown epilayer on 300 nm substrates for large scale integration of silicon spin qubiis". Journal of Crystal Growth 509 (2019) 1-7, for information on both epitaxial growth and homogenization thermal annealing in this context.

[0043] The second concentration €2.29 of the isotope 29 If depends on the first thickness Ti and the second thickness T2, as well as on the first concentration Ci, 29 of the isotope 29 If: ri ^2.29 — .29 X TT

[0044] "T 2

[0045] Taking Ci, 29 = 4%, Ti = 3 nm, and T2 = 30 nm, we obtain C2, 29 = 0.36%, or a division by 10 of the isotope concentration 29 If in the second upper layer 10 of silicon compared to the first upper layer 6 of silicon, i.e. compared to standard silicon. It is however possible that some isotopes 29Si migrate from the buried oxide layer 4 to the second upper layer 10 of silicon during homogenization thermal annealing. This effect, however, does not call into question the substantial decrease in the second concentration C2.29 of the isotope 29 If compared to the first concentration Ci, 29 of the isotope 29 Yes, and it is possible to limit this effect by limiting the thermal budget of the first homogenization thermal annealing.

[0046] The method then comprises thinning the second upper layer 10 to a third thickness T3, as illustrated in Figure 5. The same methods as for the optional thinning of the first upper layer 6 can be used. Preferably, the third thickness T3 is less than or equal to 6 nm, and more preferably less than or equal to 4 nm. The third thickness T3 can however be greater than the first thickness Ti.

[0047] The method then comprises epitaxially forming a second epitaxial layer 12 of isotope silicon 28 If on the second upper layer 10 of silicon thinned to the third thickness T3, the second epitaxial layer 12 of silicon of isotope 28 If having a fourth thickness T4. Preferably, the fourth thickness T4 is greater than or equal to 15 nm, and more preferably greater than or equal to 20 nm. We then obtain, as illustrated in Figure 6, a second epitaxial layer 12 of silicon of isotope 28 If on the second upper layer 10 of silicon, with therefore a thickness above the buried oxide layer corresponding to the sum of the third thickness T3 and the fourth thickness T4.

[0048] The process then includes a second homogenization annealing, aimed at homogenizing the isotope concentrations 28 If and 29If between the second epitaxial layer 12 of silicon and the second upper layer 10 of silicon, which then form a third upper layer 14 of silicon, as illustrated in Figure 7.

[0049] The third upper layer 14 of silicon has a third concentration €3.28 of the isotope 28 If greater than the second concentration €2.28 of the isotope 28 Yes, and a third concentration €3.29 of the isotope 29 If less than the second concentration €2.29 of the isotope 29 Yes. As in the first homogenization thermal annealing, heating the structure allows the isotopes 29If to migrate from the second upper layer 10 of silicon to the second epitaxial layer 12 of silicon. For example, the homogenization thermal annealing can be carried out at a temperature of at least 1000°C for at least 20 minutes, and preferably at least 1050°C for at least 30 minutes. It is however possible to modify the temperature and duration of the thermal annealing as long as the thermal budget allows the isotopes to migrate sufficiently 29 If towards the top of the third upper layer.

[0050] The third concentration €3.29 of the isotope 29 If depends on the third thickness T3 and the fourth thickness T3, as well as the second concentration 62.29 of the isotope 29 If : which can also be expressed as a function of the first concentration Ci, 29 of the isotope 29 If :

[0051] T T3

[0052] C33.2299 = 1.2299 X 7 - + —T ^ X - T ^ - + —

[0053] Taking Ci, 29 = 4%, Ti = 3 nm, T2 = 30 nm, T3 = 5 nm and T4 = 25 nm, we obtain C3, 29 = 0.06%, i.e. a division by more than 50 of the isotope concentration 29 If in the third upper layer 14 of silicon compared to the first upper layer 6 of silicon, that is, compared to standard silicon. A possible migration of isotopes 29 If from the buried oxide layer 4 to the third upper layer 14 of silicon during the second homogenization thermal annealing can take place, but even less pronounced than before, because the isotope concentration 29If the buried oxide layer 4 decreases with each migration. It is also possible to limit this effect by limiting the thermal budget of the second homogenization thermal annealing. In all cases, it is possible to obtain a third upper layer 14 of silicon comprising less than 0.1% of isotope 29 If.

[0054] A semiconductor device is then obtained comprising an upper layer 14 of silicon on the buried oxide layer 4 which is practically free of isotope. 29 Yes, with only two iterations of thinning-epitaxy-thermal annealing. The process is therefore very economical because it typically requires only between 30 nm and 80 nm of epitaxial growth using an expensive precursor gas consisting only of isotopes 28Yes. It is possible to increase the purity obtained by repeating a thinning and epitaxy cycle as described, and / or by further thinning the upper silicon layers 6, 10 during their thinning, and / or by increasing the thickness of the epitaxial layers 8, 12. It is sufficient to reduce the thickness of the epitaxial layers 8, 12 to reduce the costs, possibly to the detriment of the degree of purity obtained.

[0055] These thinning-epitaxy-thermal annealing cycles may have the disadvantage of deteriorating the thickness uniformity of the final upper silicon layer 14, intended to be the active layer of the semiconductor device. However, small thickness variations are acceptable for forming qubits in the semiconductor device since the qubits are generally formed in a thicker channel (for example between 10 and 15 nm) than for a channel of a conventional transistor, the thickness of which is of the order of 7 to 10 nm. If it is desired to improve the thickness homogeneity of the final upper silicon layer 14 which is above the buried oxide layer 4, it is possible to carry out a shaving, or "trimming" in English, for example by bombarding the upper silicon layer with argon.

[0056] The process can be implemented on an entire wafer, or only on the areas intended to house qubits, in order to reduce the consumption of precursor gas. 28So pure. Furthermore, not implementing the method on certain areas allows the thinner and more uniform thickness of the upper silicon layer to be maintained in the areas intended to form the transistors, and to have a greater thickness in the purified areas intended for the qubits. Thus, preferably, the steps of the method are implemented for a first area of ​​a surface of the semiconductor device, and not implemented for a second area of ​​the surface of the semiconductor device, the method subsequently comprising the formation of transistors on the second area of ​​the surface of the semiconductor device, the first area of ​​the surface being configured to house qubits. Preferably, the first area has a thickness greater than the thickness of the second area by at least 2 nm, and more preferably by at least 4 nm, compared to the thickness of the second area.For example, it is possible to use a silicon nitride mask on the second area of ​​the surface of the semiconductor device during the implementation of the described method steps.

[0057] As mentioned above, subsequent manufacturing steps, for example to produce transistors, may involve a rise in temperature of the semiconductor device, promoting the diffusion of isotopes 29 If in the final upper layer 14 from which they were practically absent. In order to limit this diffusion, it is possible to carry out, following the method described, the creation of isolation trenches 16, or STI from the English "shallow trench isolation", and the filling of the isolation trenches 16 using a purified precursor gas containing only the isotope 28 If, as shown in Figure 8. Thus, the isolation trenches 16 are devoid of isotopes 29If and these cannot therefore migrate to the final upper layer 14 of silicon purified by the described process steps. Advantageously, these are at least the isolation trenches 16 near the locations intended to house qubits. Such isolation trenches 16 pass through at least the upper layer 14, typically also the buried oxide layer 4, and generally reach the substrate 2. It is however possible to provide isolation trenches 16 with lesser depths.

[0058] It is also possible, using the same methods unless otherwise specified, to carry out only one cycle of formation by epitaxy of a first epitaxial layer 8 of a second thickness T2 then first homogenization annealing, and thinning of the second upper layer 10 to the third thickness T3. In this case, the second thickness T2 is preferably greater than or equal to 50 nm, and more preferably greater than 100 nm. As previously, the second concentration C2.29 of the isotope 29 If depends on the first thickness Ti and the second thickness T2, as well as on the first concentration Ci, 29 of T isotope 29 If :

[0059] Taking Ci, 29 = 4%, Ti = 3 nm, and Ï2 = 60 nm, we obtain C2, 29 = 0.48%, i.e. a division by more than 8 of the isotope concentration 29If in the second upper layer 10 of silicon compared to the first upper layer 6 of silicon, that is, compared to standard silicon. The greater the second thickness T2, the greater the purification will be, but the cost may be higher than in multi-cycle variants, which consume less epitaxial layer thickness.

[0060] Typically, the thinning reduces the second upper layer 10 by at least 30 nm, and preferably by at least 45 nm. The third thickness T3 is thicker, since the thinning of the second upper layer is not followed by epitaxial formation of a second epitaxial layer 12. Preferably, the third thickness T3 is between 12 nm and 25 nm.

[0061] The invention is not limited to the embodiment described and shown in the attached figures. Modifications remain possible, in particular from the point of view of the constitution of the various technical characteristics or by substitution of technical equivalents, without departing from the scope of protection of the invention, which is defined by the claims below.

Claims

Claims 1. A method of manufacturing a semiconductor device, the method comprising, starting from an initial silicon-on-insulator, SOI, structure (1), comprising a silicon substrate (2), a buried oxide layer (4), BOX, and a first upper layer (6) of silicon on the buried oxide layer (4), the first upper layer (6) of silicon having a first concentration of the isotope 28 If and a first concentration of the isotope 29 If: a) the formation by epitaxy of a first epitaxial layer (8) of isotope silicon 28 If on the first upper layer (6) of silicon, the first upper layer (6) of silicon having a first thickness (Ti) and the first epitaxial silicon layer (8) of isotope 28 If having a second thickness (T2); b) a first homogenization annealing, the first epitaxial layer (8) of isotope silicon 28If and the first upper layer (6) of silicon then forming a second upper layer (10) of silicon with a second concentration of the isotope 28 If greater than the first concentration of the isotope 28 Yes, and a second concentration of the isotope 29 If lower than the first concentration of the isotope 29 If; c) thinning the second upper layer (10) to a third thickness (T3).

2. Method according to claim 1, wherein the first thickness (Ti) is less than the third thickness (T3).

3. Method according to any one of the preceding claims, in which the first thickness (Ti) is less than 5 nm, and preferably less than or equal to 3 nm.

4. Method according to one of the preceding claims, in which the second thickness (T2) is greater than 50 nm, and preferably greater than 100 nm.

5. Method according to one of the preceding claims, in which the third thickness (T3) is between 12 nm and 25 nm.

6. Method according to one of claims 1 to 3, comprising following the thinning of the second upper layer (10): d) the formation by epitaxy of a second epitaxial layer (12) of isotope silicon 28 If on the second upper layer (10) of silicon thinned to the third thickness (T3), the second epitaxial layer (12) of isotope silicon 28 If having a fourth thickness (T4); e) a second homogenization annealing, the second epitaxial layer (12) of isotope silicon 28 If and the second upper layer (10) of silicon thinned to the third thickness (T3) then forming a third upper layer (14) of silicon with a third concentration of the isotope 28 If greater than the second concentration of the isotope 28Yes, and a third concentration of the isotope 29 If less than the second concentration of the isotope 29 If.

7. Method according to claim 6, in which the third thickness (T3) is less than or equal to 6 nm.

8. Method according to any one of claims 6 to 7, in which the second thickness (T2) and the fourth thickness (T4) are greater than 20 nm.

9. A method according to any one of the preceding claims, wherein the epitaxial formation of a first epitaxial layer (8) of isotope silicon 28 If and the epitaxial formation of a second epitaxial layer (12) of isotope silicon 28 If they are carried out from a purified precursor gas containing only the isotope 28 If.

10. A method according to any preceding claim, wherein the method steps are performed for a first area of a surface of the semiconductor device, and not performed for a second area of the surface of the semiconductor device, the method subsequently comprising forming transistors on the second area of the surface of the semiconductor device, the first area of the surface being configured to house qubits.

11. Method according to the preceding claim, in which the first zone has a thickness at least 2 nm greater than the thickness of the second zone.

12. A method according to any preceding claim, further comprising providing isolation trenches (16), and filling the isolation trenches (16) using a purified precursor gas containing only the isotope 28If.

13. Method according to any one of the preceding claims, comprising a subsequent step of localized bombardment of a surface of the structure with argon to uniformize the thickness of the third layer (14) of silicon.

14. Method according to any one of the preceding claims, comprising a prior step of thinning the first upper layer (6) of silicon to the first thickness (Ti).

15. Semiconductor device comprising a silicon substrate (2), a buried oxide layer (4), BOX, and an upper layer (10, 14) of silicon on the buried oxide layer (4), obtained by the method according to one of claims 1 to 14.

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