Linear motor drive device

Abstract

This linear motor drive device comprises: a power conversion circuit (2) having a plurality of inverters (IVa) of a first group (G4a) connected to one end of a stator winding (1a) of a first group (G1a) and a plurality of inverters (IVb) of a second group (G4b) connected to one end of a stator winding (1b) of a second group (G1b); and a control circuit (220) that generates a first carrier signal (Cwa) having a cycle determined for PWM control of the plurality of inverters (IVa) of the first group (G4a) and generates a second carrier signal (Cwb) having a cycle for PWM control of the plurality of inverters (IVb) of the second group (G4b). The difference between the phase of the first carrier signal (Cwa) and the phase of the second carrier signal (Cwb) is half of the cycle or an odd multiple of half of the cycle.

Description

Linear motor drive unit

[0001] The present disclosure relates to a linear motor drive device.

[0002] In general, when controlling an inverter in a motor drive device, the inverter's switching operation is a source of electrical noise. In particular, stray capacitance inevitably generated between the motor's stator winding and its metal housing creates a potential difference between the housing and the ground, generating common-mode noise. Furthermore, in a typical motor drive device configuration, common-mode noise propagates to the power grid via a power cable connected to the housing. This conductive noise can adversely affect other electronic devices sharing the same power supply. One known technique for suppressing this conductive noise is to control the phase of a carrier signal in a motor drive device that includes multiple motors, such as multi-axis motors, and multiple inverters, thereby canceling out the noise generated by inverter operation.

[0003] In order to suppress noise, the device of Patent Document 1 generates N vector quantities based on the magnitude of the noise current generated by each motor and the phase angle of the carrier signal used to control the drive of the inverter corresponding to each motor in a configuration including N motors and N inverters, and determines the phase angle of each carrier signal so that the sum of these N vector quantities is zero.

[0004] Japanese Patent Application Laid-Open No. 2022-137360

[0005] In some linear motor drive devices with multiple stator windings, the number of switching elements in the power conversion circuit is reduced to reduce costs. Typically, linear motors with multiple stator windings are configured with one single-phase inverter for each electrically isolated stator winding. However, by electrically connecting adjacent stator windings, it is possible to reduce the number of required switching elements by approximately half. In linear motor drive devices employing such a configuration, the electrical connection between adjacent stator windings makes it difficult to directly apply noise suppression techniques such as those described in Patent Document 1. For example, operating switching elements connected to both ends of a single stator winding in opposite phases can result in instantaneous current flow at unintended times from the perspective of current control. This results in increased current ripple. This can lead to concerns about poor controllability and efficiency, increased noise, and other issues.

[0006] Therefore, an object of the present disclosure is to provide a linear motor drive device that can suppress noise.

[0007] A linear motor drive device according to the present disclosure includes a plurality of stator windings arranged in series and at least one housing for accommodating the plurality of stator windings, the plurality of stator windings including a first group of stator windings and a second group of stator windings, wherein two adjacent stator windings belonging to the same group are electrically connected and two adjacent stator windings belonging to different groups are electrically insulated. The linear motor drive device further includes a power conversion circuit having a first group of inverters connected to one ends of the stator windings of the first group and a second group of inverters connected to one ends of the stator windings of the second group, and a control circuit that generates a first carrier signal having a predetermined period for PWM control of the first group of inverters and a second carrier signal having a predetermined period for PWM control of the second group of inverters. The difference in phase between the first carrier signal and the second carrier signal is half the period or an odd multiple of half the period.

[0008] According to the present disclosure, noise can be suppressed.

[0009] 1 is a diagram showing a linear motor drive device 600 and a portion of a linear motor driven by the linear motor drive device 600. FIG. 2 is a diagram showing a portion of a drive unit 200 and a stator winding unit 10. FIG. 3 is a diagram showing the internal configuration of the drive unit 200. FIG. 4 is a diagram for explaining the effects of embodiment 1. FIG. 5 is a diagram showing the configuration of a phase control circuit 8A of embodiment 2. FIG. 6 is a diagram showing an example of a first carrier signal Cwa and a second carrier signal Cwb. FIG. 7 is a diagram showing another example of a first carrier signal Cwa and a second carrier signal Cwb. FIG. 8 is a diagram showing the configuration of a phase control circuit 8B of embodiment 3. FIG. 9 is a diagram showing the configuration of a phase control circuit 8C of a modified example of embodiment 3.

[0010] Hereinafter, embodiments will be described with reference to the drawings. Embodiment 1 Fig. 1 is a diagram showing a linear motor drive device 600 and a part of a linear motor driven by the linear motor drive device 600.

[0011] The linear motor driving device 600 includes a higher-level device 300, a plurality of driving units 200, and a plurality of stator winding units 10. The stator winding units 10 include a plurality of stator windings.

[0012] The mover 400 includes a permanent magnet. The mover 400 moves on the guide rail 500 due to the electromagnetic force generated by the stator winding. By connecting a plurality of stator winding units 10 and drive units 200, the movement state of the plurality of movers 400 can be managed by the host device 300. This allows the trajectories of the plurality of movers 400 to be freely controlled.

[0013] 2 is a diagram showing a part of the drive unit 200 and the stator winding unit 10. The drive unit 200 includes a power conversion circuit 2.

[0014] The stator winding unit 10 includes a first group of stator windings G1a and a second group of stator windings G1b.

[0015] The first group of stator windings G1a includes stator windings 1a(1) to 1a(M). The second group of stator windings G1b includes stator windings 1b(1) to 1b(L). M + L = N. In the following description, the stator windings 1a(1) to 1a(M) may be collectively referred to as stator winding 1a, the stator windings 1b(1) to 1b(L) may be collectively referred to as stator winding 1b, and the stator windings 1a(1) to 1a(M) and 1b(1) to 1b(L) may be collectively referred to as stator winding 1.

[0016] It is desirable that the number of stator windings 1 included in each group be as equal as possible (M = L), but if N is an odd number, an effect similar to that when N is an even number can be obtained by dividing the groups so that one group has one more stator winding than the other group.

[0017] Stator windings 1 belonging to the same group are electrically and magnetically coupled to adjacent stator windings 1. Magnetic coupling refers to coupling due to mutual inductance between windings. Electrical connection refers to a state in which the windings themselves are physically connected. Stator windings in different groups are electrically insulated, but magnetic coupling is acceptable.

[0018] The second end (right end) of the stator winding 1a(i) and the first end (left end) of the stator winding 1a(i+1) are electrically and magnetically connected, where i = 1 to M-1. The second end of the stator winding 1b(j) and the first end of the stator winding 1b(j+1) are electrically and magnetically connected, where j = 1 to L-1. The second end (right end) of the stator winding 1a(M) and the first end (left end) of the stator winding 1b(1) are electrically insulated, but may be magnetically coupled.

[0019] The stator winding 1 is housed in a housing 100. The stator winding 1 does not need to be completely covered by the housing 100, and may have a partially open structure.

[0020] The power conversion circuit 2 includes a first group of inverters G4a and a second group of inverters G4b. The first group of inverters G4a includes inverters IVa(1) to IVa(M+1). The second group of inverters G4b includes inverters IVb(1) to IVb(L+1). In the following description, inverters IVa(1) to IVa(M+1) will be collectively referred to as inverter IVa, inverters IVb(1) to IVb(L+1) will be collectively referred to as inverter IVb, and inverters IVa(1) to IVa(M+1) and inverters IVb(1) to IVb(L+1) will be collectively referred to as inverter IV.

[0021] Inverter IVa(i) includes a first switching element 4Ua(i) and a second switching element 4La(i) connected in series between positive electrode line 3a and negative electrode line 3b, where i = 1 to M+1. In the following description, switching elements 4Ua(1) to 4Ua(M+1) and 4La(1) to 4La(M+1) may be collectively referred to as a first group of switching elements 4a.

[0022] Inverter IVb(j) includes a first switching element 4Ub(j) and a second switching element 4Lb(j) connected in series between a positive electrode line 3a and a negative electrode line 3b, where j = 1 to L+1. In the following description, switching elements 4Ub(1) to 4Ub(L+1) and 4Lb(1) to 4Lb(L+1) may be collectively referred to as a second group of switching elements 4b.

[0023] In the following description, switching elements 4Ua(1) to 4Ua(M+1), 4La(1) to 4La(M+1), 4Ub(1) to 4Ub(L+1), and 4Lb(1) to 4Lb(L+1) may be collectively referred to as switching element 4.

[0024] The connection node between the first switching element 4Ua(i) and the second switching element 4La(i) is connected to node NDa(i), where i = 1 to M+1, and outputs voltage Va(i). Node NDa(i) is connected to a first end (left end) of stator winding 1a(i), where i = 1 to M. Node NDa(M+1) is connected to a second end (right end) of stator winding 1a(M).

[0025] The connection node between the first switching element 4Ub(j) and the second switching element 4Lb(j) is connected to node NDb(j), where j = 1 to L+1, and outputs voltage Vb(j). Node NDb(j) is connected to the first end (left end) of stator winding 1b(j), where j = 1 to L. Node NDb(L+1) is connected to the second end (right end) of stator winding 1b(L).

[0026] The switching element 4 may be an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET).

[0027] The power conversion circuit 2 is not housed in the housing 100 that houses the stator winding 1, but is mounted on a circuit board inside the drive unit 200. When a drive current supplied from the power conversion circuit 2 flows through the stator winding 1, an electromagnetic force is generated.

[0028] 3 is a diagram showing the internal configuration of drive unit 200. Drive unit 200 includes a control circuit 220 and a power conversion circuit 2. Control circuit 220 includes a motion control circuit 9, a phase control circuit 8, a first carrier signal generation circuit 7a, a second carrier signal generation circuit 7b, a first PWM (Pulse Width Modulation) signal generation circuit 5a, and a second PWM signal generation circuit 5b.

[0029] The first PWM signal generating circuit 5a generates a PWM signal for the first group of switching elements 4a. The first PWM signal generating circuit 5a includes (M+1) comparators 6a(1) to 6a(M+1).

[0030] Comparator 6a(i) generates PWM signal Pa(i) by comparing the voltage value of first carrier signal Cwa output from first carrier signal generation circuit 7a with the voltage value of command signal Cda(i) output from motion control circuit 9, where i = 1 to M+1.

[0031] The second PWM signal generating circuit 5b generates a PWM signal for the second group of switching elements 4b. The second PWM signal generating circuit 5b includes (L+1) comparators 6b(1) to 6b(L+1).

[0032] Comparator 6b(j) generates PWM signal Pb(j) by comparing the voltage value of second carrier signal Cwb output from second carrier signal generation circuit 7b with the voltage value of command signal Cdb(j) output from motion control circuit 9, where j=1 to L+1.

[0033] The first carrier signal generating circuit 7a supplies a first carrier signal Cwa to the first PWM signal generating circuit 5a. The second carrier signal generating circuit 7b supplies a second carrier signal Cwb to the second PWM signal generating circuit 5b. The first carrier signal Cwa and the second carrier signal Cwb are periodic electrical signals having a predetermined period (T), and may be triangular waves, for example. The first carrier signal generating circuit 7a starts outputting the first carrier signal Cwa upon receiving a first timing signal Tma from the phase control circuit 8. The second carrier signal generating circuit 7b starts outputting the second carrier signal Cwb upon receiving a second timing signal Tmb from the phase control circuit 8.

[0034] The phase control circuit 8 outputs a first timing signal Tma and a second timing signal Tmb to control the phase of the first carrier signal Cwa and the phase of the second carrier signal Cwb. The phase control circuit 8 adjusts the difference between the phase of the first carrier signal Cwa output from the first carrier signal generation circuit 7a and the phase of the second carrier signal Cwb output from the second carrier signal generation circuit 7b so that it becomes half (T / 2) of the period (T) of the first carrier signal Cwa and the second carrier signal Cwb, or an odd multiple (k×(T / 2)) of half the period (T), where k is an odd number (including negative numbers).

[0035] The motion control circuit 9 performs calculations based on commands from the higher-level device 300 to calculate drive currents for the stator windings 1a(1) to 1a(M) and 1b(1) to 1b(L). Based on the calculation results, the motion control circuit 9 outputs a command signal Cda(i) to the comparator 6a(i) and a command signal Cdb(j) to the comparator 6b(j), where i = 1 to M+1 and j = 1 to L+1.

[0036] In this embodiment, the motion control circuit 9 is assumed to be included inside the drive unit 200 and housed in the same housing as the power conversion circuit 2, but it does not necessarily have to be housed in the same housing.

[0037] The effects of the first embodiment will be described with reference to Figure 4. Generally, in a motor drive device in which multiple electric motors are housed in a housing and controlled by inverter operation, stray capacitances 2000a and 2000b inevitably occur between the stator winding 1 of the motor and the housing 100. Noise sources 3000a and 3000b, which are electrical noise generated mainly due to the switching operation of the inverter, flow into the housing 100 via the stray capacitances 2000a and 2000b and reach the system power supply via the earth wire 1000 or the shield of the power cable connected to the housing 100. This noise can adversely affect other electronic devices that share the same power supply, and it is therefore necessary to keep the amount of noise propagation within allowable values ​​defined by international standards, etc.

[0038] Therefore, in a system in which multiple stator windings are housed in a housing, as in this embodiment, by inverting the phase of the control signal of the inverter that supplies power to each stator winding, the phase of the noise current generated by the switching operation of the inverter is also inverted (4000a and 4000b in Figure 4), making it possible for the noises to cancel each other out.

[0039] According to the configuration of this embodiment, the first group of stator windings G1a and the second group of stator windings G1b are always driven by inverter operations of opposite phases, so that noises can be cancelled out by each other.

[0040] The reason for dividing the multiple stator windings into two groups in this embodiment is as follows. In the linear motor drive device targeted by this embodiment, it is desirable to adopt a structure in which adjacent stator windings are electrically connected in order to reduce the cost of the power conversion circuit. However, if conventional inverter operation phase inversion control is implemented in this configuration, a phenomenon occurs in which unnecessary current that is not involved in motor motion control flows. This phenomenon occurs when two pairs of adjacent switching elements operate in opposite phases, and is a problem specific to when adjacent stators are electrically coupled. There is a concern that this unnecessary current may, for example, adversely affect the efficiency or controllability of power conversion, or increase noise.

[0041] Therefore, in this embodiment, the stator windings inside the housing are divided into two groups, each driven by inverter operation in opposite phases. In this case, the stator windings in the same group are driven by inverter operation in the same phase, so the above-mentioned problem does not occur. Furthermore, because the stator windings in different groups are driven by inverter operation in opposite phases, the directions of the noise currents flowing from the stator windings of the first and second groups are also opposite in phase. Therefore, the net noise currents within one drive unit 200 are canceled out, making it possible to reduce the noise currents flowing to the outside.

[0042] As described in the first embodiment, the phase control circuit 8 may have any specific circuit configuration as long as it has the function of adjusting the phase difference between the carrier signals Cwa and Cwb output from the two carrier signal generation circuits 7a and 7b so that the phase difference is half the period (T) of the carrier signals Cwa and Cwb or an odd multiple thereof. In the second embodiment, an example of the circuit configuration of the phase control circuit 8 is shown.

[0043] 5 is a diagram showing the configuration of a phase control circuit 8A according to embodiment 2. The phase control circuit 8A includes a clock circuit 20, a first counter circuit 11-1, and a second counter circuit 11-2.

[0044] The clock circuit 20 does not need to be a dedicated one used only within the phase control circuit 8A, and may be a clock circuit used for other circuit functions as needed. The clock circuit 20 generates a synchronization signal CLK for synchronizing the operation of the first counter circuit 11-1 and the operation of the second counter circuit 11-2, and supplies this signal to the first counter circuit 11-1 and the second counter circuit 11-2.

[0045] The first counter circuit 11 - 1 and the second counter circuit 11 - 2 perform counting in synchronization with the synchronization signal CLK output from the clock circuit 20 .

[0046] For example, the first counter circuit 11-1 increments the first counter value CT1 by 1 when it detects a rising edge of the synchronization signal CLK. The second counter circuit 11-2 increments the second counter value CT2 by 1 when it detects a rising edge of the synchronization signal CLK. The first counter circuit 11-1 outputs a first timing signal Tma to the first carrier signal generation circuit 7a when the first counter value CT1 reaches a preset first count value TH1. The second counter circuit 11-2 outputs a second timing signal Tmb to the second carrier signal generation circuit 7b when the second counter value CT2 reaches a preset second count value TH2.

[0047] The synchronization signal CLK may be of any format as long as it is a periodic electrical signal, but is preferably a rectangular wave with a fixed period, etc. The first timing signal Tma and the second timing signal Tmb may also be of any format as long as they are electrical signals, but can be digital signals such as High (1) or Low (0).

[0048] The first counter circuit 11-1 and the second counter circuit 11-2 may be configured discretely using an integrated circuit such as a digital counter IC (Integrated Circuit), or may be configured on a programmable device such as an FPGA (Field Programmable Gate Array).

[0049] The first count value TH1 and the second count value TH2 are set so that the time difference between the timing at which the first counter circuit 11-1 outputs the first timing signal Tma and the timing at which the second counter circuit 11-2 outputs the second timing signal Tmb is half the period (T) of the first carrier signal Cwa and the second carrier signal Cwb, or an odd multiple (including negative odd numbers) of half the period (T). By adopting such a configuration, it is possible to drive different groups of stator windings with inverter operation of opposite phases.

[0050] FIG. 6 is a diagram showing an example of the first carrier signal Cwa and the second carrier signal Cwb.

[0051] The time difference between the timing when the first counter circuit 11-1 outputs the first timing signal Tma and the timing when the second counter circuit 11-2 outputs the second timing signal Tmb is T / 2, which makes it possible to set the phase difference between the first carrier signal Cwa and the second carrier signal Cwb to T / 2.

[0052] FIG. 7 is a diagram showing another example of the first carrier signal Cwa and the second carrier signal Cwb.

[0053] The time difference between the timing when the first counter circuit 11-1 outputs the first timing signal Tma and the timing when the second counter circuit 11-2 outputs the second timing signal Tmb is 3T / 2, which makes it possible to set the phase difference between the first carrier signal Cwa and the second carrier signal Cwb to 3T / 2.

[0054] According to this embodiment, the phase control circuit can be configured simply and easily. Since it is sufficient to provide two counter circuits and one clock circuit in one drive unit, implementation is easy.

[0055] Third Embodiment Fig. 8 is a diagram showing the configuration of a phase control circuit 8B according to a third embodiment.

[0056] The phase control circuit 8B includes a synchronization signal generation circuit 13 and a delay circuit 12. The synchronization signal generation circuit 13 generates a first timing signal Tma. The first timing signal Tma may take various forms as an electrical signal, for example, a digital signal that transitions from High (1) to Low (0) at a certain point in time. The synchronization signal generation circuit 13 outputs the first timing signal Tma to the first carrier signal generation circuit 7a as is, and also supplies it to the delay circuit 12.

[0057] The delay circuit 12 delays the first timing signal Tma output from the synchronization signal generation circuit 13 by half the period (T) of the first carrier signal Cwa and the second carrier signal Cwb or an odd multiple of half the period (T) to generate a second timing signal Tmb, which is output to the second carrier signal generation circuit 7b. The specific configuration of the delay circuit 12 is not important.

[0058] According to this embodiment, a phase control circuit can be configured simply and easily. Since it is sufficient to provide one synchronization signal generation circuit and one delay circuit in one drive unit, implementation is easy.

[0059] Modification of the Third Embodiment Fig. 9 is a diagram showing the configuration of a phase control circuit 8C according to a modification of the third embodiment.

[0060] The phase control circuit 8C includes a synchronization signal generation circuit 13C and a delay circuit 12C. The synchronization signal generation circuit 13C generates a second timing signal Tmb. The synchronization signal generation circuit 13C outputs the second timing signal Tmb directly to the second carrier signal generation circuit 7b and also supplies it to the delay circuit 12C.

[0061] The delay circuit 12C delays the second timing signal Tmm output from the synchronization signal generation circuit 13C by half the period (T) of the first carrier signal Cwa and the second carrier signal Cwb or an odd multiple of half the period (T) to generate a first timing signal Tma and output it to the first carrier signal generation circuit 7a.

[0062] In this modification, the stator windings of different groups can also be driven by inverters operating in opposite phases.

[0063] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0064] 1, 1a, 1b stator winding, 2 power conversion circuit, 3a positive pole line, 3b negative pole line, 4Ua, 4Ub, 4La, 4Lb switching element, 5a, 5b signal generation circuit, 6a, 6b comparator, 7a, 7b carrier signal generation circuit, 8, 8A, 8B, 8C phase control circuit, 9 motion control circuit, 10 stator winding unit, 11-1, 11-2 counter circuit, 12, 12C delay circuit, 13, 13C synchronization signal generation circuit, 20 clock circuit, 100 housing, 200 drive unit, 220 control circuit, 300 upper device, 400 mover, 500 guide rail, 600 linear motor drive device, 1000 earth wire, 2000a, 2000b stray capacitance, 3000a, 3000b Noise source, IVa, IVb inverter.

Claims

1. A linear motor drive device comprising: a plurality of stator windings arranged in series; and at least one housing for accommodating the plurality of stator windings, wherein the plurality of stator windings includes a first group of a plurality of stator windings and a second group of a plurality of stator windings, wherein two adjacent stator windings belonging to the same group are electrically connected and two adjacent stator windings belonging to different groups are electrically insulated; the linear motor drive device further comprises: a power conversion circuit having a first group of a plurality of inverters connected to one ends of the stator windings of the first group, and a second group of a plurality of inverters connected to one ends of the stator windings of the second group; a control circuit that generates a first carrier signal having a determined period for PWM control of the plurality of inverters in the first group, and generates a second carrier signal having the same period for PWM control of the plurality of inverters in the second group, wherein the difference in phase between the first carrier signal and the second carrier signal is half the period or an odd multiple of half the period.

2. The control circuit includes: a first PWM signal generating circuit that generates a first PWM signal to drive the first group of inverters; a second PWM signal generating circuit that generates a second PWM signal to drive the second group of inverters; a first carrier signal generating circuit that supplies the first carrier signal to the first PWM signal generating circuit; a second carrier signal generating circuit that supplies the second carrier signal to the second PWM signal generating circuit; and a phase control circuit that outputs a first timing signal to the first carrier signal generating circuit and a second timing signal to the second carrier signal generating circuit, wherein the first carrier signal generating circuit starts outputting the first carrier signal of the cycle upon receiving the first timing signal, and the second carrier signal generating circuit starts outputting the second carrier signal of the cycle upon receiving the second timing signal, 2. The linear motor drive device according to claim 1, wherein the phase control circuit outputs the first timing signal and the second timing signal so that the time difference between the timing at which the first timing signal is output and the timing at which the second timing signal is output is half the period or an odd multiple of half the period.

3. The linear motor drive device according to claim 2, wherein the phase control circuit includes: a clock circuit that outputs a periodic synchronization signal; a first counter circuit that counts a first counter value based on the synchronization signal; and a second counter circuit that counts a second counter value based on the synchronization signal; the first counter circuit outputs the first timing signal to the first carrier signal generation circuit when the first counter value reaches a first count value; and the second counter circuit outputs the second timing signal to the second carrier signal generation circuit when the second counter value reaches a second count value; and the first count value and the second count value are set so that the time difference between the timing at which the first counter circuit outputs the first timing signal and the timing at which the second counter circuit outputs the second timing signal is half the period or an odd multiple of half the period.

4. A linear motor drive device as described in claim 2, wherein the phase control circuit includes: a synchronization signal generation circuit that outputs the first timing signal to the first carrier signal generation circuit; and a delay circuit that outputs the second timing signal, which is the first timing signal delayed by a time equivalent to half the period or an odd multiple of half the period, to the second carrier signal generation circuit.

5. A linear motor drive device as described in claim 2, wherein the phase control circuit includes: a synchronization signal generation circuit that outputs the second timing signal to the first carrier signal generation circuit; and a delay circuit that outputs the first timing signal, which is the second timing signal delayed by a time equivalent to half the period or an odd multiple of half the period, to the first carrier signal generation circuit.

6. A linear motor drive device according to any one of claims 1 to 5, wherein the first group of multiple stator windings and the second group of multiple stator windings are housed in the same housing.

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