Multilayer ceramic capacitor

Abstract

The purpose of the present invention is to provide a multilayer ceramic capacitor that enables prevention and countermeasures for the occurrence of failed chips.　This multilayer ceramic capacitor 10 according to the present invention includes: a laminate 12 including a plurality of laminated dielectric layers 14, and having a first surface 12a and a second surface 12b facing each other in a lamination direction of the plurality of dielectric layers 14, a third surface 12c and a fourth surface 12d facing each other in a first direction orthogonal to the lamination direction, and a fifth surface 12e and a sixth surface 12f facing each other in a second direction orthogonal to the lamination direction and the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate. The laminate 12 has a side margin part 41 arranged on each side of the fifth surface 12e and the sixth surface 12f of the laminate 12, and a pattern part 50 is provided inside the side margin part 41.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] In recent years, there has been a demand for small, high-capacity multilayer ceramic capacitors. Such multilayer ceramic capacitors have, for example, a rectangular parallelepiped laminate formed by alternately laminating inner dielectric layers on which inner electrodes are printed and the inner electrodes, and then laminating outer ceramic layers on the top and bottom surfaces of the laminate. The laminate also has external electrodes formed on both end surfaces of the laminate.

[0003] Some of these multilayer ceramic capacitors have a dielectric layer called a side margin portion formed on the side surface of the laminate to prevent the internal electrodes from connecting to the external electrodes on the side surface of the laminate (see, for example, Patent Document 1).

[0004] A multilayer ceramic capacitor having such a side margin is formed by laminating ceramic green sheets each having a conductive film formed on its surface that becomes an internal electrode. Next, a mother laminate is formed, and the mother laminate is cut so that the conductive film is exposed on the side where no external electrodes are formed. This results in a chip that becomes a laminate portion. Then, a ceramic slurry that becomes a side margin portion is applied to the internal electrodes exposed on both sides of the cut chip that becomes the laminate portion, thereby obtaining a laminate chip.

[0005] Patent No. 6665438

[0006] The multilayer ceramic capacitor disclosed in Patent Document 1 has the following problem: When forming the side margins during the manufacturing of the laminate, foreign matter may get caught in the capacitor, resulting in defective chips.

[0007] To prevent and address the occurrence of defective chips, it is important to identify the timing of the occurrence of foreign matter. That is, in the mass production process of multilayer ceramic capacitors, the sequence of events leading up to the occurrence of foreign matter in the laminate is (1) foreign matter occurrence, (2) foreign matter adhesion, and (3) foreign matter ingress. By identifying the timing of (1) foreign matter occurrence, it becomes possible to prevent and address the occurrence of defective chips. However, with the current structure or manufacturing method of multilayer ceramic capacitors, it has been difficult to identify the timing of such foreign matter occurrence.

[0008] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that is capable of preventing and dealing with the occurrence of defective chips.

[0009] The multilayer ceramic capacitor according to the present invention comprises a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first surface and a second surface facing each other in the stacking direction of the plurality of dielectric layers, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, a first external electrode arranged on the third surface of the laminate, and a second external electrode arranged on the fourth surface of the laminate, the laminate having side margin portions arranged on each side of the fifth surface and sixth surface of the laminate, and a pattern portion provided inside the side margin portions.

[0010] In the multilayer ceramic capacitor according to the present invention, since a patterned portion is provided inside the side margin portion, for example, by changing the patterned portion for each lot, traceability within the lot can be provided, thereby making it possible to clarify the manufacturing timing of a chip that has failed due to a foreign object being trapped. Furthermore, since the lot can be identified by the patterned portion, it is possible to clarify changes in the rate of foreign object trapping before and after equipment trouble or dust generation during maintenance work.

[0011] According to the present invention, it is possible to obtain a multilayer ceramic capacitor that can prevent and address the occurrence of defective chips.

[0012] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

[0013] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1; FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1; and FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. An exploded perspective view of a main part showing the structure of a laminate of a multilayer ceramic capacitor according to an embodiment of the present invention; An exploded side view of a main part showing the structure of a laminate of a multilayer ceramic capacitor according to an embodiment of the present invention; A diagram illustrating one step of a method for manufacturing ....

[0014] The multilayer ceramic capacitor according to this embodiment will be described below.

[0015] 1. Multilayer Ceramic Capacitor An example of a multilayer ceramic capacitor according to an embodiment of the present invention will be described. FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 3 is a plan view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4.

[0016] The multilayer ceramic capacitor 10 has a laminate 12 and external electrodes 30. The laminate 12 is formed by alternately stacking a plurality of dielectric layers 14 and a plurality of internal electrode layers 16, and is composed of an internal layer portion 15a that exhibits capacitance, and first and second external layer portions 15b1 and 15b2 that are arranged to sandwich the internal layer portion 15a from above and below, as will be described later.

[0017] Hereinafter, the configuration of each of the laminate 12, the internal electrode layer 16, and the external electrode 30 will be described in that order.

[0018] (Laminate) The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrode layers 16 stacked together. The laminate 12 further includes a first surface 12a and a second surface 12b that face the stacking direction x of the plurality of dielectric layers 14, a third surface 12c and a fourth surface 12d that face the first direction y that is perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f that face the second direction z that is perpendicular to the stacking direction x and the first direction y. The first direction y is also defined as the L direction, which is the direction connecting the third surface 12c and the fourth surface 12d. The second direction z is also defined as the W direction, which is the direction connecting the fifth surface 12e and the sixth surface 12f. The stacking direction x is also defined as the T direction, which is the direction connecting the first surface 12a and the second surface 12b.

[0019] The laminate 12 has a rectangular parallelepiped shape. The "rectangular parallelepiped shape" includes a rectangular parallelepiped with rounded corners and ridges. Note that a corner refers to a portion where three adjacent faces of the laminate 12 intersect, and a ridge refers to a portion where two adjacent faces of the laminate 12 intersect. In other words, a "rectangular parallelepiped" member refers to any member having a first surface 12a and a second surface 12b, a third surface 12c and a fourth surface 12d, and a fifth surface 12e and a sixth surface 12f.

[0020] The first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the fifth surface 12e and the sixth surface 12f may have irregularities formed on part or all of them.

[0021] As shown in Figures 4 and 5, the laminate 12 has, in the stacking direction x connecting the first surface 12a and the second surface 12b, an inner layer portion 15a in which a plurality of internal electrode layers 16 face each other, a first outer layer portion 15b1 formed from a plurality of dielectric layers 14 located between the first surface 12a and the internal electrode layer 16 located closest to the first surface 12a, and a second outer layer portion 15b2 formed from a plurality of dielectric layers 14 located between the second surface 12b and the internal electrode layer 16 located closest to the second surface 12b.

[0022] The first outer layer portion 15b1 is located on the first surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the internal electrode layer 16 closest to the first surface 12a.

[0023] The second outer layer portion 15b2 is located on the second surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second surface 12b and the internal electrode layer 16 closest to the second surface 12b.

[0024] The region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the inner layer portion 15a.

[0025] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 200 to 1000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably, for example, approximately 0.3 μm to 1.0 μm.

[0026] The material of the dielectric layer 14 is preferably, but not limited to, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, CaZrO3, etc. as a main component as a dielectric material. Furthermore, depending on the desired properties of the laminate, a material containing an auxiliary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be added.

[0027] In this embodiment, the laminate 12 has the inner layer 15a, a portion of the first outer layer 15b1, and a portion of the second outer layer 15b2 constituting the laminate portion 40, and the side portion 22a, a portion of the first outer layer 15b1, and a portion of the second outer layer 15b2 constituting the side margin portion 41.

[0028] (Side Margin Portion) Fig. 7 is an exploded perspective view of a main part showing the structure of the laminate 12 of the multilayer ceramic capacitor 10 according to the embodiment of the present invention. Fig. 8 is an exploded side view of a main part showing the structure of the laminate 12 of the multilayer ceramic capacitor 10 according to the embodiment of the present invention.

[0029] As shown in FIGS. 7 and 8, the laminate 12 has a laminated portion 40 and side margin portions 41 that sandwich the laminated portion 40 from both sides in the second direction z.

[0030] The side margin portion 41 has a first side margin portion 41a and a second side margin portion 41b.

[0031] The first side margin 41a is disposed on the fifth surface 12e side of the laminate 12. The second side margin 41b is disposed on the sixth surface 12f side of the laminate 12.

[0032] As shown in Figure 5, the first side margin portion 41a constitutes, in the laminate 12, a side portion 22a located on the fifth surface 12e side, a portion of the first outer layer portion 15b1 located directly above the side portion 22a, and a portion of the second outer layer portion 15b2 located directly below the side portion 22a.

[0033] As shown in Figure 5, the second side margin portion 41b constitutes, in the laminate 12, the side portion 22a located on the sixth surface 12f side, a portion of the first outer layer portion 15b1 located directly above the side portion 22a, and a portion of the second outer layer portion 15b2 located directly below the side portion 22a.

[0034] In the laminate 12, the laminate portion 40 constitutes the inner layer portion 15a, a portion of the first outer layer portion 15b1 located directly above the inner layer portion 15a, and a portion of the first outer layer portion 15b1 located directly below the inner layer portion 15a.

[0035] Each of the first side margin portion 41 a and the second side margin portion 41 b has a material composition different from that of the dielectric layer 14, and includes, but is not limited to, a dielectric material whose main component is, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3, and a sintering aid element. Examples of the sintering aid element include Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, and V.

[0036] Each of the first side margin portion 41 a and the second side margin portion 41 b may be made up of one layer or multiple layers, and the thickness of each of the first side margin portion 41 a and the second side margin portion 41 b may be 5 μm or more and 40 μm or less.

[0037] The side margin portion 41 in this embodiment of the present invention has an inner layer 41I arranged on the inner side of the laminated portion 40, an outer layer 41O arranged on each side of the fifth surface 12e and sixth surface 12f of the laminated body 12 located outside the inner layer 41I, and a pattern portion 50 provided inside each of the first side margin portion 41a and the second side margin portion 41b.

[0038] Specifically, as shown in Figures 7 and 8, the first side margin portion 41a has a first inner layer 41aI arranged adjacent to the laminate portion 40, a first outer layer 41aO including the fifth surface 12e of the laminate 12, and a first pattern portion 50a provided inside the first side margin portion 41a.

[0039] The second side margin portion 41b has a second inner layer 41bI arranged adjacent to the laminate portion 40, a second outer layer 41bO including the sixth surface 12f of the laminate 12, and a second pattern portion 50b provided inside the second side margin portion 41b.

[0040] As shown in FIG. 5, the first inner layer 41aI is disposed in the first side margin portion 41a so as to contact the edge of the internal electrode layer 16 located closer to the fifth surface 12e.

[0041] The first inner layer 41aI is made of a dielectric material containing, for example, BaTiO3, CaTiO3, SrTiO3, CaZrO3 or the like as a main component.

[0042] The first inner layer 41aI may contain glass containing silicon dioxide as a main component.

[0043] The first inner layer 41aI may contain a sintering aid element, such as Dy, Ni, Ba, B, Li, K, Na, Mn, Mg, Ho, Ca, or V. The sintering aid element may be one type or two or more types.

[0044] The thickness of the first inner layer 41aI is preferably 0.1 μm or more and 10 μm or less.

[0045] In the first side margin portion 41 a, the first outer layer 41 aO is located on the fifth surface 12 e side in the WT plane. As a result, the outer surface of the first side margin portion 41 a coincides with the fifth surface 12 e of the laminate 12.

[0046] The first outer layer 41aO is made of a dielectric material containing, for example, BaTiO3, CaTiO3, SrTiO3, CaZrO3, or the like as a main component.

[0047] The main component of the glass of the first outer layer 41aO is, for example, silicon dioxide, but is not limited to this.

[0048] The first outer layer 41aO may contain a sintering aid element or a sintering inhibitor element. The sintering aid element may be the same as that of the first inner layer 41aI. The sintering aid element may be one type or two or more types.

[0049] The thickness of the first outer layer 41aO is preferably 0.1 μm or more and 10 μm or less.

[0050] The first outer layer 41aO preferably has a higher Si content than the first inner layer 41aI.

[0051] As shown in FIG. 5, the second inner layer 41bI is disposed in the second side margin portion 41b so as to contact the edge of the internal electrode layer 16 located closer to the sixth surface 12f.

[0052] The material composition of the second inner layer 41bI is the same as that of the first inner layer 41aI, and a detailed description thereof will be omitted.

[0053] In the second side margin portion 41b, the second outer layer 41bO is located on the sixth surface 12f side in the WT plane. As a result, the outer surface of the second side margin portion 41b coincides with the sixth surface 12f of the laminate 12.

[0054] The material composition of the second outer layer 41bO is the same as that of the first outer layer 41aO, and a detailed description thereof will be omitted.

[0055] The boundary between the inner layer 41I and the outer layer 41O in the side margin portion 41 is detected as follows. That is, a WT cross section at half the dimension in the L direction is exposed, and Si element analysis is performed on the WT cross section using WDX (wavelength dispersive X-ray analysis). Since the outer layer 41O has a higher Si content than the inner layer 41I and Si segregation occurs at the boundary between the inner layer 41I and the outer layer 41O, by detecting a portion where the Si content is higher than the surrounding area, the detected portion can be considered to be the boundary between the inner layer 41I and the outer layer 41O.

[0056] The outer layer 41O may further include multiple layers. Taking the first side margin 41a as an example, as shown in Fig. 8, the first outer layer 41aO of the first side margin 41a may be formed by stacking a sub-outer layer 41aOo, an identification layer 41aOr, and a sub-center layer 41aOc in this order along the second direction z toward the stacking unit 40.

[0057] (Pattern Portion) The pattern portion 50 is provided inside the side margin portion 41, and is a portion that can be distinguished from other portions of the laminate 12 by observation or detection from outside the side margin portion 41 or observation or detection into the inside.

[0058] The pattern portion 50 has a first pattern portion 50a and a second pattern portion 50b. The first pattern portion 50a is provided inside the first side margin portion 41a. The second pattern portion 50b is provided inside the second side margin portion 41b.

[0059] By providing the pattern portion 50 inside the side margin portion 41, traceability can be imparted to the multilayer ceramic capacitor 10 during the mass production process of the multilayer ceramic capacitor 10, particularly during the formation and processing of each of the first side margin portion 41a and the second side margin portion 41b.

[0060] In the mass production process of multilayer ceramic capacitors 10, it has been difficult to determine the timing of the occurrence of foreign matter from the series of steps leading up to the foreign matter becoming embedded in the laminate. Furthermore, it has sometimes been impossible to observe the variation in the occurrence of defective chips within a lot. For example, in the mass production process, there are times when a break is taken during the processing of a lot or the processing is interrupted due to equipment trouble. Even in such cases, the products (chips) processed before and after the break or interruption are uniformly processed as the same lot, making it difficult to determine at which stage of processing the foreign matter became embedded.

[0061] By providing the pattern portion 50 inside the side margin portion 41, it is possible to provide traceability to each lot of the multilayer ceramic capacitor 10. This makes it possible to link the multilayer ceramic capacitor 10 to a series of flows in the mass production process of the multilayer ceramic capacitor 10 and individual processing steps of intra-lot variations, and to trace the occurrence of defective chips. This makes it possible to prevent and take measures against the occurrence of defective chips.

[0062] Furthermore, chip processing in a clean room is extremely sensitive, and the mass production process is susceptible to irregularities such as the breaks and interruptions mentioned above. However, ensuring traceability based on the pattern portion 50 can also help to identify the cause of quality defects in the multilayer ceramic capacitor 10.

[0063] Furthermore, in the manufacturing process of the multilayer ceramic capacitor 10, equipment trouble or dust generation during maintenance work may cause a change in the rate of foreign matter entrapment before and after the work, but by ensuring traceability based on the pattern portion 50, this change can be discovered.

[0064] The specific shape of the pattern portion 50 is not particularly limited, and may be, for example, a letter, a number, a code, or a graphic. In this embodiment, the first pattern portion 50a of the pattern portion 50 is made up of a plurality of first pattern bodies 51a. Each of the first pattern bodies 51a has a doughnut shape. Similarly, the second pattern portion 50b of the pattern portion 50 is made up of a plurality of second pattern bodies 51b. Each of the second pattern bodies 51b has a doughnut shape.

[0065] As described above, it is preferable that the pattern portion 50 be provided inside the side margin portion 41.

[0066] Providing the patterned portion 50 inside the side margin portion 41 makes the patterned portion 50 less susceptible to deterioration and allows the patterned portion 50 to remain resistant to external stress, compared to providing the patterned portion 50 on the surface of the laminate 12. This allows for faster and more accurate response to defects that may occur, even if the chip undergoes external stress during manufacture.

[0067] Providing the patterned portion 50 inside the side margin portion 41 can prevent the patterned portion 50 from weathering. Also, it can prevent the patterned portion 50 from being changed or removed from the outside.

[0068] The pattern portion 50 may be provided inside the side margin portion 41 and on the inner layer 41I side based on the boundary between the outer layer 41O and the inner layer 41I, but it is preferable that it be provided on the outer layer 41O side.

[0069] For example, when the outer layer 41O is made up of multiple layers, such as the first outer layer 41aO of the first side margin portion 41a shown in Fig. 8, the pattern portion 50 is preferably provided between each layer in the outer layer 41O. Specifically, when the first outer layer 41aO in the first side margin portion 41a has a sub-outer layer 41aOo, an identification layer 41aOr, and a sub-center layer 41aOc, the pattern portion 50 is preferably provided between the sub-outer layer 41aOo and the identification layer 41aOr, or between the identification layer 41aOr and the sub-center layer 41aOc.

[0070] In this case, the pattern portion 50 is provided on the outer layer 41O side with respect to the boundary between the outer layer 41O and the inner layer 41I, or is provided in a position relatively close to the exposed surface (the fifth surface 12e or the sixth surface 12f), making the pattern portion 50 easier to detect from the outside. Therefore, the pattern portion 50 is less susceptible to stress from the outside and is easily detectable from the outside, making it easier to trace if a malfunction occurs.

[0071] The pattern portion 50 may be provided in the boundary region between the outer layer 41O and the inner layer 41I in the side margin portion 41. That is, the first pattern portion 50a may be provided between the first outer layer 41aO and the first inner layer 41aI in the first side margin portion 41a, and the second pattern portion 50b may be provided between the second outer layer 41bO and the second inner layer 41bI in the second side margin portion 41b.

[0072] 7, the first side margin 41a is preferably provided as a plurality of first pattern bodies 51a on the surface 41aA of the first inner layer 41aI. The plurality of first pattern bodies 51a may also be provided on the surface of the first outer layer 41aO that faces the surface 41aA of the first inner layer 41aI.

[0073] In this case too, the pattern portion 50 is less susceptible to stress from the outside world and is easily detected from the outside world, so that if a problem occurs, it can be more easily traced.

[0074] The pattern portion 50 may be provided in the boundary region between the laminate portion 40 and the side margin portion 41. That is, the first pattern portion 50a may be provided at the boundary between the laminate portion 40 and the first inner layer 41aI of the first side margin portion 41a, and the second pattern portion 50b may be provided at the boundary between the laminate portion 40 and the second inner layer 41bI of the second side margin portion 41b.

[0075] The components of the pattern portion 50 are not particularly limited, but may be voids, or may contain metal components, radioisotope-labeled atoms, etc. However, when the pattern portion 50 is formed of a metal component, it is preferable that the pattern portion 50 does not come into contact with the external electrode 30 and the internal electrode layer 16. As the metal component, base metals such as Ni and Cu or precious metals can be used.

[0076] When the pattern portion 50 is formed by voids, it can be manufactured, for example, by incorporating a larger amount of organic compound into the portion that will become the pattern portion 50 than into the surrounding area of ​​that portion, but this manufacturing method is not limited to this. Here, the organic compound is preferably the same as that contained in the binder or solvent contained in the dielectric sheet used in manufacturing the laminate 12 of the multilayer ceramic capacitor 10. More preferably, the combustion temperature of the organic compound is equal to or lower than the combustion temperature of the binder contained in the dielectric sheet in manufacturing the multilayer ceramic capacitor 10.

[0077] This allows the pattern portion 50 to be easily formed in the manufacturing process of the multilayer ceramic capacitor. Furthermore, since the pattern portion 50 is formed using an organic compound that is originally contained in the raw materials of the multilayer ceramic capacitor, it is possible to reduce the influence on the laminate 12 and furthermore, it is possible to more reliably detect the pattern portion 50.

[0078] When the pattern portion 50 is formed by a void, it is preferable that the pattern portion 50 is located within a depth range that can be confirmed from the outside by visual inspection or a camera, specifically, within a depth range of 2 μm or more and 16 μm or less from the outermost surface of the side margin portion 41 (coinciding with the fifth surface 12e or the sixth surface 12f of the laminate 12) toward the laminate portion 40.

[0079] This allows the pattern portion 50 to be formed stably without damaging the outer layer 41O.

[0080] When the pattern portion 50 is formed by a void, the pattern inherent to the pattern portion 50 and the pattern formed by the internal electrode layer 16 cooperate to make the pattern portion 50 more clearly visible. Specifically, by observing the side margin portion 41 side, it is possible to confirm the presence of a white pattern portion (void) in the black portion derived from the internal electrode layer 16. In other words, the pattern portion 50 is a white pattern with the internal electrode layer 16 as a black background, so it can be confirmed with good visibility. In particular, when the LT surface of the chip is polished, it can be detected more clearly, which is preferable.

[0081] When the pattern portion 50 is a metal component, it can be manufactured, for example, by adding a larger amount of metal component to the portion that will become the pattern portion 50 than to the surrounding area of ​​that portion, but the manufacturing method is not limited to this.

[0082] When the pattern portion 50 is a metal component, it is preferable that the pattern portion 50 is located within a depth range that can be confirmed visually or by detection such as magnetic detection, specifically within a depth range of 2 μm or more and 16 μm or less from the outermost surface of the side margin portion 41 (coinciding with the fifth surface 12e or the sixth surface 12f of the laminate 12) toward the laminate portion 40.

[0083] This allows the pattern portion 50 to be detected reliably.

[0084] When the pattern portion 50 contains radioisotope-labeled atoms, it is preferable that the pattern portion 50 be located within a depth range that can be confirmed by detecting radiation, specifically, within a depth range of 2 μm or more and 16 μm or less from the outermost surface of the side margin portion 41 (coinciding with the fifth surface 12e or the sixth surface 12f of the laminate 12) toward the laminate portion 40.

[0085] This allows the pattern portion 50 to be detected reliably.

[0086] If the pattern portion 50 is visually visible regardless of its constituent components, it is possible to impart design and aesthetic appeal to the multilayer ceramic capacitor 10, which is preferable.

[0087] Providing the patterned portion 50 inside the side margin portion 41 or at the boundary between the laminated portion 40 and the side margin portion 41 is preferable because it can provide cushioning properties (impact resistance) to the multilayer ceramic capacitor 10.

[0088] (Internal Electrode Layers) As shown in Figures 4 and 5, the internal electrode layers 16 include first internal electrode layers 16a and second internal electrode layers 16b. The first internal electrode layers 16a and second internal electrode layers 16b are alternately stacked at equal intervals along the stacking direction x, with the dielectric layers 14 interposed therebetween. The first internal electrode layers 16a and second internal electrode layers 16b are substantially parallel to the first surface 12a and the second surface 12b, respectively.

[0089] The first internal electrode layer 16a is disposed on the surface of the dielectric layer 14. The first internal electrode layer 16a has a first opposing electrode portion 18a that faces the second internal electrode layer 16b, and a first lead electrode portion 20a that is located on one end side of the first internal electrode layer 16a and extends from the first opposing electrode portion 18a to the third surface 12c of the laminate 12. The end of the first lead electrode portion 20a is led out to the third surface 12c and exposed. Specifically, the end of the first lead electrode portion 20a is slightly recessed from the fourth surface 12d.

[0090] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first opposing electrode portion 18a may be tapered in plan view, with a slope increasing in either direction.

[0091] The shape of the first lead electrode portion 20a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the first lead electrode portion 20a may be tapered in plan view, with a slope increasing in either direction.

[0092] The second internal electrode layer 16b is disposed on a surface of a dielectric layer 14 different from the surface of the dielectric layer 14 on which the first internal electrode layer 16a is disposed. The second internal electrode layer 16b has a second opposing electrode portion 18b that faces the first internal electrode layer 16a, and a second extraction electrode portion 20b that is located on one end side of the second internal electrode layer 16b and extends from the second opposing electrode portion 18b to the fourth surface 12d of the laminate 12. The end of the second extraction electrode portion 20b is extended to and exposed on the fourth surface 12d. Specifically, the end of the second extraction electrode portion 20b is slightly recessed from the third surface 12c.

[0093] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second opposing electrode portion 18b may be tapered in plan view, with a slope increasing in either direction.

[0094] The shape of the second extraction electrode portion 20b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the second extraction electrode portion 20b may be tapered in plan view, with a slope increasing in either direction.

[0095] The laminate 12 includes side portions (hereinafter referred to as "W gaps") 22a of the laminate 12 formed between one ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the second direction z and the fifth surface 12e, and between the other ends of the first opposing electrode portion 18a and the second opposing electrode portion 18b in the second direction z and the sixth surface 12f. Furthermore, the laminate 12 includes ends (hereinafter referred to as "L gaps") 22b of the laminate 12 formed between an end of the first internal electrode layer 16a opposite to the first extraction electrode portion 20a and the fourth surface 12d, and between an end of the second internal electrode layer 16b opposite to the second extraction electrode portion 20b and the third surface 12c.

[0096] The internal electrode layers 16 can be made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals, such as an Ag-Pd alloy. When the base electrode layer of the external electrode 30, which will be described later, is a conductive resin layer, the metal constituting the internal electrode layers 16 forms a compound with the metal constituting the conductive filler contained in the conductive resin layer.

[0097] In this embodiment, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0098] The number of stacked internal electrode layers 16 is not particularly limited, but is preferably 200 to 1000. The thickness of the internal electrode layers 16 is preferably about 0.3 μm to 1.0 μm.

[0099] (External Electrodes) As shown in FIGS. 1 to 6, external electrodes 30 are disposed on the third surface 12c side and the fourth surface 12d side of the laminate 12.

[0100] The external electrode 30 has a base electrode layer 32 that covers the laminate 12 and a plating layer 34 that covers the base electrode layer 32 .

[0101] The external electrode 30 includes a first external electrode 30a and a second external electrode 30b.

[0102] The first external electrode 30a is disposed on the third surface 12c of the laminate 12. The first external electrode 30a may be disposed on a portion of the first surface 12a, a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f. In this embodiment, the first external electrode 30a is formed extending from the third surface 12c to a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. The first external electrode 30a is electrically connected to the first extraction electrode portion 20a of the first internal electrode layer 16a.

[0103] The second external electrode 30b is disposed on the fourth surface 12d of the laminate 12. The second external electrode 30b may be disposed on a portion of the first surface 12a, a portion of the second surface 12b, and a portion of the fifth surface 12e and a portion of the sixth surface 12f. In this embodiment, the second external electrode 30b is formed extending from the fourth surface 12d to a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. The second external electrode 30b is electrically connected to the second extraction electrode portion 20b of the second internal electrode layer 16b.

[0104] Within the laminate 12, capacitance is formed by the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b opposing each other via the dielectric layer 14. Therefore, capacitance can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, and the characteristics of a capacitor are exhibited.

[0105] (Underlying Electrode Layer) The underlying electrode layer 32 includes a first underlying electrode layer 32a and a second underlying electrode layer 32b.

[0106] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is disposed on the surface of the third surface 12c. The first base electrode layer 32a also extends from the third surface 12c and is disposed on a portion of the first surface 12a, a portion of the second surface 12b, a portion of the fifth surface 12e, and a portion of the sixth surface 12f. In this case, the first base electrode layer 32a is electrically connected to the first lead electrode portion 20a of the first internal electrode layer 16a.

[0107] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is disposed on the surface of the fourth face 12d. The second base electrode layer 32b also extends from the fourth face 12d and is disposed on a part of the first face 12a, a part of the second face 12b, a part of the fifth face 12e, and a part of the sixth face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 20b of the second internal electrode layer 16b.

[0108] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0109] Hereinafter, each of the configurations when the base electrode layer 32 is the baked layer, the conductive resin layer, and the thin film layer will be described.

[0110] (In the case of a baking layer) The baking layer contains a metal component and glass. The metal component of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The baking layer is formed by applying a conductive paste containing glass and a metal to the laminate and baking it. The baking layer is formed by simultaneously baking a laminated chip having internal electrode layers 16 and dielectric layers 14 and the conductive paste applied to the laminated chip, but may also be baked after baking the laminated chip having internal electrode layers 16 and dielectric layers 14. The baking layer may be a multi-layered layer.

[0111] The thickness of the first base electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d at the center in the stacking direction x is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0112] The thickness of the second base electrode layer 32b located on the fourth surface 12d in the first direction y connecting the fourth surface 12d at the center in the stacking direction x is preferably, for example, approximately 10 μm or more and 150 μm or less.

[0113] The thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on a part of the first surface 12a and the second surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0114] Furthermore, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on a part of the first surface 12a and the second surface 12b is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0115] The thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center in the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on a part of the fifth surface 12e and the sixth surface 12f is preferably, for example, approximately 10 μm or more and 100 μm or less.

[0116] Furthermore, it is preferable that the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the second base electrode layer 32b located on part of the fifth surface 12e and the sixth surface 12f, the thickness in the second direction z connecting the third surface 12c and the fourth surface 12d, is, for example, approximately 10 μm or more and 100 μm or less.

[0117] (Conductive Resin Layer) The conductive resin layer has a first conductive resin layer and a second conductive resin layer.

[0118] The first conductive resin layer is preferably arranged as a first base electrode layer 32a so as to further cover other layers such as a baked layer, and the second conductive resin layer is preferably arranged as a second base electrode layer 32b so as to further cover other layers such as a baked layer.

[0119] Specifically, the first and second conductive resin layers, as the first and second base electrode layers 32a and 32b, are preferably disposed on other layers, such as baked layers, located on the third and fourth surfaces 12c and 12d, and are provided so as to extend also onto other layers, such as baked layers, located on the first and second surfaces 12a and 12b, as well as the fifth and sixth surfaces 12e and 12f. However, the first and second conductive resin layers may be disposed only on other layers, such as baked layers, located on the third and fourth surfaces 12c and 12d.

[0120] The thickness of the first conductive resin layer and the second conductive resin layer is preferably, for example, about 10 μm or more and 200 μm or less.

[0121] The first conductive resin layer and the second conductive resin layer contain a thermosetting resin and a metal component.

[0122] Because the first conductive resin layer and the second conductive resin layer contain a thermosetting resin, they are more flexible than the base electrode layer 32 made of, for example, a plating film or a fired product of a conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0123] Specific examples of the thermosetting resin include various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0124] The first conductive resin layer and the second conductive resin layer preferably contain a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, and imidazole-based compounds can be used as the curing agent for the epoxy resin.

[0125] The metal contained in the first conductive resin layer and the second conductive resin layer may be Ag, Cu, or an alloy thereof. Alternatively, a metal powder having an Ag-coated surface may be used. When using a metal powder having an Ag-coated surface, it is preferable to use Cu or Ni as the metal powder.

[0126] Alternatively, Cu that has been treated to prevent oxidation can also be used. The reason for using Ag-coated metal is that it allows the base metal to be inexpensive while maintaining the above-mentioned properties of Ag.

[0127] The metal contained in the first conductive resin layer and the second conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0128] The shape of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited, and the conductive filler may be spherical, flat, or the like.

[0129] The average particle size of the metal contained in the first conductive resin layer and the second conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, about 0.3 μm or more and 10 μm or less.

[0130] The metals contained in the first conductive resin layer and the second conductive resin layer are mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, contact between the conductive fillers forms an electrical path inside the conductive resin layer.

[0131] The metal contained in the first conductive resin layer and the second conductive resin layer may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0132] The first conductive resin layer and the second conductive resin layer may each include a resin layer containing conductive particles and a thermosetting resin.

[0133] The conductive resin layer may be formed directly on the laminate without forming a baked layer.

[0134] (In the case of a thin film layer) When the base electrode layer 32 is formed as a thin film layer, the thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 10 μm or less in thickness on which metal particles are deposited.

[0135] Next, the first plating layer 34a and the second plating layer 34b, which are the plating layers 34 disposed on the base electrode layer 32, will be described with reference to FIGS. 4 and 5. FIG.

[0136] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag--Pd alloy, Au, and the like.

[0137] The first plating layer 34a is disposed so as to completely cover the first base electrode layer 32a, and the second plating layer 34b is disposed so as to completely cover the second base electrode layer 32b.

[0138] The first plating layer 34a and the second plating layer 34b may be formed of multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of a lower plating layer (Ni plating layer) formed on the base electrode layer 32 by Ni plating and an upper plating layer (Sn plating layer) formed on the lower plating layer by Sn plating. That is, in this case, the first plating layer 34a has a first lower plating layer and a first upper plating layer located on the surface of the first lower plating layer. Furthermore, the second plating layer 34b has a second lower plating layer and a second upper plating layer located on the surface of the second lower plating layer.

[0139] The lower plating layer made of Ni plating is used to prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10, and the upper plating layer made of Sn plating is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, making it easier to mount.

[0140] The thickness of each of the lower plating layer and the upper plating layer is preferably 1.0 μm or more and 15.0 μm or less.

[0141] 1 , the dimension of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12, the first external electrode 30a, and the second external electrode 30b in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm to 1.6 mm, the W dimension in the second direction z is 0.1 mm to 0.8 mm, and the T dimension in the stacking direction x is 0.1 mm to 0.8 mm. The dimensions of the multilayer ceramic capacitor 10 can be measured using a microscope.

[0142] 1, the laminate 12 has side margin portions 41 disposed on each side of a fifth surface 12e and a sixth surface 12f of the laminate 12, and a pattern portion 50 is provided inside the side margin portions 41. This makes it possible to prevent and take measures against the occurrence of defective chips.

[0143] 1 , the side margin portion 41 includes an inner layer 41I disposed on the inside along the second direction z and an outer layer 41O disposed on the outside of the inner layer 41I, and the pattern portion 50 is provided inside the outer layer 41O or in the boundary region between the inner layer 41I and the outer layer 41O. This makes it easier to trace if a defect occurs.

[0144] In the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 , the pattern portion 50 may be formed by a void. This allows the pattern portion 50 to be formed easily. Furthermore, the formation of the pattern portion 50 can reduce the influence on the laminate 12. Furthermore, the pattern portion 50 can be detected more reliably.

[0145] 1 , the pattern portion 50 is provided at a depth of 2 μm or more and 16 μm or less from the outermost surface (the fifth surface and the sixth surface) of the side margin portion 41 toward the inside. This allows the pattern portion 50 to be stably formed without damaging the outer layer 41O.

[0146] 1 , the laminate 12 has side margin portions 41 disposed on each side of a fifth surface 12 e and a sixth surface 12 f of the laminate 12, and a laminate portion 40 sandwiched between the side margin portions 41, and patterned portions are provided between each of the side surfaces 40 c and 40 d of the laminate portion 40 and each of the fifth surface 12 e and the sixth surface 12 f of the laminate 12, which are the outer surfaces of the side margin portions. This makes it possible to prevent and take measures against the occurrence of faulty chips.

[0147] 2. Method for Manufacturing the Multilayer Ceramic Capacitor A method for manufacturing the multilayer ceramic capacitor according to the above embodiment will now be described.

[0148] (1) Prepare a dielectric sheet and a conductive paste for the internal electrode layers. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder (for example, a known organic binder) and a solvent (for example, a known organic binder).

[0149] (2) Next, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheets by, for example, screen printing or gravure printing, to prepare a dielectric sheet on which a first internal electrode pattern corresponding to the first internal electrode layer 16 a is formed and a dielectric sheet on which a second internal electrode pattern corresponding to the second internal electrode layer 16 b is formed. Note that, with regard to the dielectric sheets, dielectric sheets for outer layers on which no internal electrode pattern is printed are also prepared.

[0150] (3) A predetermined number of dielectric sheets for outer layers on which no internal electrode pattern is formed are stacked to form a portion that will become part of the second outer layer portion 15b2, and then a dielectric sheet on which the first internal electrode pattern is formed and a dielectric sheet on which the second internal electrode pattern is formed are stacked in sequence on top of that to form a portion that will become the inner layer portion 15a.

[0151] (4) Furthermore, a predetermined number of dielectric sheets on which no internal electrode pattern is printed are stacked on top of the internal electrode pattern corresponding to the internal electrode layer located on the outermost surface of the inner layer portion 15a to form a portion that will become part of the first outer layer portion 15b1, thereby producing a laminated sheet.

[0152] (5) The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0153] (6) The laminated block is cut to a predetermined size, and laminated chips that will become laminated units 40 are cut out as shown in Fig. 9A. The laminated units 40 are formed so that the edges of the internal electrode patterns are exposed on each of the side surfaces 40c parallel to the fifth surface 12e and the side surfaces 40d parallel to the sixth surface 12f of the completed laminate 12.

[0154] 9B , a first inner layer 41aI of the first side margin 41a is prepared, having a pattern corresponding to the plurality of first pattern bodies 51a attached thereto, and the first inner layer 41aI is attached to the side surface 40c of the laminated unit 40. Also, a second inner layer 41bI of the second side margin 41b is prepared, having a pattern corresponding to the plurality of second pattern bodies 51b attached thereto, and the second inner layer 41bI is attached to the side surface 40d of the laminated unit 40.

[0155] The patterns corresponding to each of the plurality of first pattern bodies 51 a attached to the first inner layer 41 aI and the second pattern bodies 51 b attached to the second inner layer 41 bI can assume any shape (doughnut-shaped in the figure) formed by applying the same organic compound (organic solvent) as that contained in the binder and solvent of the dielectric sheet. More preferably, the combustion temperature of the organic compound is equal to or lower than the combustion temperature of the binder contained in the dielectric sheet in terms of manufacturing the multilayer ceramic capacitor 10.

[0156] In addition, after attaching the first inner layer 41aI and the second inner layer 41bI to the laminated portion 40, the first pattern body 51a and the second pattern body 51b may be attached to each surface of the attached first inner layer 41aI and second inner layer 41bI.

[0157] (9) Next, as shown in Figure 9C, a side margin sheet having a predetermined material composition is attached to the first inner layer 41aI of the first side margin portion 41a to form the first outer layer 41aO of the first side margin portion 41a. A side margin sheet having a predetermined material composition is also attached to the second inner layer 41bI of the second side margin portion 41b to form the second outer layer 41bO of the second side margin portion 41b. In this way, the side margin portion 41 is formed.

[0158] (10) After the side margins 41 are formed, the laminate 40 is degreased under predetermined conditions in a nitrogen atmosphere. As a result, the organic compounds in the pattern corresponding to the plurality of first pattern bodies 51a in the first side margin 41a are burned during the degreasing process, leaving traces of their shape as the first pattern body 50a and disappearing. The organic compounds in the pattern corresponding to the plurality of second pattern bodies 51b in the second side margin 41b are similarly burned, leaving traces of their shape as the second pattern body 50b and disappearing. Thus, the first pattern body 51a and the second pattern body 51b can be formed. At this time, the corners and ridges of the laminate 40 and the side margins 41 may be rounded by barrel polishing or the like.

[0159] (11) The degreased laminate 40 with the side margins 41 formed therein is fired to produce the laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrode layers 16, but is preferably 900° C. or higher and 1400° C. or lower.

[0160] (12) Subsequently, the base electrode layer 32 is formed. The base electrode layer 32 is a baked layer. A conductive paste containing a glass component and a metal component is prepared for each of the first base electrode layer 32 a and the second base electrode layer 32 b.

[0161] (13) A conductive paste is applied to the third surface 12c and the fourth surface 12d, which are both end surfaces of the laminate 12, by a method such as dipping or screen printing, and then a baking process is performed to form the first base electrode layer 32a and the second base electrode layer 32b. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0162] (14) The surface of the base electrode layer 32 is plated to form a plating layer 34. In this embodiment, two plating layers are formed on the surfaces of the first base electrode layer 32a and the second base electrode layer 32b. Specifically, a Ni plating layer is formed on the first base electrode layer 32a and the second base electrode layer 32b, and a Sn plating layer is formed on the Ni plating layer. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0163] In this manner, the multilayer ceramic capacitor 10 according to the present embodiment shown in FIG. 1 is manufactured.

[0164] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0165] In other words, various modifications can be made to the above-described embodiments and variants in terms of mechanism, shape, material, quantity, position, arrangement, etc., without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0166] REFERENCE SIGNS LIST 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 15a Inner layer portion 15b1 First outer layer portion 15b2 Second outer layer portion 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a First opposing electrode portion 18b Second opposing electrode portion 20a First lead electrode portion 20b Second lead electrode portion 22a Side portion 22b End portion 30 External electrode 30a First external electrode 30b Second external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 40 Laminated portion 40c, 40d Side surface 41 Side margin portion 41I Inner layer 41O Outer layer 41a First side margin portion 41b Second side margin portion 41aA, 41bA Surface 41aI First inner layer 41bI Second inner layer 41aO First outer layer 41bO Second outer layer 41aOc Sub-center layer 41aOo Sub-outer layer 41aOr Identification layer 50 Pattern portion 50a First pattern portion 50b Second pattern portion 51a First pattern main body 51b Second pattern main body

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having a first surface and a second surface facing in a stacking direction of the plurality of dielectric layers, a third surface and a fourth surface facing in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the third surface of the laminate; and a second external electrode disposed on the fourth surface of the laminate, the laminate having side margin portions disposed on each side of the fifth surface and the sixth surface of the laminate, and a pattern portion provided inside the side margin portions.

2. The multilayer ceramic capacitor according to claim 1, wherein the side margin portion includes an inner layer disposed on the inside along the second direction and an outer layer disposed outside the inner layer, and the pattern portion is provided inside the outer layer or in the boundary region between the outer layer and the inner layer.

3. A multilayer ceramic capacitor according to claim 1 or 2, wherein the pattern portion is formed by voids.

4. A multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the pattern portion is provided at a depth of 2 μm to 16 μm from the outermost surface of the side margin portion toward the inside.

5. A multilayer ceramic capacitor comprising: a laminate including a plurality of laminated dielectric layers and a plurality of internal electrode layers, the laminate having first and second surfaces facing each other in a stacking direction of the plurality of dielectric layers, third and fourth surfaces facing each other in a first direction perpendicular to the stacking direction, and fifth and sixth surfaces facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode arranged on the third surface of the laminate; and a second external electrode arranged on the fourth surface of the laminate, wherein the laminate has side margin portions arranged on each side of the fifth and sixth surfaces of the laminate, and a laminate portion sandwiched between the side margin portions, and a pattern portion is provided between the side surface of the laminate portion and the outer surface of the side margin portion.

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