Plasma processing device

Abstract

Provided is a technique capable of suppressing fluctuation of an incident angle of ions in an edge portion of a substrate in plasma processing. This plasma processing device includes: a chamber; a substrate support portion; an RF generator configured to generate an RF signal for generating plasma in the chamber; a substrate bias signal generator electrically connected to a substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to a ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, said plurality of second voltage pulse bursts each including a plurality of voltage pulses having a gradually decreasing voltage level.

Description

Plasma processing equipment

[0001] SUMMARY OF THE INVENTION An exemplary embodiment of the present disclosure relates to a plasma processing apparatus.

[0002] In a plasma processing apparatus, a technique for reducing the influence of a phase difference between an electric bias for a substrate and an electric bias for an edge ring on plasma processing is disclosed in Japanese Patent Laid-Open No. 2003-222999.

[0003] Japanese Patent Application Laid-Open No. 2021-158134

[0004] The present disclosure provides a technique capable of suppressing fluctuations in the incident angle (tilting angle) of ions at the edge portion of a substrate (hereinafter also simply referred to as "ion incident angle") during plasma processing.

[0005] In one exemplary embodiment of the present disclosure, a plasma processing apparatus includes: a chamber; a substrate support disposed in the chamber, the substrate support including: a conductive base; an electrostatic chuck disposed on the conductive base and having a substrate support surface and a ring support surface; an edge ring disposed on the ring support surface to surround a substrate on the substrate support surface; a substrate bias electrode disposed in the electrostatic chuck below the substrate support surface; and a ring bias electrode disposed in the electrostatic chuck below the ring support surface; an RF generator configured to generate an RF signal to generate a plasma in the chamber; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

[0006] According to one exemplary embodiment of the present disclosure, it is possible to provide a technique that can suppress fluctuations in the ion incident angle at the edge portion of a substrate during plasma processing.

[0007] 1 is a diagram for explaining an example of the configuration of a plasma processing system; FIG. 2 is a diagram for explaining an example of the configuration of a plasma processing apparatus; FIG. 3 is a diagram for explaining an example of the configuration of electrodes and power supplies in a substrate support part; FIG. 4 is a plan view for explaining an example of the configuration of bias electrodes in a substrate support part; FIG. 5 is a diagram for explaining an example of the waveforms of a substrate bias signal, a ring bias signal, and an RF signal; FIG. 6 is a diagram for explaining an example of a plurality of voltage pulses in a first voltage pulse burst and a second voltage pulse burst; FIG. 7 is a diagram for explaining the amount of decrease in voltage level of adjacent voltage pulses; FIG. 8 is a diagram for explaining fluctuations in the ion incident angle in plasma processing; FIG. 9 is a diagram for explaining an example of waveforms when the substrate bias signal and ring bias signal are not synchronized with the RF signal; and FIG. 10 is a diagram for explaining another example of the configuration of electrodes and power supplies in a substrate support part.

[0008] Hereinafter, each embodiment of the present disclosure will be described.

[0009] In one exemplary embodiment, a plasma processing apparatus is provided, including: a chamber; a substrate support disposed within the chamber, the substrate support including: a conductive base; an electrostatic chuck disposed on the conductive base and having a substrate support surface and a ring support surface; an edge ring disposed on the ring support surface to surround a substrate on the substrate support surface; a substrate bias electrode disposed within the electrostatic chuck below the substrate support surface; and a ring bias electrode disposed within the electrostatic chuck below the ring support surface; an RF generator configured to generate an RF signal to generate a plasma in the chamber; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

[0010] In one exemplary embodiment, each of the first plurality of voltage pulse bursts includes a plurality of voltage pulses having the same voltage level.

[0011] In one exemplary embodiment, the voltage pulses in each of the first plurality of voltage pulse bursts have a negative polarity, and the voltage pulses in each of the second plurality of voltage pulse bursts have a negative polarity.

[0012] In one exemplary embodiment, the substrate bias signal generator further includes a first DC power supply configured to generate a first DC signal, and the substrate bias signal generator is configured to generate a plurality of first voltage pulse bursts from the first DC signal.

[0013] In one exemplary embodiment, the ring bias signal generator further includes a second DC power supply configured to generate a second DC signal, and the ring bias signal generator is configured to generate a plurality of second voltage pulse bursts from the second DC signal.

[0014] In one exemplary embodiment, the ring bias signal generator further includes a second DC power supply configured to generate a second DC signal, and the ring bias signal generator is configured to generate a plurality of second voltage pulse bursts from a combination of the first DC signal and the second DC signal.

[0015] In one exemplary embodiment, the difference in voltage level between the first voltage pulse and the last voltage pulse in each of the plurality of second voltage pulse bursts is in the range of 50V to 100V.

[0016] In one exemplary embodiment, the duration of each of the plurality of second voltage pulse bursts is in the range of 100 μsec to 150 μsec.

[0017] In one exemplary embodiment, the first plurality of voltage pulse bursts are synchronized with the second plurality of voltage pulse bursts.

[0018] In one exemplary embodiment, a plasma processing apparatus is provided, including: a plasma processing chamber; a substrate support disposed within the plasma processing chamber and having a substrate support surface; an edge ring disposed to surround a substrate on the substrate support surface; a substrate bias electrode disposed below the substrate support surface; a ring bias electrode disposed below the edge ring; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

[0019] In one exemplary embodiment, each of the first plurality of voltage pulse bursts includes a plurality of voltage pulses having the same voltage level.

[0020] In one exemplary embodiment, the voltage pulses in each of the first plurality of voltage pulse bursts have a negative polarity, and the voltage pulses in each of the second plurality of voltage pulse bursts have a negative polarity.

[0021] In one exemplary embodiment, the substrate bias signal generator further includes a first DC power supply configured to generate a first DC signal, and the substrate bias signal generator is configured to generate a plurality of first voltage pulse bursts from the first DC signal.

[0022] In one exemplary embodiment, the ring bias signal generator further includes a second DC power supply configured to generate a second DC signal, and the ring bias signal generator is configured to generate a plurality of second voltage pulse bursts from the second DC signal.

[0023] In one exemplary embodiment, the ring bias signal generator further includes a second DC power supply configured to generate a second DC signal, and the ring bias signal generator is configured to generate a plurality of second voltage pulse bursts from a combination of the first DC signal and the second DC signal.

[0024] In one exemplary embodiment, the difference in voltage level between the first voltage pulse and the last voltage pulse in each of the plurality of second voltage pulse bursts is in the range of 50V to 100V.

[0025] In one exemplary embodiment, the duration of each of the plurality of second voltage pulse bursts is in the range of 100 μsec to 150 μsec.

[0026] In one exemplary embodiment, the first plurality of voltage pulse bursts are synchronized with the second plurality of voltage pulse bursts.

[0027] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are designated by the same reference numerals, and redundant explanations will be omitted. Unless otherwise specified, the positional relationships, such as up, down, left, and right, will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and the actual ratios are not limited to the ratios shown in the drawings.

[0028] <Example of Plasma Processing System> FIG. 1 is a diagram illustrating an example of the configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0029] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma generated in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like. Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0030] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0031] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0032] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10 (also simply referred to as the "chamber"), a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0033] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0034] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0035] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0036] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0037] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0038] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0039] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0040] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0041] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 100 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0042] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0043] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0044] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0045] As shown in FIG. 3, in one embodiment, the substrate support 11 includes a substrate chuck electrode 200 , at least one ring chuck electrode 201 , a substrate bias electrode 300 , and a ring bias electrode 301 .

[0046] The substrate chuck electrode 200 is disposed below the substrate support surface (central region 111 a) within the electrostatic chuck 1111. In one embodiment, the substrate chuck electrode 200 may have a circular shape. In one embodiment, the substrate chuck electrode 200 is electrically connected to a direct current (DC) power supply 200 b via a switch 200 a. When a DC voltage from the DC power supply 200 b is applied to the substrate chuck electrode 200, an electrostatic attractive force (Coulomb force) is generated between the substrate chuck electrode 200 and the substrate W. The substrate W is attracted to the electrostatic chuck 1111 by the electrostatic attractive force and is adsorbed and held on the substrate support surface.

[0047] The ring chuck electrode 201 is disposed below a ring support surface (annular region 111b) within the electrostatic chuck 1111. The ring support surface may support at least one edge ring 250 of the ring assembly 112. In one embodiment, the ring chuck electrode 201 includes an inner ring chuck electrode 210 and an outer ring chuck electrode 211. In one embodiment, the inner ring chuck electrode 210 is electrically connected to a DC power supply 210b via a switch 210a. In one embodiment, the outer ring chuck electrode 211 is disposed outside the inner ring chuck electrode 210. In one embodiment, the outer ring chuck electrode 211 is electrically connected to a DC power supply 211b via a switch 211a. In one embodiment, a potential difference is generated between the inner ring chuck electrode 210 and the outer ring chuck electrode 211, and the edge ring 250 is attracted and held to the ring support surface by the potential difference. In one embodiment, the polarity of the first ring chuck voltage applied to the inner ring chuck electrode 210 is different from the polarity of the second ring chuck voltage applied to the outer ring chuck electrode 211 .

[0048] The substrate bias electrode 300 is disposed below the substrate support surface in the electrostatic chuck 1111. The substrate bias electrode 300 may be disposed below the substrate chuck electrode 200. The ring bias electrode 301 is disposed below the ring support surface in the electrostatic chuck 1111. The ring bias electrode 301 may be disposed below the ring chuck electrode 201. The substrate bias electrode 300 and the ring bias electrode 301 may be disposed at the same height.

[0049] 4 , in one embodiment, the substrate bias electrode 300 may have a circular shape. The ring bias electrode 301 may have an annular shape with a width in the radial direction. In one embodiment, the ring bias electrode 301 has a larger diameter than the substrate bias electrode 300 and is disposed outside the substrate bias electrode 300.

[0050] As shown in FIG. 3, in one embodiment, the DC power supply 32 includes a first DC power supply 350 , a substrate bias signal generator 351 , a second DC power supply 352 , and a ring bias signal generator 353 .

[0051] The first DC power supply 350 is configured to generate a first DC signal DC1. The first DC signal DC1 may have a first primary voltage level (V1). The first primary voltage level (V1) may have a negative polarity. The first DC power supply 350 is electrically connected to a substrate bias signal generator 351. The first DC power supply 350 may supply the generated first DC signal DC1 to the substrate bias signal generator 351.

[0052] The substrate bias signal generator 351 is configured to generate a substrate bias signal DC2 from the first DC signal DC1. The substrate bias signal DC2 may have a first voltage level. The first voltage level may have the same voltage level (V1) as the first primary voltage level. The substrate bias signal DC2 has a plurality of first voltage pulse bursts. The first voltage pulse bursts may be an example of a sequence of voltage pulses. The substrate bias signal generator 351 is electrically connected to the substrate bias electrode 300 via an impedance matcher or a switch. The substrate bias signal generator 351 can supply the generated substrate bias signal DC2 to the substrate bias electrode 300. By applying the plurality of first voltage pulse bursts of the substrate bias signal DC2 to the substrate bias electrode 300, ion components in plasma formed on the substrate on the substrate support surface can be attracted to the substrate W.

[0053] The second DC power supply 352 is configured to generate a second DC signal DC3. The second DC signal DC3 may have a second primary voltage level (V2). The second primary voltage level (V2) may have a negative polarity. The second DC power supply 352 is electrically connected to the ring bias signal generator 353. The second DC power supply 352 may supply the generated second DC signal DC3 to the ring bias signal generator 353.

[0054] The ring bias signal generator 353 is configured to generate a ring bias signal DC4 from the second DC signal DC3. The ring bias signal DC4 may have a second voltage level. The second voltage level may have the same voltage level (V2) as the second primary voltage level. The ring bias signal DC4 has a plurality of second voltage pulse bursts. The second voltage pulse bursts may be an example of a sequence of voltage pulses. The ring bias signal generator 353 is electrically connected to the ring bias electrode 301 via an impedance matcher or a switch. The ring bias signal generator 353 can supply the generated ring bias signal DC4 to the ring bias electrode 301. By applying the plurality of second voltage pulse bursts of the ring bias signal DC4 to the ring bias electrode 301, ion components in the plasma formed on the edge portion of the substrate W can be attracted to the edge portion of the substrate W.

[0055] 5 and 6 show exemplary waveforms of the substrate bias signal DC2 and the ring bias signal DC4. The substrate bias signal DC2 has a first voltage pulse burst PS1 during a first state S1 (period TS1) within a repetition period T, and has a reference voltage during a second state S2 within the repetition period T. As shown in FIG. 6, the first voltage pulse burst PS1 includes a sequence of multiple voltage pulses P1 having a first voltage level V1. In the examples of FIGS. 5 and 6, the first voltage level V1 is constant in each first voltage pulse burst PS1. That is, in one embodiment, the multiple voltage pulses P1 included in each first voltage pulse burst PS1 have the same voltage level V1. The reference voltage is a reference voltage level V1. ｒｅｆ The reference voltage level V ｒｅｆ The absolute value of the reference voltage level V in the substrate bias signal DC2 is smaller than the absolute value of the first voltage level V1. In one embodiment, the first voltage level V1 has a negative polarity. ｒｅｆ has a zero voltage level.

[0056] The ring bias signal DC4 has a second voltage pulse burst PS2 during a first state S1 (period TS1) within the repetition period T, and a reference voltage during a second state S2 within the repetition period T. As shown in FIG. 6 , the second voltage pulse burst PS2 has a sequence of voltage pulses P2-1, P2-2, P2-3, ..., P2-N having a plurality of gradually decreasing voltage levels V2-1, V2-2, V2-3, ..., V2-N (N is a natural number) during the first state S1. The reference voltage is a reference voltage level V ｒｅｆ The reference voltage level V ｒｅｆ The absolute value of V2-1, V2-2, V2-3, ..., V2-N of each of the plurality of voltage pulses P2-1, P2-2, P2-3, ..., P2-N included in the second voltage pulse burst PS2 has a negative polarity. ｒｅｆ and the reference voltage level V in the ring bias signal DC4 ｒｅｆ In one embodiment, the reference voltage level V in the ring bias signal DC4 ｒｅｆ has a zero voltage level.

[0057] In one embodiment, the voltage level difference ΔV between the first voltage pulse P2-1 and the last voltage pulse P2-N in each second voltage pulse burst PS2 is in the range of 50 V to 100 V. In one embodiment, the voltage level V2-1 of the first voltage pulse P2-1 in the second voltage pulse burst PS2 is greater than the first voltage level V1 of the voltage pulse P1 in the first voltage pulse burst PS1. In one embodiment, the voltage level V2-N of the last voltage pulse P2-N in the second voltage pulse burst PS2 is the same as the first voltage level V1 of the voltage pulse P1 in the first voltage pulse burst PS1. In one embodiment, the voltage level V2-N of the last voltage pulse P2-N in the second voltage pulse burst PS2 is less than the first voltage level V1 of the voltage pulse P1 in the first voltage pulse burst PS1. In one embodiment, the voltage levels V2-1, V2-2, V2-3, ..., V2-N of the plurality of voltage pulses P2-1, P2-2, P2-3, ..., P2-N included in the second voltage pulse burst PS2 are decreased stepwise during the period TS1. As shown in Fig. 7, the amount of decrease Δd (the difference between the voltage level V2-k of voltage pulse P2-k and the voltage level V2-(k+1) of voltage pulse P2-(k+1) (k is a natural number)) for each step of the plurality of voltage levels V2-1, V2-2, V2-3, ..., V2-N of the plurality of voltage pulses P2-1, P2-2, P2-3, ..., P2-N in the second voltage pulse burst PS2 may be constant. In one embodiment, the step-by-step decrease Δd of the plurality of voltage levels V2-1, V2-2, V2-3, ..., V2-N of the plurality of voltage pulses P2-1, P2-2, P2-3, ..., P2-N in the second voltage pulse burst PS2 may gradually decrease during the period TS1. For example, the step-by-step decrease Δd may exponentially decrease during the period TS1. In one embodiment, the period TS1 is in the range of 100 μsec to 150 μsec.

[0058] In one embodiment, the first voltage pulse burst PS1 of the substrate bias signal DC2 and the second voltage pulse burst PS2 of the ring bias signal DC4 are synchronized. In the example of Figures 5 and 6, the substrate bias signal DC2 has a voltage pulse burst PS1 during a first state S1 within a repeating period T, and has a reference voltage during a second state S2 within the repeating period T. The ring bias signal DC4 has a voltage pulse burst PS2 during a first state S1 within the repeating period T, synchronized with the substrate bias signal DC2, and has a reference voltage during a second state S2 within the repeating period T. That is, the substrate bias signal DC2 and the ring bias signal DC4 have voltage pulse bursts PS1 and PS2 during a first state S1 within the repeating period T, and have a reference voltage during a second state S2 within the repeating period T.

[0059] 5 , the voltage pulse bursts of the substrate bias signal DC2 and the ring bias signal DC4 are also synchronized with the RF signal for plasma generation supplied to the lower electrode and / or the upper electrode from the first RF generating unit 31 a (RF generator) of the RF power supply 31. That is, during a first state S1 within a repetition period T of the substrate bias signal DC2 and the ring bias signal DC4 (when voltage pulse bursts PS1 and PS2 are applied), the RF signal is supplied (RF signal is ON), and during a second state S2 within the repetition period T (when a reference voltage is applied), the supply of the RF signal is stopped (RF signal is OFF).

[0060] <Example of Plasma Processing Method> The plasma processing method includes an etching process that uses plasma to etch a film on a substrate W. In one embodiment, the plasma processing method is performed by the control unit 2 in the plasma processing apparatus 1.

[0061] First, the substrate W is carried into the chamber 10 by the transport arm, placed on the substrate support 11 by the lifter, and held by suction on the substrate support 11 as shown in FIG.

[0062] Next, plasma is generated in the plasma processing space 10s by the plasma generation unit 12. First, a processing gas is supplied to the shower head 13 by the gas supply unit 20, and then supplied from the shower head 13 to the plasma processing space 10s. The processing gas supplied at this time includes a gas that generates activated species necessary for etching the substrate W.

[0063] A source RF signal is supplied from an RF power supply 31 to the upper electrode and / or the lower electrode. A bias DC signal is supplied from a DC power supply 32 to the lower electrode. The atmosphere in the plasma processing space 10s is exhausted from a gas exhaust port 10e, and the inside of the plasma processing space 10s is depressurized. Plasma is generated from the processing gas on the substrate support 11 in the plasma processing space 10s, and the substrate W is etched.

[0064] During plasma generation, an RF signal is supplied to the upper electrode and / or the lower electrode by the first RF generating unit 31a of the RF power supply 31, and a substrate bias signal DC2 is supplied to the substrate bias electrode 300 by the substrate bias signal generator 351 shown in Fig. 4. As shown in Fig. 6, the substrate bias signal DC2 has a plurality of first voltage pulse bursts PS1, and when the plurality of first voltage pulse bursts PS1 are applied to the substrate bias electrode 300, ion components in the plasma formed on the substrate on the substrate support surface are attracted to the substrate W.

[0065] 4 supplies a ring bias signal DC4 to the ring bias electrode 301. As shown in Fig. 6, the ring bias signal DC4 has a plurality of second voltage pulse bursts PS2, and when the plurality of second voltage pulse bursts PS2 are applied to the ring bias electrode 301, ion components in the plasma formed on the edge portion of the substrate W are attracted to the edge portion of the substrate W.

[0066] At this time, the voltage level (V2) of the plurality of voltage pulses P2 in each second voltage pulse burst PS2 gradually decreases as time progresses. The voltage level difference ΔV1 between the first voltage pulse P2-1 and the last voltage pulse P2-2 in each second voltage pulse burst PS2 may be in the range of 50 V to 100 V. The voltage level (V1) of the plurality of voltage pulses P1 in each first voltage pulse burst PS1 may be constant.

[0067] If the voltage levels of the plurality of voltage pulses P2 in each second voltage pulse burst PS2 are kept constant, the ion incidence angle of the plasma at the edge portion of the substrate W shown in Figure 8 gradually shifts from an inward direction (toward the substrate) to an outward direction (toward the edge ring 250) as indicated by the arrows. This is presumably because the plasma sheath at the edge portion of the substrate W gradually rises relative to the plasma sheath at the center of the substrate W due to fluctuations in plasma density during plasma processing and charging of the edge ring 250, etc. In one embodiment, the voltage levels (V2) of the plurality of voltage pulses P2 in each second voltage pulse burst PS2 are gradually reduced, thereby suppressing the relative rise in the plasma sheath at the edge portion of the substrate W, and as a result, suppressing fluctuations in the ion incidence angle at the edge portion of the substrate W during plasma processing.

[0068] According to this exemplary embodiment, the plasma processing apparatus 1 includes a substrate bias signal generator 351 configured to generate a substrate bias signal DC2 having a plurality of first voltage pulse bursts PS1, and a ring bias signal generator 353 configured to generate a ring bias signal DC4 having a plurality of second voltage pulse bursts PS2, each second voltage pulse burst PS2 including a plurality of voltage pulses P2 having gradually decreasing voltage levels, thereby suppressing fluctuations in the ion incident angle at the edge portion of the substrate W during plasma processing, and thereby suppressing fluctuations in the results of the plasma processing.

[0069] In the above embodiment, the substrate bias signal DC2 and the ring bias signal DC4 do not need to be synchronized with the RF signal for plasma generation. For example, as shown in Fig. 9, during a first state S1 in a repetition period T of the substrate bias signal DC2 and the ring bias signal DC4 (when voltage pulse bursts PS1 and PS2 are applied), the supply of the RF signal may be stopped (the RF signal may be OFF), and during a second state S2 in the repetition period T (when a reference voltage is applied), the RF signal may be supplied (the RF signal may be ON).

[0070] In the above embodiments, the ring bias signal generator 353 may be configured to generate a plurality of second voltage pulse bursts PS2 from a combination of the first DC signal DC1 and the second DC signal DC3. As shown in Fig. 10, for example, the ring bias signal generator 353 is configured to generate a ring bias signal DC4 having a plurality of second voltage pulse bursts PS2 from the first DC signal DC1 and the second DC signal DC3. The plurality of second voltage pulse bursts PS2 may have a second voltage level V3 (V1 + V2) obtained by adding the first primary voltage level V1 of the first DC signal DC1 and the second primary voltage level V2 of the second DC signal DC3.

[0071] As an example, when the voltage levels V2-1, V2-2, V2-3, ... V2-N of the plurality of voltage pulses P2-1, P2-2, P2-3, P2-N in each second voltage pulse burst PS2 are gradually decreased, the second voltage level V3 may be gradually decreased by gradually decreasing the second primary voltage level V2. The second primary voltage level V2 may be gradually decreased in each second voltage pulse burst PS2. The first primary voltage level V1 may be kept constant, and the first voltage level V1 of the plurality of voltage pulses P1 in each first voltage pulse burst PS1 may be maintained constant.

[0072] The plasma processing apparatus may be a plasma processing apparatus using any plasma source other than a capacitively coupled plasma processing apparatus, such as an inductively coupled plasma processing apparatus, a microwave plasma processing apparatus, etc. The substrate support unit may not have a configuration of a conductive base and an electrostatic chuck, as long as it has a substrate support surface.

[0073] Embodiments of the present disclosure further include the following aspects.

[0074] a substrate support disposed within the chamber, the substrate support including: a conductive base; an electrostatic chuck disposed on the conductive base, the electrostatic chuck having a substrate support surface and a ring support surface; an edge ring disposed on the ring support surface to surround a substrate on the substrate support surface; a substrate bias electrode disposed within the electrostatic chuck below the substrate support surface; and a ring bias electrode disposed within the electrostatic chuck below the ring support surface; an RF generator configured to generate an RF signal to generate a plasma in the chamber; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

[0075] (Supplementary Note 2) The plasma processing apparatus of Supplementary Note 1, wherein each of the plurality of first voltage pulse bursts includes a plurality of voltage pulses having the same voltage level.

[0076] (Supplementary Note 3) The plasma processing apparatus according to Supplementary Note 1 or 2, wherein the voltage pulse included in each of the plurality of first voltage pulse bursts has negative polarity, and the voltage pulse included in each of the plurality of second voltage pulse bursts has negative polarity.

[0077] (Supplementary Note 4) The plasma processing apparatus of any one of Supplementary Notes 1 to 3, further comprising a first DC power supply configured to generate a first DC signal, wherein the substrate bias signal generator is configured to generate the plurality of first voltage pulse bursts from the first DC signal.

[0078] (Supplementary Note 5) The plasma processing apparatus of Supplementary Note 4, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from the second DC signal.

[0079] (Supplementary Note 6) The plasma processing apparatus of Supplementary Note 4, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from a combination of the first DC signal and the second DC signal.

[0080] (Supplementary Note 7) The plasma processing apparatus according to any one of Supplementary Notes 1 to 6, wherein a difference in voltage level between a first voltage pulse and a last voltage pulse in each of the plurality of second voltage pulse bursts is within a range of 50V to 100V.

[0081] (Supplementary Note 8) The plasma processing apparatus according to any one of Supplementary Notes 1 to 7, wherein a duration of each of the plurality of second voltage pulse bursts is within a range of 100 μsec to 150 μsec.

[0082] (Supplementary Note 9) The plasma processing apparatus according to any one of Supplementary Notes 1 to 8, wherein the plurality of first voltage pulse bursts are synchronized with the plurality of second voltage pulse bursts.

[0083] (Supplementary Note 10) A plasma processing apparatus comprising: a plasma processing chamber; a substrate support disposed within the plasma processing chamber and having a substrate support surface; an edge ring disposed to surround a substrate on the substrate support surface; a substrate bias electrode disposed below the substrate support surface; a ring bias electrode disposed below the edge ring; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

[0084] 11. The plasma processing apparatus of claim 10, wherein each of the first plurality of voltage pulse bursts includes a plurality of voltage pulses having the same voltage level.

[0085] (Supplementary Note 12) The plasma processing apparatus according to Supplementary Note 10 or 11, wherein the voltage pulse included in each of the plurality of first voltage pulse bursts has negative polarity, and the voltage pulse included in each of the plurality of second voltage pulse bursts has negative polarity.

[0086] (Supplementary Note 13) The plasma processing apparatus of any one of Supplementary Notes 10 to 12, further comprising a first DC power supply configured to generate a first DC signal, wherein the substrate bias signal generator is configured to generate the plurality of first voltage pulse bursts from the first DC signal.

[0087] (Supplementary Note 14) The plasma processing apparatus of Supplementary Note 13, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from the second DC signal.

[0088] (Supplementary Note 15) The plasma processing apparatus of Supplementary Note 13, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from a combination of the first DC signal and the second DC signal.

[0089] (Supplementary Note 16) The plasma processing apparatus of any one of Supplementary Notes 10 to 15, wherein a difference in voltage level between a first voltage pulse and a last voltage pulse in each of the plurality of second voltage pulse bursts is within a range of 50V to 100V.

[0090] (Supplementary Note 17) The plasma processing apparatus according to any one of Supplementary Notes 10 to 16, wherein a duration of each of the plurality of second voltage pulse bursts is in a range of 100 μsec to 150 μsec.

[0091] (Supplementary Note 18) The plasma processing apparatus according to any one of Supplementary Notes 10 to 17, wherein the plurality of first voltage pulse bursts are synchronized with the plurality of second voltage pulse bursts.

[0092] The above embodiments are described for the purpose of explanation and are not intended to limit the scope of the present disclosure. Various modifications can be made to the above embodiments without departing from the scope and spirit of the present disclosure. For example, some components in one embodiment can be added to other embodiments. Also, some components in one embodiment can be replaced with corresponding components in other embodiments.

[0093] 1... plasma processing apparatus, 10... chamber, 11... substrate support portion, 31a... first RF generating portion, 1111... electrostatic chuck, 250... edge ring, 300... substrate bias electrode, 301... ring bias electrode, 350... first DC power supply, 351... substrate bias signal generator, 352... second DC power supply, 353... ring bias signal generator, W... substrate

Claims

1. A plasma processing apparatus comprising: a chamber; and a substrate support disposed within the chamber, the substrate support including: a conductive base; an electrostatic chuck disposed on the conductive base, the electrostatic chuck having a substrate support surface and a ring support surface; an edge ring disposed on the ring support surface to surround a substrate on the substrate support surface; a substrate bias electrode disposed within the electrostatic chuck below the substrate support surface; and a ring bias electrode disposed within the electrostatic chuck below the ring support surface; an RF generator configured to generate an RF signal to generate a plasma in the chamber; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

2. The plasma processing apparatus of claim 1, wherein each of the first plurality of voltage pulse bursts includes a plurality of voltage pulses having the same voltage level.

3. The plasma processing apparatus according to claim 2, wherein the voltage pulse included in each of the plurality of first voltage pulse bursts has a negative polarity, and the voltage pulse included in each of the plurality of second voltage pulse bursts has a negative polarity.

4. The plasma processing apparatus of claim 3, further comprising a first DC power supply configured to generate a first DC signal, wherein the substrate bias signal generator is configured to generate the plurality of first voltage pulse bursts from the first DC signal.

5. The plasma processing apparatus of claim 4, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from the second DC signal.

6. The plasma processing apparatus of claim 4, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from a combination of the first DC signal and the second DC signal.

7. A plasma processing apparatus according to any one of claims 1 to 6, wherein the difference in voltage level between the first voltage pulse and the last voltage pulse in each of the plurality of second voltage pulse bursts is in the range of 50V to 100V.

8. The plasma processing apparatus of claim 7, wherein the duration of each of the plurality of second voltage pulse bursts is in the range of 100 μsec to 150 μsec.

9. The plasma processing apparatus of claim 8, wherein the first plurality of voltage pulse bursts are synchronized with the second plurality of voltage pulse bursts.

10. A plasma processing apparatus comprising: a plasma processing chamber; a substrate support disposed within the plasma processing chamber and having a substrate support surface; an edge ring disposed to surround a substrate on the substrate support surface; a substrate bias electrode disposed below the substrate support surface; a ring bias electrode disposed below the edge ring; a substrate bias signal generator electrically connected to the substrate bias electrode and configured to generate a substrate bias signal having a plurality of first voltage pulse bursts; and a ring bias signal generator electrically connected to the ring bias electrode and configured to generate a ring bias signal having a plurality of second voltage pulse bursts, each of the plurality of second voltage pulse bursts including a plurality of voltage pulses having gradually decreasing voltage levels.

11. The plasma processing apparatus of claim 10, wherein each of the first plurality of voltage pulse bursts includes a plurality of voltage pulses having the same voltage level.

12. The plasma processing apparatus of claim 11, wherein the voltage pulse included in each of the plurality of first voltage pulse bursts has a negative polarity, and the voltage pulse included in each of the plurality of second voltage pulse bursts has a negative polarity.

13. The plasma processing apparatus of claim 12, further comprising a first DC power supply configured to generate a first DC signal, wherein the substrate bias signal generator is configured to generate the plurality of first voltage pulse bursts from the first DC signal.

14. The plasma processing apparatus of claim 13, further comprising a second DC power supply configured to generate a second DC signal, and wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from the second DC signal.

15. The plasma processing apparatus of claim 13, further comprising a second DC power supply configured to generate a second DC signal, wherein the ring bias signal generator is configured to generate the plurality of second voltage pulse bursts from a combination of the first DC signal and the second DC signal.

16. The plasma processing apparatus of any one of claims 10 to 15, wherein the difference in voltage level between the first voltage pulse and the last voltage pulse in each of the plurality of second voltage pulse bursts is in the range of 50V to 100V.

17. The plasma processing apparatus of claim 16, wherein the duration of each of the plurality of second voltage pulse bursts is in the range of 100 μsec to 150 μsec.

18. The plasma processing apparatus of claim 17, wherein the first plurality of voltage pulse bursts are synchronized with the second plurality of voltage pulse bursts.

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